drivers/gpu/drm/gma500/mid_bios.c

   1 /**************************************************************************
   2  * Copyright (c) 2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 /* TODO
  21  * - Split functions by vbt type
  22  * - Make them all take drm_device
  23  * - Check ioremap failures
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm.h>
  28 #include "gma_drm.h"
  29 #include "psb_drv.h"
  30 #include "mid_bios.h"
  31
  32 static void mid_get_fuse_settings(struct drm_device *dev)
  33 {
  34         struct drm_psb_private *dev_priv = dev->dev_private;
  35         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
  36         uint32_t fuse_value = 0;
  37         uint32_t fuse_value_tmp = 0;
  38
  39 #define FB_REG06 0xD0810600
  40 #define FB_MIPI_DISABLE  (1 << 11)
  41 #define FB_REG09 0xD0810900
  42 #define FB_REG09 0xD0810900
  43 #define FB_SKU_MASK  0x7000
  44 #define FB_SKU_SHIFT 12
  45 #define FB_SKU_100 0
  46 #define FB_SKU_100L 1
  47 #define FB_SKU_83 2
  48         pci_write_config_dword(pci_root, 0xD0, FB_REG06);
  49         pci_read_config_dword(pci_root, 0xD4, &fuse_value);
  50
  51         /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
  52         if (IS_MRST(dev))
  53                 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
  54
  55         DRM_INFO("internal display is %s\n",
  56                  dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
  57
  58          /* Prevent runtime suspend at start*/
  59          if (dev_priv->iLVDS_enable) {
  60                 dev_priv->is_lvds_on = true;
  61                 dev_priv->is_mipi_on = false;
  62         } else {
  63                 dev_priv->is_mipi_on = true;
  64                 dev_priv->is_lvds_on = false;
  65         }
  66
  67         dev_priv->video_device_fuse = fuse_value;
  68
  69         pci_write_config_dword(pci_root, 0xD0, FB_REG09);
  70         pci_read_config_dword(pci_root, 0xD4, &fuse_value);
  71
  72         dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
  73         fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
  74
  75         dev_priv->fuse_reg_value = fuse_value;
  76
  77         switch (fuse_value_tmp) {
  78         case FB_SKU_100:
  79                 dev_priv->core_freq = 200;
  80                 break;
  81         case FB_SKU_100L:
  82                 dev_priv->core_freq = 100;
  83                 break;
  84         case FB_SKU_83:
  85                 dev_priv->core_freq = 166;
  86                 break;
  87         default:
  88                 dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
  89                                                                 fuse_value_tmp);
  90                 dev_priv->core_freq = 0;
  91         }
  92         dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
  93         pci_dev_put(pci_root);
  94 }
  95
  96 /*
  97  *      Get the revison ID, B0:D2:F0;0x08
  98  */
  99 static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
 100 {
 101         uint32_t platform_rev_id = 0;
 102         struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
 103
 104         pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
 105         dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
 106         pci_dev_put(pci_gfx_root);
 107         dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n",
 108                                         dev_priv->platform_rev_id);
 109 }
 110
 111 static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
 112 {
 113         struct drm_device *dev = dev_priv->dev;
 114         struct oaktrail_vbt *vbt = &dev_priv->vbt_data;
 115         u32 addr;
 116         u16 new_size;
 117         u8 *vbt_virtual;
 118         u8 bpi;
 119         u8 number_desc = 0;
 120         struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;
 121         struct gct_r10_timing_info ti;
 122         void *pGCT;
 123         struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
 124
 125         /* Get the address of the platform config vbt, B0:D2:F0;0xFC */
 126         pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
 127         pci_dev_put(pci_gfx_root);
 128
 129         dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
 130
 131         /* check for platform config address == 0. */
 132         /* this means fw doesn't support vbt */
 133
 134         if (addr == 0) {
 135                 vbt->size = 0;
 136                 return;
 137         }
 138
 139         /* get the virtual address of the vbt */
 140         vbt_virtual = ioremap(addr, sizeof(*vbt));
 141
 142         memcpy(vbt, vbt_virtual, sizeof(*vbt));
 143         iounmap(vbt_virtual); /* Free virtual address space */
 144
 145         dev_dbg(dev->dev, "GCT revision is %x\n", vbt->revision);
 146
 147         switch (vbt->revision) {
 148         case 0:
 149                 vbt->oaktrail_gct = ioremap(addr + sizeof(*vbt) - 4,
 150                                         vbt->size - sizeof(*vbt) + 4);
 151                 pGCT = vbt->oaktrail_gct;
 152                 bpi = ((struct oaktrail_gct_v1 *)pGCT)->PD.BootPanelIndex;
 153                 dev_priv->gct_data.bpi = bpi;
 154                 dev_priv->gct_data.pt =
 155                         ((struct oaktrail_gct_v1 *)pGCT)->PD.PanelType;
 156                 memcpy(&dev_priv->gct_data.DTD,
 157                         &((struct oaktrail_gct_v1 *)pGCT)->panel[bpi].DTD,
 158                                 sizeof(struct oaktrail_timing_info));
 159                 dev_priv->gct_data.Panel_Port_Control =
 160                   ((struct oaktrail_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
 161                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 162                         ((struct oaktrail_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
 163                 break;
 164         case 1:
 165                 vbt->oaktrail_gct = ioremap(addr + sizeof(*vbt) - 4,
 166                                         vbt->size - sizeof(*vbt) + 4);
 167                 pGCT = vbt->oaktrail_gct;
 168                 bpi = ((struct oaktrail_gct_v2 *)pGCT)->PD.BootPanelIndex;
 169                 dev_priv->gct_data.bpi = bpi;
 170                 dev_priv->gct_data.pt =
 171                         ((struct oaktrail_gct_v2 *)pGCT)->PD.PanelType;
 172                 memcpy(&dev_priv->gct_data.DTD,
 173                         &((struct oaktrail_gct_v2 *)pGCT)->panel[bpi].DTD,
 174                                 sizeof(struct oaktrail_timing_info));
 175                 dev_priv->gct_data.Panel_Port_Control =
 176                   ((struct oaktrail_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
 177                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 178                         ((struct oaktrail_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
 179                 break;
 180         case 0x10:
 181                 /*header definition changed from rev 01 (v2) to rev 10h. */
 182                 /*so, some values have changed location*/
 183                 new_size = vbt->checksum; /*checksum contains lo size byte*/
 184                 /*LSB of oaktrail_gct contains hi size byte*/
 185                 new_size |= ((0xff & (unsigned int)vbt->oaktrail_gct)) << 8;
 186
 187                 vbt->checksum = vbt->size; /*size contains the checksum*/
 188                 if (new_size > 0xff)
 189                         vbt->size = 0xff; /*restrict size to 255*/
 190                 else
 191                         vbt->size = new_size;
 192
 193                 /* number of descriptors defined in the GCT */
 194                 number_desc = ((0xff00 & (unsigned int)vbt->oaktrail_gct)) >> 8;
 195                 bpi = ((0xff0000 & (unsigned int)vbt->oaktrail_gct)) >> 16;
 196                 vbt->oaktrail_gct = ioremap(addr + GCT_R10_HEADER_SIZE,
 197                                 GCT_R10_DISPLAY_DESC_SIZE * number_desc);
 198                 pGCT = vbt->oaktrail_gct;
 199                 pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
 200                 dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
 201
 202                 /*copy the GCT display timings into a temp structure*/
 203                 memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
 204
 205                 /*now copy the temp struct into the dev_priv->gct_data*/
 206                 dp_ti->pixel_clock = ti.pixel_clock;
 207                 dp_ti->hactive_hi = ti.hactive_hi;
 208                 dp_ti->hactive_lo = ti.hactive_lo;
 209                 dp_ti->hblank_hi = ti.hblank_hi;
 210                 dp_ti->hblank_lo = ti.hblank_lo;
 211                 dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
 212                 dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
 213                 dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
 214                 dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
 215                 dp_ti->vactive_hi = ti.vactive_hi;
 216                 dp_ti->vactive_lo = ti.vactive_lo;
 217                 dp_ti->vblank_hi = ti.vblank_hi;
 218                 dp_ti->vblank_lo = ti.vblank_lo;
 219                 dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
 220                 dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
 221                 dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
 222                 dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
 223
 224                 /* Move the MIPI_Display_Descriptor data from GCT to dev priv */
 225                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 226                                                         *((u8 *)pGCT + 0x0d);
 227                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
 228                                                 (*((u8 *)pGCT + 0x0e)) << 8;
 229                 break;
 230         default:
 231                 dev_err(dev->dev, "Unknown revision of GCT!\n");
 232                 vbt->size = 0;
 233         }
 234 }
 235
 236 int mid_chip_setup(struct drm_device *dev)
 237 {
 238         struct drm_psb_private *dev_priv = dev->dev_private;
 239         mid_get_fuse_settings(dev);
 240         mid_get_vbt_data(dev_priv);
 241         mid_get_pci_revID(dev_priv);
 242         return 0;
 243 }