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ahci: fix CAP.NP and PI handling
[linux-2.6/libata-dev.git] / drivers / ata / ahci.c
blob29e71bddd6ffdd12420b4749eb88f79fb51ead26
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_enable_alpm(struct ata_port *ap,
53 enum link_pm policy);
54 static void ahci_disable_alpm(struct ata_port *ap);
55
56 enum {
57 AHCI_PCI_BAR = 5,
58 AHCI_MAX_PORTS = 32,
59 AHCI_MAX_SG = 168, /* hardware max is 64K */
60 AHCI_DMA_BOUNDARY = 0xffffffff,
61 AHCI_USE_CLUSTERING = 1,
62 AHCI_MAX_CMDS = 32,
63 AHCI_CMD_SZ = 32,
64 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
65 AHCI_RX_FIS_SZ = 256,
66 AHCI_CMD_TBL_CDB = 0x40,
67 AHCI_CMD_TBL_HDR_SZ = 0x80,
68 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
69 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
70 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
71 AHCI_RX_FIS_SZ,
72 AHCI_IRQ_ON_SG = (1 << 31),
73 AHCI_CMD_ATAPI = (1 << 5),
74 AHCI_CMD_WRITE = (1 << 6),
75 AHCI_CMD_PREFETCH = (1 << 7),
76 AHCI_CMD_RESET = (1 << 8),
77 AHCI_CMD_CLR_BUSY = (1 << 10),
78
79 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
80 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
81 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
82
83 board_ahci = 0,
84 board_ahci_vt8251 = 1,
85 board_ahci_ign_iferr = 2,
86 board_ahci_sb600 = 3,
87 board_ahci_mv = 4,
88
89 /* global controller registers */
90 HOST_CAP = 0x00, /* host capabilities */
91 HOST_CTL = 0x04, /* global host control */
92 HOST_IRQ_STAT = 0x08, /* interrupt status */
93 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
94 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
95
96 /* HOST_CTL bits */
97 HOST_RESET = (1 << 0), /* reset controller; self-clear */
98 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
99 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
100
101 /* HOST_CAP bits */
102 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
103 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
104 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
105 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
106 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
107 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
108 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
109 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
110
111 /* registers for each SATA port */
112 PORT_LST_ADDR = 0x00, /* command list DMA addr */
113 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
114 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
115 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
116 PORT_IRQ_STAT = 0x10, /* interrupt status */
117 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
118 PORT_CMD = 0x18, /* port command */
119 PORT_TFDATA = 0x20, /* taskfile data */
120 PORT_SIG = 0x24, /* device TF signature */
121 PORT_CMD_ISSUE = 0x38, /* command issue */
122 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
123 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
124 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
125 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
126 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
127
128 /* PORT_IRQ_{STAT,MASK} bits */
129 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
130 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
131 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
132 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
133 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
134 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
135 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
136 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
137
138 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
139 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
140 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
141 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
142 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
143 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
144 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
145 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
146 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
147
148 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
149 PORT_IRQ_IF_ERR |
150 PORT_IRQ_CONNECT |
151 PORT_IRQ_PHYRDY |
152 PORT_IRQ_UNK_FIS |
153 PORT_IRQ_BAD_PMP,
154 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
155 PORT_IRQ_TF_ERR |
156 PORT_IRQ_HBUS_DATA_ERR,
157 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
158 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
159 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
160
161 /* PORT_CMD bits */
162 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
163 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
164 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
165 PORT_CMD_PMP = (1 << 17), /* PMP attached */
166 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
167 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
168 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
169 PORT_CMD_CLO = (1 << 3), /* Command list override */
170 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
171 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
172 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
173
174 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
175 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
176 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
177 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
178
179 /* hpriv->flags bits */
180 AHCI_HFLAG_NO_NCQ = (1 << 0),
181 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
182 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
183 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
184 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
185 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
186 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
187 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
188
189 /* ap->flags bits */
190
191 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
192 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
193 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
194 ATA_FLAG_IPM,
195 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
196
197 ICH_MAP = 0x90, /* ICH MAP register */
198 };
199
200 struct ahci_cmd_hdr {
201 __le32 opts;
202 __le32 status;
203 __le32 tbl_addr;
204 __le32 tbl_addr_hi;
205 __le32 reserved[4];
206 };
207
208 struct ahci_sg {
209 __le32 addr;
210 __le32 addr_hi;
211 __le32 reserved;
212 __le32 flags_size;
213 };
214
215 struct ahci_host_priv {
216 unsigned int flags; /* AHCI_HFLAG_* */
217 u32 cap; /* cap to use */
218 u32 port_map; /* port map to use */
219 u32 saved_cap; /* saved initial cap */
220 u32 saved_port_map; /* saved initial port_map */
221 };
222
223 struct ahci_port_priv {
224 struct ata_link *active_link;
225 struct ahci_cmd_hdr *cmd_slot;
226 dma_addr_t cmd_slot_dma;
227 void *cmd_tbl;
228 dma_addr_t cmd_tbl_dma;
229 void *rx_fis;
230 dma_addr_t rx_fis_dma;
231 /* for NCQ spurious interrupt analysis */
232 unsigned int ncq_saw_d2h:1;
233 unsigned int ncq_saw_dmas:1;
234 unsigned int ncq_saw_sdb:1;
235 u32 intr_mask; /* interrupts to enable */
236 };
237
238 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
239 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
240 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
241 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
242 static void ahci_irq_clear(struct ata_port *ap);
243 static int ahci_port_start(struct ata_port *ap);
244 static void ahci_port_stop(struct ata_port *ap);
245 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
246 static void ahci_qc_prep(struct ata_queued_cmd *qc);
247 static u8 ahci_check_status(struct ata_port *ap);
248 static void ahci_freeze(struct ata_port *ap);
249 static void ahci_thaw(struct ata_port *ap);
250 static void ahci_pmp_attach(struct ata_port *ap);
251 static void ahci_pmp_detach(struct ata_port *ap);
252 static void ahci_error_handler(struct ata_port *ap);
253 static void ahci_vt8251_error_handler(struct ata_port *ap);
254 static void ahci_p5wdh_error_handler(struct ata_port *ap);
255 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
256 static int ahci_port_resume(struct ata_port *ap);
257 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
258 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
259 u32 opts);
260 #ifdef CONFIG_PM
261 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
262 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
263 static int ahci_pci_device_resume(struct pci_dev *pdev);
264 #endif
265
266 static struct class_device_attribute *ahci_shost_attrs[] = {
267 &class_device_attr_link_power_management_policy,
268 NULL
269 };
270
271 static struct scsi_host_template ahci_sht = {
272 .module = THIS_MODULE,
273 .name = DRV_NAME,
274 .ioctl = ata_scsi_ioctl,
275 .queuecommand = ata_scsi_queuecmd,
276 .change_queue_depth = ata_scsi_change_queue_depth,
277 .can_queue = AHCI_MAX_CMDS - 1,
278 .this_id = ATA_SHT_THIS_ID,
279 .sg_tablesize = AHCI_MAX_SG,
280 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
281 .emulated = ATA_SHT_EMULATED,
282 .use_clustering = AHCI_USE_CLUSTERING,
283 .proc_name = DRV_NAME,
284 .dma_boundary = AHCI_DMA_BOUNDARY,
285 .slave_configure = ata_scsi_slave_config,
286 .slave_destroy = ata_scsi_slave_destroy,
287 .bios_param = ata_std_bios_param,
288 .shost_attrs = ahci_shost_attrs,
289 };
290
291 static const struct ata_port_operations ahci_ops = {
292 .check_status = ahci_check_status,
293 .check_altstatus = ahci_check_status,
294 .dev_select = ata_noop_dev_select,
295
296 .tf_read = ahci_tf_read,
297
298 .qc_defer = sata_pmp_qc_defer_cmd_switch,
299 .qc_prep = ahci_qc_prep,
300 .qc_issue = ahci_qc_issue,
301
302 .irq_clear = ahci_irq_clear,
303
304 .scr_read = ahci_scr_read,
305 .scr_write = ahci_scr_write,
306
307 .freeze = ahci_freeze,
308 .thaw = ahci_thaw,
309
310 .error_handler = ahci_error_handler,
311 .post_internal_cmd = ahci_post_internal_cmd,
312
313 .pmp_attach = ahci_pmp_attach,
314 .pmp_detach = ahci_pmp_detach,
315
316 #ifdef CONFIG_PM
317 .port_suspend = ahci_port_suspend,
318 .port_resume = ahci_port_resume,
319 #endif
320 .enable_pm = ahci_enable_alpm,
321 .disable_pm = ahci_disable_alpm,
322
323 .port_start = ahci_port_start,
324 .port_stop = ahci_port_stop,
325 };
326
327 static const struct ata_port_operations ahci_vt8251_ops = {
328 .check_status = ahci_check_status,
329 .check_altstatus = ahci_check_status,
330 .dev_select = ata_noop_dev_select,
331
332 .tf_read = ahci_tf_read,
333
334 .qc_defer = sata_pmp_qc_defer_cmd_switch,
335 .qc_prep = ahci_qc_prep,
336 .qc_issue = ahci_qc_issue,
337
338 .irq_clear = ahci_irq_clear,
339
340 .scr_read = ahci_scr_read,
341 .scr_write = ahci_scr_write,
342
343 .freeze = ahci_freeze,
344 .thaw = ahci_thaw,
345
346 .error_handler = ahci_vt8251_error_handler,
347 .post_internal_cmd = ahci_post_internal_cmd,
348
349 .pmp_attach = ahci_pmp_attach,
350 .pmp_detach = ahci_pmp_detach,
351
352 #ifdef CONFIG_PM
353 .port_suspend = ahci_port_suspend,
354 .port_resume = ahci_port_resume,
355 #endif
356
357 .port_start = ahci_port_start,
358 .port_stop = ahci_port_stop,
359 };
360
361 static const struct ata_port_operations ahci_p5wdh_ops = {
362 .check_status = ahci_check_status,
363 .check_altstatus = ahci_check_status,
364 .dev_select = ata_noop_dev_select,
365
366 .tf_read = ahci_tf_read,
367
368 .qc_defer = sata_pmp_qc_defer_cmd_switch,
369 .qc_prep = ahci_qc_prep,
370 .qc_issue = ahci_qc_issue,
371
372 .irq_clear = ahci_irq_clear,
373
374 .scr_read = ahci_scr_read,
375 .scr_write = ahci_scr_write,
376
377 .freeze = ahci_freeze,
378 .thaw = ahci_thaw,
379
380 .error_handler = ahci_p5wdh_error_handler,
381 .post_internal_cmd = ahci_post_internal_cmd,
382
383 .pmp_attach = ahci_pmp_attach,
384 .pmp_detach = ahci_pmp_detach,
385
386 #ifdef CONFIG_PM
387 .port_suspend = ahci_port_suspend,
388 .port_resume = ahci_port_resume,
389 #endif
390
391 .port_start = ahci_port_start,
392 .port_stop = ahci_port_stop,
393 };
394
395 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
396
397 static const struct ata_port_info ahci_port_info[] = {
398 /* board_ahci */
399 {
400 .flags = AHCI_FLAG_COMMON,
401 .link_flags = AHCI_LFLAG_COMMON,
402 .pio_mask = 0x1f, /* pio0-4 */
403 .udma_mask = ATA_UDMA6,
404 .port_ops = &ahci_ops,
405 },
406 /* board_ahci_vt8251 */
407 {
408 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
409 .flags = AHCI_FLAG_COMMON,
410 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
411 .pio_mask = 0x1f, /* pio0-4 */
412 .udma_mask = ATA_UDMA6,
413 .port_ops = &ahci_vt8251_ops,
414 },
415 /* board_ahci_ign_iferr */
416 {
417 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
418 .flags = AHCI_FLAG_COMMON,
419 .link_flags = AHCI_LFLAG_COMMON,
420 .pio_mask = 0x1f, /* pio0-4 */
421 .udma_mask = ATA_UDMA6,
422 .port_ops = &ahci_ops,
423 },
424 /* board_ahci_sb600 */
425 {
426 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
427 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
428 .flags = AHCI_FLAG_COMMON,
429 .link_flags = AHCI_LFLAG_COMMON,
430 .pio_mask = 0x1f, /* pio0-4 */
431 .udma_mask = ATA_UDMA6,
432 .port_ops = &ahci_ops,
433 },
434 /* board_ahci_mv */
435 {
436 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
437 AHCI_HFLAG_MV_PATA),
438 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
439 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
440 .link_flags = AHCI_LFLAG_COMMON,
441 .pio_mask = 0x1f, /* pio0-4 */
442 .udma_mask = ATA_UDMA6,
443 .port_ops = &ahci_ops,
444 },
445 };
446
447 static const struct pci_device_id ahci_pci_tbl[] = {
448 /* Intel */
449 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
450 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
451 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
452 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
453 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
454 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
455 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
456 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
457 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
458 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
459 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
460 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
461 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
462 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
463 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
464 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
465 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
466 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
467 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
468 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
469 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
470 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
471 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
472 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
473 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
474 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
476 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
477 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
478 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
479 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
480
481 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
482 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
483 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
484
485 /* ATI */
486 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
487 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
488 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
489 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
490 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
491 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
492 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
493
494 /* VIA */
495 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
496 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
497
498 /* NVIDIA */
499 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
500 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
501 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
502 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
503 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
504 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
505 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
506 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
507 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
508 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
509 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
510 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
511 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
512 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
513 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
514 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
515 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
516 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
517 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
518 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
519 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
524 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
525 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
526 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
527 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
528 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
529 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
530 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
536 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
537 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
538 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
539 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
540 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
541 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
542 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
543 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
548 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
549 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
550 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
551 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
552 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
553 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
554 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
555
556 /* SiS */
557 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
558 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
559 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
560
561 /* Marvell */
562 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
563
564 /* Generic, PCI class code for AHCI */
565 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
566 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
567
568 { } /* terminate list */
569 };
570
571
572 static struct pci_driver ahci_pci_driver = {
573 .name = DRV_NAME,
574 .id_table = ahci_pci_tbl,
575 .probe = ahci_init_one,
576 .remove = ata_pci_remove_one,
577 #ifdef CONFIG_PM
578 .suspend = ahci_pci_device_suspend,
579 .resume = ahci_pci_device_resume,
580 #endif
581 };
582
583
584 static inline int ahci_nr_ports(u32 cap)
585 {
586 return (cap & 0x1f) + 1;
587 }
588
589 static inline void __iomem *__ahci_port_base(struct ata_host *host,
590 unsigned int port_no)
591 {
592 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
593
594 return mmio + 0x100 + (port_no * 0x80);
595 }
596
597 static inline void __iomem *ahci_port_base(struct ata_port *ap)
598 {
599 return __ahci_port_base(ap->host, ap->port_no);
600 }
601
602 static void ahci_enable_ahci(void __iomem *mmio)
603 {
604 u32 tmp;
605
606 /* turn on AHCI_EN */
607 tmp = readl(mmio + HOST_CTL);
608 if (!(tmp & HOST_AHCI_EN)) {
609 tmp |= HOST_AHCI_EN;
610 writel(tmp, mmio + HOST_CTL);
611 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
612 WARN_ON(!(tmp & HOST_AHCI_EN));
613 }
614 }
615
616 /**
617 * ahci_save_initial_config - Save and fixup initial config values
618 * @pdev: target PCI device
619 * @hpriv: host private area to store config values
620 *
621 * Some registers containing configuration info might be setup by
622 * BIOS and might be cleared on reset. This function saves the
623 * initial values of those registers into @hpriv such that they
624 * can be restored after controller reset.
625 *
626 * If inconsistent, config values are fixed up by this function.
627 *
628 * LOCKING:
629 * None.
630 */
631 static void ahci_save_initial_config(struct pci_dev *pdev,
632 struct ahci_host_priv *hpriv)
633 {
634 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
635 u32 cap, port_map;
636 int i;
637
638 /* make sure AHCI mode is enabled before accessing CAP */
639 ahci_enable_ahci(mmio);
640
641 /* Values prefixed with saved_ are written back to host after
642 * reset. Values without are used for driver operation.
643 */
644 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
645 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
646
647 /* some chips have errata preventing 64bit use */
648 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
649 dev_printk(KERN_INFO, &pdev->dev,
650 "controller can't do 64bit DMA, forcing 32bit\n");
651 cap &= ~HOST_CAP_64;
652 }
653
654 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
655 dev_printk(KERN_INFO, &pdev->dev,
656 "controller can't do NCQ, turning off CAP_NCQ\n");
657 cap &= ~HOST_CAP_NCQ;
658 }
659
660 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
661 dev_printk(KERN_INFO, &pdev->dev,
662 "controller can't do PMP, turning off CAP_PMP\n");
663 cap &= ~HOST_CAP_PMP;
664 }
665
666 /*
667 * Temporary Marvell 6145 hack: PATA port presence
668 * is asserted through the standard AHCI port
669 * presence register, as bit 4 (counting from 0)
670 */
671 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
672 dev_printk(KERN_ERR, &pdev->dev,
673 "MV_AHCI HACK: port_map %x -> %x\n",
674 hpriv->port_map,
675 hpriv->port_map & 0xf);
676
677 port_map &= 0xf;
678 }
679
680 /* cross check port_map and cap.n_ports */
681 if (port_map) {
682 int map_ports = 0;
683
684 for (i = 0; i < AHCI_MAX_PORTS; i++)
685 if (port_map & (1 << i))
686 map_ports++;
687
688 /* If PI has more ports than n_ports, whine, clear
689 * port_map and let it be generated from n_ports.
690 */
691 if (map_ports > ahci_nr_ports(cap)) {
692 dev_printk(KERN_WARNING, &pdev->dev,
693 "implemented port map (0x%x) contains more "
694 "ports than nr_ports (%u), using nr_ports\n",
695 port_map, ahci_nr_ports(cap));
696 port_map = 0;
697 }
698 }
699
700 /* fabricate port_map from cap.nr_ports */
701 if (!port_map) {
702 port_map = (1 << ahci_nr_ports(cap)) - 1;
703 dev_printk(KERN_WARNING, &pdev->dev,
704 "forcing PORTS_IMPL to 0x%x\n", port_map);
705
706 /* write the fixed up value to the PI register */
707 hpriv->saved_port_map = port_map;
708 }
709
710 /* record values to use during operation */
711 hpriv->cap = cap;
712 hpriv->port_map = port_map;
713 }
714
715 /**
716 * ahci_restore_initial_config - Restore initial config
717 * @host: target ATA host
718 *
719 * Restore initial config stored by ahci_save_initial_config().
720 *
721 * LOCKING:
722 * None.
723 */
724 static void ahci_restore_initial_config(struct ata_host *host)
725 {
726 struct ahci_host_priv *hpriv = host->private_data;
727 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
728
729 writel(hpriv->saved_cap, mmio + HOST_CAP);
730 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
731 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
732 }
733
734 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
735 {
736 static const int offset[] = {
737 [SCR_STATUS] = PORT_SCR_STAT,
738 [SCR_CONTROL] = PORT_SCR_CTL,
739 [SCR_ERROR] = PORT_SCR_ERR,
740 [SCR_ACTIVE] = PORT_SCR_ACT,
741 [SCR_NOTIFICATION] = PORT_SCR_NTF,
742 };
743 struct ahci_host_priv *hpriv = ap->host->private_data;
744
745 if (sc_reg < ARRAY_SIZE(offset) &&
746 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
747 return offset[sc_reg];
748 return 0;
749 }
750
751 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
752 {
753 void __iomem *port_mmio = ahci_port_base(ap);
754 int offset = ahci_scr_offset(ap, sc_reg);
755
756 if (offset) {
757 *val = readl(port_mmio + offset);
758 return 0;
759 }
760 return -EINVAL;
761 }
762
763 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
764 {
765 void __iomem *port_mmio = ahci_port_base(ap);
766 int offset = ahci_scr_offset(ap, sc_reg);
767
768 if (offset) {
769 writel(val, port_mmio + offset);
770 return 0;
771 }
772 return -EINVAL;
773 }
774
775 static void ahci_start_engine(struct ata_port *ap)
776 {
777 void __iomem *port_mmio = ahci_port_base(ap);
778 u32 tmp;
779
780 /* start DMA */
781 tmp = readl(port_mmio + PORT_CMD);
782 tmp |= PORT_CMD_START;
783 writel(tmp, port_mmio + PORT_CMD);
784 readl(port_mmio + PORT_CMD); /* flush */
785 }
786
787 static int ahci_stop_engine(struct ata_port *ap)
788 {
789 void __iomem *port_mmio = ahci_port_base(ap);
790 u32 tmp;
791
792 tmp = readl(port_mmio + PORT_CMD);
793
794 /* check if the HBA is idle */
795 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
796 return 0;
797
798 /* setting HBA to idle */
799 tmp &= ~PORT_CMD_START;
800 writel(tmp, port_mmio + PORT_CMD);
801
802 /* wait for engine to stop. This could be as long as 500 msec */
803 tmp = ata_wait_register(port_mmio + PORT_CMD,
804 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
805 if (tmp & PORT_CMD_LIST_ON)
806 return -EIO;
807
808 return 0;
809 }
810
811 static void ahci_start_fis_rx(struct ata_port *ap)
812 {
813 void __iomem *port_mmio = ahci_port_base(ap);
814 struct ahci_host_priv *hpriv = ap->host->private_data;
815 struct ahci_port_priv *pp = ap->private_data;
816 u32 tmp;
817
818 /* set FIS registers */
819 if (hpriv->cap & HOST_CAP_64)
820 writel((pp->cmd_slot_dma >> 16) >> 16,
821 port_mmio + PORT_LST_ADDR_HI);
822 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
823
824 if (hpriv->cap & HOST_CAP_64)
825 writel((pp->rx_fis_dma >> 16) >> 16,
826 port_mmio + PORT_FIS_ADDR_HI);
827 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
828
829 /* enable FIS reception */
830 tmp = readl(port_mmio + PORT_CMD);
831 tmp |= PORT_CMD_FIS_RX;
832 writel(tmp, port_mmio + PORT_CMD);
833
834 /* flush */
835 readl(port_mmio + PORT_CMD);
836 }
837
838 static int ahci_stop_fis_rx(struct ata_port *ap)
839 {
840 void __iomem *port_mmio = ahci_port_base(ap);
841 u32 tmp;
842
843 /* disable FIS reception */
844 tmp = readl(port_mmio + PORT_CMD);
845 tmp &= ~PORT_CMD_FIS_RX;
846 writel(tmp, port_mmio + PORT_CMD);
847
848 /* wait for completion, spec says 500ms, give it 1000 */
849 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
850 PORT_CMD_FIS_ON, 10, 1000);
851 if (tmp & PORT_CMD_FIS_ON)
852 return -EBUSY;
853
854 return 0;
855 }
856
857 static void ahci_power_up(struct ata_port *ap)
858 {
859 struct ahci_host_priv *hpriv = ap->host->private_data;
860 void __iomem *port_mmio = ahci_port_base(ap);
861 u32 cmd;
862
863 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
864
865 /* spin up device */
866 if (hpriv->cap & HOST_CAP_SSS) {
867 cmd |= PORT_CMD_SPIN_UP;
868 writel(cmd, port_mmio + PORT_CMD);
869 }
870
871 /* wake up link */
872 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
873 }
874
875 static void ahci_disable_alpm(struct ata_port *ap)
876 {
877 struct ahci_host_priv *hpriv = ap->host->private_data;
878 void __iomem *port_mmio = ahci_port_base(ap);
879 u32 cmd;
880 struct ahci_port_priv *pp = ap->private_data;
881
882 /* IPM bits should be disabled by libata-core */
883 /* get the existing command bits */
884 cmd = readl(port_mmio + PORT_CMD);
885
886 /* disable ALPM and ASP */
887 cmd &= ~PORT_CMD_ASP;
888 cmd &= ~PORT_CMD_ALPE;
889
890 /* force the interface back to active */
891 cmd |= PORT_CMD_ICC_ACTIVE;
892
893 /* write out new cmd value */
894 writel(cmd, port_mmio + PORT_CMD);
895 cmd = readl(port_mmio + PORT_CMD);
896
897 /* wait 10ms to be sure we've come out of any low power state */
898 msleep(10);
899
900 /* clear out any PhyRdy stuff from interrupt status */
901 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
902
903 /* go ahead and clean out PhyRdy Change from Serror too */
904 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
905
906 /*
907 * Clear flag to indicate that we should ignore all PhyRdy
908 * state changes
909 */
910 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
911
912 /*
913 * Enable interrupts on Phy Ready.
914 */
915 pp->intr_mask |= PORT_IRQ_PHYRDY;
916 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
917
918 /*
919 * don't change the link pm policy - we can be called
920 * just to turn of link pm temporarily
921 */
922 }
923
924 static int ahci_enable_alpm(struct ata_port *ap,
925 enum link_pm policy)
926 {
927 struct ahci_host_priv *hpriv = ap->host->private_data;
928 void __iomem *port_mmio = ahci_port_base(ap);
929 u32 cmd;
930 struct ahci_port_priv *pp = ap->private_data;
931 u32 asp;
932
933 /* Make sure the host is capable of link power management */
934 if (!(hpriv->cap & HOST_CAP_ALPM))
935 return -EINVAL;
936
937 switch (policy) {
938 case MAX_PERFORMANCE:
939 case NOT_AVAILABLE:
940 /*
941 * if we came here with NOT_AVAILABLE,
942 * it just means this is the first time we
943 * have tried to enable - default to max performance,
944 * and let the user go to lower power modes on request.
945 */
946 ahci_disable_alpm(ap);
947 return 0;
948 case MIN_POWER:
949 /* configure HBA to enter SLUMBER */
950 asp = PORT_CMD_ASP;
951 break;
952 case MEDIUM_POWER:
953 /* configure HBA to enter PARTIAL */
954 asp = 0;
955 break;
956 default:
957 return -EINVAL;
958 }
959
960 /*
961 * Disable interrupts on Phy Ready. This keeps us from
962 * getting woken up due to spurious phy ready interrupts
963 * TBD - Hot plug should be done via polling now, is
964 * that even supported?
965 */
966 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
967 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
968
969 /*
970 * Set a flag to indicate that we should ignore all PhyRdy
971 * state changes since these can happen now whenever we
972 * change link state
973 */
974 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
975
976 /* get the existing command bits */
977 cmd = readl(port_mmio + PORT_CMD);
978
979 /*
980 * Set ASP based on Policy
981 */
982 cmd |= asp;
983
984 /*
985 * Setting this bit will instruct the HBA to aggressively
986 * enter a lower power link state when it's appropriate and
987 * based on the value set above for ASP
988 */
989 cmd |= PORT_CMD_ALPE;
990
991 /* write out new cmd value */
992 writel(cmd, port_mmio + PORT_CMD);
993 cmd = readl(port_mmio + PORT_CMD);
994
995 /* IPM bits should be set by libata-core */
996 return 0;
997 }
998
999 #ifdef CONFIG_PM
1000 static void ahci_power_down(struct ata_port *ap)
1001 {
1002 struct ahci_host_priv *hpriv = ap->host->private_data;
1003 void __iomem *port_mmio = ahci_port_base(ap);
1004 u32 cmd, scontrol;
1005
1006 if (!(hpriv->cap & HOST_CAP_SSS))
1007 return;
1008
1009 /* put device into listen mode, first set PxSCTL.DET to 0 */
1010 scontrol = readl(port_mmio + PORT_SCR_CTL);
1011 scontrol &= ~0xf;
1012 writel(scontrol, port_mmio + PORT_SCR_CTL);
1013
1014 /* then set PxCMD.SUD to 0 */
1015 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1016 cmd &= ~PORT_CMD_SPIN_UP;
1017 writel(cmd, port_mmio + PORT_CMD);
1018 }
1019 #endif
1020
1021 static void ahci_start_port(struct ata_port *ap)
1022 {
1023 /* enable FIS reception */
1024 ahci_start_fis_rx(ap);
1025
1026 /* enable DMA */
1027 ahci_start_engine(ap);
1028 }
1029
1030 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1031 {
1032 int rc;
1033
1034 /* disable DMA */
1035 rc = ahci_stop_engine(ap);
1036 if (rc) {
1037 *emsg = "failed to stop engine";
1038 return rc;
1039 }
1040
1041 /* disable FIS reception */
1042 rc = ahci_stop_fis_rx(ap);
1043 if (rc) {
1044 *emsg = "failed stop FIS RX";
1045 return rc;
1046 }
1047
1048 return 0;
1049 }
1050
1051 static int ahci_reset_controller(struct ata_host *host)
1052 {
1053 struct pci_dev *pdev = to_pci_dev(host->dev);
1054 struct ahci_host_priv *hpriv = host->private_data;
1055 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1056 u32 tmp;
1057
1058 /* we must be in AHCI mode, before using anything
1059 * AHCI-specific, such as HOST_RESET.
1060 */
1061 ahci_enable_ahci(mmio);
1062
1063 /* global controller reset */
1064 tmp = readl(mmio + HOST_CTL);
1065 if ((tmp & HOST_RESET) == 0) {
1066 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1067 readl(mmio + HOST_CTL); /* flush */
1068 }
1069
1070 /* reset must complete within 1 second, or
1071 * the hardware should be considered fried.
1072 */
1073 ssleep(1);
1074
1075 tmp = readl(mmio + HOST_CTL);
1076 if (tmp & HOST_RESET) {
1077 dev_printk(KERN_ERR, host->dev,
1078 "controller reset failed (0x%x)\n", tmp);
1079 return -EIO;
1080 }
1081
1082 /* turn on AHCI mode */
1083 ahci_enable_ahci(mmio);
1084
1085 /* some registers might be cleared on reset. restore initial values */
1086 ahci_restore_initial_config(host);
1087
1088 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1089 u16 tmp16;
1090
1091 /* configure PCS */
1092 pci_read_config_word(pdev, 0x92, &tmp16);
1093 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1094 tmp16 |= hpriv->port_map;
1095 pci_write_config_word(pdev, 0x92, tmp16);
1096 }
1097 }
1098
1099 return 0;
1100 }
1101
1102 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1103 int port_no, void __iomem *mmio,
1104 void __iomem *port_mmio)
1105 {
1106 const char *emsg = NULL;
1107 int rc;
1108 u32 tmp;
1109
1110 /* make sure port is not active */
1111 rc = ahci_deinit_port(ap, &emsg);
1112 if (rc)
1113 dev_printk(KERN_WARNING, &pdev->dev,
1114 "%s (%d)\n", emsg, rc);
1115
1116 /* clear SError */
1117 tmp = readl(port_mmio + PORT_SCR_ERR);
1118 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1119 writel(tmp, port_mmio + PORT_SCR_ERR);
1120
1121 /* clear port IRQ */
1122 tmp = readl(port_mmio + PORT_IRQ_STAT);
1123 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1124 if (tmp)
1125 writel(tmp, port_mmio + PORT_IRQ_STAT);
1126
1127 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1128 }
1129
1130 static void ahci_init_controller(struct ata_host *host)
1131 {
1132 struct ahci_host_priv *hpriv = host->private_data;
1133 struct pci_dev *pdev = to_pci_dev(host->dev);
1134 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1135 int i;
1136 void __iomem *port_mmio;
1137 u32 tmp;
1138
1139 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1140 port_mmio = __ahci_port_base(host, 4);
1141
1142 writel(0, port_mmio + PORT_IRQ_MASK);
1143
1144 /* clear port IRQ */
1145 tmp = readl(port_mmio + PORT_IRQ_STAT);
1146 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1147 if (tmp)
1148 writel(tmp, port_mmio + PORT_IRQ_STAT);
1149 }
1150
1151 for (i = 0; i < host->n_ports; i++) {
1152 struct ata_port *ap = host->ports[i];
1153
1154 port_mmio = ahci_port_base(ap);
1155 if (ata_port_is_dummy(ap))
1156 continue;
1157
1158 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1159 }
1160
1161 tmp = readl(mmio + HOST_CTL);
1162 VPRINTK("HOST_CTL 0x%x\n", tmp);
1163 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1164 tmp = readl(mmio + HOST_CTL);
1165 VPRINTK("HOST_CTL 0x%x\n", tmp);
1166 }
1167
1168 static unsigned int ahci_dev_classify(struct ata_port *ap)
1169 {
1170 void __iomem *port_mmio = ahci_port_base(ap);
1171 struct ata_taskfile tf;
1172 u32 tmp;
1173
1174 tmp = readl(port_mmio + PORT_SIG);
1175 tf.lbah = (tmp >> 24) & 0xff;
1176 tf.lbam = (tmp >> 16) & 0xff;
1177 tf.lbal = (tmp >> 8) & 0xff;
1178 tf.nsect = (tmp) & 0xff;
1179
1180 return ata_dev_classify(&tf);
1181 }
1182
1183 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1184 u32 opts)
1185 {
1186 dma_addr_t cmd_tbl_dma;
1187
1188 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1189
1190 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1191 pp->cmd_slot[tag].status = 0;
1192 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1193 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1194 }
1195
1196 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1197 {
1198 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1199 struct ahci_host_priv *hpriv = ap->host->private_data;
1200 u32 tmp;
1201 int busy, rc;
1202
1203 /* do we need to kick the port? */
1204 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1205 if (!busy && !force_restart)
1206 return 0;
1207
1208 /* stop engine */
1209 rc = ahci_stop_engine(ap);
1210 if (rc)
1211 goto out_restart;
1212
1213 /* need to do CLO? */
1214 if (!busy) {
1215 rc = 0;
1216 goto out_restart;
1217 }
1218
1219 if (!(hpriv->cap & HOST_CAP_CLO)) {
1220 rc = -EOPNOTSUPP;
1221 goto out_restart;
1222 }
1223
1224 /* perform CLO */
1225 tmp = readl(port_mmio + PORT_CMD);
1226 tmp |= PORT_CMD_CLO;
1227 writel(tmp, port_mmio + PORT_CMD);
1228
1229 rc = 0;
1230 tmp = ata_wait_register(port_mmio + PORT_CMD,
1231 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1232 if (tmp & PORT_CMD_CLO)
1233 rc = -EIO;
1234
1235 /* restart engine */
1236 out_restart:
1237 ahci_start_engine(ap);
1238 return rc;
1239 }
1240
1241 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1242 struct ata_taskfile *tf, int is_cmd, u16 flags,
1243 unsigned long timeout_msec)
1244 {
1245 const u32 cmd_fis_len = 5; /* five dwords */
1246 struct ahci_port_priv *pp = ap->private_data;
1247 void __iomem *port_mmio = ahci_port_base(ap);
1248 u8 *fis = pp->cmd_tbl;
1249 u32 tmp;
1250
1251 /* prep the command */
1252 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1253 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1254
1255 /* issue & wait */
1256 writel(1, port_mmio + PORT_CMD_ISSUE);
1257
1258 if (timeout_msec) {
1259 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1260 1, timeout_msec);
1261 if (tmp & 0x1) {
1262 ahci_kick_engine(ap, 1);
1263 return -EBUSY;
1264 }
1265 } else
1266 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1267
1268 return 0;
1269 }
1270
1271 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1272 int pmp, unsigned long deadline)
1273 {
1274 struct ata_port *ap = link->ap;
1275 const char *reason = NULL;
1276 unsigned long now, msecs;
1277 struct ata_taskfile tf;
1278 int rc;
1279
1280 DPRINTK("ENTER\n");
1281
1282 if (ata_link_offline(link)) {
1283 DPRINTK("PHY reports no device\n");
1284 *class = ATA_DEV_NONE;
1285 return 0;
1286 }
1287
1288 /* prepare for SRST (AHCI-1.1 10.4.1) */
1289 rc = ahci_kick_engine(ap, 1);
1290 if (rc && rc != -EOPNOTSUPP)
1291 ata_link_printk(link, KERN_WARNING,
1292 "failed to reset engine (errno=%d)\n", rc);
1293
1294 ata_tf_init(link->device, &tf);
1295
1296 /* issue the first D2H Register FIS */
1297 msecs = 0;
1298 now = jiffies;
1299 if (time_after(now, deadline))
1300 msecs = jiffies_to_msecs(deadline - now);
1301
1302 tf.ctl |= ATA_SRST;
1303 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1304 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1305 rc = -EIO;
1306 reason = "1st FIS failed";
1307 goto fail;
1308 }
1309
1310 /* spec says at least 5us, but be generous and sleep for 1ms */
1311 msleep(1);
1312
1313 /* issue the second D2H Register FIS */
1314 tf.ctl &= ~ATA_SRST;
1315 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1316
1317 /* wait a while before checking status */
1318 ata_wait_after_reset(ap, deadline);
1319
1320 rc = ata_wait_ready(ap, deadline);
1321 /* link occupied, -ENODEV too is an error */
1322 if (rc) {
1323 reason = "device not ready";
1324 goto fail;
1325 }
1326 *class = ahci_dev_classify(ap);
1327
1328 DPRINTK("EXIT, class=%u\n", *class);
1329 return 0;
1330
1331 fail:
1332 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1333 return rc;
1334 }
1335
1336 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1337 unsigned long deadline)
1338 {
1339 int pmp = 0;
1340
1341 if (link->ap->flags & ATA_FLAG_PMP)
1342 pmp = SATA_PMP_CTRL_PORT;
1343
1344 return ahci_do_softreset(link, class, pmp, deadline);
1345 }
1346
1347 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1348 unsigned long deadline)
1349 {
1350 struct ata_port *ap = link->ap;
1351 struct ahci_port_priv *pp = ap->private_data;
1352 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1353 struct ata_taskfile tf;
1354 int rc;
1355
1356 DPRINTK("ENTER\n");
1357
1358 ahci_stop_engine(ap);
1359
1360 /* clear D2H reception area to properly wait for D2H FIS */
1361 ata_tf_init(link->device, &tf);
1362 tf.command = 0x80;
1363 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1364
1365 rc = sata_std_hardreset(link, class, deadline);
1366
1367 ahci_start_engine(ap);
1368
1369 if (rc == 0 && ata_link_online(link))
1370 *class = ahci_dev_classify(ap);
1371 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1372 *class = ATA_DEV_NONE;
1373
1374 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1375 return rc;
1376 }
1377
1378 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1379 unsigned long deadline)
1380 {
1381 struct ata_port *ap = link->ap;
1382 u32 serror;
1383 int rc;
1384
1385 DPRINTK("ENTER\n");
1386
1387 ahci_stop_engine(ap);
1388
1389 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1390 deadline);
1391
1392 /* vt8251 needs SError cleared for the port to operate */
1393 ahci_scr_read(ap, SCR_ERROR, &serror);
1394 ahci_scr_write(ap, SCR_ERROR, serror);
1395
1396 ahci_start_engine(ap);
1397
1398 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1399
1400 /* vt8251 doesn't clear BSY on signature FIS reception,
1401 * request follow-up softreset.
1402 */
1403 return rc ?: -EAGAIN;
1404 }
1405
1406 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1407 unsigned long deadline)
1408 {
1409 struct ata_port *ap = link->ap;
1410 struct ahci_port_priv *pp = ap->private_data;
1411 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1412 struct ata_taskfile tf;
1413 int rc;
1414
1415 ahci_stop_engine(ap);
1416
1417 /* clear D2H reception area to properly wait for D2H FIS */
1418 ata_tf_init(link->device, &tf);
1419 tf.command = 0x80;
1420 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1421
1422 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1423 deadline);
1424
1425 ahci_start_engine(ap);
1426
1427 if (rc || ata_link_offline(link))
1428 return rc;
1429
1430 /* spec mandates ">= 2ms" before checking status */
1431 msleep(150);
1432
1433 /* The pseudo configuration device on SIMG4726 attached to
1434 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1435 * hardreset if no device is attached to the first downstream
1436 * port && the pseudo device locks up on SRST w/ PMP==0. To
1437 * work around this, wait for !BSY only briefly. If BSY isn't
1438 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1439 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1440 *
1441 * Wait for two seconds. Devices attached to downstream port
1442 * which can't process the following IDENTIFY after this will
1443 * have to be reset again. For most cases, this should
1444 * suffice while making probing snappish enough.
1445 */
1446 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1447 if (rc)
1448 ahci_kick_engine(ap, 0);
1449
1450 return 0;
1451 }
1452
1453 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1454 {
1455 struct ata_port *ap = link->ap;
1456 void __iomem *port_mmio = ahci_port_base(ap);
1457 u32 new_tmp, tmp;
1458
1459 ata_std_postreset(link, class);
1460
1461 /* Make sure port's ATAPI bit is set appropriately */
1462 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1463 if (*class == ATA_DEV_ATAPI)
1464 new_tmp |= PORT_CMD_ATAPI;
1465 else
1466 new_tmp &= ~PORT_CMD_ATAPI;
1467 if (new_tmp != tmp) {
1468 writel(new_tmp, port_mmio + PORT_CMD);
1469 readl(port_mmio + PORT_CMD); /* flush */
1470 }
1471 }
1472
1473 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1474 unsigned long deadline)
1475 {
1476 return ahci_do_softreset(link, class, link->pmp, deadline);
1477 }
1478
1479 static u8 ahci_check_status(struct ata_port *ap)
1480 {
1481 void __iomem *mmio = ap->ioaddr.cmd_addr;
1482
1483 return readl(mmio + PORT_TFDATA) & 0xFF;
1484 }
1485
1486 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1487 {
1488 struct ahci_port_priv *pp = ap->private_data;
1489 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1490
1491 ata_tf_from_fis(d2h_fis, tf);
1492 }
1493
1494 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1495 {
1496 struct scatterlist *sg;
1497 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1498 unsigned int si;
1499
1500 VPRINTK("ENTER\n");
1501
1502 /*
1503 * Next, the S/G list.
1504 */
1505 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1506 dma_addr_t addr = sg_dma_address(sg);
1507 u32 sg_len = sg_dma_len(sg);
1508
1509 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1510 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1511 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1512 }
1513
1514 return si;
1515 }
1516
1517 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1518 {
1519 struct ata_port *ap = qc->ap;
1520 struct ahci_port_priv *pp = ap->private_data;
1521 int is_atapi = ata_is_atapi(qc->tf.protocol);
1522 void *cmd_tbl;
1523 u32 opts;
1524 const u32 cmd_fis_len = 5; /* five dwords */
1525 unsigned int n_elem;
1526
1527 /*
1528 * Fill in command table information. First, the header,
1529 * a SATA Register - Host to Device command FIS.
1530 */
1531 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1532
1533 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1534 if (is_atapi) {
1535 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1536 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1537 }
1538
1539 n_elem = 0;
1540 if (qc->flags & ATA_QCFLAG_DMAMAP)
1541 n_elem = ahci_fill_sg(qc, cmd_tbl);
1542
1543 /*
1544 * Fill in command slot information.
1545 */
1546 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1547 if (qc->tf.flags & ATA_TFLAG_WRITE)
1548 opts |= AHCI_CMD_WRITE;
1549 if (is_atapi)
1550 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1551
1552 ahci_fill_cmd_slot(pp, qc->tag, opts);
1553 }
1554
1555 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1556 {
1557 struct ahci_host_priv *hpriv = ap->host->private_data;
1558 struct ahci_port_priv *pp = ap->private_data;
1559 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1560 struct ata_link *link = NULL;
1561 struct ata_queued_cmd *active_qc;
1562 struct ata_eh_info *active_ehi;
1563 u32 serror;
1564
1565 /* determine active link */
1566 ata_port_for_each_link(link, ap)
1567 if (ata_link_active(link))
1568 break;
1569 if (!link)
1570 link = &ap->link;
1571
1572 active_qc = ata_qc_from_tag(ap, link->active_tag);
1573 active_ehi = &link->eh_info;
1574
1575 /* record irq stat */
1576 ata_ehi_clear_desc(host_ehi);
1577 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1578
1579 /* AHCI needs SError cleared; otherwise, it might lock up */
1580 ahci_scr_read(ap, SCR_ERROR, &serror);
1581 ahci_scr_write(ap, SCR_ERROR, serror);
1582 host_ehi->serror |= serror;
1583
1584 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1585 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1586 irq_stat &= ~PORT_IRQ_IF_ERR;
1587
1588 if (irq_stat & PORT_IRQ_TF_ERR) {
1589 /* If qc is active, charge it; otherwise, the active
1590 * link. There's no active qc on NCQ errors. It will
1591 * be determined by EH by reading log page 10h.
1592 */
1593 if (active_qc)
1594 active_qc->err_mask |= AC_ERR_DEV;
1595 else
1596 active_ehi->err_mask |= AC_ERR_DEV;
1597
1598 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1599 host_ehi->serror &= ~SERR_INTERNAL;
1600 }
1601
1602 if (irq_stat & PORT_IRQ_UNK_FIS) {
1603 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1604
1605 active_ehi->err_mask |= AC_ERR_HSM;
1606 active_ehi->action |= ATA_EH_SOFTRESET;
1607 ata_ehi_push_desc(active_ehi,
1608 "unknown FIS %08x %08x %08x %08x" ,
1609 unk[0], unk[1], unk[2], unk[3]);
1610 }
1611
1612 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1613 active_ehi->err_mask |= AC_ERR_HSM;
1614 active_ehi->action |= ATA_EH_SOFTRESET;
1615 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1616 }
1617
1618 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1619 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1620 host_ehi->action |= ATA_EH_SOFTRESET;
1621 ata_ehi_push_desc(host_ehi, "host bus error");
1622 }
1623
1624 if (irq_stat & PORT_IRQ_IF_ERR) {
1625 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1626 host_ehi->action |= ATA_EH_SOFTRESET;
1627 ata_ehi_push_desc(host_ehi, "interface fatal error");
1628 }
1629
1630 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1631 ata_ehi_hotplugged(host_ehi);
1632 ata_ehi_push_desc(host_ehi, "%s",
1633 irq_stat & PORT_IRQ_CONNECT ?
1634 "connection status changed" : "PHY RDY changed");
1635 }
1636
1637 /* okay, let's hand over to EH */
1638
1639 if (irq_stat & PORT_IRQ_FREEZE)
1640 ata_port_freeze(ap);
1641 else
1642 ata_port_abort(ap);
1643 }
1644
1645 static void ahci_port_intr(struct ata_port *ap)
1646 {
1647 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1648 struct ata_eh_info *ehi = &ap->link.eh_info;
1649 struct ahci_port_priv *pp = ap->private_data;
1650 struct ahci_host_priv *hpriv = ap->host->private_data;
1651 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1652 u32 status, qc_active;
1653 int rc;
1654
1655 status = readl(port_mmio + PORT_IRQ_STAT);
1656 writel(status, port_mmio + PORT_IRQ_STAT);
1657
1658 /* ignore BAD_PMP while resetting */
1659 if (unlikely(resetting))
1660 status &= ~PORT_IRQ_BAD_PMP;
1661
1662 /* If we are getting PhyRdy, this is
1663 * just a power state change, we should
1664 * clear out this, plus the PhyRdy/Comm
1665 * Wake bits from Serror
1666 */
1667 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1668 (status & PORT_IRQ_PHYRDY)) {
1669 status &= ~PORT_IRQ_PHYRDY;
1670 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1671 }
1672
1673 if (unlikely(status & PORT_IRQ_ERROR)) {
1674 ahci_error_intr(ap, status);
1675 return;
1676 }
1677
1678 if (status & PORT_IRQ_SDB_FIS) {
1679 /* If SNotification is available, leave notification
1680 * handling to sata_async_notification(). If not,
1681 * emulate it by snooping SDB FIS RX area.
1682 *
1683 * Snooping FIS RX area is probably cheaper than
1684 * poking SNotification but some constrollers which
1685 * implement SNotification, ICH9 for example, don't
1686 * store AN SDB FIS into receive area.
1687 */
1688 if (hpriv->cap & HOST_CAP_SNTF)
1689 sata_async_notification(ap);
1690 else {
1691 /* If the 'N' bit in word 0 of the FIS is set,
1692 * we just received asynchronous notification.
1693 * Tell libata about it.
1694 */
1695 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1696 u32 f0 = le32_to_cpu(f[0]);
1697
1698 if (f0 & (1 << 15))
1699 sata_async_notification(ap);
1700 }
1701 }
1702
1703 /* pp->active_link is valid iff any command is in flight */
1704 if (ap->qc_active && pp->active_link->sactive)
1705 qc_active = readl(port_mmio + PORT_SCR_ACT);
1706 else
1707 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1708
1709 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1710
1711 /* while resetting, invalid completions are expected */
1712 if (unlikely(rc < 0 && !resetting)) {
1713 ehi->err_mask |= AC_ERR_HSM;
1714 ehi->action |= ATA_EH_SOFTRESET;
1715 ata_port_freeze(ap);
1716 }
1717 }
1718
1719 static void ahci_irq_clear(struct ata_port *ap)
1720 {
1721 /* TODO */
1722 }
1723
1724 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1725 {
1726 struct ata_host *host = dev_instance;
1727 struct ahci_host_priv *hpriv;
1728 unsigned int i, handled = 0;
1729 void __iomem *mmio;
1730 u32 irq_stat, irq_ack = 0;
1731
1732 VPRINTK("ENTER\n");
1733
1734 hpriv = host->private_data;
1735 mmio = host->iomap[AHCI_PCI_BAR];
1736
1737 /* sigh. 0xffffffff is a valid return from h/w */
1738 irq_stat = readl(mmio + HOST_IRQ_STAT);
1739 irq_stat &= hpriv->port_map;
1740 if (!irq_stat)
1741 return IRQ_NONE;
1742
1743 spin_lock(&host->lock);
1744
1745 for (i = 0; i < host->n_ports; i++) {
1746 struct ata_port *ap;
1747
1748 if (!(irq_stat & (1 << i)))
1749 continue;
1750
1751 ap = host->ports[i];
1752 if (ap) {
1753 ahci_port_intr(ap);
1754 VPRINTK("port %u\n", i);
1755 } else {
1756 VPRINTK("port %u (no irq)\n", i);
1757 if (ata_ratelimit())
1758 dev_printk(KERN_WARNING, host->dev,
1759 "interrupt on disabled port %u\n", i);
1760 }
1761
1762 irq_ack |= (1 << i);
1763 }
1764
1765 if (irq_ack) {
1766 writel(irq_ack, mmio + HOST_IRQ_STAT);
1767 handled = 1;
1768 }
1769
1770 spin_unlock(&host->lock);
1771
1772 VPRINTK("EXIT\n");
1773
1774 return IRQ_RETVAL(handled);
1775 }
1776
1777 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1778 {
1779 struct ata_port *ap = qc->ap;
1780 void __iomem *port_mmio = ahci_port_base(ap);
1781 struct ahci_port_priv *pp = ap->private_data;
1782
1783 /* Keep track of the currently active link. It will be used
1784 * in completion path to determine whether NCQ phase is in
1785 * progress.
1786 */
1787 pp->active_link = qc->dev->link;
1788
1789 if (qc->tf.protocol == ATA_PROT_NCQ)
1790 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1791 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1792 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1793
1794 return 0;
1795 }
1796
1797 static void ahci_freeze(struct ata_port *ap)
1798 {
1799 void __iomem *port_mmio = ahci_port_base(ap);
1800
1801 /* turn IRQ off */
1802 writel(0, port_mmio + PORT_IRQ_MASK);
1803 }
1804
1805 static void ahci_thaw(struct ata_port *ap)
1806 {
1807 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1808 void __iomem *port_mmio = ahci_port_base(ap);
1809 u32 tmp;
1810 struct ahci_port_priv *pp = ap->private_data;
1811
1812 /* clear IRQ */
1813 tmp = readl(port_mmio + PORT_IRQ_STAT);
1814 writel(tmp, port_mmio + PORT_IRQ_STAT);
1815 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1816
1817 /* turn IRQ back on */
1818 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1819 }
1820
1821 static void ahci_error_handler(struct ata_port *ap)
1822 {
1823 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1824 /* restart engine */
1825 ahci_stop_engine(ap);
1826 ahci_start_engine(ap);
1827 }
1828
1829 /* perform recovery */
1830 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1831 ahci_hardreset, ahci_postreset,
1832 sata_pmp_std_prereset, ahci_pmp_softreset,
1833 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1834 }
1835
1836 static void ahci_vt8251_error_handler(struct ata_port *ap)
1837 {
1838 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1839 /* restart engine */
1840 ahci_stop_engine(ap);
1841 ahci_start_engine(ap);
1842 }
1843
1844 /* perform recovery */
1845 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1846 ahci_postreset);
1847 }
1848
1849 static void ahci_p5wdh_error_handler(struct ata_port *ap)
1850 {
1851 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1852 /* restart engine */
1853 ahci_stop_engine(ap);
1854 ahci_start_engine(ap);
1855 }
1856
1857 /* perform recovery */
1858 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1859 ahci_postreset);
1860 }
1861
1862 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1863 {
1864 struct ata_port *ap = qc->ap;
1865
1866 /* make DMA engine forget about the failed command */
1867 if (qc->flags & ATA_QCFLAG_FAILED)
1868 ahci_kick_engine(ap, 1);
1869 }
1870
1871 static void ahci_pmp_attach(struct ata_port *ap)
1872 {
1873 void __iomem *port_mmio = ahci_port_base(ap);
1874 struct ahci_port_priv *pp = ap->private_data;
1875 u32 cmd;
1876
1877 cmd = readl(port_mmio + PORT_CMD);
1878 cmd |= PORT_CMD_PMP;
1879 writel(cmd, port_mmio + PORT_CMD);
1880
1881 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1882 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1883 }
1884
1885 static void ahci_pmp_detach(struct ata_port *ap)
1886 {
1887 void __iomem *port_mmio = ahci_port_base(ap);
1888 struct ahci_port_priv *pp = ap->private_data;
1889 u32 cmd;
1890
1891 cmd = readl(port_mmio + PORT_CMD);
1892 cmd &= ~PORT_CMD_PMP;
1893 writel(cmd, port_mmio + PORT_CMD);
1894
1895 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1896 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1897 }
1898
1899 static int ahci_port_resume(struct ata_port *ap)
1900 {
1901 ahci_power_up(ap);
1902 ahci_start_port(ap);
1903
1904 if (ap->nr_pmp_links)
1905 ahci_pmp_attach(ap);
1906 else
1907 ahci_pmp_detach(ap);
1908
1909 return 0;
1910 }
1911
1912 #ifdef CONFIG_PM
1913 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1914 {
1915 const char *emsg = NULL;
1916 int rc;
1917
1918 rc = ahci_deinit_port(ap, &emsg);
1919 if (rc == 0)
1920 ahci_power_down(ap);
1921 else {
1922 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1923 ahci_start_port(ap);
1924 }
1925
1926 return rc;
1927 }
1928
1929 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1930 {
1931 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1932 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1933 u32 ctl;
1934
1935 if (mesg.event == PM_EVENT_SUSPEND) {
1936 /* AHCI spec rev1.1 section 8.3.3:
1937 * Software must disable interrupts prior to requesting a
1938 * transition of the HBA to D3 state.
1939 */
1940 ctl = readl(mmio + HOST_CTL);
1941 ctl &= ~HOST_IRQ_EN;
1942 writel(ctl, mmio + HOST_CTL);
1943 readl(mmio + HOST_CTL); /* flush */
1944 }
1945
1946 return ata_pci_device_suspend(pdev, mesg);
1947 }
1948
1949 static int ahci_pci_device_resume(struct pci_dev *pdev)
1950 {
1951 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1952 int rc;
1953
1954 rc = ata_pci_device_do_resume(pdev);
1955 if (rc)
1956 return rc;
1957
1958 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1959 rc = ahci_reset_controller(host);
1960 if (rc)
1961 return rc;
1962
1963 ahci_init_controller(host);
1964 }
1965
1966 ata_host_resume(host);
1967
1968 return 0;
1969 }
1970 #endif
1971
1972 static int ahci_port_start(struct ata_port *ap)
1973 {
1974 struct device *dev = ap->host->dev;
1975 struct ahci_port_priv *pp;
1976 void *mem;
1977 dma_addr_t mem_dma;
1978 int rc;
1979
1980 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1981 if (!pp)
1982 return -ENOMEM;
1983
1984 rc = ata_pad_alloc(ap, dev);
1985 if (rc)
1986 return rc;
1987
1988 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1989 GFP_KERNEL);
1990 if (!mem)
1991 return -ENOMEM;
1992 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1993
1994 /*
1995 * First item in chunk of DMA memory: 32-slot command table,
1996 * 32 bytes each in size
1997 */
1998 pp->cmd_slot = mem;
1999 pp->cmd_slot_dma = mem_dma;
2000
2001 mem += AHCI_CMD_SLOT_SZ;
2002 mem_dma += AHCI_CMD_SLOT_SZ;
2003
2004 /*
2005 * Second item: Received-FIS area
2006 */
2007 pp->rx_fis = mem;
2008 pp->rx_fis_dma = mem_dma;
2009
2010 mem += AHCI_RX_FIS_SZ;
2011 mem_dma += AHCI_RX_FIS_SZ;
2012
2013 /*
2014 * Third item: data area for storing a single command
2015 * and its scatter-gather table
2016 */
2017 pp->cmd_tbl = mem;
2018 pp->cmd_tbl_dma = mem_dma;
2019
2020 /*
2021 * Save off initial list of interrupts to be enabled.
2022 * This could be changed later
2023 */
2024 pp->intr_mask = DEF_PORT_IRQ;
2025
2026 ap->private_data = pp;
2027
2028 /* engage engines, captain */
2029 return ahci_port_resume(ap);
2030 }
2031
2032 static void ahci_port_stop(struct ata_port *ap)
2033 {
2034 const char *emsg = NULL;
2035 int rc;
2036
2037 /* de-initialize port */
2038 rc = ahci_deinit_port(ap, &emsg);
2039 if (rc)
2040 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2041 }
2042
2043 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2044 {
2045 int rc;
2046
2047 if (using_dac &&
2048 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2049 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2050 if (rc) {
2051 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2052 if (rc) {
2053 dev_printk(KERN_ERR, &pdev->dev,
2054 "64-bit DMA enable failed\n");
2055 return rc;
2056 }
2057 }
2058 } else {
2059 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2060 if (rc) {
2061 dev_printk(KERN_ERR, &pdev->dev,
2062 "32-bit DMA enable failed\n");
2063 return rc;
2064 }
2065 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2066 if (rc) {
2067 dev_printk(KERN_ERR, &pdev->dev,
2068 "32-bit consistent DMA enable failed\n");
2069 return rc;
2070 }
2071 }
2072 return 0;
2073 }
2074
2075 static void ahci_print_info(struct ata_host *host)
2076 {
2077 struct ahci_host_priv *hpriv = host->private_data;
2078 struct pci_dev *pdev = to_pci_dev(host->dev);
2079 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2080 u32 vers, cap, impl, speed;
2081 const char *speed_s;
2082 u16 cc;
2083 const char *scc_s;
2084
2085 vers = readl(mmio + HOST_VERSION);
2086 cap = hpriv->cap;
2087 impl = hpriv->port_map;
2088
2089 speed = (cap >> 20) & 0xf;
2090 if (speed == 1)
2091 speed_s = "1.5";
2092 else if (speed == 2)
2093 speed_s = "3";
2094 else
2095 speed_s = "?";
2096
2097 pci_read_config_word(pdev, 0x0a, &cc);
2098 if (cc == PCI_CLASS_STORAGE_IDE)
2099 scc_s = "IDE";
2100 else if (cc == PCI_CLASS_STORAGE_SATA)
2101 scc_s = "SATA";
2102 else if (cc == PCI_CLASS_STORAGE_RAID)
2103 scc_s = "RAID";
2104 else
2105 scc_s = "unknown";
2106
2107 dev_printk(KERN_INFO, &pdev->dev,
2108 "AHCI %02x%02x.%02x%02x "
2109 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2110 ,
2111
2112 (vers >> 24) & 0xff,
2113 (vers >> 16) & 0xff,
2114 (vers >> 8) & 0xff,
2115 vers & 0xff,
2116
2117 ((cap >> 8) & 0x1f) + 1,
2118 (cap & 0x1f) + 1,
2119 speed_s,
2120 impl,
2121 scc_s);
2122
2123 dev_printk(KERN_INFO, &pdev->dev,
2124 "flags: "
2125 "%s%s%s%s%s%s%s"
2126 "%s%s%s%s%s%s%s\n"
2127 ,
2128
2129 cap & (1 << 31) ? "64bit " : "",
2130 cap & (1 << 30) ? "ncq " : "",
2131 cap & (1 << 29) ? "sntf " : "",
2132 cap & (1 << 28) ? "ilck " : "",
2133 cap & (1 << 27) ? "stag " : "",
2134 cap & (1 << 26) ? "pm " : "",
2135 cap & (1 << 25) ? "led " : "",
2136
2137 cap & (1 << 24) ? "clo " : "",
2138 cap & (1 << 19) ? "nz " : "",
2139 cap & (1 << 18) ? "only " : "",
2140 cap & (1 << 17) ? "pmp " : "",
2141 cap & (1 << 15) ? "pio " : "",
2142 cap & (1 << 14) ? "slum " : "",
2143 cap & (1 << 13) ? "part " : ""
2144 );
2145 }
2146
2147 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2148 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2149 * support PMP and the 4726 either directly exports the device
2150 * attached to the first downstream port or acts as a hardware storage
2151 * controller and emulate a single ATA device (can be RAID 0/1 or some
2152 * other configuration).
2153 *
2154 * When there's no device attached to the first downstream port of the
2155 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2156 * configure the 4726. However, ATA emulation of the device is very
2157 * lame. It doesn't send signature D2H Reg FIS after the initial
2158 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2159 *
2160 * The following function works around the problem by always using
2161 * hardreset on the port and not depending on receiving signature FIS
2162 * afterward. If signature FIS isn't received soon, ATA class is
2163 * assumed without follow-up softreset.
2164 */
2165 static void ahci_p5wdh_workaround(struct ata_host *host)
2166 {
2167 static struct dmi_system_id sysids[] = {
2168 {
2169 .ident = "P5W DH Deluxe",
2170 .matches = {
2171 DMI_MATCH(DMI_SYS_VENDOR,
2172 "ASUSTEK COMPUTER INC"),
2173 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2174 },
2175 },
2176 { }
2177 };
2178 struct pci_dev *pdev = to_pci_dev(host->dev);
2179
2180 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2181 dmi_check_system(sysids)) {
2182 struct ata_port *ap = host->ports[1];
2183
2184 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2185 "Deluxe on-board SIMG4726 workaround\n");
2186
2187 ap->ops = &ahci_p5wdh_ops;
2188 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2189 }
2190 }
2191
2192 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2193 {
2194 static int printed_version;
2195 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2196 const struct ata_port_info *ppi[] = { &pi, NULL };
2197 struct device *dev = &pdev->dev;
2198 struct ahci_host_priv *hpriv;
2199 struct ata_host *host;
2200 int n_ports, i, rc;
2201
2202 VPRINTK("ENTER\n");
2203
2204 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2205
2206 if (!printed_version++)
2207 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2208
2209 /* acquire resources */
2210 rc = pcim_enable_device(pdev);
2211 if (rc)
2212 return rc;
2213
2214 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2215 if (rc == -EBUSY)
2216 pcim_pin_device(pdev);
2217 if (rc)
2218 return rc;
2219
2220 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2221 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2222 u8 map;
2223
2224 /* ICH6s share the same PCI ID for both piix and ahci
2225 * modes. Enabling ahci mode while MAP indicates
2226 * combined mode is a bad idea. Yield to ata_piix.
2227 */
2228 pci_read_config_byte(pdev, ICH_MAP, &map);
2229 if (map & 0x3) {
2230 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2231 "combined mode, can't enable AHCI mode\n");
2232 return -ENODEV;
2233 }
2234 }
2235
2236 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2237 if (!hpriv)
2238 return -ENOMEM;
2239 hpriv->flags |= (unsigned long)pi.private_data;
2240
2241 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2242 pci_intx(pdev, 1);
2243
2244 /* save initial config */
2245 ahci_save_initial_config(pdev, hpriv);
2246
2247 /* prepare host */
2248 if (hpriv->cap & HOST_CAP_NCQ)
2249 pi.flags |= ATA_FLAG_NCQ;
2250
2251 if (hpriv->cap & HOST_CAP_PMP)
2252 pi.flags |= ATA_FLAG_PMP;
2253
2254 /* CAP.NP sometimes indicate the index of the last enabled
2255 * port, at other times, that of the last possible port, so
2256 * determining the maximum port number requires looking at
2257 * both CAP.NP and port_map.
2258 */
2259 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2260
2261 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2262 if (!host)
2263 return -ENOMEM;
2264 host->iomap = pcim_iomap_table(pdev);
2265 host->private_data = hpriv;
2266
2267 for (i = 0; i < host->n_ports; i++) {
2268 struct ata_port *ap = host->ports[i];
2269 void __iomem *port_mmio = ahci_port_base(ap);
2270
2271 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2272 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2273 0x100 + ap->port_no * 0x80, "port");
2274
2275 /* set initial link pm policy */
2276 ap->pm_policy = NOT_AVAILABLE;
2277
2278 /* standard SATA port setup */
2279 if (hpriv->port_map & (1 << i))
2280 ap->ioaddr.cmd_addr = port_mmio;
2281
2282 /* disabled/not-implemented port */
2283 else
2284 ap->ops = &ata_dummy_port_ops;
2285 }
2286
2287 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2288 ahci_p5wdh_workaround(host);
2289
2290 /* initialize adapter */
2291 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2292 if (rc)
2293 return rc;
2294
2295 rc = ahci_reset_controller(host);
2296 if (rc)
2297 return rc;
2298
2299 ahci_init_controller(host);
2300 ahci_print_info(host);
2301
2302 pci_set_master(pdev);
2303 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2304 &ahci_sht);
2305 }
2306
2307 static int __init ahci_init(void)
2308 {
2309 return pci_register_driver(&ahci_pci_driver);
2310 }
2311
2312 static void __exit ahci_exit(void)
2313 {
2314 pci_unregister_driver(&ahci_pci_driver);
2315 }
2316
2317
2318 MODULE_AUTHOR("Jeff Garzik");
2319 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2320 MODULE_LICENSE("GPL");
2321 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2322 MODULE_VERSION(DRV_VERSION);
2323
2324 module_init(ahci_init);
2325 module_exit(ahci_exit);
Linux 2.6 libata-dev (mirror)