2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.16"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg
=
86 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
87 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
90 static int debug
= -1; /* defaults above */
91 module_param(debug
, int, 0);
92 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly
= 128;
95 module_param(copybreak
, int, 0);
96 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
98 static int disable_msi
= 0;
99 module_param(disable_msi
, int, 0);
100 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
102 static int idle_timeout
= 100;
103 module_param(idle_timeout
, int, 0);
104 MODULE_PARM_DESC(idle_timeout
, "Watchdog timer for lost interrupts (ms)");
106 static const struct pci_device_id sky2_id_table
[] = {
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
108 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
112 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
140 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
142 /* Avoid conditionals by using array */
143 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
144 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
145 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
147 /* This driver supports yukon2 chipset only */
148 static const char *yukon2_name
[] = {
150 "EC Ultra", /* 0xb4 */
151 "Extreme", /* 0xb5 */
156 /* Access to external PHY */
157 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
161 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
162 gma_write16(hw
, port
, GM_SMI_CTRL
,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
165 for (i
= 0; i
< PHY_RETRIES
; i
++) {
166 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
171 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
175 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
179 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
180 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
182 for (i
= 0; i
< PHY_RETRIES
; i
++) {
183 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
184 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
194 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
198 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
199 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
204 static void sky2_power_on(struct sky2_hw
*hw
)
206 /* switch power to VCC (WA for VAUX problem) */
207 sky2_write8(hw
, B0_POWER_CTRL
,
208 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
210 /* disable Core Clock Division, */
211 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
213 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
214 /* enable bits are inverted */
215 sky2_write8(hw
, B2_Y2_CLK_GATE
,
216 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
217 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
218 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
220 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
222 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
225 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
226 /* set all bits to 0 except bits 15..12 and 8 */
227 reg
&= P_ASPM_CONTROL_MSK
;
228 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
230 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
231 /* set all bits to 0 except bits 28 & 27 */
232 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
233 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
235 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
237 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
238 reg
= sky2_read32(hw
, B2_GP_IO
);
239 reg
|= GLB_GPIO_STAT_RACE_DIS
;
240 sky2_write32(hw
, B2_GP_IO
, reg
);
244 static void sky2_power_aux(struct sky2_hw
*hw
)
246 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
247 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
249 /* enable bits are inverted */
250 sky2_write8(hw
, B2_Y2_CLK_GATE
,
251 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
252 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
253 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
255 /* switch power to VAUX */
256 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
257 sky2_write8(hw
, B0_POWER_CTRL
,
258 (PC_VAUX_ENA
| PC_VCC_ENA
|
259 PC_VAUX_ON
| PC_VCC_OFF
));
262 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
266 /* disable all GMAC IRQ's */
267 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
268 /* disable PHY IRQs */
269 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
271 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
272 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
273 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
274 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
276 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
277 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
278 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
281 /* flow control to advertise bits */
282 static const u16 copper_fc_adv
[] = {
284 [FC_TX
] = PHY_M_AN_ASP
,
285 [FC_RX
] = PHY_M_AN_PC
,
286 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
289 /* flow control to advertise bits when using 1000BaseX */
290 static const u16 fiber_fc_adv
[] = {
291 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
292 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
293 [FC_RX
] = PHY_M_P_SYM_MD_X
,
294 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
297 /* flow control to GMA disable bits */
298 static const u16 gm_fc_disable
[] = {
299 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
300 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
301 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
306 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
308 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
309 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
311 if (sky2
->autoneg
== AUTONEG_ENABLE
312 && !(hw
->chip_id
== CHIP_ID_YUKON_XL
313 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
314 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
315 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
317 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
319 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
321 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
322 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
323 /* set downshift counter to 3x and enable downshift */
324 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
326 /* set master & slave downshift counter to 1x */
327 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
329 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
332 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
333 if (sky2_is_copper(hw
)) {
334 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
335 /* enable automatic crossover */
336 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
338 /* disable energy detect */
339 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
341 /* enable automatic crossover */
342 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
344 /* downshift on PHY 88E1112 and 88E1149 is changed */
345 if (sky2
->autoneg
== AUTONEG_ENABLE
346 && (hw
->chip_id
== CHIP_ID_YUKON_XL
347 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
348 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
349 /* set downshift counter to 3x and enable downshift */
350 ctrl
&= ~PHY_M_PC_DSC_MSK
;
351 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
355 /* workaround for deviation #4.88 (CRC errors) */
356 /* disable Automatic Crossover */
358 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
361 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
363 /* special setup for PHY 88E1112 Fiber */
364 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& !sky2_is_copper(hw
)) {
365 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
367 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
368 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
369 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
370 ctrl
&= ~PHY_M_MAC_MD_MSK
;
371 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
372 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
374 if (hw
->pmd_type
== 'P') {
375 /* select page 1 to access Fiber registers */
376 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
378 /* for SFP-module set SIGDET polarity to low */
379 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
380 ctrl
|= PHY_M_FIB_SIGD_POL
;
381 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
384 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
392 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
393 if (sky2_is_copper(hw
)) {
394 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
395 ct1000
|= PHY_M_1000C_AFD
;
396 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
397 ct1000
|= PHY_M_1000C_AHD
;
398 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
399 adv
|= PHY_M_AN_100_FD
;
400 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
401 adv
|= PHY_M_AN_100_HD
;
402 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
403 adv
|= PHY_M_AN_10_FD
;
404 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
405 adv
|= PHY_M_AN_10_HD
;
407 adv
|= copper_fc_adv
[sky2
->flow_mode
];
408 } else { /* special defines for FIBER (88E1040S only) */
409 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
410 adv
|= PHY_M_AN_1000X_AFD
;
411 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
412 adv
|= PHY_M_AN_1000X_AHD
;
414 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
417 /* Restart Auto-negotiation */
418 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
420 /* forced speed/duplex settings */
421 ct1000
= PHY_M_1000C_MSE
;
423 /* Disable auto update for duplex flow control and speed */
424 reg
|= GM_GPCR_AU_ALL_DIS
;
426 switch (sky2
->speed
) {
428 ctrl
|= PHY_CT_SP1000
;
429 reg
|= GM_GPCR_SPEED_1000
;
432 ctrl
|= PHY_CT_SP100
;
433 reg
|= GM_GPCR_SPEED_100
;
437 if (sky2
->duplex
== DUPLEX_FULL
) {
438 reg
|= GM_GPCR_DUP_FULL
;
439 ctrl
|= PHY_CT_DUP_MD
;
440 } else if (sky2
->speed
< SPEED_1000
)
441 sky2
->flow_mode
= FC_NONE
;
444 reg
|= gm_fc_disable
[sky2
->flow_mode
];
446 /* Forward pause packets to GMAC? */
447 if (sky2
->flow_mode
& FC_RX
)
448 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
450 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
453 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
455 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
456 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
458 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
459 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
461 /* Setup Phy LED's */
462 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
465 switch (hw
->chip_id
) {
466 case CHIP_ID_YUKON_FE
:
467 /* on 88E3082 these bits are at 11..9 (shifted left) */
468 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
470 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
472 /* delete ACT LED control bits */
473 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
474 /* change ACT LED control to blink mode */
475 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
476 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
479 case CHIP_ID_YUKON_XL
:
480 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
482 /* select page 3 to access LED control register */
483 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
485 /* set LED Function Control register */
486 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
487 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
488 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
489 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
490 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
492 /* set Polarity Control register */
493 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
494 (PHY_M_POLC_LS1_P_MIX(4) |
495 PHY_M_POLC_IS0_P_MIX(4) |
496 PHY_M_POLC_LOS_CTRL(2) |
497 PHY_M_POLC_INIT_CTRL(2) |
498 PHY_M_POLC_STA1_CTRL(2) |
499 PHY_M_POLC_STA0_CTRL(2)));
501 /* restore page register */
502 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
505 case CHIP_ID_YUKON_EC_U
:
506 case CHIP_ID_YUKON_EX
:
507 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
509 /* select page 3 to access LED control register */
510 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
512 /* set LED Function Control register */
513 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
514 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
515 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
516 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
517 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
519 /* set Blink Rate in LED Timer Control Register */
520 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
521 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
522 /* restore page register */
523 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
527 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
528 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
529 /* turn off the Rx LED (LED_RX) */
530 ledover
&= ~PHY_M_LED_MO_RX
;
533 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
534 hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
) {
535 /* apply fixes in PHY AFE */
536 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
538 /* increase differential signal amplitude in 10BASE-T */
539 gm_phy_write(hw
, port
, 0x18, 0xaa99);
540 gm_phy_write(hw
, port
, 0x17, 0x2011);
542 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
543 gm_phy_write(hw
, port
, 0x18, 0xa204);
544 gm_phy_write(hw
, port
, 0x17, 0x2002);
546 /* set page register to 0 */
547 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
548 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
549 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
551 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
552 /* turn on 100 Mbps LED (LED_LINK100) */
553 ledover
|= PHY_M_LED_MO_100
;
557 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
561 /* Enable phy interrupt on auto-negotiation complete (or link up) */
562 if (sky2
->autoneg
== AUTONEG_ENABLE
)
563 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
565 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
568 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
571 static const u32 phy_power
[]
572 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
574 /* looks like this XL is back asswards .. */
575 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
578 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
579 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
581 /* Turn off phy power saving */
582 reg1
&= ~phy_power
[port
];
584 reg1
|= phy_power
[port
];
586 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
587 sky2_pci_read32(hw
, PCI_DEV_REG1
);
588 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
592 /* Force a renegotiation */
593 static void sky2_phy_reinit(struct sky2_port
*sky2
)
595 spin_lock_bh(&sky2
->phy_lock
);
596 sky2_phy_init(sky2
->hw
, sky2
->port
);
597 spin_unlock_bh(&sky2
->phy_lock
);
600 /* Put device in state to listen for Wake On Lan */
601 static void sky2_wol_init(struct sky2_port
*sky2
)
603 struct sky2_hw
*hw
= sky2
->hw
;
604 unsigned port
= sky2
->port
;
605 enum flow_control save_mode
;
609 /* Bring hardware out of reset */
610 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
611 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
613 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
614 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
617 * sky2_reset will re-enable on resume
619 save_mode
= sky2
->flow_mode
;
620 ctrl
= sky2
->advertising
;
622 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
623 sky2
->flow_mode
= FC_NONE
;
624 sky2_phy_power(hw
, port
, 1);
625 sky2_phy_reinit(sky2
);
627 sky2
->flow_mode
= save_mode
;
628 sky2
->advertising
= ctrl
;
630 /* Set GMAC to no flow control and auto update for speed/duplex */
631 gma_write16(hw
, port
, GM_GP_CTRL
,
632 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
633 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
635 /* Set WOL address */
636 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
637 sky2
->netdev
->dev_addr
, ETH_ALEN
);
639 /* Turn on appropriate WOL control bits */
640 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
642 if (sky2
->wol
& WAKE_PHY
)
643 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
645 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
647 if (sky2
->wol
& WAKE_MAGIC
)
648 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
650 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
652 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
653 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
655 /* Turn on legacy PCI-Express PME mode */
656 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
657 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
658 reg1
|= PCI_Y2_PME_LEGACY
;
659 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
660 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
663 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
667 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
669 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
!= CHIP_REV_YU_EX_A0
) {
670 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
672 (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) ? TX_JUMBO_ENA
: TX_JUMBO_DIS
);
674 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
675 /* set Tx GMAC FIFO Almost Empty Threshold */
676 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
677 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
679 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
680 TX_JUMBO_ENA
| TX_STFW_DIS
);
682 /* Can't do offload because of lack of store/forward */
683 hw
->dev
[port
]->features
&= ~(NETIF_F_TSO
| NETIF_F_SG
686 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
687 TX_JUMBO_DIS
| TX_STFW_ENA
);
691 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
693 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
697 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
699 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
700 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
702 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
704 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
705 /* WA DEV_472 -- looks like crossed wires on port 2 */
706 /* clear GMAC 1 Control reset */
707 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
709 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
710 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
711 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
712 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
713 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
716 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
718 /* Enable Transmit FIFO Underrun */
719 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
721 spin_lock_bh(&sky2
->phy_lock
);
722 sky2_phy_init(hw
, port
);
723 spin_unlock_bh(&sky2
->phy_lock
);
726 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
727 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
729 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
730 gma_read16(hw
, port
, i
);
731 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
733 /* transmit control */
734 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
736 /* receive control reg: unicast + multicast + no FCS */
737 gma_write16(hw
, port
, GM_RX_CTRL
,
738 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
740 /* transmit flow control */
741 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
743 /* transmit parameter */
744 gma_write16(hw
, port
, GM_TX_PARAM
,
745 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
746 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
747 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
748 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
750 /* serial mode register */
751 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
752 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
754 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
755 reg
|= GM_SMOD_JUMBO_ENA
;
757 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
759 /* virtual address for data */
760 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
762 /* physical address: used for pause frames */
763 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
765 /* ignore counter overflows */
766 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
767 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
768 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
770 /* Configure Rx MAC FIFO */
771 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
772 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
773 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
774 rx_reg
|= GMF_RX_OVER_ON
;
776 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
778 /* Flush Rx MAC FIFO on any flow control or error */
779 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
781 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
782 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
784 /* Configure Tx MAC FIFO */
785 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
786 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
788 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
789 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
790 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
792 sky2_set_tx_stfwd(hw
, port
);
797 /* Assign Ram Buffer allocation to queue */
798 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
802 /* convert from K bytes to qwords used for hw register */
805 end
= start
+ space
- 1;
807 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
808 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
809 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
810 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
811 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
813 if (q
== Q_R1
|| q
== Q_R2
) {
814 u32 tp
= space
- space
/4;
816 /* On receive queue's set the thresholds
817 * give receiver priority when > 3/4 full
818 * send pause when down to 2K
820 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
821 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
824 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
825 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
827 /* Enable store & forward on Tx queue's because
828 * Tx FIFO is only 1K on Yukon
830 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
833 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
834 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
837 /* Setup Bus Memory Interface */
838 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
840 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
841 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
842 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
843 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
846 /* Setup prefetch unit registers. This is the interface between
847 * hardware and driver list elements
849 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
852 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
853 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
854 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
855 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
856 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
857 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
859 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
862 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
864 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
866 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
871 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
872 struct sky2_tx_le
*le
)
874 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
877 /* Update chip's next pointer */
878 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
880 /* Make sure write' to descriptors are complete before we tell hardware */
882 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
884 /* Synchronize I/O on since next processor may write to tail */
889 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
891 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
892 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
897 /* Build description to hardware for one receive segment */
898 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
899 dma_addr_t map
, unsigned len
)
901 struct sky2_rx_le
*le
;
902 u32 hi
= upper_32_bits(map
);
904 if (sky2
->rx_addr64
!= hi
) {
905 le
= sky2_next_rx(sky2
);
906 le
->addr
= cpu_to_le32(hi
);
907 le
->opcode
= OP_ADDR64
| HW_OWNER
;
908 sky2
->rx_addr64
= upper_32_bits(map
+ len
);
911 le
= sky2_next_rx(sky2
);
912 le
->addr
= cpu_to_le32((u32
) map
);
913 le
->length
= cpu_to_le16(len
);
914 le
->opcode
= op
| HW_OWNER
;
917 /* Build description to hardware for one possibly fragmented skb */
918 static void sky2_rx_submit(struct sky2_port
*sky2
,
919 const struct rx_ring_info
*re
)
923 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
925 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
926 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
930 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
933 struct sk_buff
*skb
= re
->skb
;
936 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
937 pci_unmap_len_set(re
, data_size
, size
);
939 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
940 re
->frag_addr
[i
] = pci_map_page(pdev
,
941 skb_shinfo(skb
)->frags
[i
].page
,
942 skb_shinfo(skb
)->frags
[i
].page_offset
,
943 skb_shinfo(skb
)->frags
[i
].size
,
947 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
949 struct sk_buff
*skb
= re
->skb
;
952 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
955 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
956 pci_unmap_page(pdev
, re
->frag_addr
[i
],
957 skb_shinfo(skb
)->frags
[i
].size
,
961 /* Tell chip where to start receive checksum.
962 * Actually has two checksums, but set both same to avoid possible byte
965 static void rx_set_checksum(struct sky2_port
*sky2
)
967 struct sky2_rx_le
*le
;
969 if (sky2
->hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
970 le
= sky2_next_rx(sky2
);
971 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
973 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
975 sky2_write32(sky2
->hw
,
976 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
977 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
983 * The RX Stop command will not work for Yukon-2 if the BMU does not
984 * reach the end of packet and since we can't make sure that we have
985 * incoming data, we must reset the BMU while it is not doing a DMA
986 * transfer. Since it is possible that the RX path is still active,
987 * the RX RAM buffer will be stopped first, so any possible incoming
988 * data will not trigger a DMA. After the RAM buffer is stopped, the
989 * BMU is polled until any DMA in progress is ended and only then it
992 static void sky2_rx_stop(struct sky2_port
*sky2
)
994 struct sky2_hw
*hw
= sky2
->hw
;
995 unsigned rxq
= rxqaddr
[sky2
->port
];
998 /* disable the RAM Buffer receive queue */
999 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1001 for (i
= 0; i
< 0xffff; i
++)
1002 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1003 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1006 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
1007 sky2
->netdev
->name
);
1009 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1011 /* reset the Rx prefetch unit */
1012 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1016 /* Clean out receive buffer area, assumes receiver hardware stopped */
1017 static void sky2_rx_clean(struct sky2_port
*sky2
)
1021 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1022 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1023 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1026 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1033 /* Basic MII support */
1034 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1036 struct mii_ioctl_data
*data
= if_mii(ifr
);
1037 struct sky2_port
*sky2
= netdev_priv(dev
);
1038 struct sky2_hw
*hw
= sky2
->hw
;
1039 int err
= -EOPNOTSUPP
;
1041 if (!netif_running(dev
))
1042 return -ENODEV
; /* Phy still in reset */
1046 data
->phy_id
= PHY_ADDR_MARV
;
1052 spin_lock_bh(&sky2
->phy_lock
);
1053 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1054 spin_unlock_bh(&sky2
->phy_lock
);
1056 data
->val_out
= val
;
1061 if (!capable(CAP_NET_ADMIN
))
1064 spin_lock_bh(&sky2
->phy_lock
);
1065 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1067 spin_unlock_bh(&sky2
->phy_lock
);
1073 #ifdef SKY2_VLAN_TAG_USED
1074 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1076 struct sky2_port
*sky2
= netdev_priv(dev
);
1077 struct sky2_hw
*hw
= sky2
->hw
;
1078 u16 port
= sky2
->port
;
1080 netif_tx_lock_bh(dev
);
1081 netif_poll_disable(sky2
->hw
->dev
[0]);
1085 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1087 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1090 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1092 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1096 netif_poll_enable(sky2
->hw
->dev
[0]);
1097 netif_tx_unlock_bh(dev
);
1102 * Allocate an skb for receiving. If the MTU is large enough
1103 * make the skb non-linear with a fragment list of pages.
1105 * It appears the hardware has a bug in the FIFO logic that
1106 * cause it to hang if the FIFO gets overrun and the receive buffer
1107 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1108 * aligned except if slab debugging is enabled.
1110 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1112 struct sk_buff
*skb
;
1116 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ RX_SKB_ALIGN
);
1120 p
= (unsigned long) skb
->data
;
1121 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
1123 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1124 struct page
*page
= alloc_page(GFP_ATOMIC
);
1128 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1138 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1140 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1144 * Allocate and setup receiver buffer pool.
1145 * Normal case this ends up creating one list element for skb
1146 * in the receive ring. Worst case if using large MTU and each
1147 * allocation falls on a different 64 bit region, that results
1148 * in 6 list elements per ring entry.
1149 * One element is used for checksum enable/disable, and one
1150 * extra to avoid wrap.
1152 static int sky2_rx_start(struct sky2_port
*sky2
)
1154 struct sky2_hw
*hw
= sky2
->hw
;
1155 struct rx_ring_info
*re
;
1156 unsigned rxq
= rxqaddr
[sky2
->port
];
1157 unsigned i
, size
, space
, thresh
;
1159 sky2
->rx_put
= sky2
->rx_next
= 0;
1162 /* On PCI express lowering the watermark gives better performance */
1163 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1164 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1166 /* These chips have no ram buffer?
1167 * MAC Rx RAM Read is controlled by hardware */
1168 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1169 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1170 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1171 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1173 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1175 rx_set_checksum(sky2
);
1177 /* Space needed for frame data + headers rounded up */
1178 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1180 /* Stopping point for hardware truncation */
1181 thresh
= (size
- 8) / sizeof(u32
);
1183 /* Account for overhead of skb - to avoid order > 0 allocation */
1184 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1185 + sizeof(struct skb_shared_info
);
1187 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1188 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1190 if (sky2
->rx_nfrags
!= 0) {
1191 /* Compute residue after pages */
1192 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1199 /* Optimize to handle small packets and headers */
1200 if (size
< copybreak
)
1202 if (size
< ETH_HLEN
)
1205 sky2
->rx_data_size
= size
;
1208 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1209 re
= sky2
->rx_ring
+ i
;
1211 re
->skb
= sky2_rx_alloc(sky2
);
1215 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1216 sky2_rx_submit(sky2
, re
);
1220 * The receiver hangs if it receives frames larger than the
1221 * packet buffer. As a workaround, truncate oversize frames, but
1222 * the register is limited to 9 bits, so if you do frames > 2052
1223 * you better get the MTU right!
1226 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1228 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1229 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1232 /* Tell chip about available buffers */
1233 sky2_rx_update(sky2
, rxq
);
1236 sky2_rx_clean(sky2
);
1240 /* Bring up network interface. */
1241 static int sky2_up(struct net_device
*dev
)
1243 struct sky2_port
*sky2
= netdev_priv(dev
);
1244 struct sky2_hw
*hw
= sky2
->hw
;
1245 unsigned port
= sky2
->port
;
1247 int cap
, err
= -ENOMEM
;
1248 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1251 * On dual port PCI-X card, there is an problem where status
1252 * can be received out of order due to split transactions
1254 if (otherdev
&& netif_running(otherdev
) &&
1255 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1256 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1259 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1260 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1261 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1267 if (netif_msg_ifup(sky2
))
1268 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1270 netif_carrier_off(dev
);
1272 /* must be power of 2 */
1273 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1275 sizeof(struct sky2_tx_le
),
1280 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1284 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1286 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1290 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1292 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1297 sky2_phy_power(hw
, port
, 1);
1299 sky2_mac_init(hw
, port
);
1301 /* Register is number of 4K blocks on internal RAM buffer. */
1302 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1303 printk(KERN_INFO PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1309 rxspace
= ramsize
/ 2;
1311 rxspace
= 8 + (2*(ramsize
- 16))/3;
1313 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1314 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1316 /* Make sure SyncQ is disabled */
1317 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1321 sky2_qset(hw
, txqaddr
[port
]);
1323 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1324 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1325 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1327 /* Set almost empty threshold */
1328 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1329 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1330 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1332 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1335 err
= sky2_rx_start(sky2
);
1339 /* Enable interrupts from phy/mac for port */
1340 imask
= sky2_read32(hw
, B0_IMSK
);
1341 imask
|= portirq_msk
[port
];
1342 sky2_write32(hw
, B0_IMSK
, imask
);
1348 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1349 sky2
->rx_le
, sky2
->rx_le_map
);
1353 pci_free_consistent(hw
->pdev
,
1354 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1355 sky2
->tx_le
, sky2
->tx_le_map
);
1358 kfree(sky2
->tx_ring
);
1359 kfree(sky2
->rx_ring
);
1361 sky2
->tx_ring
= NULL
;
1362 sky2
->rx_ring
= NULL
;
1366 /* Modular subtraction in ring */
1367 static inline int tx_dist(unsigned tail
, unsigned head
)
1369 return (head
- tail
) & (TX_RING_SIZE
- 1);
1372 /* Number of list elements available for next tx */
1373 static inline int tx_avail(const struct sky2_port
*sky2
)
1375 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1378 /* Estimate of number of transmit list elements required */
1379 static unsigned tx_le_req(const struct sk_buff
*skb
)
1383 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1384 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1386 if (skb_is_gso(skb
))
1389 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1396 * Put one packet in ring for transmit.
1397 * A single packet can generate multiple list elements, and
1398 * the number of ring elements will probably be less than the number
1399 * of list elements used.
1401 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1403 struct sky2_port
*sky2
= netdev_priv(dev
);
1404 struct sky2_hw
*hw
= sky2
->hw
;
1405 struct sky2_tx_le
*le
= NULL
;
1406 struct tx_ring_info
*re
;
1413 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1414 return NETDEV_TX_BUSY
;
1416 if (unlikely(netif_msg_tx_queued(sky2
)))
1417 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1418 dev
->name
, sky2
->tx_prod
, skb
->len
);
1420 len
= skb_headlen(skb
);
1421 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1422 addr64
= upper_32_bits(mapping
);
1424 /* Send high bits if changed or crosses boundary */
1425 if (addr64
!= sky2
->tx_addr64
||
1426 upper_32_bits(mapping
+ len
) != sky2
->tx_addr64
) {
1427 le
= get_tx_le(sky2
);
1428 le
->addr
= cpu_to_le32(addr64
);
1429 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1430 sky2
->tx_addr64
= upper_32_bits(mapping
+ len
);
1433 /* Check for TCP Segmentation Offload */
1434 mss
= skb_shinfo(skb
)->gso_size
;
1436 if (hw
->chip_id
!= CHIP_ID_YUKON_EX
)
1437 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1439 if (mss
!= sky2
->tx_last_mss
) {
1440 le
= get_tx_le(sky2
);
1441 le
->addr
= cpu_to_le32(mss
);
1442 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
1443 le
->opcode
= OP_MSS
| HW_OWNER
;
1445 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1446 sky2
->tx_last_mss
= mss
;
1451 #ifdef SKY2_VLAN_TAG_USED
1452 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1453 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1455 le
= get_tx_le(sky2
);
1457 le
->opcode
= OP_VLAN
|HW_OWNER
;
1459 le
->opcode
|= OP_VLAN
;
1460 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1465 /* Handle TCP checksum offload */
1466 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1467 /* On Yukon EX (some versions) encoding change. */
1468 if (hw
->chip_id
== CHIP_ID_YUKON_EX
1469 && hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
1470 ctrl
|= CALSUM
; /* auto checksum */
1472 const unsigned offset
= skb_transport_offset(skb
);
1475 tcpsum
= offset
<< 16; /* sum start */
1476 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1478 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1479 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1482 if (tcpsum
!= sky2
->tx_tcpsum
) {
1483 sky2
->tx_tcpsum
= tcpsum
;
1485 le
= get_tx_le(sky2
);
1486 le
->addr
= cpu_to_le32(tcpsum
);
1487 le
->length
= 0; /* initial checksum value */
1488 le
->ctrl
= 1; /* one packet */
1489 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1494 le
= get_tx_le(sky2
);
1495 le
->addr
= cpu_to_le32((u32
) mapping
);
1496 le
->length
= cpu_to_le16(len
);
1498 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1500 re
= tx_le_re(sky2
, le
);
1502 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1503 pci_unmap_len_set(re
, maplen
, len
);
1505 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1506 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1508 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1509 frag
->size
, PCI_DMA_TODEVICE
);
1510 addr64
= upper_32_bits(mapping
);
1511 if (addr64
!= sky2
->tx_addr64
) {
1512 le
= get_tx_le(sky2
);
1513 le
->addr
= cpu_to_le32(addr64
);
1515 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1516 sky2
->tx_addr64
= addr64
;
1519 le
= get_tx_le(sky2
);
1520 le
->addr
= cpu_to_le32((u32
) mapping
);
1521 le
->length
= cpu_to_le16(frag
->size
);
1523 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1525 re
= tx_le_re(sky2
, le
);
1527 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1528 pci_unmap_len_set(re
, maplen
, frag
->size
);
1533 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1534 netif_stop_queue(dev
);
1536 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1538 dev
->trans_start
= jiffies
;
1539 return NETDEV_TX_OK
;
1543 * Free ring elements from starting at tx_cons until "done"
1545 * NB: the hardware will tell us about partial completion of multi-part
1546 * buffers so make sure not to free skb to early.
1548 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1550 struct net_device
*dev
= sky2
->netdev
;
1551 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1554 BUG_ON(done
>= TX_RING_SIZE
);
1556 for (idx
= sky2
->tx_cons
; idx
!= done
;
1557 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1558 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1559 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1561 switch(le
->opcode
& ~HW_OWNER
) {
1564 pci_unmap_single(pdev
,
1565 pci_unmap_addr(re
, mapaddr
),
1566 pci_unmap_len(re
, maplen
),
1570 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1571 pci_unmap_len(re
, maplen
),
1576 if (le
->ctrl
& EOP
) {
1577 if (unlikely(netif_msg_tx_done(sky2
)))
1578 printk(KERN_DEBUG
"%s: tx done %u\n",
1581 sky2
->net_stats
.tx_packets
++;
1582 sky2
->net_stats
.tx_bytes
+= re
->skb
->len
;
1584 dev_kfree_skb_any(re
->skb
);
1585 sky2
->tx_next
= RING_NEXT(idx
, TX_RING_SIZE
);
1589 sky2
->tx_cons
= idx
;
1592 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1593 netif_wake_queue(dev
);
1596 /* Cleanup all untransmitted buffers, assume transmitter not running */
1597 static void sky2_tx_clean(struct net_device
*dev
)
1599 struct sky2_port
*sky2
= netdev_priv(dev
);
1601 netif_tx_lock_bh(dev
);
1602 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1603 netif_tx_unlock_bh(dev
);
1606 /* Network shutdown */
1607 static int sky2_down(struct net_device
*dev
)
1609 struct sky2_port
*sky2
= netdev_priv(dev
);
1610 struct sky2_hw
*hw
= sky2
->hw
;
1611 unsigned port
= sky2
->port
;
1615 /* Never really got started! */
1619 if (netif_msg_ifdown(sky2
))
1620 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1622 /* Stop more packets from being queued */
1623 netif_stop_queue(dev
);
1625 /* Disable port IRQ */
1626 imask
= sky2_read32(hw
, B0_IMSK
);
1627 imask
&= ~portirq_msk
[port
];
1628 sky2_write32(hw
, B0_IMSK
, imask
);
1630 sky2_gmac_reset(hw
, port
);
1632 /* Stop transmitter */
1633 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1634 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1636 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1637 RB_RST_SET
| RB_DIS_OP_MD
);
1639 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1640 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1641 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1643 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1645 /* Workaround shared GMAC reset */
1646 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1647 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1648 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1650 /* Disable Force Sync bit and Enable Alloc bit */
1651 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1652 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1654 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1655 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1656 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1658 /* Reset the PCI FIFO of the async Tx queue */
1659 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1660 BMU_RST_SET
| BMU_FIFO_RST
);
1662 /* Reset the Tx prefetch units */
1663 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1666 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1670 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1671 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1673 sky2_phy_power(hw
, port
, 0);
1675 netif_carrier_off(dev
);
1677 /* turn off LED's */
1678 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1680 synchronize_irq(hw
->pdev
->irq
);
1683 sky2_rx_clean(sky2
);
1685 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1686 sky2
->rx_le
, sky2
->rx_le_map
);
1687 kfree(sky2
->rx_ring
);
1689 pci_free_consistent(hw
->pdev
,
1690 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1691 sky2
->tx_le
, sky2
->tx_le_map
);
1692 kfree(sky2
->tx_ring
);
1697 sky2
->rx_ring
= NULL
;
1698 sky2
->tx_ring
= NULL
;
1703 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1705 if (!sky2_is_copper(hw
))
1708 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1709 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1711 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1712 case PHY_M_PS_SPEED_1000
:
1714 case PHY_M_PS_SPEED_100
:
1721 static void sky2_link_up(struct sky2_port
*sky2
)
1723 struct sky2_hw
*hw
= sky2
->hw
;
1724 unsigned port
= sky2
->port
;
1726 static const char *fc_name
[] = {
1734 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1735 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1736 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1738 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1740 netif_carrier_on(sky2
->netdev
);
1742 /* Turn on link LED */
1743 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1744 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1746 if (hw
->chip_id
== CHIP_ID_YUKON_XL
1747 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
1748 || hw
->chip_id
== CHIP_ID_YUKON_EX
) {
1749 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1750 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1752 switch(sky2
->speed
) {
1754 led
|= PHY_M_LEDC_INIT_CTRL(7);
1758 led
|= PHY_M_LEDC_STA1_CTRL(7);
1762 led
|= PHY_M_LEDC_STA0_CTRL(7);
1766 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1767 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1768 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1771 if (netif_msg_link(sky2
))
1772 printk(KERN_INFO PFX
1773 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1774 sky2
->netdev
->name
, sky2
->speed
,
1775 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1776 fc_name
[sky2
->flow_status
]);
1779 static void sky2_link_down(struct sky2_port
*sky2
)
1781 struct sky2_hw
*hw
= sky2
->hw
;
1782 unsigned port
= sky2
->port
;
1785 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1787 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1788 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1789 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1791 netif_carrier_off(sky2
->netdev
);
1793 /* Turn on link LED */
1794 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1796 if (netif_msg_link(sky2
))
1797 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1799 sky2_phy_init(hw
, port
);
1802 static enum flow_control
sky2_flow(int rx
, int tx
)
1805 return tx
? FC_BOTH
: FC_RX
;
1807 return tx
? FC_TX
: FC_NONE
;
1810 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1812 struct sky2_hw
*hw
= sky2
->hw
;
1813 unsigned port
= sky2
->port
;
1816 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1817 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1818 if (lpa
& PHY_M_AN_RF
) {
1819 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1823 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1824 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1825 sky2
->netdev
->name
);
1829 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1830 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1832 /* Since the pause result bits seem to in different positions on
1833 * different chips. look at registers.
1835 if (!sky2_is_copper(hw
)) {
1836 /* Shift for bits in fiber PHY */
1837 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
1838 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
1840 if (advert
& ADVERTISE_1000XPAUSE
)
1841 advert
|= ADVERTISE_PAUSE_CAP
;
1842 if (advert
& ADVERTISE_1000XPSE_ASYM
)
1843 advert
|= ADVERTISE_PAUSE_ASYM
;
1844 if (lpa
& LPA_1000XPAUSE
)
1845 lpa
|= LPA_PAUSE_CAP
;
1846 if (lpa
& LPA_1000XPAUSE_ASYM
)
1847 lpa
|= LPA_PAUSE_ASYM
;
1850 sky2
->flow_status
= FC_NONE
;
1851 if (advert
& ADVERTISE_PAUSE_CAP
) {
1852 if (lpa
& LPA_PAUSE_CAP
)
1853 sky2
->flow_status
= FC_BOTH
;
1854 else if (advert
& ADVERTISE_PAUSE_ASYM
)
1855 sky2
->flow_status
= FC_RX
;
1856 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
1857 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
1858 sky2
->flow_status
= FC_TX
;
1861 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1862 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
1863 sky2
->flow_status
= FC_NONE
;
1865 if (sky2
->flow_status
& FC_TX
)
1866 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1868 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1873 /* Interrupt from PHY */
1874 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1876 struct net_device
*dev
= hw
->dev
[port
];
1877 struct sky2_port
*sky2
= netdev_priv(dev
);
1878 u16 istatus
, phystat
;
1880 if (!netif_running(dev
))
1883 spin_lock(&sky2
->phy_lock
);
1884 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1885 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1887 if (netif_msg_intr(sky2
))
1888 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1889 sky2
->netdev
->name
, istatus
, phystat
);
1891 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1892 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1897 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1898 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1900 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1902 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1904 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1905 if (phystat
& PHY_M_PS_LINK_UP
)
1908 sky2_link_down(sky2
);
1911 spin_unlock(&sky2
->phy_lock
);
1914 /* Transmit timeout is only called if we are running, carrier is up
1915 * and tx queue is full (stopped).
1917 static void sky2_tx_timeout(struct net_device
*dev
)
1919 struct sky2_port
*sky2
= netdev_priv(dev
);
1920 struct sky2_hw
*hw
= sky2
->hw
;
1922 if (netif_msg_timer(sky2
))
1923 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1925 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1926 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
1927 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
1928 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
1930 /* can't restart safely under softirq */
1931 schedule_work(&hw
->restart_work
);
1934 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1936 struct sky2_port
*sky2
= netdev_priv(dev
);
1937 struct sky2_hw
*hw
= sky2
->hw
;
1938 unsigned port
= sky2
->port
;
1943 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1946 if (new_mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_FE
)
1949 if (!netif_running(dev
)) {
1954 imask
= sky2_read32(hw
, B0_IMSK
);
1955 sky2_write32(hw
, B0_IMSK
, 0);
1957 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1958 netif_stop_queue(dev
);
1959 netif_poll_disable(hw
->dev
[0]);
1961 synchronize_irq(hw
->pdev
->irq
);
1963 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
)
1964 sky2_set_tx_stfwd(hw
, port
);
1966 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1967 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1969 sky2_rx_clean(sky2
);
1973 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1974 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1976 if (dev
->mtu
> ETH_DATA_LEN
)
1977 mode
|= GM_SMOD_JUMBO_ENA
;
1979 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
1981 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
1983 err
= sky2_rx_start(sky2
);
1984 sky2_write32(hw
, B0_IMSK
, imask
);
1989 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
1991 netif_poll_enable(hw
->dev
[0]);
1992 netif_wake_queue(dev
);
1998 /* For small just reuse existing skb for next receive */
1999 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2000 const struct rx_ring_info
*re
,
2003 struct sk_buff
*skb
;
2005 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
2007 skb_reserve(skb
, 2);
2008 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2009 length
, PCI_DMA_FROMDEVICE
);
2010 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2011 skb
->ip_summed
= re
->skb
->ip_summed
;
2012 skb
->csum
= re
->skb
->csum
;
2013 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2014 length
, PCI_DMA_FROMDEVICE
);
2015 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2016 skb_put(skb
, length
);
2021 /* Adjust length of skb with fragments to match received data */
2022 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2023 unsigned int length
)
2028 /* put header into skb */
2029 size
= min(length
, hdr_space
);
2034 num_frags
= skb_shinfo(skb
)->nr_frags
;
2035 for (i
= 0; i
< num_frags
; i
++) {
2036 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2039 /* don't need this page */
2040 __free_page(frag
->page
);
2041 --skb_shinfo(skb
)->nr_frags
;
2043 size
= min(length
, (unsigned) PAGE_SIZE
);
2046 skb
->data_len
+= size
;
2047 skb
->truesize
+= size
;
2054 /* Normal packet - take skb from ring element and put in a new one */
2055 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2056 struct rx_ring_info
*re
,
2057 unsigned int length
)
2059 struct sk_buff
*skb
, *nskb
;
2060 unsigned hdr_space
= sky2
->rx_data_size
;
2062 /* Don't be tricky about reusing pages (yet) */
2063 nskb
= sky2_rx_alloc(sky2
);
2064 if (unlikely(!nskb
))
2068 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2070 prefetch(skb
->data
);
2072 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
2074 if (skb_shinfo(skb
)->nr_frags
)
2075 skb_put_frags(skb
, hdr_space
, length
);
2077 skb_put(skb
, length
);
2082 * Receive one packet.
2083 * For larger packets, get new buffer.
2085 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2086 u16 length
, u32 status
)
2088 struct sky2_port
*sky2
= netdev_priv(dev
);
2089 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2090 struct sk_buff
*skb
= NULL
;
2092 if (unlikely(netif_msg_rx_status(sky2
)))
2093 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2094 dev
->name
, sky2
->rx_next
, status
, length
);
2096 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2097 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2099 if (status
& GMR_FS_ANY_ERR
)
2102 if (!(status
& GMR_FS_RX_OK
))
2105 if (status
>> 16 != length
)
2108 if (length
< copybreak
)
2109 skb
= receive_copy(sky2
, re
, length
);
2111 skb
= receive_new(sky2
, re
, length
);
2113 sky2_rx_submit(sky2
, re
);
2118 /* Truncation of overlength packets
2119 causes PHY length to not match MAC length */
2120 ++sky2
->net_stats
.rx_length_errors
;
2123 ++sky2
->net_stats
.rx_errors
;
2124 if (status
& GMR_FS_RX_FF_OV
) {
2125 sky2
->net_stats
.rx_over_errors
++;
2129 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2130 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2131 dev
->name
, status
, length
);
2133 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2134 sky2
->net_stats
.rx_length_errors
++;
2135 if (status
& GMR_FS_FRAGMENT
)
2136 sky2
->net_stats
.rx_frame_errors
++;
2137 if (status
& GMR_FS_CRC_ERR
)
2138 sky2
->net_stats
.rx_crc_errors
++;
2143 /* Transmit complete */
2144 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2146 struct sky2_port
*sky2
= netdev_priv(dev
);
2148 if (netif_running(dev
)) {
2150 sky2_tx_complete(sky2
, last
);
2151 netif_tx_unlock(dev
);
2155 /* Process status response ring */
2156 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
2159 unsigned rx
[2] = { 0, 0 };
2160 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
2164 while (hw
->st_idx
!= hwidx
) {
2165 struct sky2_port
*sky2
;
2166 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2167 unsigned port
= le
->css
& CSS_LINK_BIT
;
2168 struct net_device
*dev
;
2169 struct sk_buff
*skb
;
2173 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2175 dev
= hw
->dev
[port
];
2176 sky2
= netdev_priv(dev
);
2177 length
= le16_to_cpu(le
->length
);
2178 status
= le32_to_cpu(le
->status
);
2180 switch (le
->opcode
& ~HW_OWNER
) {
2183 skb
= sky2_receive(dev
, length
, status
);
2184 if (unlikely(!skb
)) {
2185 sky2
->net_stats
.rx_dropped
++;
2189 /* This chip reports checksum status differently */
2190 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2191 if (sky2
->rx_csum
&&
2192 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2193 (le
->css
& CSS_TCPUDPCSOK
))
2194 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2196 skb
->ip_summed
= CHECKSUM_NONE
;
2199 skb
->protocol
= eth_type_trans(skb
, dev
);
2200 sky2
->net_stats
.rx_packets
++;
2201 sky2
->net_stats
.rx_bytes
+= skb
->len
;
2202 dev
->last_rx
= jiffies
;
2204 #ifdef SKY2_VLAN_TAG_USED
2205 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2206 vlan_hwaccel_receive_skb(skb
,
2208 be16_to_cpu(sky2
->rx_tag
));
2211 netif_receive_skb(skb
);
2213 /* Stop after net poll weight */
2214 if (++work_done
>= to_do
)
2218 #ifdef SKY2_VLAN_TAG_USED
2220 sky2
->rx_tag
= length
;
2224 sky2
->rx_tag
= length
;
2231 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2234 /* Both checksum counters are programmed to start at
2235 * the same offset, so unless there is a problem they
2236 * should match. This failure is an early indication that
2237 * hardware receive checksumming won't work.
2239 if (likely(status
>> 16 == (status
& 0xffff))) {
2240 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2241 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2242 skb
->csum
= status
& 0xffff;
2244 printk(KERN_NOTICE PFX
"%s: hardware receive "
2245 "checksum problem (status = %#x)\n",
2248 sky2_write32(sky2
->hw
,
2249 Q_ADDR(rxqaddr
[port
], Q_CSR
),
2255 /* TX index reports status for both ports */
2256 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2257 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2259 sky2_tx_done(hw
->dev
[1],
2260 ((status
>> 24) & 0xff)
2261 | (u16
)(length
& 0xf) << 8);
2265 if (net_ratelimit())
2266 printk(KERN_WARNING PFX
2267 "unknown status opcode 0x%x\n", le
->opcode
);
2271 /* Fully processed status ring so clear irq */
2272 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2276 sky2_rx_update(netdev_priv(hw
->dev
[0]), Q_R1
);
2279 sky2_rx_update(netdev_priv(hw
->dev
[1]), Q_R2
);
2284 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2286 struct net_device
*dev
= hw
->dev
[port
];
2288 if (net_ratelimit())
2289 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2292 if (status
& Y2_IS_PAR_RD1
) {
2293 if (net_ratelimit())
2294 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2297 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2300 if (status
& Y2_IS_PAR_WR1
) {
2301 if (net_ratelimit())
2302 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2305 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2308 if (status
& Y2_IS_PAR_MAC1
) {
2309 if (net_ratelimit())
2310 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2311 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2314 if (status
& Y2_IS_PAR_RX1
) {
2315 if (net_ratelimit())
2316 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2317 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2320 if (status
& Y2_IS_TCP_TXA1
) {
2321 if (net_ratelimit())
2322 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2324 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2328 static void sky2_hw_intr(struct sky2_hw
*hw
)
2330 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2332 if (status
& Y2_IS_TIST_OV
)
2333 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2335 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2338 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2339 if (net_ratelimit())
2340 dev_err(&hw
->pdev
->dev
, "PCI hardware error (0x%x)\n",
2343 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2344 sky2_pci_write16(hw
, PCI_STATUS
,
2345 pci_err
| PCI_STATUS_ERROR_BITS
);
2346 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2349 if (status
& Y2_IS_PCI_EXP
) {
2350 /* PCI-Express uncorrectable Error occurred */
2353 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2355 if (net_ratelimit())
2356 dev_err(&hw
->pdev
->dev
, "PCI Express error (0x%x)\n",
2359 /* clear the interrupt */
2360 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2361 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2363 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2365 if (pex_err
& PEX_FATAL_ERRORS
) {
2366 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2367 hwmsk
&= ~Y2_IS_PCI_EXP
;
2368 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2372 if (status
& Y2_HWE_L1_MASK
)
2373 sky2_hw_error(hw
, 0, status
);
2375 if (status
& Y2_HWE_L1_MASK
)
2376 sky2_hw_error(hw
, 1, status
);
2379 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2381 struct net_device
*dev
= hw
->dev
[port
];
2382 struct sky2_port
*sky2
= netdev_priv(dev
);
2383 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2385 if (netif_msg_intr(sky2
))
2386 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2389 if (status
& GM_IS_RX_CO_OV
)
2390 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2392 if (status
& GM_IS_TX_CO_OV
)
2393 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2395 if (status
& GM_IS_RX_FF_OR
) {
2396 ++sky2
->net_stats
.rx_fifo_errors
;
2397 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2400 if (status
& GM_IS_TX_FF_UR
) {
2401 ++sky2
->net_stats
.tx_fifo_errors
;
2402 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2406 /* This should never happen it is a bug. */
2407 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
,
2408 u16 q
, unsigned ring_size
)
2410 struct net_device
*dev
= hw
->dev
[port
];
2411 struct sky2_port
*sky2
= netdev_priv(dev
);
2413 const u64
*le
= (q
== Q_R1
|| q
== Q_R2
)
2414 ? (u64
*) sky2
->rx_le
: (u64
*) sky2
->tx_le
;
2416 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2417 printk(KERN_ERR PFX
"%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2418 dev
->name
, (unsigned) q
, idx
, (unsigned long long) le
[idx
],
2419 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2421 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2424 /* If idle then force a fake soft NAPI poll once a second
2425 * to work around cases where sharing an edge triggered interrupt.
2427 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2429 if (idle_timeout
> 0)
2430 mod_timer(&hw
->idle_timer
,
2431 jiffies
+ msecs_to_jiffies(idle_timeout
));
2434 static void sky2_idle(unsigned long arg
)
2436 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2437 struct net_device
*dev
= hw
->dev
[0];
2439 if (__netif_rx_schedule_prep(dev
))
2440 __netif_rx_schedule(dev
);
2442 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2445 /* Hardware/software error handling */
2446 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2448 if (net_ratelimit())
2449 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2451 if (status
& Y2_IS_HW_ERR
)
2454 if (status
& Y2_IS_IRQ_MAC1
)
2455 sky2_mac_intr(hw
, 0);
2457 if (status
& Y2_IS_IRQ_MAC2
)
2458 sky2_mac_intr(hw
, 1);
2460 if (status
& Y2_IS_CHK_RX1
)
2461 sky2_le_error(hw
, 0, Q_R1
, RX_LE_SIZE
);
2463 if (status
& Y2_IS_CHK_RX2
)
2464 sky2_le_error(hw
, 1, Q_R2
, RX_LE_SIZE
);
2466 if (status
& Y2_IS_CHK_TXA1
)
2467 sky2_le_error(hw
, 0, Q_XA1
, TX_RING_SIZE
);
2469 if (status
& Y2_IS_CHK_TXA2
)
2470 sky2_le_error(hw
, 1, Q_XA2
, TX_RING_SIZE
);
2473 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2475 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2477 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2479 if (unlikely(status
& Y2_IS_ERROR
))
2480 sky2_err_intr(hw
, status
);
2482 if (status
& Y2_IS_IRQ_PHY1
)
2483 sky2_phy_intr(hw
, 0);
2485 if (status
& Y2_IS_IRQ_PHY2
)
2486 sky2_phy_intr(hw
, 1);
2488 work_done
= sky2_status_intr(hw
, min(dev0
->quota
, *budget
));
2489 *budget
-= work_done
;
2490 dev0
->quota
-= work_done
;
2493 if (hw
->st_idx
!= sky2_read16(hw
, STAT_PUT_IDX
))
2496 /* Bug/Errata workaround?
2497 * Need to kick the TX irq moderation timer.
2499 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_START
) {
2500 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2501 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2503 netif_rx_complete(dev0
);
2505 sky2_read32(hw
, B0_Y2_SP_LISR
);
2509 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2511 struct sky2_hw
*hw
= dev_id
;
2512 struct net_device
*dev0
= hw
->dev
[0];
2515 /* Reading this mask interrupts as side effect */
2516 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2517 if (status
== 0 || status
== ~0)
2520 prefetch(&hw
->st_le
[hw
->st_idx
]);
2521 if (likely(__netif_rx_schedule_prep(dev0
)))
2522 __netif_rx_schedule(dev0
);
2527 #ifdef CONFIG_NET_POLL_CONTROLLER
2528 static void sky2_netpoll(struct net_device
*dev
)
2530 struct sky2_port
*sky2
= netdev_priv(dev
);
2531 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2533 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2534 __netif_rx_schedule(dev0
);
2538 /* Chip internal frequency for clock calculations */
2539 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2541 switch (hw
->chip_id
) {
2542 case CHIP_ID_YUKON_EC
:
2543 case CHIP_ID_YUKON_EC_U
:
2544 case CHIP_ID_YUKON_EX
:
2545 return 125; /* 125 Mhz */
2546 case CHIP_ID_YUKON_FE
:
2547 return 100; /* 100 Mhz */
2548 default: /* YUKON_XL */
2549 return 156; /* 156 Mhz */
2553 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2555 return sky2_mhz(hw
) * us
;
2558 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2560 return clk
/ sky2_mhz(hw
);
2564 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2568 /* Enable all clocks */
2569 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2571 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2573 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2574 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2575 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2580 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2582 /* This rev is really old, and requires untested workarounds */
2583 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2584 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2585 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2586 hw
->chip_id
, hw
->chip_rev
);
2590 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2592 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2593 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2594 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2601 static void sky2_reset(struct sky2_hw
*hw
)
2607 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2608 status
= sky2_read16(hw
, HCU_CCSR
);
2609 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2610 HCU_CCSR_UC_STATE_MSK
);
2611 sky2_write16(hw
, HCU_CCSR
, status
);
2613 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2614 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2617 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2618 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2620 /* clear PCI errors, if any */
2621 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2623 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2624 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2627 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2629 /* clear any PEX errors */
2630 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2631 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2636 for (i
= 0; i
< hw
->ports
; i
++) {
2637 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2638 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2640 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2641 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
2642 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
2646 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2648 /* Clear I2C IRQ noise */
2649 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2651 /* turn off hardware timer (unused) */
2652 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2653 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2655 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2657 /* Turn off descriptor polling */
2658 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2660 /* Turn off receive timestamp */
2661 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2662 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2664 /* enable the Tx Arbiters */
2665 for (i
= 0; i
< hw
->ports
; i
++)
2666 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2668 /* Initialize ram interface */
2669 for (i
= 0; i
< hw
->ports
; i
++) {
2670 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2672 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2673 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2674 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2675 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2676 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2677 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2678 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2679 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2680 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2681 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2682 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2683 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2686 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2688 for (i
= 0; i
< hw
->ports
; i
++)
2689 sky2_gmac_reset(hw
, i
);
2691 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2694 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2695 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2697 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2698 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2700 /* Set the list last index */
2701 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2703 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2704 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2706 /* set Status-FIFO ISR watermark */
2707 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2708 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2710 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2712 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2713 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2714 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2716 /* enable status unit */
2717 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2719 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2720 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2721 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2724 static void sky2_restart(struct work_struct
*work
)
2726 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
2727 struct net_device
*dev
;
2730 del_timer_sync(&hw
->idle_timer
);
2733 sky2_write32(hw
, B0_IMSK
, 0);
2734 sky2_read32(hw
, B0_IMSK
);
2736 netif_poll_disable(hw
->dev
[0]);
2738 for (i
= 0; i
< hw
->ports
; i
++) {
2740 if (netif_running(dev
))
2745 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
2746 netif_poll_enable(hw
->dev
[0]);
2748 for (i
= 0; i
< hw
->ports
; i
++) {
2750 if (netif_running(dev
)) {
2753 printk(KERN_INFO PFX
"%s: could not restart %d\n",
2760 sky2_idle_start(hw
);
2765 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
2767 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
2770 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2772 const struct sky2_port
*sky2
= netdev_priv(dev
);
2774 wol
->supported
= sky2_wol_supported(sky2
->hw
);
2775 wol
->wolopts
= sky2
->wol
;
2778 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2780 struct sky2_port
*sky2
= netdev_priv(dev
);
2781 struct sky2_hw
*hw
= sky2
->hw
;
2783 if (wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
2786 sky2
->wol
= wol
->wolopts
;
2788 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
)
2789 sky2_write32(hw
, B0_CTST
, sky2
->wol
2790 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
2792 if (!netif_running(dev
))
2793 sky2_wol_init(sky2
);
2797 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2799 if (sky2_is_copper(hw
)) {
2800 u32 modes
= SUPPORTED_10baseT_Half
2801 | SUPPORTED_10baseT_Full
2802 | SUPPORTED_100baseT_Half
2803 | SUPPORTED_100baseT_Full
2804 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2806 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2807 modes
|= SUPPORTED_1000baseT_Half
2808 | SUPPORTED_1000baseT_Full
;
2811 return SUPPORTED_1000baseT_Half
2812 | SUPPORTED_1000baseT_Full
2817 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2819 struct sky2_port
*sky2
= netdev_priv(dev
);
2820 struct sky2_hw
*hw
= sky2
->hw
;
2822 ecmd
->transceiver
= XCVR_INTERNAL
;
2823 ecmd
->supported
= sky2_supported_modes(hw
);
2824 ecmd
->phy_address
= PHY_ADDR_MARV
;
2825 if (sky2_is_copper(hw
)) {
2826 ecmd
->supported
= SUPPORTED_10baseT_Half
2827 | SUPPORTED_10baseT_Full
2828 | SUPPORTED_100baseT_Half
2829 | SUPPORTED_100baseT_Full
2830 | SUPPORTED_1000baseT_Half
2831 | SUPPORTED_1000baseT_Full
2832 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2833 ecmd
->port
= PORT_TP
;
2834 ecmd
->speed
= sky2
->speed
;
2836 ecmd
->speed
= SPEED_1000
;
2837 ecmd
->port
= PORT_FIBRE
;
2840 ecmd
->advertising
= sky2
->advertising
;
2841 ecmd
->autoneg
= sky2
->autoneg
;
2842 ecmd
->duplex
= sky2
->duplex
;
2846 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2848 struct sky2_port
*sky2
= netdev_priv(dev
);
2849 const struct sky2_hw
*hw
= sky2
->hw
;
2850 u32 supported
= sky2_supported_modes(hw
);
2852 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2853 ecmd
->advertising
= supported
;
2859 switch (ecmd
->speed
) {
2861 if (ecmd
->duplex
== DUPLEX_FULL
)
2862 setting
= SUPPORTED_1000baseT_Full
;
2863 else if (ecmd
->duplex
== DUPLEX_HALF
)
2864 setting
= SUPPORTED_1000baseT_Half
;
2869 if (ecmd
->duplex
== DUPLEX_FULL
)
2870 setting
= SUPPORTED_100baseT_Full
;
2871 else if (ecmd
->duplex
== DUPLEX_HALF
)
2872 setting
= SUPPORTED_100baseT_Half
;
2878 if (ecmd
->duplex
== DUPLEX_FULL
)
2879 setting
= SUPPORTED_10baseT_Full
;
2880 else if (ecmd
->duplex
== DUPLEX_HALF
)
2881 setting
= SUPPORTED_10baseT_Half
;
2889 if ((setting
& supported
) == 0)
2892 sky2
->speed
= ecmd
->speed
;
2893 sky2
->duplex
= ecmd
->duplex
;
2896 sky2
->autoneg
= ecmd
->autoneg
;
2897 sky2
->advertising
= ecmd
->advertising
;
2899 if (netif_running(dev
))
2900 sky2_phy_reinit(sky2
);
2905 static void sky2_get_drvinfo(struct net_device
*dev
,
2906 struct ethtool_drvinfo
*info
)
2908 struct sky2_port
*sky2
= netdev_priv(dev
);
2910 strcpy(info
->driver
, DRV_NAME
);
2911 strcpy(info
->version
, DRV_VERSION
);
2912 strcpy(info
->fw_version
, "N/A");
2913 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2916 static const struct sky2_stat
{
2917 char name
[ETH_GSTRING_LEN
];
2920 { "tx_bytes", GM_TXO_OK_HI
},
2921 { "rx_bytes", GM_RXO_OK_HI
},
2922 { "tx_broadcast", GM_TXF_BC_OK
},
2923 { "rx_broadcast", GM_RXF_BC_OK
},
2924 { "tx_multicast", GM_TXF_MC_OK
},
2925 { "rx_multicast", GM_RXF_MC_OK
},
2926 { "tx_unicast", GM_TXF_UC_OK
},
2927 { "rx_unicast", GM_RXF_UC_OK
},
2928 { "tx_mac_pause", GM_TXF_MPAUSE
},
2929 { "rx_mac_pause", GM_RXF_MPAUSE
},
2930 { "collisions", GM_TXF_COL
},
2931 { "late_collision",GM_TXF_LAT_COL
},
2932 { "aborted", GM_TXF_ABO_COL
},
2933 { "single_collisions", GM_TXF_SNG_COL
},
2934 { "multi_collisions", GM_TXF_MUL_COL
},
2936 { "rx_short", GM_RXF_SHT
},
2937 { "rx_runt", GM_RXE_FRAG
},
2938 { "rx_64_byte_packets", GM_RXF_64B
},
2939 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2940 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2941 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2942 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2943 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2944 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2945 { "rx_too_long", GM_RXF_LNG_ERR
},
2946 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2947 { "rx_jabber", GM_RXF_JAB_PKT
},
2948 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2950 { "tx_64_byte_packets", GM_TXF_64B
},
2951 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2952 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2953 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2954 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2955 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2956 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2957 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2960 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2962 struct sky2_port
*sky2
= netdev_priv(dev
);
2964 return sky2
->rx_csum
;
2967 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2969 struct sky2_port
*sky2
= netdev_priv(dev
);
2971 sky2
->rx_csum
= data
;
2973 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2974 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2979 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2981 struct sky2_port
*sky2
= netdev_priv(netdev
);
2982 return sky2
->msg_enable
;
2985 static int sky2_nway_reset(struct net_device
*dev
)
2987 struct sky2_port
*sky2
= netdev_priv(dev
);
2989 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
2992 sky2_phy_reinit(sky2
);
2997 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2999 struct sky2_hw
*hw
= sky2
->hw
;
3000 unsigned port
= sky2
->port
;
3003 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
3004 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
3005 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
3006 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
3008 for (i
= 2; i
< count
; i
++)
3009 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
3012 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3014 struct sky2_port
*sky2
= netdev_priv(netdev
);
3015 sky2
->msg_enable
= value
;
3018 static int sky2_get_stats_count(struct net_device
*dev
)
3020 return ARRAY_SIZE(sky2_stats
);
3023 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3024 struct ethtool_stats
*stats
, u64
* data
)
3026 struct sky2_port
*sky2
= netdev_priv(dev
);
3028 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3031 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3035 switch (stringset
) {
3037 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3038 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3039 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3044 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
3046 struct sky2_port
*sky2
= netdev_priv(dev
);
3047 return &sky2
->net_stats
;
3050 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3052 struct sky2_port
*sky2
= netdev_priv(dev
);
3053 struct sky2_hw
*hw
= sky2
->hw
;
3054 unsigned port
= sky2
->port
;
3055 const struct sockaddr
*addr
= p
;
3057 if (!is_valid_ether_addr(addr
->sa_data
))
3058 return -EADDRNOTAVAIL
;
3060 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3061 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3062 dev
->dev_addr
, ETH_ALEN
);
3063 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3064 dev
->dev_addr
, ETH_ALEN
);
3066 /* virtual address for data */
3067 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3069 /* physical address: used for pause frames */
3070 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3075 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3079 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3080 filter
[bit
>> 3] |= 1 << (bit
& 7);
3083 static void sky2_set_multicast(struct net_device
*dev
)
3085 struct sky2_port
*sky2
= netdev_priv(dev
);
3086 struct sky2_hw
*hw
= sky2
->hw
;
3087 unsigned port
= sky2
->port
;
3088 struct dev_mc_list
*list
= dev
->mc_list
;
3092 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3094 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3095 memset(filter
, 0, sizeof(filter
));
3097 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3098 reg
|= GM_RXCR_UCF_ENA
;
3100 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3101 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3102 else if (dev
->flags
& IFF_ALLMULTI
)
3103 memset(filter
, 0xff, sizeof(filter
));
3104 else if (dev
->mc_count
== 0 && !rx_pause
)
3105 reg
&= ~GM_RXCR_MCF_ENA
;
3108 reg
|= GM_RXCR_MCF_ENA
;
3111 sky2_add_filter(filter
, pause_mc_addr
);
3113 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3114 sky2_add_filter(filter
, list
->dmi_addr
);
3117 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3118 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3119 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3120 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3121 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3122 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3123 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3124 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3126 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3129 /* Can have one global because blinking is controlled by
3130 * ethtool and that is always under RTNL mutex
3132 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
3136 switch (hw
->chip_id
) {
3137 case CHIP_ID_YUKON_XL
:
3138 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3139 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3140 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3141 on
? (PHY_M_LEDC_LOS_CTRL(1) |
3142 PHY_M_LEDC_INIT_CTRL(7) |
3143 PHY_M_LEDC_STA1_CTRL(7) |
3144 PHY_M_LEDC_STA0_CTRL(7))
3147 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3151 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
3152 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3153 on
? PHY_M_LED_ALL
: 0);
3157 /* blink LED's for finding board */
3158 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3160 struct sky2_port
*sky2
= netdev_priv(dev
);
3161 struct sky2_hw
*hw
= sky2
->hw
;
3162 unsigned port
= sky2
->port
;
3163 u16 ledctrl
, ledover
= 0;
3168 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
3169 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
3173 /* save initial values */
3174 spin_lock_bh(&sky2
->phy_lock
);
3175 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3176 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3177 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3178 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
3179 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3181 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
3182 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
3186 while (!interrupted
&& ms
> 0) {
3187 sky2_led(hw
, port
, onoff
);
3190 spin_unlock_bh(&sky2
->phy_lock
);
3191 interrupted
= msleep_interruptible(250);
3192 spin_lock_bh(&sky2
->phy_lock
);
3197 /* resume regularly scheduled programming */
3198 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3199 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3200 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3201 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
3202 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3204 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
3205 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
3207 spin_unlock_bh(&sky2
->phy_lock
);
3212 static void sky2_get_pauseparam(struct net_device
*dev
,
3213 struct ethtool_pauseparam
*ecmd
)
3215 struct sky2_port
*sky2
= netdev_priv(dev
);
3217 switch (sky2
->flow_mode
) {
3219 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3222 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3225 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3228 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3231 ecmd
->autoneg
= sky2
->autoneg
;
3234 static int sky2_set_pauseparam(struct net_device
*dev
,
3235 struct ethtool_pauseparam
*ecmd
)
3237 struct sky2_port
*sky2
= netdev_priv(dev
);
3239 sky2
->autoneg
= ecmd
->autoneg
;
3240 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3242 if (netif_running(dev
))
3243 sky2_phy_reinit(sky2
);
3248 static int sky2_get_coalesce(struct net_device
*dev
,
3249 struct ethtool_coalesce
*ecmd
)
3251 struct sky2_port
*sky2
= netdev_priv(dev
);
3252 struct sky2_hw
*hw
= sky2
->hw
;
3254 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3255 ecmd
->tx_coalesce_usecs
= 0;
3257 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3258 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3260 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3262 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3263 ecmd
->rx_coalesce_usecs
= 0;
3265 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3266 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3268 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3270 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3271 ecmd
->rx_coalesce_usecs_irq
= 0;
3273 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3274 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3277 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3282 /* Note: this affect both ports */
3283 static int sky2_set_coalesce(struct net_device
*dev
,
3284 struct ethtool_coalesce
*ecmd
)
3286 struct sky2_port
*sky2
= netdev_priv(dev
);
3287 struct sky2_hw
*hw
= sky2
->hw
;
3288 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3290 if (ecmd
->tx_coalesce_usecs
> tmax
||
3291 ecmd
->rx_coalesce_usecs
> tmax
||
3292 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3295 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3297 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3299 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3302 if (ecmd
->tx_coalesce_usecs
== 0)
3303 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3305 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3306 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3307 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3309 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3311 if (ecmd
->rx_coalesce_usecs
== 0)
3312 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3314 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3315 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3316 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3318 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3320 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3321 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3323 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3324 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3325 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3327 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3331 static void sky2_get_ringparam(struct net_device
*dev
,
3332 struct ethtool_ringparam
*ering
)
3334 struct sky2_port
*sky2
= netdev_priv(dev
);
3336 ering
->rx_max_pending
= RX_MAX_PENDING
;
3337 ering
->rx_mini_max_pending
= 0;
3338 ering
->rx_jumbo_max_pending
= 0;
3339 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3341 ering
->rx_pending
= sky2
->rx_pending
;
3342 ering
->rx_mini_pending
= 0;
3343 ering
->rx_jumbo_pending
= 0;
3344 ering
->tx_pending
= sky2
->tx_pending
;
3347 static int sky2_set_ringparam(struct net_device
*dev
,
3348 struct ethtool_ringparam
*ering
)
3350 struct sky2_port
*sky2
= netdev_priv(dev
);
3353 if (ering
->rx_pending
> RX_MAX_PENDING
||
3354 ering
->rx_pending
< 8 ||
3355 ering
->tx_pending
< MAX_SKB_TX_LE
||
3356 ering
->tx_pending
> TX_RING_SIZE
- 1)
3359 if (netif_running(dev
))
3362 sky2
->rx_pending
= ering
->rx_pending
;
3363 sky2
->tx_pending
= ering
->tx_pending
;
3365 if (netif_running(dev
)) {
3370 sky2_set_multicast(dev
);
3376 static int sky2_get_regs_len(struct net_device
*dev
)
3382 * Returns copy of control register region
3383 * Note: ethtool_get_regs always provides full size (16k) buffer
3385 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3388 const struct sky2_port
*sky2
= netdev_priv(dev
);
3389 const void __iomem
*io
= sky2
->hw
->regs
;
3392 memset(p
, 0, regs
->len
);
3394 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3396 /* skip diagnostic ram region */
3397 memcpy_fromio(p
+ B3_RI_WTO_R1
, io
+ B3_RI_WTO_R1
, 0x2000 - B3_RI_WTO_R1
);
3399 /* copy GMAC registers */
3400 memcpy_fromio(p
+ BASE_GMAC_1
, io
+ BASE_GMAC_1
, 0x1000);
3401 if (sky2
->hw
->ports
> 1)
3402 memcpy_fromio(p
+ BASE_GMAC_2
, io
+ BASE_GMAC_2
, 0x1000);
3406 /* In order to do Jumbo packets on these chips, need to turn off the
3407 * transmit store/forward. Therefore checksum offload won't work.
3409 static int no_tx_offload(struct net_device
*dev
)
3411 const struct sky2_port
*sky2
= netdev_priv(dev
);
3412 const struct sky2_hw
*hw
= sky2
->hw
;
3414 return dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
;
3417 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3419 if (data
&& no_tx_offload(dev
))
3422 return ethtool_op_set_tx_csum(dev
, data
);
3426 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3428 if (data
&& no_tx_offload(dev
))
3431 return ethtool_op_set_tso(dev
, data
);
3434 static int sky2_get_eeprom_len(struct net_device
*dev
)
3436 struct sky2_port
*sky2
= netdev_priv(dev
);
3439 reg2
= sky2_pci_read32(sky2
->hw
, PCI_DEV_REG2
);
3440 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
3443 static u32
sky2_vpd_read(struct sky2_hw
*hw
, int cap
, u16 offset
)
3445 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
3447 while (!(sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
))
3449 return sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
3452 static void sky2_vpd_write(struct sky2_hw
*hw
, int cap
, u16 offset
, u32 val
)
3454 sky2_pci_write32(hw
, cap
+ PCI_VPD_DATA
, val
);
3455 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
3458 } while (sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
);
3461 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3464 struct sky2_port
*sky2
= netdev_priv(dev
);
3465 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3466 int length
= eeprom
->len
;
3467 u16 offset
= eeprom
->offset
;
3472 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
3474 while (length
> 0) {
3475 u32 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3476 int n
= min_t(int, length
, sizeof(val
));
3478 memcpy(data
, &val
, n
);
3486 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3489 struct sky2_port
*sky2
= netdev_priv(dev
);
3490 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3491 int length
= eeprom
->len
;
3492 u16 offset
= eeprom
->offset
;
3497 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
3500 while (length
> 0) {
3502 int n
= min_t(int, length
, sizeof(val
));
3504 if (n
< sizeof(val
))
3505 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3506 memcpy(&val
, data
, n
);
3508 sky2_vpd_write(sky2
->hw
, cap
, offset
, val
);
3518 static const struct ethtool_ops sky2_ethtool_ops
= {
3519 .get_settings
= sky2_get_settings
,
3520 .set_settings
= sky2_set_settings
,
3521 .get_drvinfo
= sky2_get_drvinfo
,
3522 .get_wol
= sky2_get_wol
,
3523 .set_wol
= sky2_set_wol
,
3524 .get_msglevel
= sky2_get_msglevel
,
3525 .set_msglevel
= sky2_set_msglevel
,
3526 .nway_reset
= sky2_nway_reset
,
3527 .get_regs_len
= sky2_get_regs_len
,
3528 .get_regs
= sky2_get_regs
,
3529 .get_link
= ethtool_op_get_link
,
3530 .get_eeprom_len
= sky2_get_eeprom_len
,
3531 .get_eeprom
= sky2_get_eeprom
,
3532 .set_eeprom
= sky2_set_eeprom
,
3533 .get_sg
= ethtool_op_get_sg
,
3534 .set_sg
= ethtool_op_set_sg
,
3535 .get_tx_csum
= ethtool_op_get_tx_csum
,
3536 .set_tx_csum
= sky2_set_tx_csum
,
3537 .get_tso
= ethtool_op_get_tso
,
3538 .set_tso
= sky2_set_tso
,
3539 .get_rx_csum
= sky2_get_rx_csum
,
3540 .set_rx_csum
= sky2_set_rx_csum
,
3541 .get_strings
= sky2_get_strings
,
3542 .get_coalesce
= sky2_get_coalesce
,
3543 .set_coalesce
= sky2_set_coalesce
,
3544 .get_ringparam
= sky2_get_ringparam
,
3545 .set_ringparam
= sky2_set_ringparam
,
3546 .get_pauseparam
= sky2_get_pauseparam
,
3547 .set_pauseparam
= sky2_set_pauseparam
,
3548 .phys_id
= sky2_phys_id
,
3549 .get_stats_count
= sky2_get_stats_count
,
3550 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3553 #ifdef CONFIG_SKY2_DEBUG
3555 static struct dentry
*sky2_debug
;
3557 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
3559 struct net_device
*dev
= seq
->private;
3560 const struct sky2_port
*sky2
= netdev_priv(dev
);
3561 const struct sky2_hw
*hw
= sky2
->hw
;
3562 unsigned port
= sky2
->port
;
3566 if (!netif_running(dev
))
3569 seq_printf(seq
, "IRQ src=%x mask=%x control=%x\n",
3570 sky2_read32(hw
, B0_ISRC
),
3571 sky2_read32(hw
, B0_IMSK
),
3572 sky2_read32(hw
, B0_Y2_SP_ICR
));
3574 netif_poll_disable(hw
->dev
[0]);
3575 last
= sky2_read16(hw
, STAT_PUT_IDX
);
3577 if (hw
->st_idx
== last
)
3578 seq_puts(seq
, "Status ring (empty)\n");
3580 seq_puts(seq
, "Status ring\n");
3581 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< STATUS_RING_SIZE
;
3582 idx
= RING_NEXT(idx
, STATUS_RING_SIZE
)) {
3583 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
3584 seq_printf(seq
, "[%d] %#x %d %#x\n",
3585 idx
, le
->opcode
, le
->length
, le
->status
);
3587 seq_puts(seq
, "\n");
3590 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
3591 sky2
->tx_cons
, sky2
->tx_prod
,
3592 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
3593 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
3595 /* Dump contents of tx ring */
3597 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< TX_RING_SIZE
;
3598 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
3599 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
3600 u32 a
= le32_to_cpu(le
->addr
);
3603 seq_printf(seq
, "%u:", idx
);
3606 switch(le
->opcode
& ~HW_OWNER
) {
3608 seq_printf(seq
, " %#x:", a
);
3611 seq_printf(seq
, " mtu=%d", a
);
3614 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
3617 seq_printf(seq
, " csum=%#x", a
);
3620 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
3623 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
3626 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
3629 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
3630 a
, le16_to_cpu(le
->length
));
3633 if (le
->ctrl
& EOP
) {
3634 seq_putc(seq
, '\n');
3639 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
3640 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
3641 last
= sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
3642 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
3644 netif_poll_enable(hw
->dev
[0]);
3648 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
3650 return single_open(file
, sky2_debug_show
, inode
->i_private
);
3653 static const struct file_operations sky2_debug_fops
= {
3654 .owner
= THIS_MODULE
,
3655 .open
= sky2_debug_open
,
3657 .llseek
= seq_lseek
,
3658 .release
= single_release
,
3662 * Use network device events to create/remove/rename
3663 * debugfs file entries
3665 static int sky2_device_event(struct notifier_block
*unused
,
3666 unsigned long event
, void *ptr
)
3668 struct net_device
*dev
= ptr
;
3670 if (dev
->open
== sky2_up
) {
3671 struct sky2_port
*sky2
= netdev_priv(dev
);
3674 case NETDEV_CHANGENAME
:
3675 if (!netif_running(dev
))
3679 case NETDEV_GOING_DOWN
:
3680 if (sky2
->debugfs
) {
3681 printk(KERN_DEBUG PFX
"%s: remove debugfs\n",
3683 debugfs_remove(sky2
->debugfs
);
3684 sky2
->debugfs
= NULL
;
3687 if (event
!= NETDEV_CHANGENAME
)
3689 /* fallthrough for changename */
3693 d
= debugfs_create_file(dev
->name
, S_IRUGO
,
3696 if (d
== NULL
|| IS_ERR(d
))
3697 printk(KERN_INFO PFX
3698 "%s: debugfs create failed\n",
3710 static struct notifier_block sky2_notifier
= {
3711 .notifier_call
= sky2_device_event
,
3715 static __init
void sky2_debug_init(void)
3719 ent
= debugfs_create_dir("sky2", NULL
);
3720 if (!ent
|| IS_ERR(ent
))
3724 register_netdevice_notifier(&sky2_notifier
);
3727 static __exit
void sky2_debug_cleanup(void)
3730 unregister_netdevice_notifier(&sky2_notifier
);
3731 debugfs_remove(sky2_debug
);
3737 #define sky2_debug_init()
3738 #define sky2_debug_cleanup()
3742 /* Initialize network device */
3743 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3745 int highmem
, int wol
)
3747 struct sky2_port
*sky2
;
3748 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3751 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed");
3755 SET_MODULE_OWNER(dev
);
3756 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3757 dev
->irq
= hw
->pdev
->irq
;
3758 dev
->open
= sky2_up
;
3759 dev
->stop
= sky2_down
;
3760 dev
->do_ioctl
= sky2_ioctl
;
3761 dev
->hard_start_xmit
= sky2_xmit_frame
;
3762 dev
->get_stats
= sky2_get_stats
;
3763 dev
->set_multicast_list
= sky2_set_multicast
;
3764 dev
->set_mac_address
= sky2_set_mac_address
;
3765 dev
->change_mtu
= sky2_change_mtu
;
3766 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3767 dev
->tx_timeout
= sky2_tx_timeout
;
3768 dev
->watchdog_timeo
= TX_WATCHDOG
;
3770 dev
->poll
= sky2_poll
;
3771 dev
->weight
= NAPI_WEIGHT
;
3772 #ifdef CONFIG_NET_POLL_CONTROLLER
3773 /* Network console (only works on port 0)
3774 * because netpoll makes assumptions about NAPI
3777 dev
->poll_controller
= sky2_netpoll
;
3780 sky2
= netdev_priv(dev
);
3783 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3785 /* Auto speed and flow control */
3786 sky2
->autoneg
= AUTONEG_ENABLE
;
3787 sky2
->flow_mode
= FC_BOTH
;
3791 sky2
->advertising
= sky2_supported_modes(hw
);
3795 spin_lock_init(&sky2
->phy_lock
);
3796 sky2
->tx_pending
= TX_DEF_PENDING
;
3797 sky2
->rx_pending
= RX_DEF_PENDING
;
3799 hw
->dev
[port
] = dev
;
3803 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
3805 dev
->features
|= NETIF_F_HIGHDMA
;
3807 #ifdef SKY2_VLAN_TAG_USED
3808 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3809 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3812 /* read the mac address */
3813 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3814 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3819 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3821 const struct sky2_port
*sky2
= netdev_priv(dev
);
3823 if (netif_msg_probe(sky2
))
3824 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3826 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3827 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3830 /* Handle software interrupt used during MSI test */
3831 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
3833 struct sky2_hw
*hw
= dev_id
;
3834 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3839 if (status
& Y2_IS_IRQ_SW
) {
3841 wake_up(&hw
->msi_wait
);
3842 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3844 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3849 /* Test interrupt path by forcing a a software IRQ */
3850 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3852 struct pci_dev
*pdev
= hw
->pdev
;
3855 init_waitqueue_head (&hw
->msi_wait
);
3857 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3859 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
3861 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
3865 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3866 sky2_read8(hw
, B0_CTST
);
3868 wait_event_timeout(hw
->msi_wait
, hw
->msi
, HZ
/10);
3871 /* MSI test failed, go back to INTx mode */
3872 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
3873 "switching to INTx mode.\n");
3876 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3879 sky2_write32(hw
, B0_IMSK
, 0);
3880 sky2_read32(hw
, B0_IMSK
);
3882 free_irq(pdev
->irq
, hw
);
3887 static int __devinit
pci_wake_enabled(struct pci_dev
*dev
)
3889 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3894 if (pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
))
3896 return value
& PCI_PM_CTRL_PME_ENABLE
;
3899 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3900 const struct pci_device_id
*ent
)
3902 struct net_device
*dev
;
3904 int err
, using_dac
= 0, wol_default
;
3906 err
= pci_enable_device(pdev
);
3908 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
3912 err
= pci_request_regions(pdev
, DRV_NAME
);
3914 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
3915 goto err_out_disable
;
3918 pci_set_master(pdev
);
3920 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3921 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3923 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3925 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
3926 "for consistent allocations\n");
3927 goto err_out_free_regions
;
3930 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3932 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
3933 goto err_out_free_regions
;
3937 wol_default
= pci_wake_enabled(pdev
) ? WAKE_MAGIC
: 0;
3940 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3942 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
3943 goto err_out_free_regions
;
3948 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3950 dev_err(&pdev
->dev
, "cannot map device registers\n");
3951 goto err_out_free_hw
;
3955 /* The sk98lin vendor driver uses hardware byte swapping but
3956 * this driver uses software swapping.
3960 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3961 reg
&= ~PCI_REV_DESC
;
3962 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3966 /* ring for status responses */
3967 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3970 goto err_out_iounmap
;
3972 err
= sky2_init(hw
);
3974 goto err_out_iounmap
;
3976 dev_info(&pdev
->dev
, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3977 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3978 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3979 hw
->chip_id
, hw
->chip_rev
);
3983 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
3986 goto err_out_free_pci
;
3989 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3990 err
= sky2_test_msi(hw
);
3991 if (err
== -EOPNOTSUPP
)
3992 pci_disable_msi(pdev
);
3994 goto err_out_free_netdev
;
3997 err
= register_netdev(dev
);
3999 dev_err(&pdev
->dev
, "cannot register net device\n");
4000 goto err_out_free_netdev
;
4003 err
= request_irq(pdev
->irq
, sky2_intr
, hw
->msi
? 0 : IRQF_SHARED
,
4006 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4007 goto err_out_unregister
;
4009 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4011 sky2_show_addr(dev
);
4013 if (hw
->ports
> 1) {
4014 struct net_device
*dev1
;
4016 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
4018 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
4019 else if ((err
= register_netdev(dev1
))) {
4020 dev_warn(&pdev
->dev
,
4021 "register of second port failed (%d)\n", err
);
4025 sky2_show_addr(dev1
);
4028 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
4029 INIT_WORK(&hw
->restart_work
, sky2_restart
);
4031 sky2_idle_start(hw
);
4033 pci_set_drvdata(pdev
, hw
);
4039 pci_disable_msi(pdev
);
4040 unregister_netdev(dev
);
4041 err_out_free_netdev
:
4044 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4045 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4050 err_out_free_regions
:
4051 pci_release_regions(pdev
);
4053 pci_disable_device(pdev
);
4055 pci_set_drvdata(pdev
, NULL
);
4059 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
4061 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4062 struct net_device
*dev0
, *dev1
;
4067 del_timer_sync(&hw
->idle_timer
);
4069 flush_scheduled_work();
4071 sky2_write32(hw
, B0_IMSK
, 0);
4072 synchronize_irq(hw
->pdev
->irq
);
4077 unregister_netdev(dev1
);
4078 unregister_netdev(dev0
);
4082 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
4083 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4084 sky2_read8(hw
, B0_CTST
);
4086 free_irq(pdev
->irq
, hw
);
4088 pci_disable_msi(pdev
);
4089 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4090 pci_release_regions(pdev
);
4091 pci_disable_device(pdev
);
4099 pci_set_drvdata(pdev
, NULL
);
4103 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4105 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4111 del_timer_sync(&hw
->idle_timer
);
4112 netif_poll_disable(hw
->dev
[0]);
4114 for (i
= 0; i
< hw
->ports
; i
++) {
4115 struct net_device
*dev
= hw
->dev
[i
];
4116 struct sky2_port
*sky2
= netdev_priv(dev
);
4118 if (netif_running(dev
))
4122 sky2_wol_init(sky2
);
4127 sky2_write32(hw
, B0_IMSK
, 0);
4130 pci_save_state(pdev
);
4131 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
4132 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4137 static int sky2_resume(struct pci_dev
*pdev
)
4139 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4145 err
= pci_set_power_state(pdev
, PCI_D0
);
4149 err
= pci_restore_state(pdev
);
4153 pci_enable_wake(pdev
, PCI_D0
, 0);
4155 /* Re-enable all clocks */
4156 if (hw
->chip_id
== CHIP_ID_YUKON_EX
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
4157 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
4161 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4163 for (i
= 0; i
< hw
->ports
; i
++) {
4164 struct net_device
*dev
= hw
->dev
[i
];
4165 if (netif_running(dev
)) {
4168 printk(KERN_ERR PFX
"%s: could not up: %d\n",
4176 netif_poll_enable(hw
->dev
[0]);
4177 sky2_idle_start(hw
);
4180 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
4181 pci_disable_device(pdev
);
4186 static void sky2_shutdown(struct pci_dev
*pdev
)
4188 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4194 del_timer_sync(&hw
->idle_timer
);
4195 netif_poll_disable(hw
->dev
[0]);
4197 for (i
= 0; i
< hw
->ports
; i
++) {
4198 struct net_device
*dev
= hw
->dev
[i
];
4199 struct sky2_port
*sky2
= netdev_priv(dev
);
4203 sky2_wol_init(sky2
);
4210 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
4211 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
4213 pci_disable_device(pdev
);
4214 pci_set_power_state(pdev
, PCI_D3hot
);
4218 static struct pci_driver sky2_driver
= {
4220 .id_table
= sky2_id_table
,
4221 .probe
= sky2_probe
,
4222 .remove
= __devexit_p(sky2_remove
),
4224 .suspend
= sky2_suspend
,
4225 .resume
= sky2_resume
,
4227 .shutdown
= sky2_shutdown
,
4230 static int __init
sky2_init_module(void)
4233 return pci_register_driver(&sky2_driver
);
4236 static void __exit
sky2_cleanup_module(void)
4238 pci_unregister_driver(&sky2_driver
);
4239 sky2_debug_cleanup();
4242 module_init(sky2_init_module
);
4243 module_exit(sky2_cleanup_module
);
4245 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4246 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4247 MODULE_LICENSE("GPL");
4248 MODULE_VERSION(DRV_VERSION
);