?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
8139cp/8139too: do not read into reserved registers
[linux-2.6/libata-dev.git] / drivers / net / ethernet / realtek / 8139cp.c
blob886e6bec971a3ecaf6a44ed23813a6a7dd675a6a
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
54
55
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/interrupt.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/delay.h>
67 #include <linux/ethtool.h>
68 #include <linux/gfp.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/crc32.h>
72 #include <linux/in.h>
73 #include <linux/ip.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
76 #include <linux/cache.h>
77 #include <asm/io.h>
78 #include <asm/irq.h>
79 #include <asm/uaccess.h>
80
81 /* These identify the driver base version and may not be removed. */
82 static char version[] =
83 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
84
85 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
86 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
87 MODULE_VERSION(DRV_VERSION);
88 MODULE_LICENSE("GPL");
89
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
93
94 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
96 static int multicast_filter_limit = 32;
97 module_param(multicast_filter_limit, int, 0);
98 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
99
100 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
101 NETIF_MSG_PROBE | \
102 NETIF_MSG_LINK)
103 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
104 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
105 #define CP_REGS_SIZE (0xff + 1)
106 #define CP_REGS_VER 1 /* version 1 */
107 #define CP_RX_RING_SIZE 64
108 #define CP_TX_RING_SIZE 64
109 #define CP_RING_BYTES \
110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
112 CP_STATS_SIZE)
113 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
114 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
115 #define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
119
120 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
121 #define CP_INTERNAL_PHY 32
122
123 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
124 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
125 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
126 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
128
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define TX_TIMEOUT (6*HZ)
131
132 /* hardware minimum and maximum for a single frame's data payload */
133 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
134 #define CP_MAX_MTU 4096
135
136 enum {
137 /* NIC register offsets */
138 MAC0 = 0x00, /* Ethernet hardware address. */
139 MAR0 = 0x08, /* Multicast filter. */
140 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
141 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
142 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
143 Cmd = 0x37, /* Command register */
144 IntrMask = 0x3C, /* Interrupt mask */
145 IntrStatus = 0x3E, /* Interrupt status */
146 TxConfig = 0x40, /* Tx configuration */
147 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
148 RxConfig = 0x44, /* Rx configuration */
149 RxMissed = 0x4C, /* 24 bits valid, write clears */
150 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
151 Config1 = 0x52, /* Config1 */
152 Config3 = 0x59, /* Config3 */
153 Config4 = 0x5A, /* Config4 */
154 MultiIntr = 0x5C, /* Multiple interrupt select */
155 BasicModeCtrl = 0x62, /* MII BMCR */
156 BasicModeStatus = 0x64, /* MII BMSR */
157 NWayAdvert = 0x66, /* MII ADVERTISE */
158 NWayLPAR = 0x68, /* MII LPA */
159 NWayExpansion = 0x6A, /* MII Expansion */
160 Config5 = 0xD8, /* Config5 */
161 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
162 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
163 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
164 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
165 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
166 TxThresh = 0xEC, /* Early Tx threshold */
167 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
168 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
169
170 /* Tx and Rx status descriptors */
171 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
172 RingEnd = (1 << 30), /* End of descriptor ring */
173 FirstFrag = (1 << 29), /* First segment of a packet */
174 LastFrag = (1 << 28), /* Final segment of a packet */
175 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
176 MSSShift = 16, /* MSS value position */
177 MSSMask = 0xfff, /* MSS value: 11 bits */
178 TxError = (1 << 23), /* Tx error summary */
179 RxError = (1 << 20), /* Rx error summary */
180 IPCS = (1 << 18), /* Calculate IP checksum */
181 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
182 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
183 TxVlanTag = (1 << 17), /* Add VLAN tag */
184 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
185 IPFail = (1 << 15), /* IP checksum failed */
186 UDPFail = (1 << 14), /* UDP/IP checksum failed */
187 TCPFail = (1 << 13), /* TCP/IP checksum failed */
188 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
189 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
190 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
191 RxProtoTCP = 1,
192 RxProtoUDP = 2,
193 RxProtoIP = 3,
194 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
195 TxOWC = (1 << 22), /* Tx Out-of-window collision */
196 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
197 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
198 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
199 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
200 RxErrFrame = (1 << 27), /* Rx frame alignment error */
201 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
202 RxErrCRC = (1 << 18), /* Rx CRC error */
203 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
204 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
205 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
206
207 /* StatsAddr register */
208 DumpStats = (1 << 3), /* Begin stats dump */
209
210 /* RxConfig register */
211 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
212 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
213 AcceptErr = 0x20, /* Accept packets with CRC errors */
214 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
215 AcceptBroadcast = 0x08, /* Accept broadcast packets */
216 AcceptMulticast = 0x04, /* Accept multicast packets */
217 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
218 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
219
220 /* IntrMask / IntrStatus registers */
221 PciErr = (1 << 15), /* System error on the PCI bus */
222 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
223 LenChg = (1 << 13), /* Cable length change */
224 SWInt = (1 << 8), /* Software-requested interrupt */
225 TxEmpty = (1 << 7), /* No Tx descriptors available */
226 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
227 LinkChg = (1 << 5), /* Packet underrun, or link change */
228 RxEmpty = (1 << 4), /* No Rx descriptors available */
229 TxErr = (1 << 3), /* Tx error */
230 TxOK = (1 << 2), /* Tx packet sent */
231 RxErr = (1 << 1), /* Rx error */
232 RxOK = (1 << 0), /* Rx packet received */
233 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
234 but hardware likes to raise it */
235
236 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
237 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
238 RxErr | RxOK | IntrResvd,
239
240 /* C mode command register */
241 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
242 RxOn = (1 << 3), /* Rx mode enable */
243 TxOn = (1 << 2), /* Tx mode enable */
244
245 /* C+ mode command register */
246 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
247 RxChkSum = (1 << 5), /* Rx checksum offload enable */
248 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
249 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
250 CpRxOn = (1 << 1), /* Rx mode enable */
251 CpTxOn = (1 << 0), /* Tx mode enable */
252
253 /* Cfg9436 EEPROM control register */
254 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
255 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
256
257 /* TxConfig register */
258 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
259 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
260
261 /* Early Tx Threshold register */
262 TxThreshMask = 0x3f, /* Mask bits 5-0 */
263 TxThreshMax = 2048, /* Max early Tx threshold */
264
265 /* Config1 register */
266 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
267 LWACT = (1 << 4), /* LWAKE active mode */
268 PMEnable = (1 << 0), /* Enable various PM features of chip */
269
270 /* Config3 register */
271 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
272 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
273 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
274
275 /* Config4 register */
276 LWPTN = (1 << 1), /* LWAKE Pattern */
277 LWPME = (1 << 4), /* LANWAKE vs PMEB */
278
279 /* Config5 register */
280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LANWake = (1 << 1), /* Enable LANWake signal */
284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
285
286 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
287 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
288 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
289 };
290
291 static const unsigned int cp_rx_config =
292 (RX_FIFO_THRESH << RxCfgFIFOShift) |
293 (RX_DMA_BURST << RxCfgDMAShift);
294
295 struct cp_desc {
296 __le32 opts1;
297 __le32 opts2;
298 __le64 addr;
299 };
300
301 struct cp_dma_stats {
302 __le64 tx_ok;
303 __le64 rx_ok;
304 __le64 tx_err;
305 __le32 rx_err;
306 __le16 rx_fifo;
307 __le16 frame_align;
308 __le32 tx_ok_1col;
309 __le32 tx_ok_mcol;
310 __le64 rx_ok_phys;
311 __le64 rx_ok_bcast;
312 __le32 rx_ok_mcast;
313 __le16 tx_abort;
314 __le16 tx_underrun;
315 } __packed;
316
317 struct cp_extra_stats {
318 unsigned long rx_frags;
319 };
320
321 struct cp_private {
322 void __iomem *regs;
323 struct net_device *dev;
324 spinlock_t lock;
325 u32 msg_enable;
326
327 struct napi_struct napi;
328
329 struct pci_dev *pdev;
330 u32 rx_config;
331 u16 cpcmd;
332
333 struct cp_extra_stats cp_stats;
334
335 unsigned rx_head ____cacheline_aligned;
336 unsigned rx_tail;
337 struct cp_desc *rx_ring;
338 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
339
340 unsigned tx_head ____cacheline_aligned;
341 unsigned tx_tail;
342 struct cp_desc *tx_ring;
343 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
344
345 unsigned rx_buf_sz;
346 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
347
348 dma_addr_t ring_dma;
349
350 struct mii_if_info mii_if;
351 };
352
353 #define cpr8(reg) readb(cp->regs + (reg))
354 #define cpr16(reg) readw(cp->regs + (reg))
355 #define cpr32(reg) readl(cp->regs + (reg))
356 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
357 #define cpw16(reg,val) writew((val), cp->regs + (reg))
358 #define cpw32(reg,val) writel((val), cp->regs + (reg))
359 #define cpw8_f(reg,val) do { \
360 writeb((val), cp->regs + (reg)); \
361 readb(cp->regs + (reg)); \
362 } while (0)
363 #define cpw16_f(reg,val) do { \
364 writew((val), cp->regs + (reg)); \
365 readw(cp->regs + (reg)); \
366 } while (0)
367 #define cpw32_f(reg,val) do { \
368 writel((val), cp->regs + (reg)); \
369 readl(cp->regs + (reg)); \
370 } while (0)
371
372
373 static void __cp_set_rx_mode (struct net_device *dev);
374 static void cp_tx (struct cp_private *cp);
375 static void cp_clean_rings (struct cp_private *cp);
376 #ifdef CONFIG_NET_POLL_CONTROLLER
377 static void cp_poll_controller(struct net_device *dev);
378 #endif
379 static int cp_get_eeprom_len(struct net_device *dev);
380 static int cp_get_eeprom(struct net_device *dev,
381 struct ethtool_eeprom *eeprom, u8 *data);
382 static int cp_set_eeprom(struct net_device *dev,
383 struct ethtool_eeprom *eeprom, u8 *data);
384
385 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
386 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
387 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
388 { },
389 };
390 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
391
392 static struct {
393 const char str[ETH_GSTRING_LEN];
394 } ethtool_stats_keys[] = {
395 { "tx_ok" },
396 { "rx_ok" },
397 { "tx_err" },
398 { "rx_err" },
399 { "rx_fifo" },
400 { "frame_align" },
401 { "tx_ok_1col" },
402 { "tx_ok_mcol" },
403 { "rx_ok_phys" },
404 { "rx_ok_bcast" },
405 { "rx_ok_mcast" },
406 { "tx_abort" },
407 { "tx_underrun" },
408 { "rx_frags" },
409 };
410
411
412 static inline void cp_set_rxbufsize (struct cp_private *cp)
413 {
414 unsigned int mtu = cp->dev->mtu;
415
416 if (mtu > ETH_DATA_LEN)
417 /* MTU + ethernet header + FCS + optional VLAN tag */
418 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
419 else
420 cp->rx_buf_sz = PKT_BUF_SZ;
421 }
422
423 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
424 struct cp_desc *desc)
425 {
426 u32 opts2 = le32_to_cpu(desc->opts2);
427
428 skb->protocol = eth_type_trans (skb, cp->dev);
429
430 cp->dev->stats.rx_packets++;
431 cp->dev->stats.rx_bytes += skb->len;
432
433 if (opts2 & RxVlanTagged)
434 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
435
436 napi_gro_receive(&cp->napi, skb);
437 }
438
439 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
440 u32 status, u32 len)
441 {
442 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
443 rx_tail, status, len);
444 cp->dev->stats.rx_errors++;
445 if (status & RxErrFrame)
446 cp->dev->stats.rx_frame_errors++;
447 if (status & RxErrCRC)
448 cp->dev->stats.rx_crc_errors++;
449 if ((status & RxErrRunt) || (status & RxErrLong))
450 cp->dev->stats.rx_length_errors++;
451 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
452 cp->dev->stats.rx_length_errors++;
453 if (status & RxErrFIFO)
454 cp->dev->stats.rx_fifo_errors++;
455 }
456
457 static inline unsigned int cp_rx_csum_ok (u32 status)
458 {
459 unsigned int protocol = (status >> 16) & 0x3;
460
461 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
462 ((protocol == RxProtoUDP) && !(status & UDPFail)))
463 return 1;
464 else
465 return 0;
466 }
467
468 static int cp_rx_poll(struct napi_struct *napi, int budget)
469 {
470 struct cp_private *cp = container_of(napi, struct cp_private, napi);
471 struct net_device *dev = cp->dev;
472 unsigned int rx_tail = cp->rx_tail;
473 int rx;
474
475 rx_status_loop:
476 rx = 0;
477 cpw16(IntrStatus, cp_rx_intr_mask);
478
479 while (1) {
480 u32 status, len;
481 dma_addr_t mapping;
482 struct sk_buff *skb, *new_skb;
483 struct cp_desc *desc;
484 const unsigned buflen = cp->rx_buf_sz;
485
486 skb = cp->rx_skb[rx_tail];
487 BUG_ON(!skb);
488
489 desc = &cp->rx_ring[rx_tail];
490 status = le32_to_cpu(desc->opts1);
491 if (status & DescOwn)
492 break;
493
494 len = (status & 0x1fff) - 4;
495 mapping = le64_to_cpu(desc->addr);
496
497 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
498 /* we don't support incoming fragmented frames.
499 * instead, we attempt to ensure that the
500 * pre-allocated RX skbs are properly sized such
501 * that RX fragments are never encountered
502 */
503 cp_rx_err_acct(cp, rx_tail, status, len);
504 dev->stats.rx_dropped++;
505 cp->cp_stats.rx_frags++;
506 goto rx_next;
507 }
508
509 if (status & (RxError | RxErrFIFO)) {
510 cp_rx_err_acct(cp, rx_tail, status, len);
511 goto rx_next;
512 }
513
514 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
515 rx_tail, status, len);
516
517 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
518 if (!new_skb) {
519 dev->stats.rx_dropped++;
520 goto rx_next;
521 }
522
523 dma_unmap_single(&cp->pdev->dev, mapping,
524 buflen, PCI_DMA_FROMDEVICE);
525
526 /* Handle checksum offloading for incoming packets. */
527 if (cp_rx_csum_ok(status))
528 skb->ip_summed = CHECKSUM_UNNECESSARY;
529 else
530 skb_checksum_none_assert(skb);
531
532 skb_put(skb, len);
533
534 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
535 PCI_DMA_FROMDEVICE);
536 cp->rx_skb[rx_tail] = new_skb;
537
538 cp_rx_skb(cp, skb, desc);
539 rx++;
540
541 rx_next:
542 cp->rx_ring[rx_tail].opts2 = 0;
543 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
544 if (rx_tail == (CP_RX_RING_SIZE - 1))
545 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
546 cp->rx_buf_sz);
547 else
548 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
549 rx_tail = NEXT_RX(rx_tail);
550
551 if (rx >= budget)
552 break;
553 }
554
555 cp->rx_tail = rx_tail;
556
557 /* if we did not reach work limit, then we're done with
558 * this round of polling
559 */
560 if (rx < budget) {
561 unsigned long flags;
562
563 if (cpr16(IntrStatus) & cp_rx_intr_mask)
564 goto rx_status_loop;
565
566 spin_lock_irqsave(&cp->lock, flags);
567 __napi_complete(napi);
568 cpw16_f(IntrMask, cp_intr_mask);
569 spin_unlock_irqrestore(&cp->lock, flags);
570 }
571
572 return rx;
573 }
574
575 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
576 {
577 struct net_device *dev = dev_instance;
578 struct cp_private *cp;
579 u16 status;
580
581 if (unlikely(dev == NULL))
582 return IRQ_NONE;
583 cp = netdev_priv(dev);
584
585 status = cpr16(IntrStatus);
586 if (!status || (status == 0xFFFF))
587 return IRQ_NONE;
588
589 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
590 status, cpr8(Cmd), cpr16(CpCmd));
591
592 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
593
594 spin_lock(&cp->lock);
595
596 /* close possible race's with dev_close */
597 if (unlikely(!netif_running(dev))) {
598 cpw16(IntrMask, 0);
599 spin_unlock(&cp->lock);
600 return IRQ_HANDLED;
601 }
602
603 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
604 if (napi_schedule_prep(&cp->napi)) {
605 cpw16_f(IntrMask, cp_norx_intr_mask);
606 __napi_schedule(&cp->napi);
607 }
608
609 if (status & (TxOK | TxErr | TxEmpty | SWInt))
610 cp_tx(cp);
611 if (status & LinkChg)
612 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
613
614 spin_unlock(&cp->lock);
615
616 if (status & PciErr) {
617 u16 pci_status;
618
619 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
620 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
621 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
622 status, pci_status);
623
624 /* TODO: reset hardware */
625 }
626
627 return IRQ_HANDLED;
628 }
629
630 #ifdef CONFIG_NET_POLL_CONTROLLER
631 /*
632 * Polling receive - used by netconsole and other diagnostic tools
633 * to allow network i/o with interrupts disabled.
634 */
635 static void cp_poll_controller(struct net_device *dev)
636 {
637 disable_irq(dev->irq);
638 cp_interrupt(dev->irq, dev);
639 enable_irq(dev->irq);
640 }
641 #endif
642
643 static void cp_tx (struct cp_private *cp)
644 {
645 unsigned tx_head = cp->tx_head;
646 unsigned tx_tail = cp->tx_tail;
647
648 while (tx_tail != tx_head) {
649 struct cp_desc *txd = cp->tx_ring + tx_tail;
650 struct sk_buff *skb;
651 u32 status;
652
653 rmb();
654 status = le32_to_cpu(txd->opts1);
655 if (status & DescOwn)
656 break;
657
658 skb = cp->tx_skb[tx_tail];
659 BUG_ON(!skb);
660
661 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
662 le32_to_cpu(txd->opts1) & 0xffff,
663 PCI_DMA_TODEVICE);
664
665 if (status & LastFrag) {
666 if (status & (TxError | TxFIFOUnder)) {
667 netif_dbg(cp, tx_err, cp->dev,
668 "tx err, status 0x%x\n", status);
669 cp->dev->stats.tx_errors++;
670 if (status & TxOWC)
671 cp->dev->stats.tx_window_errors++;
672 if (status & TxMaxCol)
673 cp->dev->stats.tx_aborted_errors++;
674 if (status & TxLinkFail)
675 cp->dev->stats.tx_carrier_errors++;
676 if (status & TxFIFOUnder)
677 cp->dev->stats.tx_fifo_errors++;
678 } else {
679 cp->dev->stats.collisions +=
680 ((status >> TxColCntShift) & TxColCntMask);
681 cp->dev->stats.tx_packets++;
682 cp->dev->stats.tx_bytes += skb->len;
683 netif_dbg(cp, tx_done, cp->dev,
684 "tx done, slot %d\n", tx_tail);
685 }
686 dev_kfree_skb_irq(skb);
687 }
688
689 cp->tx_skb[tx_tail] = NULL;
690
691 tx_tail = NEXT_TX(tx_tail);
692 }
693
694 cp->tx_tail = tx_tail;
695
696 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
697 netif_wake_queue(cp->dev);
698 }
699
700 static inline u32 cp_tx_vlan_tag(struct sk_buff *skb)
701 {
702 return vlan_tx_tag_present(skb) ?
703 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
704 }
705
706 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
707 struct net_device *dev)
708 {
709 struct cp_private *cp = netdev_priv(dev);
710 unsigned entry;
711 u32 eor, flags;
712 unsigned long intr_flags;
713 __le32 opts2;
714 int mss = 0;
715
716 spin_lock_irqsave(&cp->lock, intr_flags);
717
718 /* This is a hard error, log it. */
719 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
720 netif_stop_queue(dev);
721 spin_unlock_irqrestore(&cp->lock, intr_flags);
722 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
723 return NETDEV_TX_BUSY;
724 }
725
726 entry = cp->tx_head;
727 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
728 mss = skb_shinfo(skb)->gso_size;
729
730 opts2 = cpu_to_le32(cp_tx_vlan_tag(skb));
731
732 if (skb_shinfo(skb)->nr_frags == 0) {
733 struct cp_desc *txd = &cp->tx_ring[entry];
734 u32 len;
735 dma_addr_t mapping;
736
737 len = skb->len;
738 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
739 txd->opts2 = opts2;
740 txd->addr = cpu_to_le64(mapping);
741 wmb();
742
743 flags = eor | len | DescOwn | FirstFrag | LastFrag;
744
745 if (mss)
746 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
747 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
748 const struct iphdr *ip = ip_hdr(skb);
749 if (ip->protocol == IPPROTO_TCP)
750 flags |= IPCS | TCPCS;
751 else if (ip->protocol == IPPROTO_UDP)
752 flags |= IPCS | UDPCS;
753 else
754 WARN_ON(1); /* we need a WARN() */
755 }
756
757 txd->opts1 = cpu_to_le32(flags);
758 wmb();
759
760 cp->tx_skb[entry] = skb;
761 entry = NEXT_TX(entry);
762 } else {
763 struct cp_desc *txd;
764 u32 first_len, first_eor;
765 dma_addr_t first_mapping;
766 int frag, first_entry = entry;
767 const struct iphdr *ip = ip_hdr(skb);
768
769 /* We must give this initial chunk to the device last.
770 * Otherwise we could race with the device.
771 */
772 first_eor = eor;
773 first_len = skb_headlen(skb);
774 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
775 first_len, PCI_DMA_TODEVICE);
776 cp->tx_skb[entry] = skb;
777 entry = NEXT_TX(entry);
778
779 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
780 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
781 u32 len;
782 u32 ctrl;
783 dma_addr_t mapping;
784
785 len = skb_frag_size(this_frag);
786 mapping = dma_map_single(&cp->pdev->dev,
787 skb_frag_address(this_frag),
788 len, PCI_DMA_TODEVICE);
789 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
790
791 ctrl = eor | len | DescOwn;
792
793 if (mss)
794 ctrl |= LargeSend |
795 ((mss & MSSMask) << MSSShift);
796 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
797 if (ip->protocol == IPPROTO_TCP)
798 ctrl |= IPCS | TCPCS;
799 else if (ip->protocol == IPPROTO_UDP)
800 ctrl |= IPCS | UDPCS;
801 else
802 BUG();
803 }
804
805 if (frag == skb_shinfo(skb)->nr_frags - 1)
806 ctrl |= LastFrag;
807
808 txd = &cp->tx_ring[entry];
809 txd->opts2 = opts2;
810 txd->addr = cpu_to_le64(mapping);
811 wmb();
812
813 txd->opts1 = cpu_to_le32(ctrl);
814 wmb();
815
816 cp->tx_skb[entry] = skb;
817 entry = NEXT_TX(entry);
818 }
819
820 txd = &cp->tx_ring[first_entry];
821 txd->opts2 = opts2;
822 txd->addr = cpu_to_le64(first_mapping);
823 wmb();
824
825 if (skb->ip_summed == CHECKSUM_PARTIAL) {
826 if (ip->protocol == IPPROTO_TCP)
827 txd->opts1 = cpu_to_le32(first_eor | first_len |
828 FirstFrag | DescOwn |
829 IPCS | TCPCS);
830 else if (ip->protocol == IPPROTO_UDP)
831 txd->opts1 = cpu_to_le32(first_eor | first_len |
832 FirstFrag | DescOwn |
833 IPCS | UDPCS);
834 else
835 BUG();
836 } else
837 txd->opts1 = cpu_to_le32(first_eor | first_len |
838 FirstFrag | DescOwn);
839 wmb();
840 }
841 cp->tx_head = entry;
842 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
843 entry, skb->len);
844 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
845 netif_stop_queue(dev);
846
847 spin_unlock_irqrestore(&cp->lock, intr_flags);
848
849 cpw8(TxPoll, NormalTxPoll);
850
851 return NETDEV_TX_OK;
852 }
853
854 /* Set or clear the multicast filter for this adaptor.
855 This routine is not state sensitive and need not be SMP locked. */
856
857 static void __cp_set_rx_mode (struct net_device *dev)
858 {
859 struct cp_private *cp = netdev_priv(dev);
860 u32 mc_filter[2]; /* Multicast hash filter */
861 int rx_mode;
862 u32 tmp;
863
864 /* Note: do not reorder, GCC is clever about common statements. */
865 if (dev->flags & IFF_PROMISC) {
866 /* Unconditionally log net taps. */
867 rx_mode =
868 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
869 AcceptAllPhys;
870 mc_filter[1] = mc_filter[0] = 0xffffffff;
871 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
872 (dev->flags & IFF_ALLMULTI)) {
873 /* Too many to filter perfectly -- accept all multicasts. */
874 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
875 mc_filter[1] = mc_filter[0] = 0xffffffff;
876 } else {
877 struct netdev_hw_addr *ha;
878 rx_mode = AcceptBroadcast | AcceptMyPhys;
879 mc_filter[1] = mc_filter[0] = 0;
880 netdev_for_each_mc_addr(ha, dev) {
881 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
882
883 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
884 rx_mode |= AcceptMulticast;
885 }
886 }
887
888 /* We can safely update without stopping the chip. */
889 tmp = cp_rx_config | rx_mode;
890 if (cp->rx_config != tmp) {
891 cpw32_f (RxConfig, tmp);
892 cp->rx_config = tmp;
893 }
894 cpw32_f (MAR0 + 0, mc_filter[0]);
895 cpw32_f (MAR0 + 4, mc_filter[1]);
896 }
897
898 static void cp_set_rx_mode (struct net_device *dev)
899 {
900 unsigned long flags;
901 struct cp_private *cp = netdev_priv(dev);
902
903 spin_lock_irqsave (&cp->lock, flags);
904 __cp_set_rx_mode(dev);
905 spin_unlock_irqrestore (&cp->lock, flags);
906 }
907
908 static void __cp_get_stats(struct cp_private *cp)
909 {
910 /* only lower 24 bits valid; write any value to clear */
911 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
912 cpw32 (RxMissed, 0);
913 }
914
915 static struct net_device_stats *cp_get_stats(struct net_device *dev)
916 {
917 struct cp_private *cp = netdev_priv(dev);
918 unsigned long flags;
919
920 /* The chip only need report frame silently dropped. */
921 spin_lock_irqsave(&cp->lock, flags);
922 if (netif_running(dev) && netif_device_present(dev))
923 __cp_get_stats(cp);
924 spin_unlock_irqrestore(&cp->lock, flags);
925
926 return &dev->stats;
927 }
928
929 static void cp_stop_hw (struct cp_private *cp)
930 {
931 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
932 cpw16_f(IntrMask, 0);
933 cpw8(Cmd, 0);
934 cpw16_f(CpCmd, 0);
935 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
936
937 cp->rx_tail = 0;
938 cp->tx_head = cp->tx_tail = 0;
939 }
940
941 static void cp_reset_hw (struct cp_private *cp)
942 {
943 unsigned work = 1000;
944
945 cpw8(Cmd, CmdReset);
946
947 while (work--) {
948 if (!(cpr8(Cmd) & CmdReset))
949 return;
950
951 schedule_timeout_uninterruptible(10);
952 }
953
954 netdev_err(cp->dev, "hardware reset timeout\n");
955 }
956
957 static inline void cp_start_hw (struct cp_private *cp)
958 {
959 cpw16(CpCmd, cp->cpcmd);
960 cpw8(Cmd, RxOn | TxOn);
961 }
962
963 static void cp_init_hw (struct cp_private *cp)
964 {
965 struct net_device *dev = cp->dev;
966 dma_addr_t ring_dma;
967
968 cp_reset_hw(cp);
969
970 cpw8_f (Cfg9346, Cfg9346_Unlock);
971
972 /* Restore our idea of the MAC address. */
973 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
974 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
975
976 cp_start_hw(cp);
977 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
978
979 __cp_set_rx_mode(dev);
980 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
981
982 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
983 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
984 cpw8(Config3, PARMEnable);
985 cp->wol_enabled = 0;
986
987 cpw8(Config5, cpr8(Config5) & PMEStatus);
988
989 cpw32_f(HiTxRingAddr, 0);
990 cpw32_f(HiTxRingAddr + 4, 0);
991
992 ring_dma = cp->ring_dma;
993 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
994 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
995
996 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
997 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
998 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
999
1000 cpw16(MultiIntr, 0);
1001
1002 cpw16_f(IntrMask, cp_intr_mask);
1003
1004 cpw8_f(Cfg9346, Cfg9346_Lock);
1005 }
1006
1007 static int cp_refill_rx(struct cp_private *cp)
1008 {
1009 struct net_device *dev = cp->dev;
1010 unsigned i;
1011
1012 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1013 struct sk_buff *skb;
1014 dma_addr_t mapping;
1015
1016 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1017 if (!skb)
1018 goto err_out;
1019
1020 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1021 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1022 cp->rx_skb[i] = skb;
1023
1024 cp->rx_ring[i].opts2 = 0;
1025 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1026 if (i == (CP_RX_RING_SIZE - 1))
1027 cp->rx_ring[i].opts1 =
1028 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1029 else
1030 cp->rx_ring[i].opts1 =
1031 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1032 }
1033
1034 return 0;
1035
1036 err_out:
1037 cp_clean_rings(cp);
1038 return -ENOMEM;
1039 }
1040
1041 static void cp_init_rings_index (struct cp_private *cp)
1042 {
1043 cp->rx_tail = 0;
1044 cp->tx_head = cp->tx_tail = 0;
1045 }
1046
1047 static int cp_init_rings (struct cp_private *cp)
1048 {
1049 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1050 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1051
1052 cp_init_rings_index(cp);
1053
1054 return cp_refill_rx (cp);
1055 }
1056
1057 static int cp_alloc_rings (struct cp_private *cp)
1058 {
1059 void *mem;
1060
1061 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1062 &cp->ring_dma, GFP_KERNEL);
1063 if (!mem)
1064 return -ENOMEM;
1065
1066 cp->rx_ring = mem;
1067 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1068
1069 return cp_init_rings(cp);
1070 }
1071
1072 static void cp_clean_rings (struct cp_private *cp)
1073 {
1074 struct cp_desc *desc;
1075 unsigned i;
1076
1077 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1078 if (cp->rx_skb[i]) {
1079 desc = cp->rx_ring + i;
1080 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1081 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1082 dev_kfree_skb(cp->rx_skb[i]);
1083 }
1084 }
1085
1086 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1087 if (cp->tx_skb[i]) {
1088 struct sk_buff *skb = cp->tx_skb[i];
1089
1090 desc = cp->tx_ring + i;
1091 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1092 le32_to_cpu(desc->opts1) & 0xffff,
1093 PCI_DMA_TODEVICE);
1094 if (le32_to_cpu(desc->opts1) & LastFrag)
1095 dev_kfree_skb(skb);
1096 cp->dev->stats.tx_dropped++;
1097 }
1098 }
1099
1100 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1101 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1102
1103 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1104 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1105 }
1106
1107 static void cp_free_rings (struct cp_private *cp)
1108 {
1109 cp_clean_rings(cp);
1110 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1111 cp->ring_dma);
1112 cp->rx_ring = NULL;
1113 cp->tx_ring = NULL;
1114 }
1115
1116 static int cp_open (struct net_device *dev)
1117 {
1118 struct cp_private *cp = netdev_priv(dev);
1119 int rc;
1120
1121 netif_dbg(cp, ifup, dev, "enabling interface\n");
1122
1123 rc = cp_alloc_rings(cp);
1124 if (rc)
1125 return rc;
1126
1127 napi_enable(&cp->napi);
1128
1129 cp_init_hw(cp);
1130
1131 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1132 if (rc)
1133 goto err_out_hw;
1134
1135 netif_carrier_off(dev);
1136 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1137 netif_start_queue(dev);
1138
1139 return 0;
1140
1141 err_out_hw:
1142 napi_disable(&cp->napi);
1143 cp_stop_hw(cp);
1144 cp_free_rings(cp);
1145 return rc;
1146 }
1147
1148 static int cp_close (struct net_device *dev)
1149 {
1150 struct cp_private *cp = netdev_priv(dev);
1151 unsigned long flags;
1152
1153 napi_disable(&cp->napi);
1154
1155 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1156
1157 spin_lock_irqsave(&cp->lock, flags);
1158
1159 netif_stop_queue(dev);
1160 netif_carrier_off(dev);
1161
1162 cp_stop_hw(cp);
1163
1164 spin_unlock_irqrestore(&cp->lock, flags);
1165
1166 free_irq(dev->irq, dev);
1167
1168 cp_free_rings(cp);
1169 return 0;
1170 }
1171
1172 static void cp_tx_timeout(struct net_device *dev)
1173 {
1174 struct cp_private *cp = netdev_priv(dev);
1175 unsigned long flags;
1176 int rc;
1177
1178 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1179 cpr8(Cmd), cpr16(CpCmd),
1180 cpr16(IntrStatus), cpr16(IntrMask));
1181
1182 spin_lock_irqsave(&cp->lock, flags);
1183
1184 cp_stop_hw(cp);
1185 cp_clean_rings(cp);
1186 rc = cp_init_rings(cp);
1187 cp_start_hw(cp);
1188
1189 netif_wake_queue(dev);
1190
1191 spin_unlock_irqrestore(&cp->lock, flags);
1192 }
1193
1194 #ifdef BROKEN
1195 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1196 {
1197 struct cp_private *cp = netdev_priv(dev);
1198 int rc;
1199 unsigned long flags;
1200
1201 /* check for invalid MTU, according to hardware limits */
1202 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1203 return -EINVAL;
1204
1205 /* if network interface not up, no need for complexity */
1206 if (!netif_running(dev)) {
1207 dev->mtu = new_mtu;
1208 cp_set_rxbufsize(cp); /* set new rx buf size */
1209 return 0;
1210 }
1211
1212 spin_lock_irqsave(&cp->lock, flags);
1213
1214 cp_stop_hw(cp); /* stop h/w and free rings */
1215 cp_clean_rings(cp);
1216
1217 dev->mtu = new_mtu;
1218 cp_set_rxbufsize(cp); /* set new rx buf size */
1219
1220 rc = cp_init_rings(cp); /* realloc and restart h/w */
1221 cp_start_hw(cp);
1222
1223 spin_unlock_irqrestore(&cp->lock, flags);
1224
1225 return rc;
1226 }
1227 #endif /* BROKEN */
1228
1229 static const char mii_2_8139_map[8] = {
1230 BasicModeCtrl,
1231 BasicModeStatus,
1232 0,
1233 0,
1234 NWayAdvert,
1235 NWayLPAR,
1236 NWayExpansion,
1237 0
1238 };
1239
1240 static int mdio_read(struct net_device *dev, int phy_id, int location)
1241 {
1242 struct cp_private *cp = netdev_priv(dev);
1243
1244 return location < 8 && mii_2_8139_map[location] ?
1245 readw(cp->regs + mii_2_8139_map[location]) : 0;
1246 }
1247
1248
1249 static void mdio_write(struct net_device *dev, int phy_id, int location,
1250 int value)
1251 {
1252 struct cp_private *cp = netdev_priv(dev);
1253
1254 if (location == 0) {
1255 cpw8(Cfg9346, Cfg9346_Unlock);
1256 cpw16(BasicModeCtrl, value);
1257 cpw8(Cfg9346, Cfg9346_Lock);
1258 } else if (location < 8 && mii_2_8139_map[location])
1259 cpw16(mii_2_8139_map[location], value);
1260 }
1261
1262 /* Set the ethtool Wake-on-LAN settings */
1263 static int netdev_set_wol (struct cp_private *cp,
1264 const struct ethtool_wolinfo *wol)
1265 {
1266 u8 options;
1267
1268 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1269 /* If WOL is being disabled, no need for complexity */
1270 if (wol->wolopts) {
1271 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1272 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1273 }
1274
1275 cpw8 (Cfg9346, Cfg9346_Unlock);
1276 cpw8 (Config3, options);
1277 cpw8 (Cfg9346, Cfg9346_Lock);
1278
1279 options = 0; /* Paranoia setting */
1280 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1281 /* If WOL is being disabled, no need for complexity */
1282 if (wol->wolopts) {
1283 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1284 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1285 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1286 }
1287
1288 cpw8 (Config5, options);
1289
1290 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1291
1292 return 0;
1293 }
1294
1295 /* Get the ethtool Wake-on-LAN settings */
1296 static void netdev_get_wol (struct cp_private *cp,
1297 struct ethtool_wolinfo *wol)
1298 {
1299 u8 options;
1300
1301 wol->wolopts = 0; /* Start from scratch */
1302 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1303 WAKE_MCAST | WAKE_UCAST;
1304 /* We don't need to go on if WOL is disabled */
1305 if (!cp->wol_enabled) return;
1306
1307 options = cpr8 (Config3);
1308 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1309 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1310
1311 options = 0; /* Paranoia setting */
1312 options = cpr8 (Config5);
1313 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1314 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1315 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1316 }
1317
1318 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1319 {
1320 struct cp_private *cp = netdev_priv(dev);
1321
1322 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1323 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1324 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
1325 }
1326
1327 static void cp_get_ringparam(struct net_device *dev,
1328 struct ethtool_ringparam *ring)
1329 {
1330 ring->rx_max_pending = CP_RX_RING_SIZE;
1331 ring->tx_max_pending = CP_TX_RING_SIZE;
1332 ring->rx_pending = CP_RX_RING_SIZE;
1333 ring->tx_pending = CP_TX_RING_SIZE;
1334 }
1335
1336 static int cp_get_regs_len(struct net_device *dev)
1337 {
1338 return CP_REGS_SIZE;
1339 }
1340
1341 static int cp_get_sset_count (struct net_device *dev, int sset)
1342 {
1343 switch (sset) {
1344 case ETH_SS_STATS:
1345 return CP_NUM_STATS;
1346 default:
1347 return -EOPNOTSUPP;
1348 }
1349 }
1350
1351 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1352 {
1353 struct cp_private *cp = netdev_priv(dev);
1354 int rc;
1355 unsigned long flags;
1356
1357 spin_lock_irqsave(&cp->lock, flags);
1358 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1359 spin_unlock_irqrestore(&cp->lock, flags);
1360
1361 return rc;
1362 }
1363
1364 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1365 {
1366 struct cp_private *cp = netdev_priv(dev);
1367 int rc;
1368 unsigned long flags;
1369
1370 spin_lock_irqsave(&cp->lock, flags);
1371 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1372 spin_unlock_irqrestore(&cp->lock, flags);
1373
1374 return rc;
1375 }
1376
1377 static int cp_nway_reset(struct net_device *dev)
1378 {
1379 struct cp_private *cp = netdev_priv(dev);
1380 return mii_nway_restart(&cp->mii_if);
1381 }
1382
1383 static u32 cp_get_msglevel(struct net_device *dev)
1384 {
1385 struct cp_private *cp = netdev_priv(dev);
1386 return cp->msg_enable;
1387 }
1388
1389 static void cp_set_msglevel(struct net_device *dev, u32 value)
1390 {
1391 struct cp_private *cp = netdev_priv(dev);
1392 cp->msg_enable = value;
1393 }
1394
1395 static int cp_set_features(struct net_device *dev, netdev_features_t features)
1396 {
1397 struct cp_private *cp = netdev_priv(dev);
1398 unsigned long flags;
1399
1400 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1401 return 0;
1402
1403 spin_lock_irqsave(&cp->lock, flags);
1404
1405 if (features & NETIF_F_RXCSUM)
1406 cp->cpcmd |= RxChkSum;
1407 else
1408 cp->cpcmd &= ~RxChkSum;
1409
1410 if (features & NETIF_F_HW_VLAN_RX)
1411 cp->cpcmd |= RxVlanOn;
1412 else
1413 cp->cpcmd &= ~RxVlanOn;
1414
1415 cpw16_f(CpCmd, cp->cpcmd);
1416 spin_unlock_irqrestore(&cp->lock, flags);
1417
1418 return 0;
1419 }
1420
1421 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1422 void *p)
1423 {
1424 struct cp_private *cp = netdev_priv(dev);
1425 unsigned long flags;
1426
1427 if (regs->len < CP_REGS_SIZE)
1428 return /* -EINVAL */;
1429
1430 regs->version = CP_REGS_VER;
1431
1432 spin_lock_irqsave(&cp->lock, flags);
1433 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1434 spin_unlock_irqrestore(&cp->lock, flags);
1435 }
1436
1437 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1438 {
1439 struct cp_private *cp = netdev_priv(dev);
1440 unsigned long flags;
1441
1442 spin_lock_irqsave (&cp->lock, flags);
1443 netdev_get_wol (cp, wol);
1444 spin_unlock_irqrestore (&cp->lock, flags);
1445 }
1446
1447 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1448 {
1449 struct cp_private *cp = netdev_priv(dev);
1450 unsigned long flags;
1451 int rc;
1452
1453 spin_lock_irqsave (&cp->lock, flags);
1454 rc = netdev_set_wol (cp, wol);
1455 spin_unlock_irqrestore (&cp->lock, flags);
1456
1457 return rc;
1458 }
1459
1460 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1461 {
1462 switch (stringset) {
1463 case ETH_SS_STATS:
1464 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1465 break;
1466 default:
1467 BUG();
1468 break;
1469 }
1470 }
1471
1472 static void cp_get_ethtool_stats (struct net_device *dev,
1473 struct ethtool_stats *estats, u64 *tmp_stats)
1474 {
1475 struct cp_private *cp = netdev_priv(dev);
1476 struct cp_dma_stats *nic_stats;
1477 dma_addr_t dma;
1478 int i;
1479
1480 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1481 &dma, GFP_KERNEL);
1482 if (!nic_stats)
1483 return;
1484
1485 /* begin NIC statistics dump */
1486 cpw32(StatsAddr + 4, (u64)dma >> 32);
1487 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1488 cpr32(StatsAddr);
1489
1490 for (i = 0; i < 1000; i++) {
1491 if ((cpr32(StatsAddr) & DumpStats) == 0)
1492 break;
1493 udelay(10);
1494 }
1495 cpw32(StatsAddr, 0);
1496 cpw32(StatsAddr + 4, 0);
1497 cpr32(StatsAddr);
1498
1499 i = 0;
1500 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1501 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1502 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1503 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1504 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1505 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1506 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1507 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1508 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1509 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1510 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1511 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1512 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1513 tmp_stats[i++] = cp->cp_stats.rx_frags;
1514 BUG_ON(i != CP_NUM_STATS);
1515
1516 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1517 }
1518
1519 static const struct ethtool_ops cp_ethtool_ops = {
1520 .get_drvinfo = cp_get_drvinfo,
1521 .get_regs_len = cp_get_regs_len,
1522 .get_sset_count = cp_get_sset_count,
1523 .get_settings = cp_get_settings,
1524 .set_settings = cp_set_settings,
1525 .nway_reset = cp_nway_reset,
1526 .get_link = ethtool_op_get_link,
1527 .get_msglevel = cp_get_msglevel,
1528 .set_msglevel = cp_set_msglevel,
1529 .get_regs = cp_get_regs,
1530 .get_wol = cp_get_wol,
1531 .set_wol = cp_set_wol,
1532 .get_strings = cp_get_strings,
1533 .get_ethtool_stats = cp_get_ethtool_stats,
1534 .get_eeprom_len = cp_get_eeprom_len,
1535 .get_eeprom = cp_get_eeprom,
1536 .set_eeprom = cp_set_eeprom,
1537 .get_ringparam = cp_get_ringparam,
1538 };
1539
1540 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1541 {
1542 struct cp_private *cp = netdev_priv(dev);
1543 int rc;
1544 unsigned long flags;
1545
1546 if (!netif_running(dev))
1547 return -EINVAL;
1548
1549 spin_lock_irqsave(&cp->lock, flags);
1550 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1551 spin_unlock_irqrestore(&cp->lock, flags);
1552 return rc;
1553 }
1554
1555 static int cp_set_mac_address(struct net_device *dev, void *p)
1556 {
1557 struct cp_private *cp = netdev_priv(dev);
1558 struct sockaddr *addr = p;
1559
1560 if (!is_valid_ether_addr(addr->sa_data))
1561 return -EADDRNOTAVAIL;
1562
1563 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1564
1565 spin_lock_irq(&cp->lock);
1566
1567 cpw8_f(Cfg9346, Cfg9346_Unlock);
1568 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1569 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1570 cpw8_f(Cfg9346, Cfg9346_Lock);
1571
1572 spin_unlock_irq(&cp->lock);
1573
1574 return 0;
1575 }
1576
1577 /* Serial EEPROM section. */
1578
1579 /* EEPROM_Ctrl bits. */
1580 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1581 #define EE_CS 0x08 /* EEPROM chip select. */
1582 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1583 #define EE_WRITE_0 0x00
1584 #define EE_WRITE_1 0x02
1585 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1586 #define EE_ENB (0x80 | EE_CS)
1587
1588 /* Delay between EEPROM clock transitions.
1589 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1590 */
1591
1592 #define eeprom_delay() readb(ee_addr)
1593
1594 /* The EEPROM commands include the alway-set leading bit. */
1595 #define EE_EXTEND_CMD (4)
1596 #define EE_WRITE_CMD (5)
1597 #define EE_READ_CMD (6)
1598 #define EE_ERASE_CMD (7)
1599
1600 #define EE_EWDS_ADDR (0)
1601 #define EE_WRAL_ADDR (1)
1602 #define EE_ERAL_ADDR (2)
1603 #define EE_EWEN_ADDR (3)
1604
1605 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1606
1607 static void eeprom_cmd_start(void __iomem *ee_addr)
1608 {
1609 writeb (EE_ENB & ~EE_CS, ee_addr);
1610 writeb (EE_ENB, ee_addr);
1611 eeprom_delay ();
1612 }
1613
1614 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1615 {
1616 int i;
1617
1618 /* Shift the command bits out. */
1619 for (i = cmd_len - 1; i >= 0; i--) {
1620 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1621 writeb (EE_ENB | dataval, ee_addr);
1622 eeprom_delay ();
1623 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1624 eeprom_delay ();
1625 }
1626 writeb (EE_ENB, ee_addr);
1627 eeprom_delay ();
1628 }
1629
1630 static void eeprom_cmd_end(void __iomem *ee_addr)
1631 {
1632 writeb (~EE_CS, ee_addr);
1633 eeprom_delay ();
1634 }
1635
1636 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1637 int addr_len)
1638 {
1639 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1640
1641 eeprom_cmd_start(ee_addr);
1642 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1643 eeprom_cmd_end(ee_addr);
1644 }
1645
1646 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1647 {
1648 int i;
1649 u16 retval = 0;
1650 void __iomem *ee_addr = ioaddr + Cfg9346;
1651 int read_cmd = location | (EE_READ_CMD << addr_len);
1652
1653 eeprom_cmd_start(ee_addr);
1654 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1655
1656 for (i = 16; i > 0; i--) {
1657 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1658 eeprom_delay ();
1659 retval =
1660 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1661 0);
1662 writeb (EE_ENB, ee_addr);
1663 eeprom_delay ();
1664 }
1665
1666 eeprom_cmd_end(ee_addr);
1667
1668 return retval;
1669 }
1670
1671 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1672 int addr_len)
1673 {
1674 int i;
1675 void __iomem *ee_addr = ioaddr + Cfg9346;
1676 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1677
1678 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1679
1680 eeprom_cmd_start(ee_addr);
1681 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1682 eeprom_cmd(ee_addr, val, 16);
1683 eeprom_cmd_end(ee_addr);
1684
1685 eeprom_cmd_start(ee_addr);
1686 for (i = 0; i < 20000; i++)
1687 if (readb(ee_addr) & EE_DATA_READ)
1688 break;
1689 eeprom_cmd_end(ee_addr);
1690
1691 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1692 }
1693
1694 static int cp_get_eeprom_len(struct net_device *dev)
1695 {
1696 struct cp_private *cp = netdev_priv(dev);
1697 int size;
1698
1699 spin_lock_irq(&cp->lock);
1700 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1701 spin_unlock_irq(&cp->lock);
1702
1703 return size;
1704 }
1705
1706 static int cp_get_eeprom(struct net_device *dev,
1707 struct ethtool_eeprom *eeprom, u8 *data)
1708 {
1709 struct cp_private *cp = netdev_priv(dev);
1710 unsigned int addr_len;
1711 u16 val;
1712 u32 offset = eeprom->offset >> 1;
1713 u32 len = eeprom->len;
1714 u32 i = 0;
1715
1716 eeprom->magic = CP_EEPROM_MAGIC;
1717
1718 spin_lock_irq(&cp->lock);
1719
1720 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1721
1722 if (eeprom->offset & 1) {
1723 val = read_eeprom(cp->regs, offset, addr_len);
1724 data[i++] = (u8)(val >> 8);
1725 offset++;
1726 }
1727
1728 while (i < len - 1) {
1729 val = read_eeprom(cp->regs, offset, addr_len);
1730 data[i++] = (u8)val;
1731 data[i++] = (u8)(val >> 8);
1732 offset++;
1733 }
1734
1735 if (i < len) {
1736 val = read_eeprom(cp->regs, offset, addr_len);
1737 data[i] = (u8)val;
1738 }
1739
1740 spin_unlock_irq(&cp->lock);
1741 return 0;
1742 }
1743
1744 static int cp_set_eeprom(struct net_device *dev,
1745 struct ethtool_eeprom *eeprom, u8 *data)
1746 {
1747 struct cp_private *cp = netdev_priv(dev);
1748 unsigned int addr_len;
1749 u16 val;
1750 u32 offset = eeprom->offset >> 1;
1751 u32 len = eeprom->len;
1752 u32 i = 0;
1753
1754 if (eeprom->magic != CP_EEPROM_MAGIC)
1755 return -EINVAL;
1756
1757 spin_lock_irq(&cp->lock);
1758
1759 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1760
1761 if (eeprom->offset & 1) {
1762 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1763 val |= (u16)data[i++] << 8;
1764 write_eeprom(cp->regs, offset, val, addr_len);
1765 offset++;
1766 }
1767
1768 while (i < len - 1) {
1769 val = (u16)data[i++];
1770 val |= (u16)data[i++] << 8;
1771 write_eeprom(cp->regs, offset, val, addr_len);
1772 offset++;
1773 }
1774
1775 if (i < len) {
1776 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1777 val |= (u16)data[i];
1778 write_eeprom(cp->regs, offset, val, addr_len);
1779 }
1780
1781 spin_unlock_irq(&cp->lock);
1782 return 0;
1783 }
1784
1785 /* Put the board into D3cold state and wait for WakeUp signal */
1786 static void cp_set_d3_state (struct cp_private *cp)
1787 {
1788 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1789 pci_set_power_state (cp->pdev, PCI_D3hot);
1790 }
1791
1792 static const struct net_device_ops cp_netdev_ops = {
1793 .ndo_open = cp_open,
1794 .ndo_stop = cp_close,
1795 .ndo_validate_addr = eth_validate_addr,
1796 .ndo_set_mac_address = cp_set_mac_address,
1797 .ndo_set_rx_mode = cp_set_rx_mode,
1798 .ndo_get_stats = cp_get_stats,
1799 .ndo_do_ioctl = cp_ioctl,
1800 .ndo_start_xmit = cp_start_xmit,
1801 .ndo_tx_timeout = cp_tx_timeout,
1802 .ndo_set_features = cp_set_features,
1803 #ifdef BROKEN
1804 .ndo_change_mtu = cp_change_mtu,
1805 #endif
1806
1807 #ifdef CONFIG_NET_POLL_CONTROLLER
1808 .ndo_poll_controller = cp_poll_controller,
1809 #endif
1810 };
1811
1812 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1813 {
1814 struct net_device *dev;
1815 struct cp_private *cp;
1816 int rc;
1817 void __iomem *regs;
1818 resource_size_t pciaddr;
1819 unsigned int addr_len, i, pci_using_dac;
1820
1821 #ifndef MODULE
1822 static int version_printed;
1823 if (version_printed++ == 0)
1824 pr_info("%s", version);
1825 #endif
1826
1827 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1828 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1829 dev_info(&pdev->dev,
1830 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1831 pdev->vendor, pdev->device, pdev->revision);
1832 return -ENODEV;
1833 }
1834
1835 dev = alloc_etherdev(sizeof(struct cp_private));
1836 if (!dev)
1837 return -ENOMEM;
1838 SET_NETDEV_DEV(dev, &pdev->dev);
1839
1840 cp = netdev_priv(dev);
1841 cp->pdev = pdev;
1842 cp->dev = dev;
1843 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1844 spin_lock_init (&cp->lock);
1845 cp->mii_if.dev = dev;
1846 cp->mii_if.mdio_read = mdio_read;
1847 cp->mii_if.mdio_write = mdio_write;
1848 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1849 cp->mii_if.phy_id_mask = 0x1f;
1850 cp->mii_if.reg_num_mask = 0x1f;
1851 cp_set_rxbufsize(cp);
1852
1853 rc = pci_enable_device(pdev);
1854 if (rc)
1855 goto err_out_free;
1856
1857 rc = pci_set_mwi(pdev);
1858 if (rc)
1859 goto err_out_disable;
1860
1861 rc = pci_request_regions(pdev, DRV_NAME);
1862 if (rc)
1863 goto err_out_mwi;
1864
1865 pciaddr = pci_resource_start(pdev, 1);
1866 if (!pciaddr) {
1867 rc = -EIO;
1868 dev_err(&pdev->dev, "no MMIO resource\n");
1869 goto err_out_res;
1870 }
1871 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1872 rc = -EIO;
1873 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1874 (unsigned long long)pci_resource_len(pdev, 1));
1875 goto err_out_res;
1876 }
1877
1878 /* Configure DMA attributes. */
1879 if ((sizeof(dma_addr_t) > 4) &&
1880 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1881 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1882 pci_using_dac = 1;
1883 } else {
1884 pci_using_dac = 0;
1885
1886 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1887 if (rc) {
1888 dev_err(&pdev->dev,
1889 "No usable DMA configuration, aborting\n");
1890 goto err_out_res;
1891 }
1892 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1893 if (rc) {
1894 dev_err(&pdev->dev,
1895 "No usable consistent DMA configuration, aborting\n");
1896 goto err_out_res;
1897 }
1898 }
1899
1900 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1901 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1902
1903 dev->features |= NETIF_F_RXCSUM;
1904 dev->hw_features |= NETIF_F_RXCSUM;
1905
1906 regs = ioremap(pciaddr, CP_REGS_SIZE);
1907 if (!regs) {
1908 rc = -EIO;
1909 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1910 (unsigned long long)pci_resource_len(pdev, 1),
1911 (unsigned long long)pciaddr);
1912 goto err_out_res;
1913 }
1914 dev->base_addr = (unsigned long) regs;
1915 cp->regs = regs;
1916
1917 cp_stop_hw(cp);
1918
1919 /* read MAC address from EEPROM */
1920 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1921 for (i = 0; i < 3; i++)
1922 ((__le16 *) (dev->dev_addr))[i] =
1923 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1924 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1925
1926 dev->netdev_ops = &cp_netdev_ops;
1927 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1928 dev->ethtool_ops = &cp_ethtool_ops;
1929 dev->watchdog_timeo = TX_TIMEOUT;
1930
1931 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1932
1933 if (pci_using_dac)
1934 dev->features |= NETIF_F_HIGHDMA;
1935
1936 /* disabled by default until verified */
1937 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1938 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1939 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1940 NETIF_F_HIGHDMA;
1941
1942 dev->irq = pdev->irq;
1943
1944 rc = register_netdev(dev);
1945 if (rc)
1946 goto err_out_iomap;
1947
1948 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1949 dev->base_addr, dev->dev_addr, dev->irq);
1950
1951 pci_set_drvdata(pdev, dev);
1952
1953 /* enable busmastering and memory-write-invalidate */
1954 pci_set_master(pdev);
1955
1956 if (cp->wol_enabled)
1957 cp_set_d3_state (cp);
1958
1959 return 0;
1960
1961 err_out_iomap:
1962 iounmap(regs);
1963 err_out_res:
1964 pci_release_regions(pdev);
1965 err_out_mwi:
1966 pci_clear_mwi(pdev);
1967 err_out_disable:
1968 pci_disable_device(pdev);
1969 err_out_free:
1970 free_netdev(dev);
1971 return rc;
1972 }
1973
1974 static void cp_remove_one (struct pci_dev *pdev)
1975 {
1976 struct net_device *dev = pci_get_drvdata(pdev);
1977 struct cp_private *cp = netdev_priv(dev);
1978
1979 unregister_netdev(dev);
1980 iounmap(cp->regs);
1981 if (cp->wol_enabled)
1982 pci_set_power_state (pdev, PCI_D0);
1983 pci_release_regions(pdev);
1984 pci_clear_mwi(pdev);
1985 pci_disable_device(pdev);
1986 pci_set_drvdata(pdev, NULL);
1987 free_netdev(dev);
1988 }
1989
1990 #ifdef CONFIG_PM
1991 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1992 {
1993 struct net_device *dev = pci_get_drvdata(pdev);
1994 struct cp_private *cp = netdev_priv(dev);
1995 unsigned long flags;
1996
1997 if (!netif_running(dev))
1998 return 0;
1999
2000 netif_device_detach (dev);
2001 netif_stop_queue (dev);
2002
2003 spin_lock_irqsave (&cp->lock, flags);
2004
2005 /* Disable Rx and Tx */
2006 cpw16 (IntrMask, 0);
2007 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2008
2009 spin_unlock_irqrestore (&cp->lock, flags);
2010
2011 pci_save_state(pdev);
2012 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2013 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2014
2015 return 0;
2016 }
2017
2018 static int cp_resume (struct pci_dev *pdev)
2019 {
2020 struct net_device *dev = pci_get_drvdata (pdev);
2021 struct cp_private *cp = netdev_priv(dev);
2022 unsigned long flags;
2023
2024 if (!netif_running(dev))
2025 return 0;
2026
2027 netif_device_attach (dev);
2028
2029 pci_set_power_state(pdev, PCI_D0);
2030 pci_restore_state(pdev);
2031 pci_enable_wake(pdev, PCI_D0, 0);
2032
2033 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2034 cp_init_rings_index (cp);
2035 cp_init_hw (cp);
2036 netif_start_queue (dev);
2037
2038 spin_lock_irqsave (&cp->lock, flags);
2039
2040 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2041
2042 spin_unlock_irqrestore (&cp->lock, flags);
2043
2044 return 0;
2045 }
2046 #endif /* CONFIG_PM */
2047
2048 static struct pci_driver cp_driver = {
2049 .name = DRV_NAME,
2050 .id_table = cp_pci_tbl,
2051 .probe = cp_init_one,
2052 .remove = cp_remove_one,
2053 #ifdef CONFIG_PM
2054 .resume = cp_resume,
2055 .suspend = cp_suspend,
2056 #endif
2057 };
2058
2059 static int __init cp_init (void)
2060 {
2061 #ifdef MODULE
2062 pr_info("%s", version);
2063 #endif
2064 return pci_register_driver(&cp_driver);
2065 }
2066
2067 static void __exit cp_exit (void)
2068 {
2069 pci_unregister_driver (&cp_driver);
2070 }
2071
2072 module_init(cp_init);
2073 module_exit(cp_exit);
Linux 2.6 libata-dev (mirror)