drivers/staging/brcm80211/phy/wlc_phy_int.h

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef _wlc_phy_int_h_
  18 #define _wlc_phy_int_h_
  19
  20 #include <typedefs.h>
  21 #include <bcmutils.h>
  22
  23 #include <bcmsrom_fmt.h>
  24 #include <wlc_phy_hal.h>
  25
  26 #define PHYHAL_ERROR    0x0001
  27 #define PHYHAL_TRACE    0x0002
  28 #define PHYHAL_INFORM   0x0004
  29
  30 extern uint32 phyhal_msg_level;
  31
  32 #define PHY_INFORM_ON()         (phyhal_msg_level & PHYHAL_INFORM)
  33 #define PHY_THERMAL_ON()        (phyhal_msg_level & PHYHAL_THERMAL)
  34 #define PHY_CAL_ON()            (phyhal_msg_level & PHYHAL_CAL)
  35
  36 #ifdef BOARD_TYPE
  37 #define BOARDTYPE(_type) BOARD_TYPE
  38 #else
  39 #define BOARDTYPE(_type) _type
  40 #endif
  41
  42 #define LCNXN_BASEREV           16
  43
  44 struct wlc_hw_info;
  45 typedef struct phy_info phy_info_t;
  46 typedef void (*initfn_t) (phy_info_t *);
  47 typedef void (*chansetfn_t) (phy_info_t *, chanspec_t);
  48 typedef int (*longtrnfn_t) (phy_info_t *, int);
  49 typedef void (*txiqccgetfn_t) (phy_info_t *, uint16 *, uint16 *);
  50 typedef void (*txiqccsetfn_t) (phy_info_t *, uint16, uint16);
  51 typedef uint16(*txloccgetfn_t) (phy_info_t *);
  52 typedef void (*radioloftgetfn_t) (phy_info_t *, uint8 *, uint8 *, uint8 *,
  53                                   uint8 *);
  54 typedef int32(*rxsigpwrfn_t) (phy_info_t *, int32);
  55 typedef void (*detachfn_t) (phy_info_t *);
  56
  57 #undef ISNPHY
  58 #undef ISLCNPHY
  59 #define ISNPHY(pi)      PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
  60 #define ISLCNPHY(pi)    PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
  61
  62 #define ISPHY_11N_CAP(pi)       (ISNPHY(pi) || ISLCNPHY(pi))
  63
  64 #define IS20MHZ(pi)     ((pi)->bw == WL_CHANSPEC_BW_20)
  65 #define IS40MHZ(pi)     ((pi)->bw == WL_CHANSPEC_BW_40)
  66
  67 #define PHY_GET_RFATTN(rfgain)  ((rfgain) & 0x0f)
  68 #define PHY_GET_PADMIX(rfgain)  (((rfgain) & 0x10) >> 4)
  69 #define PHY_GET_RFGAINID(rfattn, padmix, width) ((rfattn) + ((padmix)*(width)))
  70 #define PHY_SAT(x, n)           ((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
  71                                 ((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
  72 #define PHY_SHIFT_ROUND(x, n)   ((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
  73 #define PHY_HW_ROUND(x, s)              ((x >> s) + ((x >> (s-1)) & (s != 0)))
  74
  75 #define CH_5G_GROUP     3
  76 #define A_LOW_CHANS     0
  77 #define A_MID_CHANS     1
  78 #define A_HIGH_CHANS    2
  79 #define CH_2G_GROUP     1
  80 #define G_ALL_CHANS     0
  81
  82 #define FIRST_REF5_CHANNUM      149
  83 #define LAST_REF5_CHANNUM       165
  84 #define FIRST_5G_CHAN           14
  85 #define LAST_5G_CHAN            50
  86 #define FIRST_MID_5G_CHAN       14
  87 #define LAST_MID_5G_CHAN        35
  88 #define FIRST_HIGH_5G_CHAN      36
  89 #define LAST_HIGH_5G_CHAN       41
  90 #define FIRST_LOW_5G_CHAN       42
  91 #define LAST_LOW_5G_CHAN        50
  92
  93 #define BASE_LOW_5G_CHAN        4900
  94 #define BASE_MID_5G_CHAN        5100
  95 #define BASE_HIGH_5G_CHAN       5500
  96
  97 #define CHAN5G_FREQ(chan)  (5000 + chan*5)
  98 #define CHAN2G_FREQ(chan)  (2407 + chan*5)
  99
 100 #define TXP_FIRST_CCK           0
 101 #define TXP_LAST_CCK            3
 102 #define TXP_FIRST_OFDM          4
 103 #define TXP_LAST_OFDM           11
 104 #define TXP_FIRST_OFDM_20_CDD   12
 105 #define TXP_LAST_OFDM_20_CDD    19
 106 #define TXP_FIRST_MCS_20_SISO   20
 107 #define TXP_LAST_MCS_20_SISO    27
 108 #define TXP_FIRST_MCS_20_CDD    28
 109 #define TXP_LAST_MCS_20_CDD     35
 110 #define TXP_FIRST_MCS_20_STBC   36
 111 #define TXP_LAST_MCS_20_STBC    43
 112 #define TXP_FIRST_MCS_20_SDM    44
 113 #define TXP_LAST_MCS_20_SDM     51
 114 #define TXP_FIRST_OFDM_40_SISO  52
 115 #define TXP_LAST_OFDM_40_SISO   59
 116 #define TXP_FIRST_OFDM_40_CDD   60
 117 #define TXP_LAST_OFDM_40_CDD    67
 118 #define TXP_FIRST_MCS_40_SISO   68
 119 #define TXP_LAST_MCS_40_SISO    75
 120 #define TXP_FIRST_MCS_40_CDD    76
 121 #define TXP_LAST_MCS_40_CDD     83
 122 #define TXP_FIRST_MCS_40_STBC   84
 123 #define TXP_LAST_MCS_40_STBC    91
 124 #define TXP_FIRST_MCS_40_SDM    92
 125 #define TXP_LAST_MCS_40_SDM     99
 126 #define TXP_MCS_32              100
 127 #define TXP_NUM_RATES           101
 128 #define ADJ_PWR_TBL_LEN         84
 129
 130 #define TXP_FIRST_SISO_MCS_20   20
 131 #define TXP_LAST_SISO_MCS_20    27
 132
 133 #define PHY_CORE_NUM_1  1
 134 #define PHY_CORE_NUM_2  2
 135 #define PHY_CORE_NUM_3  3
 136 #define PHY_CORE_NUM_4  4
 137 #define PHY_CORE_MAX    PHY_CORE_NUM_4
 138 #define PHY_CORE_0      0
 139 #define PHY_CORE_1      1
 140 #define PHY_CORE_2      2
 141 #define PHY_CORE_3      3
 142
 143 #define MA_WINDOW_SZ            8
 144
 145 #define PHY_NOISE_SAMPLE_MON            1
 146 #define PHY_NOISE_SAMPLE_EXTERNAL       2
 147 #define PHY_NOISE_WINDOW_SZ     16
 148 #define PHY_NOISE_GLITCH_INIT_MA 10
 149 #define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
 150 #define PHY_NOISE_STATE_MON             0x1
 151 #define PHY_NOISE_STATE_EXTERNAL        0x2
 152 #define PHY_NOISE_SAMPLE_LOG_NUM_NPHY   10
 153 #define PHY_NOISE_SAMPLE_LOG_NUM_UCODE  9
 154
 155 #define PHY_NOISE_OFFSETFACT_4322  (-103)
 156 #define PHY_NOISE_MA_WINDOW_SZ  2
 157
 158 #define PHY_RSSI_TABLE_SIZE     64
 159 #define RSSI_ANT_MERGE_MAX      0
 160 #define RSSI_ANT_MERGE_MIN      1
 161 #define RSSI_ANT_MERGE_AVG      2
 162
 163 #define PHY_TSSI_TABLE_SIZE     64
 164 #define APHY_TSSI_TABLE_SIZE    256
 165 #define TX_GAIN_TABLE_LENGTH    64
 166 #define DEFAULT_11A_TXP_IDX     24
 167 #define NUM_TSSI_FRAMES        4
 168 #define NULL_TSSI               0x7f
 169 #define NULL_TSSI_W             0x7f7f
 170
 171 #define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
 172
 173 #define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
 174
 175 #define PHY_TXPWR_MIN           10
 176 #define PHY_TXPWR_MIN_NPHY      8
 177 #define RADIOPWR_OVERRIDE_DEF   (-1)
 178
 179 #define PWRTBL_NUM_COEFF        3
 180
 181 #define SPURAVOID_DISABLE       0
 182 #define SPURAVOID_AUTO          1
 183 #define SPURAVOID_FORCEON       2
 184 #define SPURAVOID_FORCEON2      3
 185
 186 #define PHY_SW_TIMER_FAST               15
 187 #define PHY_SW_TIMER_SLOW               60
 188 #define PHY_SW_TIMER_GLACIAL    120
 189
 190 #define PHY_PERICAL_AUTO        0
 191 #define PHY_PERICAL_FULL        1
 192 #define PHY_PERICAL_PARTIAL     2
 193
 194 #define PHY_PERICAL_NODELAY     0
 195 #define PHY_PERICAL_INIT_DELAY  5
 196 #define PHY_PERICAL_ASSOC_DELAY 5
 197 #define PHY_PERICAL_WDOG_DELAY  5
 198
 199 #define MPHASE_TXCAL_NUMCMDS    2
 200 #define PHY_PERICAL_MPHASE_PENDING(pi)  (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
 201
 202 enum {
 203         MPHASE_CAL_STATE_IDLE = 0,
 204         MPHASE_CAL_STATE_INIT = 1,
 205         MPHASE_CAL_STATE_TXPHASE0,
 206         MPHASE_CAL_STATE_TXPHASE1,
 207         MPHASE_CAL_STATE_TXPHASE2,
 208         MPHASE_CAL_STATE_TXPHASE3,
 209         MPHASE_CAL_STATE_TXPHASE4,
 210         MPHASE_CAL_STATE_TXPHASE5,
 211         MPHASE_CAL_STATE_PAPDCAL,
 212         MPHASE_CAL_STATE_RXCAL,
 213         MPHASE_CAL_STATE_RSSICAL,
 214         MPHASE_CAL_STATE_IDLETSSI
 215 };
 216
 217 typedef enum {
 218         CAL_FULL,
 219         CAL_RECAL,
 220         CAL_CURRECAL,
 221         CAL_DIGCAL,
 222         CAL_GCTRL,
 223         CAL_SOFT,
 224         CAL_DIGLO
 225 } phy_cal_mode_t;
 226
 227 #define RDR_NTIERS  1
 228 #define RDR_TIER_SIZE 64
 229 #define RDR_LIST_SIZE 512/3
 230 #define RDR_EPOCH_SIZE 40
 231 #define RDR_NANTENNAS 2
 232 #define RDR_NTIER_SIZE  RDR_LIST_SIZE
 233 #define RDR_LP_BUFFER_SIZE 64
 234 #define LP_LEN_HIS_SIZE 10
 235
 236 #define STATIC_NUM_RF 32
 237 #define STATIC_NUM_BB 9
 238
 239 #define BB_MULT_MASK            0x0000ffff
 240 #define BB_MULT_VALID_MASK      0x80000000
 241
 242 #define CORDIC_AG       39797
 243 #define CORDIC_NI       18
 244 #define FIXED(X)        ((int32)((X) << 16))
 245 #define FLOAT(X)        (((X) >= 0) ? ((((X) >> 15) + 1) >> 1) : -((((-(X)) >> 15) + 1) >> 1))
 246
 247 #define PHY_CHAIN_TX_DISABLE_TEMP       115
 248 #define PHY_HYSTERESIS_DELTATEMP        5
 249
 250 #define PHY_BITSCNT(x)  bcm_bitcount((uint8 *)&(x), sizeof(uint8))
 251
 252 #define MOD_PHY_REG(pi, phy_type, reg_name, field, value) \
 253         mod_phy_reg(pi, phy_type##_##reg_name, phy_type##_##reg_name##_##field##_MASK, \
 254         (value) << phy_type##_##reg_name##_##field##_##SHIFT);
 255 #define READ_PHY_REG(pi, phy_type, reg_name, field) \
 256         ((read_phy_reg(pi, phy_type##_##reg_name) & phy_type##_##reg_name##_##field##_##MASK)\
 257         >> phy_type##_##reg_name##_##field##_##SHIFT)
 258
 259 #define VALID_PHYTYPE(phytype)  (((uint)phytype == PHY_TYPE_N) || \
 260                                 ((uint)phytype == PHY_TYPE_LCN))
 261
 262 #define VALID_N_RADIO(radioid)  ((radioid == BCM2055_ID) || (radioid == BCM2056_ID) || \
 263                                 (radioid == BCM2057_ID))
 264 #define VALID_LCN_RADIO(radioid)        (radioid == BCM2064_ID)
 265
 266 #define VALID_RADIO(pi, radioid)        (\
 267         (ISNPHY(pi) ? VALID_N_RADIO(radioid) : FALSE) || \
 268         (ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : FALSE))
 269
 270 #define SCAN_INPROG_PHY(pi)     (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
 271 #define RM_INPROG_PHY(pi)       (mboolisset(pi->measure_hold, PHY_HOLD_FOR_RM))
 272 #define PLT_INPROG_PHY(pi)      (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
 273 #define ASSOC_INPROG_PHY(pi)    (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
 274 #define SCAN_RM_IN_PROGRESS(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
 275 #define PHY_MUTED(pi)           (mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
 276 #define PUB_NOT_ASSOC(pi)       (mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
 277
 278 #if defined(EXT_CBALL)
 279 #define NORADIO_ENAB(pub) ((pub).radioid == NORADIO_ID)
 280 #else
 281 #define NORADIO_ENAB(pub) 0
 282 #endif
 283
 284 #define PHY_LTRN_LIST_LEN       64
 285 extern uint16 ltrn_list[PHY_LTRN_LIST_LEN];
 286
 287 typedef struct _phy_table_info {
 288         uint table;
 289         int q;
 290         uint max;
 291 } phy_table_info_t;
 292
 293 typedef struct phytbl_info {
 294         const void *tbl_ptr;
 295         uint32 tbl_len;
 296         uint32 tbl_id;
 297         uint32 tbl_offset;
 298         uint32 tbl_width;
 299 } phytbl_info_t;
 300
 301 typedef struct {
 302         uint8 curr_home_channel;
 303         uint16 crsminpwrthld_40_stored;
 304         uint16 crsminpwrthld_20L_stored;
 305         uint16 crsminpwrthld_20U_stored;
 306         uint16 init_gain_code_core1_stored;
 307         uint16 init_gain_code_core2_stored;
 308         uint16 init_gain_codeb_core1_stored;
 309         uint16 init_gain_codeb_core2_stored;
 310         uint16 init_gain_table_stored[4];
 311
 312         uint16 clip1_hi_gain_code_core1_stored;
 313         uint16 clip1_hi_gain_code_core2_stored;
 314         uint16 clip1_hi_gain_codeb_core1_stored;
 315         uint16 clip1_hi_gain_codeb_core2_stored;
 316         uint16 nb_clip_thresh_core1_stored;
 317         uint16 nb_clip_thresh_core2_stored;
 318         uint16 init_ofdmlna2gainchange_stored[4];
 319         uint16 init_ccklna2gainchange_stored[4];
 320         uint16 clip1_lo_gain_code_core1_stored;
 321         uint16 clip1_lo_gain_code_core2_stored;
 322         uint16 clip1_lo_gain_codeb_core1_stored;
 323         uint16 clip1_lo_gain_codeb_core2_stored;
 324         uint16 w1_clip_thresh_core1_stored;
 325         uint16 w1_clip_thresh_core2_stored;
 326         uint16 radio_2056_core1_rssi_gain_stored;
 327         uint16 radio_2056_core2_rssi_gain_stored;
 328         uint16 energy_drop_timeout_len_stored;
 329
 330         uint16 ed_crs40_assertthld0_stored;
 331         uint16 ed_crs40_assertthld1_stored;
 332         uint16 ed_crs40_deassertthld0_stored;
 333         uint16 ed_crs40_deassertthld1_stored;
 334         uint16 ed_crs20L_assertthld0_stored;
 335         uint16 ed_crs20L_assertthld1_stored;
 336         uint16 ed_crs20L_deassertthld0_stored;
 337         uint16 ed_crs20L_deassertthld1_stored;
 338         uint16 ed_crs20U_assertthld0_stored;
 339         uint16 ed_crs20U_assertthld1_stored;
 340         uint16 ed_crs20U_deassertthld0_stored;
 341         uint16 ed_crs20U_deassertthld1_stored;
 342
 343         uint16 badplcp_ma;
 344         uint16 badplcp_ma_previous;
 345         uint16 badplcp_ma_total;
 346         uint16 badplcp_ma_list[MA_WINDOW_SZ];
 347         int badplcp_ma_index;
 348         int16 pre_badplcp_cnt;
 349         int16 bphy_pre_badplcp_cnt;
 350
 351         uint16 init_gain_core1;
 352         uint16 init_gain_core2;
 353         uint16 init_gainb_core1;
 354         uint16 init_gainb_core2;
 355         uint16 init_gain_rfseq[4];
 356
 357         uint16 crsminpwr0;
 358         uint16 crsminpwrl0;
 359         uint16 crsminpwru0;
 360
 361         int16 crsminpwr_index;
 362
 363         uint16 radio_2057_core1_rssi_wb1a_gc_stored;
 364         uint16 radio_2057_core2_rssi_wb1a_gc_stored;
 365         uint16 radio_2057_core1_rssi_wb1g_gc_stored;
 366         uint16 radio_2057_core2_rssi_wb1g_gc_stored;
 367         uint16 radio_2057_core1_rssi_wb2_gc_stored;
 368         uint16 radio_2057_core2_rssi_wb2_gc_stored;
 369         uint16 radio_2057_core1_rssi_nb_gc_stored;
 370         uint16 radio_2057_core2_rssi_nb_gc_stored;
 371
 372 } interference_info_t;
 373
 374 typedef struct {
 375         uint16 rc_cal_ovr;
 376         uint16 phycrsth1;
 377         uint16 phycrsth2;
 378         uint16 init_n1p1_gain;
 379         uint16 p1_p2_gain;
 380         uint16 n1_n2_gain;
 381         uint16 n1_p1_gain;
 382         uint16 div_search_gain;
 383         uint16 div_p1_p2_gain;
 384         uint16 div_search_gn_change;
 385         uint16 table_7_2;
 386         uint16 table_7_3;
 387         uint16 cckshbits_gnref;
 388         uint16 clip_thresh;
 389         uint16 clip2_thresh;
 390         uint16 clip3_thresh;
 391         uint16 clip_p2_thresh;
 392         uint16 clip_pwdn_thresh;
 393         uint16 clip_n1p1_thresh;
 394         uint16 clip_n1_pwdn_thresh;
 395         uint16 bbconfig;
 396         uint16 cthr_sthr_shdin;
 397         uint16 energy;
 398         uint16 clip_p1_p2_thresh;
 399         uint16 threshold;
 400         uint16 reg15;
 401         uint16 reg16;
 402         uint16 reg17;
 403         uint16 div_srch_idx;
 404         uint16 div_srch_p1_p2;
 405         uint16 div_srch_gn_back;
 406         uint16 ant_dwell;
 407         uint16 ant_wr_settle;
 408 } aci_save_gphy_t;
 409
 410 typedef struct _lo_complex_t {
 411         int8 i;
 412         int8 q;
 413 } lo_complex_abgphy_info_t;
 414
 415 typedef struct _nphy_iq_comp {
 416         int16 a0;
 417         int16 b0;
 418         int16 a1;
 419         int16 b1;
 420 } nphy_iq_comp_t;
 421
 422 typedef struct _nphy_txpwrindex {
 423         int8 index;
 424         int8 index_internal;
 425         int8 index_internal_save;
 426         uint16 AfectrlOverride;
 427         uint16 AfeCtrlDacGain;
 428         uint16 rad_gain;
 429         uint8 bbmult;
 430         uint16 iqcomp_a;
 431         uint16 iqcomp_b;
 432         uint16 locomp;
 433 } phy_txpwrindex_t;
 434
 435 typedef struct {
 436
 437         uint16 txcal_coeffs_2G[8];
 438         uint16 txcal_radio_regs_2G[8];
 439         nphy_iq_comp_t rxcal_coeffs_2G;
 440
 441         uint16 txcal_coeffs_5G[8];
 442         uint16 txcal_radio_regs_5G[8];
 443         nphy_iq_comp_t rxcal_coeffs_5G;
 444 } txiqcal_cache_t;
 445
 446 typedef struct _nphy_pwrctrl {
 447         int8 max_pwr_2g;
 448         int8 idle_targ_2g;
 449         int16 pwrdet_2g_a1;
 450         int16 pwrdet_2g_b0;
 451         int16 pwrdet_2g_b1;
 452         int8 max_pwr_5gm;
 453         int8 idle_targ_5gm;
 454         int8 max_pwr_5gh;
 455         int8 max_pwr_5gl;
 456         int16 pwrdet_5gm_a1;
 457         int16 pwrdet_5gm_b0;
 458         int16 pwrdet_5gm_b1;
 459         int16 pwrdet_5gl_a1;
 460         int16 pwrdet_5gl_b0;
 461         int16 pwrdet_5gl_b1;
 462         int16 pwrdet_5gh_a1;
 463         int16 pwrdet_5gh_b0;
 464         int16 pwrdet_5gh_b1;
 465         int8 idle_targ_5gl;
 466         int8 idle_targ_5gh;
 467         int8 idle_tssi_2g;
 468         int8 idle_tssi_5g;
 469         int8 idle_tssi;
 470         int16 a1;
 471         int16 b0;
 472         int16 b1;
 473 } phy_pwrctrl_t;
 474
 475 typedef struct _nphy_txgains {
 476         uint16 txlpf[2];
 477         uint16 txgm[2];
 478         uint16 pga[2];
 479         uint16 pad[2];
 480         uint16 ipa[2];
 481 } nphy_txgains_t;
 482
 483 #define PHY_NOISEVAR_BUFSIZE 10
 484
 485 typedef struct _nphy_noisevar_buf {
 486         int bufcount;
 487         int tone_id[PHY_NOISEVAR_BUFSIZE];
 488         uint32 noise_vars[PHY_NOISEVAR_BUFSIZE];
 489         uint32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
 490 } phy_noisevar_buf_t;
 491
 492 typedef struct {
 493         uint16 rssical_radio_regs_2G[2];
 494         uint16 rssical_phyregs_2G[12];
 495
 496         uint16 rssical_radio_regs_5G[2];
 497         uint16 rssical_phyregs_5G[12];
 498 } rssical_cache_t;
 499
 500 typedef struct {
 501
 502         uint16 txiqlocal_a;
 503         uint16 txiqlocal_b;
 504         uint16 txiqlocal_didq;
 505         uint8 txiqlocal_ei0;
 506         uint8 txiqlocal_eq0;
 507         uint8 txiqlocal_fi0;
 508         uint8 txiqlocal_fq0;
 509
 510         uint16 txiqlocal_bestcoeffs[11];
 511         uint16 txiqlocal_bestcoeffs_valid;
 512
 513         uint32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
 514         uint16 analog_gain_ref;
 515         uint16 lut_begin;
 516         uint16 lut_end;
 517         uint16 lut_step;
 518         uint16 rxcompdbm;
 519         uint16 papdctrl;
 520         uint16 sslpnCalibClkEnCtrl;
 521
 522         uint16 rxiqcal_coeff_a0;
 523         uint16 rxiqcal_coeff_b0;
 524 } lcnphy_cal_results_t;
 525
 526 struct shared_phy {
 527         struct phy_info *phy_head;
 528         uint unit;
 529         osl_t *osh;
 530         si_t *sih;
 531         void *physhim;
 532         uint corerev;
 533         uint32 machwcap;
 534         bool up;
 535         bool clk;
 536         uint now;
 537         uint16 vid;
 538         uint16 did;
 539         uint chip;
 540         uint chiprev;
 541         uint chippkg;
 542         uint sromrev;
 543         uint boardtype;
 544         uint boardrev;
 545         uint boardvendor;
 546         uint32 boardflags;
 547         uint32 boardflags2;
 548         uint bustype;
 549         uint buscorerev;
 550         uint fast_timer;
 551         uint slow_timer;
 552         uint glacial_timer;
 553         uint8 rx_antdiv;
 554         int8 phy_noise_window[MA_WINDOW_SZ];
 555         uint phy_noise_index;
 556         uint8 hw_phytxchain;
 557         uint8 hw_phyrxchain;
 558         uint8 phytxchain;
 559         uint8 phyrxchain;
 560         uint8 rssi_mode;
 561         bool _rifs_phy;
 562 };
 563
 564 struct phy_pub {
 565         uint phy_type;
 566         uint phy_rev;
 567         uint8 phy_corenum;
 568         uint16 radioid;
 569         uint8 radiorev;
 570         uint8 radiover;
 571
 572         uint coreflags;
 573         uint ana_rev;
 574         bool abgphy_encore;
 575 };
 576
 577 struct phy_info_nphy;
 578 typedef struct phy_info_nphy phy_info_nphy_t;
 579
 580 struct phy_info_lcnphy;
 581 typedef struct phy_info_lcnphy phy_info_lcnphy_t;
 582
 583 struct phy_func_ptr {
 584         initfn_t init;
 585         initfn_t calinit;
 586         chansetfn_t chanset;
 587         initfn_t txpwrrecalc;
 588         longtrnfn_t longtrn;
 589         txiqccgetfn_t txiqccget;
 590         txiqccsetfn_t txiqccset;
 591         txloccgetfn_t txloccget;
 592         radioloftgetfn_t radioloftget;
 593         initfn_t carrsuppr;
 594         rxsigpwrfn_t rxsigpwr;
 595         detachfn_t detach;
 596 };
 597 typedef struct phy_func_ptr phy_func_ptr_t;
 598
 599 struct phy_info {
 600         wlc_phy_t pubpi_ro;
 601         shared_phy_t *sh;
 602         phy_func_ptr_t pi_fptr;
 603         void *pi_ptr;
 604
 605         union {
 606                 phy_info_lcnphy_t *pi_lcnphy;
 607         } u;
 608         bool user_txpwr_at_rfport;
 609
 610         d11regs_t *regs;
 611         struct phy_info *next;
 612         char *vars;
 613         wlc_phy_t pubpi;
 614
 615         bool do_initcal;
 616         bool phytest_on;
 617         bool ofdm_rateset_war;
 618         bool bf_preempt_4306;
 619         chanspec_t radio_chanspec;
 620         uint8 antsel_type;
 621         uint16 bw;
 622         uint8 txpwr_percent;
 623         bool phy_init_por;
 624
 625         bool init_in_progress;
 626         bool initialized;
 627         bool sbtml_gm;
 628         uint refcnt;
 629         bool watchdog_override;
 630         uint8 phynoise_state;
 631         uint phynoise_now;
 632         int phynoise_chan_watchdog;
 633         bool phynoise_polling;
 634         bool disable_percal;
 635         mbool measure_hold;
 636
 637         int16 txpa_2g[PWRTBL_NUM_COEFF];
 638         int16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
 639         int16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
 640         int16 txpa_5g_low[PWRTBL_NUM_COEFF];
 641         int16 txpa_5g_mid[PWRTBL_NUM_COEFF];
 642         int16 txpa_5g_hi[PWRTBL_NUM_COEFF];
 643
 644         uint8 tx_srom_max_2g;
 645         uint8 tx_srom_max_5g_low;
 646         uint8 tx_srom_max_5g_mid;
 647         uint8 tx_srom_max_5g_hi;
 648         uint8 tx_srom_max_rate_2g[TXP_NUM_RATES];
 649         uint8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
 650         uint8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
 651         uint8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
 652         uint8 tx_user_target[TXP_NUM_RATES];
 653         int8 tx_power_offset[TXP_NUM_RATES];
 654         uint8 tx_power_target[TXP_NUM_RATES];
 655
 656         srom_fem_t srom_fem2g;
 657         srom_fem_t srom_fem5g;
 658
 659         uint8 tx_power_max;
 660         uint8 tx_power_max_rate_ind;
 661         bool hwpwrctrl;
 662         uint8 nphy_txpwrctrl;
 663         int8 nphy_txrx_chain;
 664         bool phy_5g_pwrgain;
 665
 666         uint16 phy_wreg;
 667         uint16 phy_wreg_limit;
 668
 669         int8 n_preamble_override;
 670         uint8 antswitch;
 671         uint8 aa2g, aa5g;
 672
 673         int8 idle_tssi[CH_5G_GROUP];
 674         int8 target_idle_tssi;
 675         int8 txpwr_est_Pout;
 676         uint8 tx_power_min;
 677         uint8 txpwr_limit[TXP_NUM_RATES];
 678         uint8 txpwr_env_limit[TXP_NUM_RATES];
 679         uint8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
 680
 681         bool channel_14_wide_filter;
 682
 683         bool txpwroverride;
 684         bool txpwridx_override_aphy;
 685         int16 radiopwr_override;
 686         uint16 hwpwr_txcur;
 687         uint8 saved_txpwr_idx;
 688
 689         bool edcrs_threshold_lock;
 690
 691         uint32 tr_R_gain_val;
 692         uint32 tr_T_gain_val;
 693
 694         int16 ofdm_analog_filt_bw_override;
 695         int16 cck_analog_filt_bw_override;
 696         int16 ofdm_rccal_override;
 697         int16 cck_rccal_override;
 698         uint16 extlna_type;
 699
 700         uint interference_mode_crs_time;
 701         uint16 crsglitch_prev;
 702         bool interference_mode_crs;
 703
 704         uint32 phy_tx_tone_freq;
 705         uint phy_lastcal;
 706         bool phy_forcecal;
 707         bool phy_fixed_noise;
 708         uint32 xtalfreq;
 709         uint8 pdiv;
 710         int8 carrier_suppr_disable;
 711
 712         bool phy_bphy_evm;
 713         bool phy_bphy_rfcs;
 714         int8 phy_scraminit;
 715         uint8 phy_gpiosel;
 716
 717         int16 phy_txcore_disable_temp;
 718         int16 phy_txcore_enable_temp;
 719         int8 phy_tempsense_offset;
 720         bool phy_txcore_heatedup;
 721
 722         uint16 radiopwr;
 723         uint16 bb_atten;
 724         uint16 txctl1;
 725
 726         uint16 mintxbias;
 727         uint16 mintxmag;
 728         lo_complex_abgphy_info_t gphy_locomp_iq[STATIC_NUM_RF][STATIC_NUM_BB];
 729         int8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
 730         uint16 gain_table[TX_GAIN_TABLE_LENGTH];
 731         bool loopback_gain;
 732         int16 max_lpback_gain_hdB;
 733         int16 trsw_rx_gain_hdB;
 734         uint8 power_vec[8];
 735
 736         uint16 rc_cal;
 737         int nrssi_table_delta;
 738         int nrssi_slope_scale;
 739         int nrssi_slope_offset;
 740         int min_rssi;
 741         int max_rssi;
 742
 743         int8 txpwridx;
 744         uint8 min_txpower;
 745
 746         uint8 a_band_high_disable;
 747
 748         uint16 tx_vos;
 749         uint16 global_tx_bb_dc_bias_loft;
 750
 751         int rf_max;
 752         int bb_max;
 753         int rf_list_size;
 754         int bb_list_size;
 755         uint16 *rf_attn_list;
 756         uint16 *bb_attn_list;
 757         uint16 padmix_mask;
 758         uint16 padmix_reg;
 759         uint16 *txmag_list;
 760         uint txmag_len;
 761         bool txmag_enable;
 762
 763         int8 *a_tssi_to_dbm;
 764         int8 *m_tssi_to_dbm;
 765         int8 *l_tssi_to_dbm;
 766         int8 *h_tssi_to_dbm;
 767         uint8 *hwtxpwr;
 768
 769         uint16 freqtrack_saved_regs[2];
 770         int cur_interference_mode;
 771         bool hwpwrctrl_capable;
 772         bool temppwrctrl_capable;
 773
 774         uint phycal_nslope;
 775         uint phycal_noffset;
 776         uint phycal_mlo;
 777         uint phycal_txpower;
 778
 779         bool pkteng_in_progress;
 780         uint8 phy_aa2g;
 781
 782         bool nphy_tableloaded;
 783         int8 nphy_rssisel;
 784         uint32 nphy_bb_mult_save;
 785         uint16 nphy_txiqlocal_bestc[11];
 786         bool nphy_txiqlocal_coeffsvalid;
 787         phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2];
 788         phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2];
 789         uint16 cck2gpo;
 790         uint32 ofdm2gpo;
 791         uint32 ofdm5gpo;
 792         uint32 ofdm5glpo;
 793         uint32 ofdm5ghpo;
 794         uint8 bw402gpo;
 795         uint8 bw405gpo;
 796         uint8 bw405glpo;
 797         uint8 bw405ghpo;
 798         uint8 cdd2gpo;
 799         uint8 cdd5gpo;
 800         uint8 cdd5glpo;
 801         uint8 cdd5ghpo;
 802         uint8 stbc2gpo;
 803         uint8 stbc5gpo;
 804         uint8 stbc5glpo;
 805         uint8 stbc5ghpo;
 806         uint8 bwdup2gpo;
 807         uint8 bwdup5gpo;
 808         uint8 bwdup5glpo;
 809         uint8 bwdup5ghpo;
 810         uint16 mcs2gpo[8];
 811         uint16 mcs5gpo[8];
 812         uint16 mcs5glpo[8];
 813         uint16 mcs5ghpo[8];
 814         uint32 nphy_rxcalparams;
 815
 816         uint8 phy_spuravoid;
 817         bool phy_isspuravoid;
 818
 819         uint8 phy_pabias;
 820         uint8 nphy_papd_skip;
 821         uint8 nphy_tssi_slope;
 822
 823         int16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
 824         uint8 nphy_noise_index;
 825
 826         uint8 nphy_txpid2g[PHY_CORE_NUM_2];
 827         uint8 nphy_txpid5g[PHY_CORE_NUM_2];
 828         uint8 nphy_txpid5gl[PHY_CORE_NUM_2];
 829         uint8 nphy_txpid5gh[PHY_CORE_NUM_2];
 830
 831         bool nphy_gain_boost;
 832         bool nphy_elna_gain_config;
 833         uint16 old_bphy_test;
 834         uint16 old_bphy_testcontrol;
 835
 836         bool phyhang_avoid;
 837
 838         bool rssical_nphy;
 839         uint8 nphy_perical;
 840         uint nphy_perical_last;
 841         uint8 cal_type_override;
 842         uint8 mphase_cal_phase_id;
 843         uint8 mphase_txcal_cmdidx;
 844         uint8 mphase_txcal_numcmds;
 845         uint16 mphase_txcal_bestcoeffs[11];
 846         chanspec_t nphy_txiqlocal_chanspec;
 847         chanspec_t nphy_iqcal_chanspec_2G;
 848         chanspec_t nphy_iqcal_chanspec_5G;
 849         chanspec_t nphy_rssical_chanspec_2G;
 850         chanspec_t nphy_rssical_chanspec_5G;
 851         struct wlapi_timer *phycal_timer;
 852         bool use_int_tx_iqlo_cal_nphy;
 853         bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
 854         int16 nphy_lastcal_temp;
 855
 856         txiqcal_cache_t calibration_cache;
 857         rssical_cache_t rssical_cache;
 858
 859         uint8 nphy_txpwr_idx[2];
 860         uint8 nphy_papd_cal_type;
 861         uint nphy_papd_last_cal;
 862         uint16 nphy_papd_tx_gain_at_last_cal[2];
 863         uint8 nphy_papd_cal_gain_index[2];
 864         int16 nphy_papd_epsilon_offset[2];
 865         bool nphy_papd_recal_enable;
 866         uint32 nphy_papd_recal_counter;
 867         bool nphy_force_papd_cal;
 868         bool nphy_papdcomp;
 869         bool ipa2g_on;
 870         bool ipa5g_on;
 871
 872         uint16 classifier_state;
 873         uint16 clip_state[2];
 874         uint nphy_deaf_count;
 875         uint8 rxiq_samps;
 876         uint8 rxiq_antsel;
 877
 878         uint16 rfctrlIntc1_save;
 879         uint16 rfctrlIntc2_save;
 880         bool first_cal_after_assoc;
 881         uint16 tx_rx_cal_radio_saveregs[22];
 882         uint16 tx_rx_cal_phy_saveregs[15];
 883
 884         uint8 nphy_cal_orig_pwr_idx[2];
 885         uint8 nphy_txcal_pwr_idx[2];
 886         uint8 nphy_rxcal_pwr_idx[2];
 887         uint16 nphy_cal_orig_tx_gain[2];
 888         nphy_txgains_t nphy_cal_target_gain;
 889         uint16 nphy_txcal_bbmult;
 890         uint16 nphy_gmval;
 891
 892         uint16 nphy_saved_bbconf;
 893
 894         bool nphy_gband_spurwar_en;
 895         bool nphy_gband_spurwar2_en;
 896         bool nphy_aband_spurwar_en;
 897         uint16 nphy_rccal_value;
 898         uint16 nphy_crsminpwr[3];
 899         phy_noisevar_buf_t nphy_saved_noisevars;
 900         bool nphy_anarxlpf_adjusted;
 901         bool nphy_crsminpwr_adjusted;
 902         bool nphy_noisevars_adjusted;
 903
 904         bool nphy_rxcal_active;
 905         uint16 radar_percal_mask;
 906         bool dfs_lp_buffer_nphy;
 907
 908         uint16 nphy_fineclockgatecontrol;
 909
 910         int8 rx2tx_biasentry;
 911
 912         uint16 crsminpwr0;
 913         uint16 crsminpwrl0;
 914         uint16 crsminpwru0;
 915         int16 noise_crsminpwr_index;
 916         uint16 init_gain_core1;
 917         uint16 init_gain_core2;
 918         uint16 init_gainb_core1;
 919         uint16 init_gainb_core2;
 920         uint8 aci_noise_curr_channel;
 921         uint16 init_gain_rfseq[4];
 922
 923         bool radio_is_on;
 924
 925         bool nphy_sample_play_lpf_bw_ctl_ovr;
 926
 927         uint16 tbl_data_hi;
 928         uint16 tbl_data_lo;
 929         uint16 tbl_addr;
 930
 931         uint tbl_save_id;
 932         uint tbl_save_offset;
 933
 934         uint8 txpwrctrl;
 935         int8 txpwrindex[PHY_CORE_MAX];
 936
 937         uint8 phycal_tempdelta;
 938         uint32 mcs20_po;
 939         uint32 mcs40_po;
 940 };
 941
 942 typedef int32 fixed;
 943
 944 typedef struct _cint32 {
 945         fixed q;
 946         fixed i;
 947 } cint32;
 948
 949 typedef struct radio_regs {
 950         uint16 address;
 951         uint32 init_a;
 952         uint32 init_g;
 953         uint8 do_init_a;
 954         uint8 do_init_g;
 955 } radio_regs_t;
 956
 957 typedef struct radio_20xx_regs {
 958         uint16 address;
 959         uint8 init;
 960         uint8 do_init;
 961 } radio_20xx_regs_t;
 962
 963 typedef struct lcnphy_radio_regs {
 964         uint16 address;
 965         uint8 init_a;
 966         uint8 init_g;
 967         uint8 do_init_a;
 968         uint8 do_init_g;
 969 } lcnphy_radio_regs_t;
 970
 971 extern lcnphy_radio_regs_t lcnphy_radio_regs_2064[];
 972 extern lcnphy_radio_regs_t lcnphy_radio_regs_2066[];
 973 extern radio_regs_t regs_2055[], regs_SYN_2056[], regs_TX_2056[],
 974     regs_RX_2056[];
 975 extern radio_regs_t regs_SYN_2056_A1[], regs_TX_2056_A1[], regs_RX_2056_A1[];
 976 extern radio_regs_t regs_SYN_2056_rev5[], regs_TX_2056_rev5[],
 977     regs_RX_2056_rev5[];
 978 extern radio_regs_t regs_SYN_2056_rev6[], regs_TX_2056_rev6[],
 979     regs_RX_2056_rev6[];
 980 extern radio_regs_t regs_SYN_2056_rev7[], regs_TX_2056_rev7[],
 981     regs_RX_2056_rev7[];
 982 extern radio_regs_t regs_SYN_2056_rev8[], regs_TX_2056_rev8[],
 983     regs_RX_2056_rev8[];
 984 extern radio_20xx_regs_t regs_2057_rev4[], regs_2057_rev5[], regs_2057_rev5v1[];
 985 extern radio_20xx_regs_t regs_2057_rev7[], regs_2057_rev8[];
 986
 987 extern char *phy_getvar(phy_info_t *pi, const char *name);
 988 extern int phy_getintvar(phy_info_t *pi, const char *name);
 989 #define PHY_GETVAR(pi, name)    phy_getvar(pi, name)
 990 #define PHY_GETINTVAR(pi, name) phy_getintvar(pi, name)
 991
 992 extern uint16 read_phy_reg(phy_info_t *pi, uint16 addr);
 993 extern void write_phy_reg(phy_info_t *pi, uint16 addr, uint16 val);
 994 extern void and_phy_reg(phy_info_t *pi, uint16 addr, uint16 val);
 995 extern void or_phy_reg(phy_info_t *pi, uint16 addr, uint16 val);
 996 extern void mod_phy_reg(phy_info_t *pi, uint16 addr, uint16 mask, uint16 val);
 997
 998 extern uint16 read_radio_reg(phy_info_t *pi, uint16 addr);
 999 extern void or_radio_reg(phy_info_t *pi, uint16 addr, uint16 val);
1000 extern void and_radio_reg(phy_info_t *pi, uint16 addr, uint16 val);
1001 extern void mod_radio_reg(phy_info_t *pi, uint16 addr, uint16 mask,
1002                           uint16 val);
1003 extern void xor_radio_reg(phy_info_t *pi, uint16 addr, uint16 mask);
1004
1005 extern void write_radio_reg(phy_info_t *pi, uint16 addr, uint16 val);
1006
1007 extern void wlc_phyreg_enter(wlc_phy_t *pih);
1008 extern void wlc_phyreg_exit(wlc_phy_t *pih);
1009 extern void wlc_radioreg_enter(wlc_phy_t *pih);
1010 extern void wlc_radioreg_exit(wlc_phy_t *pih);
1011
1012 extern void wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
1013                                uint16 tblAddr, uint16 tblDataHi,
1014                                uint16 tblDatalo);
1015 extern void wlc_phy_write_table(phy_info_t *pi,
1016                                 const phytbl_info_t *ptbl_info, uint16 tblAddr,
1017                                 uint16 tblDataHi, uint16 tblDatalo);
1018 extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
1019                                uint16 tblAddr, uint16 tblDataHi,
1020                                uint16 tblDataLo);
1021 extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, uint32 val);
1022
1023 extern void write_phy_channel_reg(phy_info_t *pi, uint val);
1024 extern void wlc_phy_txpower_update_shm(phy_info_t *pi);
1025
1026 extern void wlc_phy_cordic(fixed theta, cint32 *val);
1027 extern uint8 wlc_phy_nbits(int32 value);
1028 extern uint32 wlc_phy_sqrt_int(uint32 value);
1029 extern void wlc_phy_compute_dB(uint32 *cmplx_pwr, int8 *p_dB, uint8 core);
1030
1031 extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi,
1032                                              radio_20xx_regs_t *radioregs);
1033 extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs,
1034                                     uint16 core_offset);
1035
1036 extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi);
1037
1038 extern void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on);
1039 extern void wlc_phy_papd_decode_epsilon(uint32 epsilon, int32 *eps_real,
1040                                         int32 *eps_imag);
1041
1042 extern void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi);
1043 extern void wlc_phy_cal_perical_mphase_restart(phy_info_t *pi);
1044
1045 extern bool wlc_phy_attach_nphy(phy_info_t *pi);
1046 extern bool wlc_phy_attach_lcnphy(phy_info_t *pi);
1047
1048 extern void wlc_phy_detach_lcnphy(phy_info_t *pi);
1049
1050 extern void wlc_phy_init_nphy(phy_info_t *pi);
1051 extern void wlc_phy_init_lcnphy(phy_info_t *pi);
1052
1053 extern void wlc_phy_cal_init_nphy(phy_info_t *pi);
1054 extern void wlc_phy_cal_init_lcnphy(phy_info_t *pi);
1055
1056 extern void wlc_phy_chanspec_set_nphy(phy_info_t *pi, chanspec_t chanspec);
1057 extern void wlc_phy_chanspec_set_lcnphy(phy_info_t *pi, chanspec_t chanspec);
1058 extern void wlc_phy_chanspec_set_fixup_lcnphy(phy_info_t *pi,
1059                                               chanspec_t chanspec);
1060 extern int wlc_phy_channel2freq(uint channel);
1061 extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
1062 extern int wlc_phy_chanspec_bandrange_get(phy_info_t *, chanspec_t);
1063
1064 extern void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, uint16 mode);
1065 extern int8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi);
1066
1067 extern void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi);
1068 extern void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi);
1069 extern void wlc_phy_txpower_recalc_target_lcnphy(phy_info_t *pi);
1070
1071 extern void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index);
1072 extern void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable);
1073 extern void wlc_lcnphy_stop_tx_tone(phy_info_t *pi);
1074 extern void wlc_lcnphy_start_tx_tone(phy_info_t *pi, int32 f_kHz,
1075                                      uint16 max_val, bool iqcalmode);
1076
1077 extern void wlc_phy_txpower_sromlimit_get_nphy(phy_info_t *pi, uint chan,
1078                                                uint8 *max_pwr, uint8 rate_id);
1079 extern void wlc_phy_ofdm_to_mcs_powers_nphy(uint8 *power, uint8 rate_mcs_start,
1080                                             uint8 rate_mcs_end,
1081                                             uint8 rate_ofdm_start);
1082 extern void wlc_phy_mcs_to_ofdm_powers_nphy(uint8 *power,
1083                                             uint8 rate_ofdm_start,
1084                                             uint8 rate_ofdm_end,
1085                                             uint8 rate_mcs_start);
1086
1087 extern uint16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode);
1088 extern int16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode);
1089 extern int8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode);
1090 extern int8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode);
1091 extern void wlc_phy_carrier_suppress_lcnphy(phy_info_t *pi);
1092 extern void wlc_lcnphy_crsuprs(phy_info_t *pi, int channel);
1093 extern void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode);
1094 extern void wlc_2064_vco_cal(phy_info_t *pi);
1095
1096 extern void wlc_phy_txpower_recalc_target(phy_info_t *pi);
1097 extern uint32 wlc_phy_qdiv_roundup(uint32 dividend, uint32 divisor,
1098                                    uint8 precision);
1099
1100 #define LCNPHY_TBL_ID_PAPDCOMPDELTATBL  0x18
1101 #define LCNPHY_TX_POWER_TABLE_SIZE      128
1102 #define LCNPHY_MAX_TX_POWER_INDEX       (LCNPHY_TX_POWER_TABLE_SIZE - 1)
1103 #define LCNPHY_TBL_ID_TXPWRCTL  0x07
1104 #define LCNPHY_TX_PWR_CTRL_OFF  0
1105 #define LCNPHY_TX_PWR_CTRL_SW           (0x1 << 15)
1106 #define LCNPHY_TX_PWR_CTRL_HW         ((0x1 << 15) | \
1107                                         (0x1 << 14) | \
1108                                         (0x1 << 13))
1109
1110 #define LCNPHY_TX_PWR_CTRL_TEMPBASED    0xE001
1111
1112 extern void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti);
1113 extern void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti);
1114 extern void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, uint16 a, uint16 b);
1115 extern void wlc_lcnphy_set_tx_locc(phy_info_t *pi, uint16 didq);
1116 extern void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, uint16 *a, uint16 *b);
1117 extern uint16 wlc_lcnphy_get_tx_locc(phy_info_t *pi);
1118 extern void wlc_lcnphy_get_radio_loft(phy_info_t *pi, uint8 *ei0,
1119                                       uint8 *eq0, uint8 *fi0, uint8 *fq0);
1120 extern void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode);
1121 extern void wlc_lcnphy_deaf_mode(phy_info_t *pi, bool mode);
1122 extern bool wlc_phy_tpc_isenabled_lcnphy(phy_info_t *pi);
1123 extern void wlc_lcnphy_tx_pwr_update_npt(phy_info_t *pi);
1124 extern int32 wlc_lcnphy_tssi2dbm(int32 tssi, int32 a1, int32 b0, int32 b1);
1125 extern void wlc_lcnphy_get_tssi(phy_info_t *pi, int8 *ofdm_pwr,
1126                                 int8 *cck_pwr);
1127 extern void wlc_lcnphy_tx_power_adjustment(wlc_phy_t *ppi);
1128
1129 extern int32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, int32 gain_index);
1130
1131 #define NPHY_MAX_HPVGA1_INDEX           10
1132 #define NPHY_DEF_HPVGA1_INDEXLIMIT      7
1133
1134 typedef struct _phy_iq_est {
1135         int32 iq_prod;
1136         uint32 i_pwr;
1137         uint32 q_pwr;
1138 } phy_iq_est_t;
1139
1140 extern void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable);
1141 extern void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode);
1142
1143 #define wlc_phy_write_table_nphy(pi, pti)       wlc_phy_write_table(pi, pti, 0x72, \
1144         0x74, 0x73)
1145 #define wlc_phy_read_table_nphy(pi, pti)        wlc_phy_read_table(pi, pti, 0x72, \
1146         0x74, 0x73)
1147 #define wlc_nphy_table_addr(pi, id, off)        wlc_phy_table_addr((pi), (id), (off), \
1148         0x72, 0x74, 0x73)
1149 #define wlc_nphy_table_data_write(pi, w, v)     wlc_phy_table_data_write((pi), (w), (v))
1150
1151 extern void wlc_phy_table_read_nphy(phy_info_t *pi, uint32, uint32 l, uint32 o,
1152                                     uint32 w, void *d);
1153 extern void wlc_phy_table_write_nphy(phy_info_t *pi, uint32, uint32, uint32,
1154                                      uint32, const void *);
1155
1156 #define PHY_IPA(pi) \
1157         ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
1158          (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
1159
1160 #define WLC_PHY_WAR_PR51571(pi) \
1161         if ((BUSTYPE((pi)->sh->bustype) == PCI_BUS) && NREV_LT((pi)->pubpi.phy_rev, 3)) \
1162                 (void)R_REG((pi)->sh->osh, &(pi)->regs->maccontrol)
1163
1164 extern void wlc_phy_cal_perical_nphy_run(phy_info_t *pi, uint8 caltype);
1165 extern void wlc_phy_aci_reset_nphy(phy_info_t *pi);
1166 extern void wlc_phy_pa_override_nphy(phy_info_t *pi, bool en);
1167
1168 extern uint8 wlc_phy_get_chan_freq_range_nphy(phy_info_t *pi, uint chan);
1169 extern void wlc_phy_switch_radio_nphy(phy_info_t *pi, bool on);
1170
1171 extern void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi);
1172
1173 extern void wlc_phy_force_rfseq_nphy(phy_info_t *pi, uint8 cmd);
1174 extern int16 wlc_phy_tempsense_nphy(phy_info_t *pi);
1175
1176 extern uint16 wlc_phy_classifier_nphy(phy_info_t *pi, uint16 mask, uint16 val);
1177
1178 extern void wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est,
1179                                    uint16 num_samps, uint8 wait_time,
1180                                    uint8 wait_for_crs);
1181
1182 extern void wlc_phy_rx_iq_coeffs_nphy(phy_info_t *pi, uint8 write,
1183                                       nphy_iq_comp_t *comp);
1184 extern void wlc_phy_aci_and_noise_reduction_nphy(phy_info_t *pi);
1185
1186 extern void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, uint8 rxcore_bitmask);
1187 extern uint8 wlc_phy_rxcore_getstate_nphy(wlc_phy_t *pih);
1188
1189 extern void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, uint8 ctrl_type);
1190 extern void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi);
1191 extern void wlc_phy_txpwr_apply_nphy(phy_info_t *pi);
1192 extern void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi);
1193 extern uint16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi);
1194
1195 extern nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi);
1196 extern int wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
1197                                    bool full, bool m);
1198 extern int wlc_phy_cal_rxiq_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
1199                                  uint8 type, bool d);
1200 extern void wlc_phy_txpwr_index_nphy(phy_info_t *pi, uint8 core_mask,
1201                                      int8 txpwrindex, bool res);
1202 extern void wlc_phy_rssisel_nphy(phy_info_t *pi, uint8 core, uint8 rssi_type);
1203 extern int wlc_phy_poll_rssi_nphy(phy_info_t *pi, uint8 rssi_type,
1204                                   int32 *rssi_buf, uint8 nsamps);
1205 extern void wlc_phy_rssi_cal_nphy(phy_info_t *pi);
1206 extern int wlc_phy_aci_scan_nphy(phy_info_t *pi);
1207 extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower,
1208                                         bool debug);
1209 extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, uint16 max_val,
1210                                 uint8 mode, uint8, bool);
1211 extern void wlc_phy_stopplayback_nphy(phy_info_t *pi);
1212 extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf,
1213                                      uint8 num_samps);
1214 extern void wlc_phy_radio205x_vcocal_nphy(phy_info_t *pi);
1215
1216 extern int wlc_phy_rssi_compute_nphy(phy_info_t *pi, wlc_d11rxhdr_t *wlc_rxh);
1217
1218 #define NPHY_TESTPATTERN_BPHY_EVM   0
1219 #define NPHY_TESTPATTERN_BPHY_RFCS  1
1220
1221 extern void wlc_phy_nphy_tkip_rifs_war(phy_info_t *pi, uint8 rifs);
1222
1223 void wlc_phy_get_pwrdet_offsets(phy_info_t *pi, int8 *cckoffset,
1224                                 int8 *ofdmoffset);
1225 extern int8 wlc_phy_upd_rssi_offset(phy_info_t *pi, int8 rssi,
1226                                     chanspec_t chanspec);
1227
1228 extern bool wlc_phy_n_txpower_ipa_ison(phy_info_t *pih);
1229 #endif                          /* _wlc_phy_int_h_ */