2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
26 * Data structure to export all chip specific common variables
27 * public (read-only) portion of siutils handle returned by si_attach()
30 uint socitype
; /* SOCI_SB, SOCI_AI */
32 uint bustype
; /* SI_BUS, PCI_BUS */
33 uint buscoretype
; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
34 uint buscorerev
; /* buscore rev */
35 uint buscoreidx
; /* buscore index */
36 int ccrev
; /* chip common core rev */
37 uint32 cccaps
; /* chip common capabilities */
38 uint32 cccaps_ext
; /* chip common capabilities extension */
39 int pmurev
; /* pmu core rev */
40 uint32 pmucaps
; /* pmu capabilities */
41 uint boardtype
; /* board type */
42 uint boardvendor
; /* board vendor */
43 uint boardflags
; /* board flags */
44 uint boardflags2
; /* board flags2 */
45 uint chip
; /* chip number */
46 uint chiprev
; /* chip revision */
47 uint chippkg
; /* chip package option */
48 uint32 chipst
; /* chip status */
49 bool issim
; /* chip is in simulation or emulation */
50 uint socirev
; /* SOC interconnect rev */
58 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
59 * for monolithic driver, it is readonly to prevent accident change
62 typedef struct si_pub si_t
;
64 typedef const struct si_pub si_t
;
68 * Many of the routines below take an 'sih' handle as their first arg.
69 * Allocate this by calling si_attach(). Free it by calling si_detach().
70 * At any one time, the sih is logically focused on one particular si core
71 * (the "current core").
72 * Use si_setcore() or si_setcoreidx() to change the association to another core.
75 #define BADIDX (SI_MAXCORES + 1)
77 /* clkctl xtal what flags */
78 #define XTAL 0x1 /* primary crystal oscillator (2050) */
79 #define PLL 0x2 /* main chip pll */
82 #define CLK_FAST 0 /* force fast (pll) clock */
83 #define CLK_DYNAMIC 2 /* enable dynamic clock control */
85 /* GPIO usage priorities */
86 #define GPIO_DRV_PRIORITY 0 /* Driver */
87 #define GPIO_APP_PRIORITY 1 /* Application */
88 #define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
90 /* GPIO pull up/down */
94 /* GPIO event regtype */
95 #define GPIO_REGEVT 0 /* GPIO register event */
96 #define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
97 #define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
100 #define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
102 /* SI routine enumeration: to be used by update function with multiple hooks */
103 #define SI_DOATTACH 1
107 #define ISSIM_ENAB(sih) 0
109 /* PMU clock/power control */
110 #if defined(BCMPMUCTL)
111 #define PMUCTL_ENAB(sih) (BCMPMUCTL)
113 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
116 /* chipcommon clock/power control (exclusive with PMU's) */
117 #if defined(BCMPMUCTL) && BCMPMUCTL
118 #define CCCTL_ENAB(sih) (0)
119 #define CCPLL_ENAB(sih) (0)
121 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
122 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
125 typedef void (*gpio_handler_t
) (uint32 stat
, void *arg
);
127 /* External PA enable mask */
128 #define GPIO_CTRL_EPA_EN_MASK 0x40
130 /* === exported functions === */
131 extern si_t
*si_attach(uint pcidev
, osl_t
*osh
, void *regs
, uint bustype
,
132 void *sdh
, char **vars
, uint
*varsz
);
134 extern void si_detach(si_t
*sih
);
135 extern bool si_pci_war16165(si_t
*sih
);
137 extern uint
si_corelist(si_t
*sih
, uint coreid
[]);
138 extern uint
si_coreid(si_t
*sih
);
139 extern uint
si_flag(si_t
*sih
);
140 extern uint
si_intflag(si_t
*sih
);
141 extern uint
si_coreidx(si_t
*sih
);
142 extern uint
si_coreunit(si_t
*sih
);
143 extern uint
si_corevendor(si_t
*sih
);
144 extern uint
si_corerev(si_t
*sih
);
145 extern void *si_osh(si_t
*sih
);
146 extern void si_setosh(si_t
*sih
, osl_t
*osh
);
147 extern uint
si_corereg(si_t
*sih
, uint coreidx
, uint regoff
, uint mask
,
149 extern void *si_coreregs(si_t
*sih
);
150 extern void si_write_wrapperreg(si_t
*sih
, uint32 offset
, uint32 val
);
151 extern uint32
si_core_cflags(si_t
*sih
, uint32 mask
, uint32 val
);
152 extern void si_core_cflags_wo(si_t
*sih
, uint32 mask
, uint32 val
);
153 extern uint32
si_core_sflags(si_t
*sih
, uint32 mask
, uint32 val
);
154 extern bool si_iscoreup(si_t
*sih
);
155 extern uint
si_findcoreidx(si_t
*sih
, uint coreid
, uint coreunit
);
157 extern void *si_setcoreidx(si_t
*sih
, uint coreidx
);
159 extern void *si_setcore(si_t
*sih
, uint coreid
, uint coreunit
);
160 extern void *si_switch_core(si_t
*sih
, uint coreid
, uint
*origidx
,
162 extern void si_restore_core(si_t
*sih
, uint coreid
, uint intr_val
);
163 extern int si_numaddrspaces(si_t
*sih
);
164 extern uint32
si_addrspace(si_t
*sih
, uint asidx
);
165 extern uint32
si_addrspacesize(si_t
*sih
, uint asidx
);
166 extern int si_corebist(si_t
*sih
);
167 extern void si_core_reset(si_t
*sih
, uint32 bits
, uint32 resetbits
);
168 extern void si_core_disable(si_t
*sih
, uint32 bits
);
169 extern uint32
si_clock_rate(uint32 pll_type
, uint32 n
, uint32 m
);
170 extern uint32
si_clock(si_t
*sih
);
171 extern uint32
si_alp_clock(si_t
*sih
);
172 extern uint32
si_ilp_clock(si_t
*sih
);
173 extern void si_pci_setup(si_t
*sih
, uint coremask
);
174 extern void si_setint(si_t
*sih
, int siflag
);
175 extern bool si_backplane64(si_t
*sih
);
176 extern void si_register_intr_callback(si_t
*sih
, void *intrsoff_fn
,
177 void *intrsrestore_fn
,
178 void *intrsenabled_fn
, void *intr_arg
);
179 extern void si_deregister_intr_callback(si_t
*sih
);
180 extern void si_clkctl_init(si_t
*sih
);
181 extern uint16
si_clkctl_fast_pwrup_delay(si_t
*sih
);
182 extern bool si_clkctl_cc(si_t
*sih
, uint mode
);
183 extern int si_clkctl_xtal(si_t
*sih
, uint what
, bool on
);
184 extern uint32
si_gpiotimerval(si_t
*sih
, uint32 mask
, uint32 val
);
185 extern bool si_deviceremoved(si_t
*sih
);
186 extern uint32
si_socram_size(si_t
*sih
);
187 extern uint32
si_socdevram_size(si_t
*sih
);
188 extern void si_socdevram(si_t
*sih
, bool set
, uint8
*ennable
,
190 extern bool si_socdevram_pkg(si_t
*sih
);
192 extern void si_watchdog(si_t
*sih
, uint ticks
);
193 extern void si_watchdog_ms(si_t
*sih
, uint32 ms
);
194 extern void *si_gpiosetcore(si_t
*sih
);
195 extern uint32
si_gpiocontrol(si_t
*sih
, uint32 mask
, uint32 val
,
197 extern uint32
si_gpioouten(si_t
*sih
, uint32 mask
, uint32 val
, uint8 priority
);
198 extern uint32
si_gpioout(si_t
*sih
, uint32 mask
, uint32 val
, uint8 priority
);
199 extern uint32
si_gpioin(si_t
*sih
);
200 extern uint32
si_gpiointpolarity(si_t
*sih
, uint32 mask
, uint32 val
,
202 extern uint32
si_gpiointmask(si_t
*sih
, uint32 mask
, uint32 val
,
204 extern uint32
si_gpioled(si_t
*sih
, uint32 mask
, uint32 val
);
205 extern uint32
si_gpioreserve(si_t
*sih
, uint32 gpio_num
, uint8 priority
);
206 extern uint32
si_gpiorelease(si_t
*sih
, uint32 gpio_num
, uint8 priority
);
207 extern uint32
si_gpiopull(si_t
*sih
, bool updown
, uint32 mask
, uint32 val
);
208 extern uint32
si_gpioevent(si_t
*sih
, uint regtype
, uint32 mask
, uint32 val
);
209 extern uint32
si_gpio_int_enable(si_t
*sih
, bool enable
);
211 /* GPIO event handlers */
212 extern void *si_gpio_handler_register(si_t
*sih
, uint32 e
, bool lev
,
213 gpio_handler_t cb
, void *arg
);
214 extern void si_gpio_handler_unregister(si_t
*sih
, void *gpioh
);
215 extern void si_gpio_handler_process(si_t
*sih
);
217 /* Wake-on-wireless-LAN (WOWL) */
218 extern bool si_pci_pmecap(si_t
*sih
);
220 extern bool si_pci_fastpmecap(struct osl_info
*osh
);
221 extern bool si_pci_pmestat(si_t
*sih
);
222 extern void si_pci_pmeclr(si_t
*sih
);
223 extern void si_pci_pmeen(si_t
*sih
);
224 extern uint
si_pcie_readreg(void *sih
, uint addrtype
, uint offset
);
227 extern void si_sdio_init(si_t
*sih
);
230 extern uint16
si_d11_devid(si_t
*sih
);
232 #define si_eci(sih) 0
233 #define si_eci_init(sih) (0)
234 #define si_eci_notify_bt(sih, type, val) (0)
235 #define si_seci(sih) 0
236 static INLINE
void *si_seci_init(si_t
*sih
, uint8 use_seci
)
242 extern bool si_is_otp_disabled(si_t
*sih
);
243 extern bool si_is_otp_powered(si_t
*sih
);
244 extern void si_otp_power(si_t
*sih
, bool on
);
246 /* SPROM availability */
247 extern bool si_is_sprom_available(si_t
*sih
);
248 extern bool si_is_sprom_enabled(si_t
*sih
);
249 extern void si_sprom_enable(si_t
*sih
, bool enable
);
250 #ifdef SI_SPROM_PROBE
251 extern void si_sprom_init(si_t
*sih
);
252 #endif /* SI_SPROM_PROBE */
254 /* OTP/SROM CIS stuff */
255 extern int si_cis_source(si_t
*sih
);
256 #define CIS_DEFAULT 0
260 /* Fab-id information */
261 #define DEFAULT_FAB 0x0 /* Original/first fab used for this chip */
262 #define CSM_FAB7 0x1 /* CSM Fab7 chip */
263 #define TSMC_FAB12 0x2 /* TSMC Fab12/Fab14 chip */
264 #define SMIC_FAB4 0x3 /* SMIC Fab4 chip */
266 #define SI_ERROR(args)
269 #define SI_MSG(args) printf args
274 /* Define SI_VMSG to printf for verbose debugging, but don't check it in */
275 #define SI_VMSG(args)
277 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
279 typedef uint32(*si_intrsoff_t
) (void *intr_arg
);
280 typedef void (*si_intrsrestore_t
) (void *intr_arg
, uint32 arg
);
281 typedef bool(*si_intrsenabled_t
) (void *intr_arg
);
283 typedef struct gpioh_item
{
286 gpio_handler_t handler
;
288 struct gpioh_item
*next
;
291 /* misc si info needed by some of the routines */
292 typedef struct si_info
{
293 struct si_pub pub
; /* back plane public state (must be first field) */
294 void *osh
; /* osl os handle */
295 void *sdh
; /* bcmsdh handle */
296 uint dev_coreid
; /* the core provides driver functions */
297 void *intr_arg
; /* interrupt callback function arg */
298 si_intrsoff_t intrsoff_fn
; /* turns chip interrupts off */
299 si_intrsrestore_t intrsrestore_fn
; /* restore chip interrupts */
300 si_intrsenabled_t intrsenabled_fn
; /* check if interrupts are enabled */
302 void *pch
; /* PCI/E core handle */
304 gpioh_item_t
*gpioh_head
; /* GPIO event handlers list */
306 bool memseg
; /* flag to toggle MEM_SEG register */
311 void *curmap
; /* current regs va */
312 void *regs
[SI_MAXCORES
]; /* other regs va */
314 uint curidx
; /* current core index */
315 uint numcores
; /* # discovered cores */
316 uint coreid
[SI_MAXCORES
]; /* id of each core */
317 uint32 coresba
[SI_MAXCORES
]; /* backplane address of each core */
318 void *regs2
[SI_MAXCORES
]; /* va of each core second register set (usbh20) */
319 uint32 coresba2
[SI_MAXCORES
]; /* address of each core second register set (usbh20) */
320 uint32 coresba_size
[SI_MAXCORES
]; /* backplane address space size */
321 uint32 coresba2_size
[SI_MAXCORES
]; /* second address space size */
323 void *curwrap
; /* current wrapper va */
324 void *wrappers
[SI_MAXCORES
]; /* other cores wrapper va */
325 uint32 wrapba
[SI_MAXCORES
]; /* address of controlling wrapper */
327 uint32 cia
[SI_MAXCORES
]; /* erom cia entry for each core */
328 uint32 cib
[SI_MAXCORES
]; /* erom cia entry for each core */
329 uint32 oob_router
; /* oob router registers for axi */
332 #define SI_INFO(sih) (si_info_t *)(uintptr)sih
334 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
335 ISALIGNED((x), SI_CORE_SIZE))
336 #define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
337 #define BADCOREADDR 0
338 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
339 #define NOREV -1 /* Invalid rev */
341 /* Newer chips can access PCI/PCIE and CC core without requiring to change
344 #define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
345 (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
347 #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
348 #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
351 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
352 * before after core switching to avoid invalid register accesss inside ISR.
354 #define INTR_OFF(si, intr_val) \
355 if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
356 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
357 #define INTR_RESTORE(si, intr_val) \
358 if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
359 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
361 /* dynamic clock control defines */
362 #define LPOMINFREQ 25000 /* low power oscillator min */
363 #define LPOMAXFREQ 43000 /* low power oscillator max */
364 #define XTALMINFREQ 19800000 /* 20 MHz - 1% */
365 #define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
366 #define PCIMINFREQ 25000000 /* 25 MHz */
367 #define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
369 #define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
370 #define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
372 #define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
373 ((si)->pub.buscoretype == PCI_CORE_ID))
374 #define PCIE(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
375 ((si)->pub.buscoretype == PCIE_CORE_ID))
376 #define PCI_FORCEHT(si) \
377 (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
379 /* GPIO Based LED powersave defines */
380 #define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
381 #define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
383 #ifndef DEFAULT_GPIOTIMERVAL
384 #define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
388 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
389 * The returned path is NULL terminated and has trailing '/'.
390 * Return 0 on success, nonzero otherwise.
392 extern int si_devpath(si_t
*sih
, char *path
, int size
);
393 /* Read variable with prepending the devpath to the name */
394 extern char *si_getdevpathvar(si_t
*sih
, const char *name
);
395 extern int si_getdevpathintvar(si_t
*sih
, const char *name
);
397 extern uint8
si_pcieclkreq(si_t
*sih
, uint32 mask
, uint32 val
);
398 extern uint32
si_pcielcreg(si_t
*sih
, uint32 mask
, uint32 val
);
399 extern void si_war42780_clkreq(si_t
*sih
, bool clkreq
);
400 extern void si_pci_sleep(si_t
*sih
);
401 extern void si_pci_down(si_t
*sih
);
402 extern void si_pci_up(si_t
*sih
);
403 extern void si_pcie_war_ovr_update(si_t
*sih
, uint8 aspm
);
404 extern void si_pcie_extendL1timer(si_t
*sih
, bool extend
);
405 extern int si_pci_fixcfg(si_t
*sih
);
406 extern void si_chippkg_set(si_t
*sih
, uint
);
408 extern void si_chipcontrl_epa4331(si_t
*sih
, bool on
);
409 /* Enable Ex-PA for 4313 */
410 extern void si_epa_4313war(si_t
*sih
);
412 /* === debug routines === */
413 extern uint32
si_pciereg(si_t
*sih
, uint32 offset
, uint32 mask
, uint32 val
,
415 extern uint32
si_pcieserdesreg(si_t
*sih
, uint32 mdioslave
, uint32 offset
,
416 uint32 mask
, uint32 val
);
418 char *si_getnvramflvar(si_t
*sih
, const char *name
);
420 /* AMBA Interconnect exported externs */
421 extern si_t
*ai_attach(uint pcidev
, osl_t
*osh
, void *regs
, uint bustype
,
422 void *sdh
, char **vars
, uint
*varsz
);
423 extern si_t
*ai_kattach(osl_t
*osh
);
424 extern void ai_scan(si_t
*sih
, void *regs
, uint devid
);
426 extern uint
ai_flag(si_t
*sih
);
427 extern void ai_setint(si_t
*sih
, int siflag
);
428 extern uint
ai_coreidx(si_t
*sih
);
429 extern uint
ai_corevendor(si_t
*sih
);
430 extern uint
ai_corerev(si_t
*sih
);
431 extern bool ai_iscoreup(si_t
*sih
);
432 extern void *ai_setcoreidx(si_t
*sih
, uint coreidx
);
433 extern uint32
ai_core_cflags(si_t
*sih
, uint32 mask
, uint32 val
);
434 extern void ai_core_cflags_wo(si_t
*sih
, uint32 mask
, uint32 val
);
435 extern uint32
ai_core_sflags(si_t
*sih
, uint32 mask
, uint32 val
);
436 extern uint
ai_corereg(si_t
*sih
, uint coreidx
, uint regoff
, uint mask
,
438 extern void ai_core_reset(si_t
*sih
, uint32 bits
, uint32 resetbits
);
439 extern void ai_core_disable(si_t
*sih
, uint32 bits
);
440 extern int ai_numaddrspaces(si_t
*sih
);
441 extern uint32
ai_addrspace(si_t
*sih
, uint asidx
);
442 extern uint32
ai_addrspacesize(si_t
*sih
, uint asidx
);
443 extern void ai_write_wrap_reg(si_t
*sih
, uint32 offset
, uint32 val
);
446 extern void ai_view(si_t
*sih
, bool verbose
);
450 #define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
451 #define si_coreid(sih) sb_coreid(sih)
452 #define si_corerev(sih) sb_corerev(sih)
455 #endif /* _siutils_h_ */