arch/arm/mach-omap2/devices.c

   1 /*
   2  * linux/arch/arm/mach-omap2/devices.c
   3  *
   4  * OMAP2 platform device setup/initialization
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/io.h>
  16 #include <linux/clk.h>
  17 #include <linux/err.h>
  18
  19 #include <mach/hardware.h>
  20 #include <mach/irqs.h>
  21 #include <asm/mach-types.h>
  22 #include <asm/mach/map.h>
  23 #include <asm/pmu.h>
  24
  25 #include <plat/tc.h>
  26 #include <plat/board.h>
  27 #include <plat/mcbsp.h>
  28 #include <mach/gpio.h>
  29 #include <plat/mmc.h>
  30 #include <plat/dma.h>
  31 #include <plat/omap_hwmod.h>
  32 #include <plat/omap_device.h>
  33
  34 #include "mux.h"
  35 #include "control.h"
  36
  37 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
  38
  39 static struct resource cam_resources[] = {
  40         {
  41                 .start          = OMAP24XX_CAMERA_BASE,
  42                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
  43                 .flags          = IORESOURCE_MEM,
  44         },
  45         {
  46                 .start          = INT_24XX_CAM_IRQ,
  47                 .flags          = IORESOURCE_IRQ,
  48         }
  49 };
  50
  51 static struct platform_device omap_cam_device = {
  52         .name           = "omap24xxcam",
  53         .id             = -1,
  54         .num_resources  = ARRAY_SIZE(cam_resources),
  55         .resource       = cam_resources,
  56 };
  57
  58 static inline void omap_init_camera(void)
  59 {
  60         platform_device_register(&omap_cam_device);
  61 }
  62
  63 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
  64
  65 static struct resource omap3isp_resources[] = {
  66         {
  67                 .start          = OMAP3430_ISP_BASE,
  68                 .end            = OMAP3430_ISP_END,
  69                 .flags          = IORESOURCE_MEM,
  70         },
  71         {
  72                 .start          = OMAP3430_ISP_CBUFF_BASE,
  73                 .end            = OMAP3430_ISP_CBUFF_END,
  74                 .flags          = IORESOURCE_MEM,
  75         },
  76         {
  77                 .start          = OMAP3430_ISP_CCP2_BASE,
  78                 .end            = OMAP3430_ISP_CCP2_END,
  79                 .flags          = IORESOURCE_MEM,
  80         },
  81         {
  82                 .start          = OMAP3430_ISP_CCDC_BASE,
  83                 .end            = OMAP3430_ISP_CCDC_END,
  84                 .flags          = IORESOURCE_MEM,
  85         },
  86         {
  87                 .start          = OMAP3430_ISP_HIST_BASE,
  88                 .end            = OMAP3430_ISP_HIST_END,
  89                 .flags          = IORESOURCE_MEM,
  90         },
  91         {
  92                 .start          = OMAP3430_ISP_H3A_BASE,
  93                 .end            = OMAP3430_ISP_H3A_END,
  94                 .flags          = IORESOURCE_MEM,
  95         },
  96         {
  97                 .start          = OMAP3430_ISP_PREV_BASE,
  98                 .end            = OMAP3430_ISP_PREV_END,
  99                 .flags          = IORESOURCE_MEM,
 100         },
 101         {
 102                 .start          = OMAP3430_ISP_RESZ_BASE,
 103                 .end            = OMAP3430_ISP_RESZ_END,
 104                 .flags          = IORESOURCE_MEM,
 105         },
 106         {
 107                 .start          = OMAP3430_ISP_SBL_BASE,
 108                 .end            = OMAP3430_ISP_SBL_END,
 109                 .flags          = IORESOURCE_MEM,
 110         },
 111         {
 112                 .start          = OMAP3430_ISP_CSI2A_BASE,
 113                 .end            = OMAP3430_ISP_CSI2A_END,
 114                 .flags          = IORESOURCE_MEM,
 115         },
 116         {
 117                 .start          = OMAP3430_ISP_CSI2PHY_BASE,
 118                 .end            = OMAP3430_ISP_CSI2PHY_END,
 119                 .flags          = IORESOURCE_MEM,
 120         },
 121         {
 122                 .start          = INT_34XX_CAM_IRQ,
 123                 .flags          = IORESOURCE_IRQ,
 124         }
 125 };
 126
 127 static struct platform_device omap3isp_device = {
 128         .name           = "omap3isp",
 129         .id             = -1,
 130         .num_resources  = ARRAY_SIZE(omap3isp_resources),
 131         .resource       = omap3isp_resources,
 132 };
 133
 134 static inline void omap_init_camera(void)
 135 {
 136         platform_device_register(&omap3isp_device);
 137 }
 138 #else
 139 static inline void omap_init_camera(void)
 140 {
 141 }
 142 #endif
 143
 144 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
 145
 146 #define MBOX_REG_SIZE   0x120
 147
 148 #ifdef CONFIG_ARCH_OMAP2
 149 static struct resource omap2_mbox_resources[] = {
 150         {
 151                 .start          = OMAP24XX_MAILBOX_BASE,
 152                 .end            = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 153                 .flags          = IORESOURCE_MEM,
 154         },
 155         {
 156                 .start          = INT_24XX_MAIL_U0_MPU,
 157                 .flags          = IORESOURCE_IRQ,
 158                 .name           = "dsp",
 159         },
 160         {
 161                 .start          = INT_24XX_MAIL_U3_MPU,
 162                 .flags          = IORESOURCE_IRQ,
 163                 .name           = "iva",
 164         },
 165 };
 166 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
 167 #else
 168 #define omap2_mbox_resources            NULL
 169 #define omap2_mbox_resources_sz         0
 170 #endif
 171
 172 #ifdef CONFIG_ARCH_OMAP3
 173 static struct resource omap3_mbox_resources[] = {
 174         {
 175                 .start          = OMAP34XX_MAILBOX_BASE,
 176                 .end            = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 177                 .flags          = IORESOURCE_MEM,
 178         },
 179         {
 180                 .start          = INT_24XX_MAIL_U0_MPU,
 181                 .flags          = IORESOURCE_IRQ,
 182                 .name           = "dsp",
 183         },
 184 };
 185 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
 186 #else
 187 #define omap3_mbox_resources            NULL
 188 #define omap3_mbox_resources_sz         0
 189 #endif
 190
 191 #ifdef CONFIG_ARCH_OMAP4
 192
 193 #define OMAP4_MBOX_REG_SIZE     0x130
 194 static struct resource omap4_mbox_resources[] = {
 195         {
 196                 .start          = OMAP44XX_MAILBOX_BASE,
 197                 .end            = OMAP44XX_MAILBOX_BASE +
 198                                         OMAP4_MBOX_REG_SIZE - 1,
 199                 .flags          = IORESOURCE_MEM,
 200         },
 201         {
 202                 .start          = OMAP44XX_IRQ_MAIL_U0,
 203                 .flags          = IORESOURCE_IRQ,
 204                 .name           = "mbox",
 205         },
 206 };
 207 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
 208 #else
 209 #define omap4_mbox_resources            NULL
 210 #define omap4_mbox_resources_sz         0
 211 #endif
 212
 213 static struct platform_device mbox_device = {
 214         .name           = "omap-mailbox",
 215         .id             = -1,
 216 };
 217
 218 static inline void omap_init_mbox(void)
 219 {
 220         if (cpu_is_omap24xx()) {
 221                 mbox_device.resource = omap2_mbox_resources;
 222                 mbox_device.num_resources = omap2_mbox_resources_sz;
 223         } else if (cpu_is_omap34xx()) {
 224                 mbox_device.resource = omap3_mbox_resources;
 225                 mbox_device.num_resources = omap3_mbox_resources_sz;
 226         } else if (cpu_is_omap44xx()) {
 227                 mbox_device.resource = omap4_mbox_resources;
 228                 mbox_device.num_resources = omap4_mbox_resources_sz;
 229         } else {
 230                 pr_err("%s: platform not supported\n", __func__);
 231                 return;
 232         }
 233         platform_device_register(&mbox_device);
 234 }
 235 #else
 236 static inline void omap_init_mbox(void) { }
 237 #endif /* CONFIG_OMAP_MBOX_FWK */
 238
 239 static inline void omap_init_sti(void) {}
 240
 241 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
 242
 243 static struct platform_device omap_pcm = {
 244         .name   = "omap-pcm-audio",
 245         .id     = -1,
 246 };
 247
 248 /*
 249  * OMAP2420 has 2 McBSP ports
 250  * OMAP2430 has 5 McBSP ports
 251  * OMAP3 has 5 McBSP ports
 252  * OMAP4 has 4 McBSP ports
 253  */
 254 OMAP_MCBSP_PLATFORM_DEVICE(1);
 255 OMAP_MCBSP_PLATFORM_DEVICE(2);
 256 OMAP_MCBSP_PLATFORM_DEVICE(3);
 257 OMAP_MCBSP_PLATFORM_DEVICE(4);
 258 OMAP_MCBSP_PLATFORM_DEVICE(5);
 259
 260 static void omap_init_audio(void)
 261 {
 262         platform_device_register(&omap_mcbsp1);
 263         platform_device_register(&omap_mcbsp2);
 264         if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 265                 platform_device_register(&omap_mcbsp3);
 266                 platform_device_register(&omap_mcbsp4);
 267         }
 268         if (cpu_is_omap243x() || cpu_is_omap34xx())
 269                 platform_device_register(&omap_mcbsp5);
 270
 271         platform_device_register(&omap_pcm);
 272 }
 273
 274 #else
 275 static inline void omap_init_audio(void) {}
 276 #endif
 277
 278 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 279
 280 #include <plat/mcspi.h>
 281
 282 #define OMAP2_MCSPI1_BASE               0x48098000
 283 #define OMAP2_MCSPI2_BASE               0x4809a000
 284 #define OMAP2_MCSPI3_BASE               0x480b8000
 285 #define OMAP2_MCSPI4_BASE               0x480ba000
 286
 287 #define OMAP4_MCSPI1_BASE               0x48098100
 288 #define OMAP4_MCSPI2_BASE               0x4809a100
 289 #define OMAP4_MCSPI3_BASE               0x480b8100
 290 #define OMAP4_MCSPI4_BASE               0x480ba100
 291
 292 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
 293         .num_cs         = 4,
 294 };
 295
 296 static struct resource omap2_mcspi1_resources[] = {
 297         {
 298                 .start          = OMAP2_MCSPI1_BASE,
 299                 .end            = OMAP2_MCSPI1_BASE + 0xff,
 300                 .flags          = IORESOURCE_MEM,
 301         },
 302 };
 303
 304 static struct platform_device omap2_mcspi1 = {
 305         .name           = "omap2_mcspi",
 306         .id             = 1,
 307         .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
 308         .resource       = omap2_mcspi1_resources,
 309         .dev            = {
 310                 .platform_data = &omap2_mcspi1_config,
 311         },
 312 };
 313
 314 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
 315         .num_cs         = 2,
 316 };
 317
 318 static struct resource omap2_mcspi2_resources[] = {
 319         {
 320                 .start          = OMAP2_MCSPI2_BASE,
 321                 .end            = OMAP2_MCSPI2_BASE + 0xff,
 322                 .flags          = IORESOURCE_MEM,
 323         },
 324 };
 325
 326 static struct platform_device omap2_mcspi2 = {
 327         .name           = "omap2_mcspi",
 328         .id             = 2,
 329         .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
 330         .resource       = omap2_mcspi2_resources,
 331         .dev            = {
 332                 .platform_data = &omap2_mcspi2_config,
 333         },
 334 };
 335
 336 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
 337         defined(CONFIG_ARCH_OMAP4)
 338 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
 339         .num_cs         = 2,
 340 };
 341
 342 static struct resource omap2_mcspi3_resources[] = {
 343         {
 344         .start          = OMAP2_MCSPI3_BASE,
 345         .end            = OMAP2_MCSPI3_BASE + 0xff,
 346         .flags          = IORESOURCE_MEM,
 347         },
 348 };
 349
 350 static struct platform_device omap2_mcspi3 = {
 351         .name           = "omap2_mcspi",
 352         .id             = 3,
 353         .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
 354         .resource       = omap2_mcspi3_resources,
 355         .dev            = {
 356                 .platform_data = &omap2_mcspi3_config,
 357         },
 358 };
 359 #endif
 360
 361 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 362 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
 363         .num_cs         = 1,
 364 };
 365
 366 static struct resource omap2_mcspi4_resources[] = {
 367         {
 368                 .start          = OMAP2_MCSPI4_BASE,
 369                 .end            = OMAP2_MCSPI4_BASE + 0xff,
 370                 .flags          = IORESOURCE_MEM,
 371         },
 372 };
 373
 374 static struct platform_device omap2_mcspi4 = {
 375         .name           = "omap2_mcspi",
 376         .id             = 4,
 377         .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
 378         .resource       = omap2_mcspi4_resources,
 379         .dev            = {
 380                 .platform_data = &omap2_mcspi4_config,
 381         },
 382 };
 383 #endif
 384
 385 #ifdef CONFIG_ARCH_OMAP4
 386 static inline void omap4_mcspi_fixup(void)
 387 {
 388         omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
 389         omap2_mcspi1_resources[0].end   = OMAP4_MCSPI1_BASE + 0xff;
 390         omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
 391         omap2_mcspi2_resources[0].end   = OMAP4_MCSPI2_BASE + 0xff;
 392         omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
 393         omap2_mcspi3_resources[0].end   = OMAP4_MCSPI3_BASE + 0xff;
 394         omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
 395         omap2_mcspi4_resources[0].end   = OMAP4_MCSPI4_BASE + 0xff;
 396 }
 397 #else
 398 static inline void omap4_mcspi_fixup(void)
 399 {
 400 }
 401 #endif
 402
 403 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
 404         defined(CONFIG_ARCH_OMAP4)
 405 static inline void omap2_mcspi3_init(void)
 406 {
 407         platform_device_register(&omap2_mcspi3);
 408 }
 409 #else
 410 static inline void omap2_mcspi3_init(void)
 411 {
 412 }
 413 #endif
 414
 415 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 416 static inline void omap2_mcspi4_init(void)
 417 {
 418         platform_device_register(&omap2_mcspi4);
 419 }
 420 #else
 421 static inline void omap2_mcspi4_init(void)
 422 {
 423 }
 424 #endif
 425
 426 static void omap_init_mcspi(void)
 427 {
 428         if (cpu_is_omap44xx())
 429                 omap4_mcspi_fixup();
 430
 431         platform_device_register(&omap2_mcspi1);
 432         platform_device_register(&omap2_mcspi2);
 433
 434         if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
 435                 omap2_mcspi3_init();
 436
 437         if (cpu_is_omap343x() || cpu_is_omap44xx())
 438                 omap2_mcspi4_init();
 439 }
 440
 441 #else
 442 static inline void omap_init_mcspi(void) {}
 443 #endif
 444
 445 static struct resource omap2_pmu_resource = {
 446         .start  = 3,
 447         .end    = 3,
 448         .flags  = IORESOURCE_IRQ,
 449 };
 450
 451 static struct resource omap3_pmu_resource = {
 452         .start  = INT_34XX_BENCH_MPU_EMUL,
 453         .end    = INT_34XX_BENCH_MPU_EMUL,
 454         .flags  = IORESOURCE_IRQ,
 455 };
 456
 457 static struct platform_device omap_pmu_device = {
 458         .name           = "arm-pmu",
 459         .id             = ARM_PMU_DEVICE_CPU,
 460         .num_resources  = 1,
 461 };
 462
 463 static void omap_init_pmu(void)
 464 {
 465         if (cpu_is_omap24xx())
 466                 omap_pmu_device.resource = &omap2_pmu_resource;
 467         else if (cpu_is_omap34xx())
 468                 omap_pmu_device.resource = &omap3_pmu_resource;
 469         else
 470                 return;
 471
 472         platform_device_register(&omap_pmu_device);
 473 }
 474
 475
 476 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
 477
 478 #ifdef CONFIG_ARCH_OMAP2
 479 static struct resource omap2_sham_resources[] = {
 480         {
 481                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
 482                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
 483                 .flags  = IORESOURCE_MEM,
 484         },
 485         {
 486                 .start  = INT_24XX_SHA1MD5,
 487                 .flags  = IORESOURCE_IRQ,
 488         }
 489 };
 490 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
 491 #else
 492 #define omap2_sham_resources            NULL
 493 #define omap2_sham_resources_sz         0
 494 #endif
 495
 496 #ifdef CONFIG_ARCH_OMAP3
 497 static struct resource omap3_sham_resources[] = {
 498         {
 499                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
 500                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
 501                 .flags  = IORESOURCE_MEM,
 502         },
 503         {
 504                 .start  = INT_34XX_SHA1MD52_IRQ,
 505                 .flags  = IORESOURCE_IRQ,
 506         },
 507         {
 508                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
 509                 .flags  = IORESOURCE_DMA,
 510         }
 511 };
 512 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
 513 #else
 514 #define omap3_sham_resources            NULL
 515 #define omap3_sham_resources_sz         0
 516 #endif
 517
 518 static struct platform_device sham_device = {
 519         .name           = "omap-sham",
 520         .id             = -1,
 521 };
 522
 523 static void omap_init_sham(void)
 524 {
 525         if (cpu_is_omap24xx()) {
 526                 sham_device.resource = omap2_sham_resources;
 527                 sham_device.num_resources = omap2_sham_resources_sz;
 528         } else if (cpu_is_omap34xx()) {
 529                 sham_device.resource = omap3_sham_resources;
 530                 sham_device.num_resources = omap3_sham_resources_sz;
 531         } else {
 532                 pr_err("%s: platform not supported\n", __func__);
 533                 return;
 534         }
 535         platform_device_register(&sham_device);
 536 }
 537 #else
 538 static inline void omap_init_sham(void) { }
 539 #endif
 540
 541 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
 542
 543 #ifdef CONFIG_ARCH_OMAP2
 544 static struct resource omap2_aes_resources[] = {
 545         {
 546                 .start  = OMAP24XX_SEC_AES_BASE,
 547                 .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
 548                 .flags  = IORESOURCE_MEM,
 549         },
 550         {
 551                 .start  = OMAP24XX_DMA_AES_TX,
 552                 .flags  = IORESOURCE_DMA,
 553         },
 554         {
 555                 .start  = OMAP24XX_DMA_AES_RX,
 556                 .flags  = IORESOURCE_DMA,
 557         }
 558 };
 559 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
 560 #else
 561 #define omap2_aes_resources             NULL
 562 #define omap2_aes_resources_sz          0
 563 #endif
 564
 565 #ifdef CONFIG_ARCH_OMAP3
 566 static struct resource omap3_aes_resources[] = {
 567         {
 568                 .start  = OMAP34XX_SEC_AES_BASE,
 569                 .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
 570                 .flags  = IORESOURCE_MEM,
 571         },
 572         {
 573                 .start  = OMAP34XX_DMA_AES2_TX,
 574                 .flags  = IORESOURCE_DMA,
 575         },
 576         {
 577                 .start  = OMAP34XX_DMA_AES2_RX,
 578                 .flags  = IORESOURCE_DMA,
 579         }
 580 };
 581 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
 582 #else
 583 #define omap3_aes_resources             NULL
 584 #define omap3_aes_resources_sz          0
 585 #endif
 586
 587 static struct platform_device aes_device = {
 588         .name           = "omap-aes",
 589         .id             = -1,
 590 };
 591
 592 static void omap_init_aes(void)
 593 {
 594         if (cpu_is_omap24xx()) {
 595                 aes_device.resource = omap2_aes_resources;
 596                 aes_device.num_resources = omap2_aes_resources_sz;
 597         } else if (cpu_is_omap34xx()) {
 598                 aes_device.resource = omap3_aes_resources;
 599                 aes_device.num_resources = omap3_aes_resources_sz;
 600         } else {
 601                 pr_err("%s: platform not supported\n", __func__);
 602                 return;
 603         }
 604         platform_device_register(&aes_device);
 605 }
 606
 607 #else
 608 static inline void omap_init_aes(void) { }
 609 #endif
 610
 611 /*-------------------------------------------------------------------------*/
 612
 613 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 614
 615 #define MMCHS_SYSCONFIG                 0x0010
 616 #define MMCHS_SYSCONFIG_SWRESET         (1 << 1)
 617 #define MMCHS_SYSSTATUS                 0x0014
 618 #define MMCHS_SYSSTATUS_RESETDONE       (1 << 0)
 619
 620 static struct platform_device dummy_pdev = {
 621         .dev = {
 622                 .bus = &platform_bus_type,
 623         },
 624 };
 625
 626 /**
 627  * omap_hsmmc_reset() - Full reset of each HS-MMC controller
 628  *
 629  * Ensure that each MMC controller is fully reset.  Controllers
 630  * left in an unknown state (by bootloader) may prevent retention
 631  * or OFF-mode.  This is especially important in cases where the
 632  * MMC driver is not enabled, _or_ built as a module.
 633  *
 634  * In order for reset to work, interface, functional and debounce
 635  * clocks must be enabled.  The debounce clock comes from func_32k_clk
 636  * and is not under SW control, so we only enable i- and f-clocks.
 637  **/
 638 static void __init omap_hsmmc_reset(void)
 639 {
 640         u32 i, nr_controllers;
 641
 642         if (cpu_is_omap242x())
 643                 return;
 644
 645         nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
 646                 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
 647
 648         for (i = 0; i < nr_controllers; i++) {
 649                 u32 v, base = 0;
 650                 struct clk *iclk, *fclk;
 651                 struct device *dev = &dummy_pdev.dev;
 652
 653                 switch (i) {
 654                 case 0:
 655                         base = OMAP2_MMC1_BASE;
 656                         break;
 657                 case 1:
 658                         base = OMAP2_MMC2_BASE;
 659                         break;
 660                 case 2:
 661                         base = OMAP3_MMC3_BASE;
 662                         break;
 663                 case 3:
 664                         if (!cpu_is_omap44xx())
 665                                 return;
 666                         base = OMAP4_MMC4_BASE;
 667                         break;
 668                 case 4:
 669                         if (!cpu_is_omap44xx())
 670                                 return;
 671                         base = OMAP4_MMC5_BASE;
 672                         break;
 673                 }
 674
 675                 if (cpu_is_omap44xx())
 676                         base += OMAP4_MMC_REG_OFFSET;
 677
 678                 dummy_pdev.id = i;
 679                 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
 680                 iclk = clk_get(dev, "ick");
 681                 if (iclk && clk_enable(iclk))
 682                         iclk = NULL;
 683
 684                 fclk = clk_get(dev, "fck");
 685                 if (fclk && clk_enable(fclk))
 686                         fclk = NULL;
 687
 688                 if (!iclk || !fclk) {
 689                         printk(KERN_WARNING
 690                                "%s: Unable to enable clocks for MMC%d, "
 691                                "cannot reset.\n",  __func__, i);
 692                         break;
 693                 }
 694
 695                 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
 696                 v = omap_readl(base + MMCHS_SYSSTATUS);
 697                 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
 698                          MMCHS_SYSSTATUS_RESETDONE))
 699                         cpu_relax();
 700
 701                 if (fclk) {
 702                         clk_disable(fclk);
 703                         clk_put(fclk);
 704                 }
 705                 if (iclk) {
 706                         clk_disable(iclk);
 707                         clk_put(iclk);
 708                 }
 709         }
 710 }
 711 #else
 712 static inline void omap_hsmmc_reset(void) {}
 713 #endif
 714
 715 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
 716         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 717
 718 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
 719                         int controller_nr)
 720 {
 721         if ((mmc_controller->slots[0].switch_pin > 0) && \
 722                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
 723                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
 724                                         OMAP_PIN_INPUT_PULLUP);
 725         if ((mmc_controller->slots[0].gpio_wp > 0) && \
 726                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
 727                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
 728                                         OMAP_PIN_INPUT_PULLUP);
 729
 730         if (cpu_is_omap2420() && controller_nr == 0) {
 731                 omap_mux_init_signal("sdmmc_cmd", 0);
 732                 omap_mux_init_signal("sdmmc_clki", 0);
 733                 omap_mux_init_signal("sdmmc_clko", 0);
 734                 omap_mux_init_signal("sdmmc_dat0", 0);
 735                 omap_mux_init_signal("sdmmc_dat_dir0", 0);
 736                 omap_mux_init_signal("sdmmc_cmd_dir", 0);
 737                 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
 738                         omap_mux_init_signal("sdmmc_dat1", 0);
 739                         omap_mux_init_signal("sdmmc_dat2", 0);
 740                         omap_mux_init_signal("sdmmc_dat3", 0);
 741                         omap_mux_init_signal("sdmmc_dat_dir1", 0);
 742                         omap_mux_init_signal("sdmmc_dat_dir2", 0);
 743                         omap_mux_init_signal("sdmmc_dat_dir3", 0);
 744                 }
 745
 746                 /*
 747                  * Use internal loop-back in MMC/SDIO Module Input Clock
 748                  * selection
 749                  */
 750                 if (mmc_controller->slots[0].internal_clock) {
 751                         u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 752                         v |= (1 << 24);
 753                         omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 754                 }
 755         }
 756
 757         if (cpu_is_omap34xx()) {
 758                 if (controller_nr == 0) {
 759                         omap_mux_init_signal("sdmmc1_clk",
 760                                 OMAP_PIN_INPUT_PULLUP);
 761                         omap_mux_init_signal("sdmmc1_cmd",
 762                                 OMAP_PIN_INPUT_PULLUP);
 763                         omap_mux_init_signal("sdmmc1_dat0",
 764                                 OMAP_PIN_INPUT_PULLUP);
 765                         if (mmc_controller->slots[0].caps &
 766                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 767                                 omap_mux_init_signal("sdmmc1_dat1",
 768                                         OMAP_PIN_INPUT_PULLUP);
 769                                 omap_mux_init_signal("sdmmc1_dat2",
 770                                         OMAP_PIN_INPUT_PULLUP);
 771                                 omap_mux_init_signal("sdmmc1_dat3",
 772                                         OMAP_PIN_INPUT_PULLUP);
 773                         }
 774                         if (mmc_controller->slots[0].caps &
 775                                                 MMC_CAP_8_BIT_DATA) {
 776                                 omap_mux_init_signal("sdmmc1_dat4",
 777                                         OMAP_PIN_INPUT_PULLUP);
 778                                 omap_mux_init_signal("sdmmc1_dat5",
 779                                         OMAP_PIN_INPUT_PULLUP);
 780                                 omap_mux_init_signal("sdmmc1_dat6",
 781                                         OMAP_PIN_INPUT_PULLUP);
 782                                 omap_mux_init_signal("sdmmc1_dat7",
 783                                         OMAP_PIN_INPUT_PULLUP);
 784                         }
 785                 }
 786                 if (controller_nr == 1) {
 787                         /* MMC2 */
 788                         omap_mux_init_signal("sdmmc2_clk",
 789                                 OMAP_PIN_INPUT_PULLUP);
 790                         omap_mux_init_signal("sdmmc2_cmd",
 791                                 OMAP_PIN_INPUT_PULLUP);
 792                         omap_mux_init_signal("sdmmc2_dat0",
 793                                 OMAP_PIN_INPUT_PULLUP);
 794
 795                         /*
 796                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
 797                          * in the board-*.c files
 798                          */
 799                         if (mmc_controller->slots[0].caps &
 800                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 801                                 omap_mux_init_signal("sdmmc2_dat1",
 802                                         OMAP_PIN_INPUT_PULLUP);
 803                                 omap_mux_init_signal("sdmmc2_dat2",
 804                                         OMAP_PIN_INPUT_PULLUP);
 805                                 omap_mux_init_signal("sdmmc2_dat3",
 806                                         OMAP_PIN_INPUT_PULLUP);
 807                         }
 808                         if (mmc_controller->slots[0].caps &
 809                                                         MMC_CAP_8_BIT_DATA) {
 810                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 811                                         OMAP_PIN_INPUT_PULLUP);
 812                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 813                                         OMAP_PIN_INPUT_PULLUP);
 814                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 815                                         OMAP_PIN_INPUT_PULLUP);
 816                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 817                                         OMAP_PIN_INPUT_PULLUP);
 818                         }
 819                 }
 820
 821                 /*
 822                  * For MMC3 the pins need to be muxed in the board-*.c files
 823                  */
 824         }
 825 }
 826
 827 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
 828                         int nr_controllers)
 829 {
 830         int i;
 831         char *name;
 832
 833         for (i = 0; i < nr_controllers; i++) {
 834                 unsigned long base, size;
 835                 unsigned int irq = 0;
 836
 837                 if (!mmc_data[i])
 838                         continue;
 839
 840                 omap2_mmc_mux(mmc_data[i], i);
 841
 842                 switch (i) {
 843                 case 0:
 844                         base = OMAP2_MMC1_BASE;
 845                         irq = INT_24XX_MMC_IRQ;
 846                         break;
 847                 case 1:
 848                         base = OMAP2_MMC2_BASE;
 849                         irq = INT_24XX_MMC2_IRQ;
 850                         break;
 851                 case 2:
 852                         if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
 853                                 return;
 854                         base = OMAP3_MMC3_BASE;
 855                         irq = INT_34XX_MMC3_IRQ;
 856                         break;
 857                 case 3:
 858                         if (!cpu_is_omap44xx())
 859                                 return;
 860                         base = OMAP4_MMC4_BASE;
 861                         irq = OMAP44XX_IRQ_MMC4;
 862                         break;
 863                 case 4:
 864                         if (!cpu_is_omap44xx())
 865                                 return;
 866                         base = OMAP4_MMC5_BASE;
 867                         irq = OMAP44XX_IRQ_MMC5;
 868                         break;
 869                 default:
 870                         continue;
 871                 }
 872
 873                 if (cpu_is_omap2420()) {
 874                         size = OMAP2420_MMC_SIZE;
 875                         name = "mmci-omap";
 876                 } else if (cpu_is_omap44xx()) {
 877                         if (i < 3)
 878                                 irq += OMAP44XX_IRQ_GIC_START;
 879                         size = OMAP4_HSMMC_SIZE;
 880                         name = "mmci-omap-hs";
 881                 } else {
 882                         size = OMAP3_HSMMC_SIZE;
 883                         name = "mmci-omap-hs";
 884                 }
 885                 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
 886         };
 887 }
 888
 889 #endif
 890
 891 /*-------------------------------------------------------------------------*/
 892
 893 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
 894 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
 895 #define OMAP_HDQ_BASE   0x480B2000
 896 #endif
 897 static struct resource omap_hdq_resources[] = {
 898         {
 899                 .start          = OMAP_HDQ_BASE,
 900                 .end            = OMAP_HDQ_BASE + 0x1C,
 901                 .flags          = IORESOURCE_MEM,
 902         },
 903         {
 904                 .start          = INT_24XX_HDQ_IRQ,
 905                 .flags          = IORESOURCE_IRQ,
 906         },
 907 };
 908 static struct platform_device omap_hdq_dev = {
 909         .name = "omap_hdq",
 910         .id = 0,
 911         .dev = {
 912                 .platform_data = NULL,
 913         },
 914         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
 915         .resource       = omap_hdq_resources,
 916 };
 917 static inline void omap_hdq_init(void)
 918 {
 919         (void) platform_device_register(&omap_hdq_dev);
 920 }
 921 #else
 922 static inline void omap_hdq_init(void) {}
 923 #endif
 924
 925 /*---------------------------------------------------------------------------*/
 926
 927 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
 928         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
 929 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
 930 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
 931 };
 932 #else
 933 static struct resource omap_vout_resource[2] = {
 934 };
 935 #endif
 936
 937 static struct platform_device omap_vout_device = {
 938         .name           = "omap_vout",
 939         .num_resources  = ARRAY_SIZE(omap_vout_resource),
 940         .resource       = &omap_vout_resource[0],
 941         .id             = -1,
 942 };
 943 static void omap_init_vout(void)
 944 {
 945         if (platform_device_register(&omap_vout_device) < 0)
 946                 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
 947 }
 948 #else
 949 static inline void omap_init_vout(void) {}
 950 #endif
 951
 952 /*-------------------------------------------------------------------------*/
 953
 954 /*
 955  * Inorder to avoid any assumptions from bootloader regarding WDT
 956  * settings, WDT module is reset during init. This enables the watchdog
 957  * timer. Hence it is required to disable the watchdog after the WDT reset
 958  * during init. Otherwise the system would reboot as per the default
 959  * watchdog timer registers settings.
 960  */
 961 #define OMAP_WDT_WPS    (0x34)
 962 #define OMAP_WDT_SPR    (0x48)
 963
 964 static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused)
 965 {
 966         void __iomem *base;
 967         int ret;
 968
 969         if (!oh) {
 970                 pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
 971                 return -EINVAL;
 972         }
 973
 974         base = omap_hwmod_get_mpu_rt_va(oh);
 975         if (!base) {
 976                 pr_err("%s: Could not get the base address for %s\n",
 977                                 oh->name, __func__);
 978                 return -EINVAL;
 979         }
 980
 981         /* Enable the clocks before accessing the WDT registers */
 982         ret = omap_hwmod_enable(oh);
 983         if (ret) {
 984                 pr_err("%s: Could not enable clocks for %s\n",
 985                                 oh->name, __func__);
 986                 return ret;
 987         }
 988
 989         /* sequence required to disable watchdog */
 990         __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
 991         while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
 992                 cpu_relax();
 993
 994         __raw_writel(0x5555, base + OMAP_WDT_SPR);
 995         while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
 996                 cpu_relax();
 997
 998         ret = omap_hwmod_idle(oh);
 999         if (ret)
1000                 pr_err("%s: Could not disable clocks for %s\n",
1001                                 oh->name, __func__);
1002
1003         return ret;
1004 }
1005
1006 static void __init omap_disable_wdt(void)
1007 {
1008         if (cpu_class_is_omap2())
1009                 omap_hwmod_for_each_by_class("wd_timer",
1010                                                 omap2_disable_wdt, NULL);
1011         return;
1012 }
1013
1014 static int __init omap2_init_devices(void)
1015 {
1016         /* please keep these calls, and their implementations above,
1017          * in alphabetical order so they're easier to sort through.
1018          */
1019         omap_disable_wdt();
1020         omap_hsmmc_reset();
1021         omap_init_audio();
1022         omap_init_camera();
1023         omap_init_mbox();
1024         omap_init_mcspi();
1025         omap_init_pmu();
1026         omap_hdq_init();
1027         omap_init_sti();
1028         omap_init_sham();
1029         omap_init_aes();
1030         omap_init_vout();
1031
1032         return 0;
1033 }
1034 arch_initcall(omap2_init_devices);
1035
1036 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
1037 struct omap_device_pm_latency omap_wdt_latency[] = {
1038         [0] = {
1039                 .deactivate_func = omap_device_idle_hwmods,
1040                 .activate_func   = omap_device_enable_hwmods,
1041                 .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
1042         },
1043 };
1044
1045 static int __init omap_init_wdt(void)
1046 {
1047         int id = -1;
1048         struct omap_device *od;
1049         struct omap_hwmod *oh;
1050         char *oh_name = "wd_timer2";
1051         char *dev_name = "omap_wdt";
1052
1053         if (!cpu_class_is_omap2())
1054                 return 0;
1055
1056         oh = omap_hwmod_lookup(oh_name);
1057         if (!oh) {
1058                 pr_err("Could not look up wd_timer%d hwmod\n", id);
1059                 return -EINVAL;
1060         }
1061
1062         od = omap_device_build(dev_name, id, oh, NULL, 0,
1063                                 omap_wdt_latency,
1064                                 ARRAY_SIZE(omap_wdt_latency), 0);
1065         WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
1066                                 dev_name, oh->name);
1067         return 0;
1068 }
1069 subsys_initcall(omap_init_wdt);
1070 #endif