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Merge tag 'v3.5-rc4' into drm-intel-next-queued
[linux-2.6/libata-dev.git] / drivers / gpu / drm / i915 / intel_dp.c
blob76a708029dcb9fb94abaf5c13b75c633df474c04
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc.h"
34 #include "drm_crtc_helper.h"
35 #include "drm_edid.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "drm_dp_helper.h"
40
41 #define DP_RECEIVER_CAP_SIZE 0xf
42 #define DP_LINK_STATUS_SIZE 6
43 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44
45 #define DP_LINK_CONFIGURATION_SIZE 9
46
47 struct intel_dp {
48 struct intel_encoder base;
49 uint32_t output_reg;
50 uint32_t DP;
51 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
52 bool has_audio;
53 enum hdmi_force_audio force_audio;
54 uint32_t color_range;
55 int dpms_mode;
56 uint8_t link_bw;
57 uint8_t lane_count;
58 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
59 struct i2c_adapter adapter;
60 struct i2c_algo_dp_aux_data algo;
61 bool is_pch_edp;
62 uint8_t train_set[4];
63 int panel_power_up_delay;
64 int panel_power_down_delay;
65 int panel_power_cycle_delay;
66 int backlight_on_delay;
67 int backlight_off_delay;
68 struct drm_display_mode *panel_fixed_mode; /* for eDP */
69 struct delayed_work panel_vdd_work;
70 bool want_panel_vdd;
71 struct edid *edid; /* cached EDID for eDP */
72 int edid_mode_count;
73 };
74
75 /**
76 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
77 * @intel_dp: DP struct
78 *
79 * If a CPU or PCH DP output is attached to an eDP panel, this function
80 * will return true, and false otherwise.
81 */
82 static bool is_edp(struct intel_dp *intel_dp)
83 {
84 return intel_dp->base.type == INTEL_OUTPUT_EDP;
85 }
86
87 /**
88 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
89 * @intel_dp: DP struct
90 *
91 * Returns true if the given DP struct corresponds to a PCH DP port attached
92 * to an eDP panel, false otherwise. Helpful for determining whether we
93 * may need FDI resources for a given DP output or not.
94 */
95 static bool is_pch_edp(struct intel_dp *intel_dp)
96 {
97 return intel_dp->is_pch_edp;
98 }
99
100 /**
101 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
102 * @intel_dp: DP struct
103 *
104 * Returns true if the given DP struct corresponds to a CPU eDP port.
105 */
106 static bool is_cpu_edp(struct intel_dp *intel_dp)
107 {
108 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
109 }
110
111 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
112 {
113 return container_of(encoder, struct intel_dp, base.base);
114 }
115
116 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
117 {
118 return container_of(intel_attached_encoder(connector),
119 struct intel_dp, base);
120 }
121
122 /**
123 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
124 * @encoder: DRM encoder
125 *
126 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
127 * by intel_display.c.
128 */
129 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
130 {
131 struct intel_dp *intel_dp;
132
133 if (!encoder)
134 return false;
135
136 intel_dp = enc_to_intel_dp(encoder);
137
138 return is_pch_edp(intel_dp);
139 }
140
141 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
142 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
143 static void intel_dp_link_down(struct intel_dp *intel_dp);
144
145 void
146 intel_edp_link_config(struct intel_encoder *intel_encoder,
147 int *lane_num, int *link_bw)
148 {
149 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
150
151 *lane_num = intel_dp->lane_count;
152 if (intel_dp->link_bw == DP_LINK_BW_1_62)
153 *link_bw = 162000;
154 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
155 *link_bw = 270000;
156 }
157
158 int
159 intel_edp_target_clock(struct intel_encoder *intel_encoder,
160 struct drm_display_mode *mode)
161 {
162 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
163
164 if (intel_dp->panel_fixed_mode)
165 return intel_dp->panel_fixed_mode->clock;
166 else
167 return mode->clock;
168 }
169
170 static int
171 intel_dp_max_lane_count(struct intel_dp *intel_dp)
172 {
173 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
174 switch (max_lane_count) {
175 case 1: case 2: case 4:
176 break;
177 default:
178 max_lane_count = 4;
179 }
180 return max_lane_count;
181 }
182
183 static int
184 intel_dp_max_link_bw(struct intel_dp *intel_dp)
185 {
186 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
187
188 switch (max_link_bw) {
189 case DP_LINK_BW_1_62:
190 case DP_LINK_BW_2_7:
191 break;
192 default:
193 max_link_bw = DP_LINK_BW_1_62;
194 break;
195 }
196 return max_link_bw;
197 }
198
199 static int
200 intel_dp_link_clock(uint8_t link_bw)
201 {
202 if (link_bw == DP_LINK_BW_2_7)
203 return 270000;
204 else
205 return 162000;
206 }
207
208 /*
209 * The units on the numbers in the next two are... bizarre. Examples will
210 * make it clearer; this one parallels an example in the eDP spec.
211 *
212 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
213 *
214 * 270000 * 1 * 8 / 10 == 216000
215 *
216 * The actual data capacity of that configuration is 2.16Gbit/s, so the
217 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
218 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
219 * 119000. At 18bpp that's 2142000 kilobits per second.
220 *
221 * Thus the strange-looking division by 10 in intel_dp_link_required, to
222 * get the result in decakilobits instead of kilobits.
223 */
224
225 static int
226 intel_dp_link_required(int pixel_clock, int bpp)
227 {
228 return (pixel_clock * bpp + 9) / 10;
229 }
230
231 static int
232 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
233 {
234 return (max_link_clock * max_lanes * 8) / 10;
235 }
236
237 static bool
238 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
239 struct drm_display_mode *mode,
240 bool adjust_mode)
241 {
242 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
243 int max_lanes = intel_dp_max_lane_count(intel_dp);
244 int max_rate, mode_rate;
245
246 mode_rate = intel_dp_link_required(mode->clock, 24);
247 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
248
249 if (mode_rate > max_rate) {
250 mode_rate = intel_dp_link_required(mode->clock, 18);
251 if (mode_rate > max_rate)
252 return false;
253
254 if (adjust_mode)
255 mode->private_flags
256 |= INTEL_MODE_DP_FORCE_6BPC;
257
258 return true;
259 }
260
261 return true;
262 }
263
264 static int
265 intel_dp_mode_valid(struct drm_connector *connector,
266 struct drm_display_mode *mode)
267 {
268 struct intel_dp *intel_dp = intel_attached_dp(connector);
269
270 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
271 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
272 return MODE_PANEL;
273
274 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
275 return MODE_PANEL;
276 }
277
278 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
279 return MODE_CLOCK_HIGH;
280
281 if (mode->clock < 10000)
282 return MODE_CLOCK_LOW;
283
284 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
285 return MODE_H_ILLEGAL;
286
287 return MODE_OK;
288 }
289
290 static uint32_t
291 pack_aux(uint8_t *src, int src_bytes)
292 {
293 int i;
294 uint32_t v = 0;
295
296 if (src_bytes > 4)
297 src_bytes = 4;
298 for (i = 0; i < src_bytes; i++)
299 v |= ((uint32_t) src[i]) << ((3-i) * 8);
300 return v;
301 }
302
303 static void
304 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
305 {
306 int i;
307 if (dst_bytes > 4)
308 dst_bytes = 4;
309 for (i = 0; i < dst_bytes; i++)
310 dst[i] = src >> ((3-i) * 8);
311 }
312
313 /* hrawclock is 1/4 the FSB frequency */
314 static int
315 intel_hrawclk(struct drm_device *dev)
316 {
317 struct drm_i915_private *dev_priv = dev->dev_private;
318 uint32_t clkcfg;
319
320 clkcfg = I915_READ(CLKCFG);
321 switch (clkcfg & CLKCFG_FSB_MASK) {
322 case CLKCFG_FSB_400:
323 return 100;
324 case CLKCFG_FSB_533:
325 return 133;
326 case CLKCFG_FSB_667:
327 return 166;
328 case CLKCFG_FSB_800:
329 return 200;
330 case CLKCFG_FSB_1067:
331 return 266;
332 case CLKCFG_FSB_1333:
333 return 333;
334 /* these two are just a guess; one of them might be right */
335 case CLKCFG_FSB_1600:
336 case CLKCFG_FSB_1600_ALT:
337 return 400;
338 default:
339 return 133;
340 }
341 }
342
343 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
344 {
345 struct drm_device *dev = intel_dp->base.base.dev;
346 struct drm_i915_private *dev_priv = dev->dev_private;
347
348 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
349 }
350
351 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
352 {
353 struct drm_device *dev = intel_dp->base.base.dev;
354 struct drm_i915_private *dev_priv = dev->dev_private;
355
356 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
357 }
358
359 static void
360 intel_dp_check_edp(struct intel_dp *intel_dp)
361 {
362 struct drm_device *dev = intel_dp->base.base.dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
364
365 if (!is_edp(intel_dp))
366 return;
367 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
368 WARN(1, "eDP powered off while attempting aux channel communication.\n");
369 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
370 I915_READ(PCH_PP_STATUS),
371 I915_READ(PCH_PP_CONTROL));
372 }
373 }
374
375 static int
376 intel_dp_aux_ch(struct intel_dp *intel_dp,
377 uint8_t *send, int send_bytes,
378 uint8_t *recv, int recv_size)
379 {
380 uint32_t output_reg = intel_dp->output_reg;
381 struct drm_device *dev = intel_dp->base.base.dev;
382 struct drm_i915_private *dev_priv = dev->dev_private;
383 uint32_t ch_ctl = output_reg + 0x10;
384 uint32_t ch_data = ch_ctl + 4;
385 int i;
386 int recv_bytes;
387 uint32_t status;
388 uint32_t aux_clock_divider;
389 int try, precharge;
390
391 intel_dp_check_edp(intel_dp);
392 /* The clock divider is based off the hrawclk,
393 * and would like to run at 2MHz. So, take the
394 * hrawclk value and divide by 2 and use that
395 *
396 * Note that PCH attached eDP panels should use a 125MHz input
397 * clock divider.
398 */
399 if (is_cpu_edp(intel_dp)) {
400 if (IS_GEN6(dev) || IS_GEN7(dev))
401 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
402 else
403 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
404 } else if (HAS_PCH_SPLIT(dev))
405 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
406 else
407 aux_clock_divider = intel_hrawclk(dev) / 2;
408
409 if (IS_GEN6(dev))
410 precharge = 3;
411 else
412 precharge = 5;
413
414 /* Try to wait for any previous AUX channel activity */
415 for (try = 0; try < 3; try++) {
416 status = I915_READ(ch_ctl);
417 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
418 break;
419 msleep(1);
420 }
421
422 if (try == 3) {
423 WARN(1, "dp_aux_ch not started status 0x%08x\n",
424 I915_READ(ch_ctl));
425 return -EBUSY;
426 }
427
428 /* Must try at least 3 times according to DP spec */
429 for (try = 0; try < 5; try++) {
430 /* Load the send data into the aux channel data registers */
431 for (i = 0; i < send_bytes; i += 4)
432 I915_WRITE(ch_data + i,
433 pack_aux(send + i, send_bytes - i));
434
435 /* Send the command and wait for it to complete */
436 I915_WRITE(ch_ctl,
437 DP_AUX_CH_CTL_SEND_BUSY |
438 DP_AUX_CH_CTL_TIME_OUT_400us |
439 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
440 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
441 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
442 DP_AUX_CH_CTL_DONE |
443 DP_AUX_CH_CTL_TIME_OUT_ERROR |
444 DP_AUX_CH_CTL_RECEIVE_ERROR);
445 for (;;) {
446 status = I915_READ(ch_ctl);
447 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
448 break;
449 udelay(100);
450 }
451
452 /* Clear done status and any errors */
453 I915_WRITE(ch_ctl,
454 status |
455 DP_AUX_CH_CTL_DONE |
456 DP_AUX_CH_CTL_TIME_OUT_ERROR |
457 DP_AUX_CH_CTL_RECEIVE_ERROR);
458
459 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
460 DP_AUX_CH_CTL_RECEIVE_ERROR))
461 continue;
462 if (status & DP_AUX_CH_CTL_DONE)
463 break;
464 }
465
466 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
467 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
468 return -EBUSY;
469 }
470
471 /* Check for timeout or receive error.
472 * Timeouts occur when the sink is not connected
473 */
474 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
475 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
476 return -EIO;
477 }
478
479 /* Timeouts occur when the device isn't connected, so they're
480 * "normal" -- don't fill the kernel log with these */
481 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
482 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
483 return -ETIMEDOUT;
484 }
485
486 /* Unload any bytes sent back from the other side */
487 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
488 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
489 if (recv_bytes > recv_size)
490 recv_bytes = recv_size;
491
492 for (i = 0; i < recv_bytes; i += 4)
493 unpack_aux(I915_READ(ch_data + i),
494 recv + i, recv_bytes - i);
495
496 return recv_bytes;
497 }
498
499 /* Write data to the aux channel in native mode */
500 static int
501 intel_dp_aux_native_write(struct intel_dp *intel_dp,
502 uint16_t address, uint8_t *send, int send_bytes)
503 {
504 int ret;
505 uint8_t msg[20];
506 int msg_bytes;
507 uint8_t ack;
508
509 intel_dp_check_edp(intel_dp);
510 if (send_bytes > 16)
511 return -1;
512 msg[0] = AUX_NATIVE_WRITE << 4;
513 msg[1] = address >> 8;
514 msg[2] = address & 0xff;
515 msg[3] = send_bytes - 1;
516 memcpy(&msg[4], send, send_bytes);
517 msg_bytes = send_bytes + 4;
518 for (;;) {
519 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
520 if (ret < 0)
521 return ret;
522 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
523 break;
524 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
525 udelay(100);
526 else
527 return -EIO;
528 }
529 return send_bytes;
530 }
531
532 /* Write a single byte to the aux channel in native mode */
533 static int
534 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
535 uint16_t address, uint8_t byte)
536 {
537 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
538 }
539
540 /* read bytes from a native aux channel */
541 static int
542 intel_dp_aux_native_read(struct intel_dp *intel_dp,
543 uint16_t address, uint8_t *recv, int recv_bytes)
544 {
545 uint8_t msg[4];
546 int msg_bytes;
547 uint8_t reply[20];
548 int reply_bytes;
549 uint8_t ack;
550 int ret;
551
552 intel_dp_check_edp(intel_dp);
553 msg[0] = AUX_NATIVE_READ << 4;
554 msg[1] = address >> 8;
555 msg[2] = address & 0xff;
556 msg[3] = recv_bytes - 1;
557
558 msg_bytes = 4;
559 reply_bytes = recv_bytes + 1;
560
561 for (;;) {
562 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
563 reply, reply_bytes);
564 if (ret == 0)
565 return -EPROTO;
566 if (ret < 0)
567 return ret;
568 ack = reply[0];
569 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
570 memcpy(recv, reply + 1, ret - 1);
571 return ret - 1;
572 }
573 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
574 udelay(100);
575 else
576 return -EIO;
577 }
578 }
579
580 static int
581 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
582 uint8_t write_byte, uint8_t *read_byte)
583 {
584 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
585 struct intel_dp *intel_dp = container_of(adapter,
586 struct intel_dp,
587 adapter);
588 uint16_t address = algo_data->address;
589 uint8_t msg[5];
590 uint8_t reply[2];
591 unsigned retry;
592 int msg_bytes;
593 int reply_bytes;
594 int ret;
595
596 intel_dp_check_edp(intel_dp);
597 /* Set up the command byte */
598 if (mode & MODE_I2C_READ)
599 msg[0] = AUX_I2C_READ << 4;
600 else
601 msg[0] = AUX_I2C_WRITE << 4;
602
603 if (!(mode & MODE_I2C_STOP))
604 msg[0] |= AUX_I2C_MOT << 4;
605
606 msg[1] = address >> 8;
607 msg[2] = address;
608
609 switch (mode) {
610 case MODE_I2C_WRITE:
611 msg[3] = 0;
612 msg[4] = write_byte;
613 msg_bytes = 5;
614 reply_bytes = 1;
615 break;
616 case MODE_I2C_READ:
617 msg[3] = 0;
618 msg_bytes = 4;
619 reply_bytes = 2;
620 break;
621 default:
622 msg_bytes = 3;
623 reply_bytes = 1;
624 break;
625 }
626
627 for (retry = 0; retry < 5; retry++) {
628 ret = intel_dp_aux_ch(intel_dp,
629 msg, msg_bytes,
630 reply, reply_bytes);
631 if (ret < 0) {
632 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
633 return ret;
634 }
635
636 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
637 case AUX_NATIVE_REPLY_ACK:
638 /* I2C-over-AUX Reply field is only valid
639 * when paired with AUX ACK.
640 */
641 break;
642 case AUX_NATIVE_REPLY_NACK:
643 DRM_DEBUG_KMS("aux_ch native nack\n");
644 return -EREMOTEIO;
645 case AUX_NATIVE_REPLY_DEFER:
646 udelay(100);
647 continue;
648 default:
649 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
650 reply[0]);
651 return -EREMOTEIO;
652 }
653
654 switch (reply[0] & AUX_I2C_REPLY_MASK) {
655 case AUX_I2C_REPLY_ACK:
656 if (mode == MODE_I2C_READ) {
657 *read_byte = reply[1];
658 }
659 return reply_bytes - 1;
660 case AUX_I2C_REPLY_NACK:
661 DRM_DEBUG_KMS("aux_i2c nack\n");
662 return -EREMOTEIO;
663 case AUX_I2C_REPLY_DEFER:
664 DRM_DEBUG_KMS("aux_i2c defer\n");
665 udelay(100);
666 break;
667 default:
668 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
669 return -EREMOTEIO;
670 }
671 }
672
673 DRM_ERROR("too many retries, giving up\n");
674 return -EREMOTEIO;
675 }
676
677 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
678 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
679
680 static int
681 intel_dp_i2c_init(struct intel_dp *intel_dp,
682 struct intel_connector *intel_connector, const char *name)
683 {
684 int ret;
685
686 DRM_DEBUG_KMS("i2c_init %s\n", name);
687 intel_dp->algo.running = false;
688 intel_dp->algo.address = 0;
689 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
690
691 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
692 intel_dp->adapter.owner = THIS_MODULE;
693 intel_dp->adapter.class = I2C_CLASS_DDC;
694 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
695 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
696 intel_dp->adapter.algo_data = &intel_dp->algo;
697 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
698
699 ironlake_edp_panel_vdd_on(intel_dp);
700 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
701 ironlake_edp_panel_vdd_off(intel_dp, false);
702 return ret;
703 }
704
705 static bool
706 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
707 struct drm_display_mode *adjusted_mode)
708 {
709 struct drm_device *dev = encoder->dev;
710 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
711 int lane_count, clock;
712 int max_lane_count = intel_dp_max_lane_count(intel_dp);
713 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
714 int bpp, mode_rate;
715 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
716
717 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
718 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
719 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
720 mode, adjusted_mode);
721 }
722
723 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
724 return false;
725
726 DRM_DEBUG_KMS("DP link computation with max lane count %i "
727 "max bw %02x pixel clock %iKHz\n",
728 max_lane_count, bws[max_clock], adjusted_mode->clock);
729
730 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
731 return false;
732
733 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
734 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
735
736 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
737 for (clock = 0; clock <= max_clock; clock++) {
738 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
739
740 if (mode_rate <= link_avail) {
741 intel_dp->link_bw = bws[clock];
742 intel_dp->lane_count = lane_count;
743 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
744 DRM_DEBUG_KMS("DP link bw %02x lane "
745 "count %d clock %d bpp %d\n",
746 intel_dp->link_bw, intel_dp->lane_count,
747 adjusted_mode->clock, bpp);
748 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
749 mode_rate, link_avail);
750 return true;
751 }
752 }
753 }
754
755 return false;
756 }
757
758 struct intel_dp_m_n {
759 uint32_t tu;
760 uint32_t gmch_m;
761 uint32_t gmch_n;
762 uint32_t link_m;
763 uint32_t link_n;
764 };
765
766 static void
767 intel_reduce_ratio(uint32_t *num, uint32_t *den)
768 {
769 while (*num > 0xffffff || *den > 0xffffff) {
770 *num >>= 1;
771 *den >>= 1;
772 }
773 }
774
775 static void
776 intel_dp_compute_m_n(int bpp,
777 int nlanes,
778 int pixel_clock,
779 int link_clock,
780 struct intel_dp_m_n *m_n)
781 {
782 m_n->tu = 64;
783 m_n->gmch_m = (pixel_clock * bpp) >> 3;
784 m_n->gmch_n = link_clock * nlanes;
785 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
786 m_n->link_m = pixel_clock;
787 m_n->link_n = link_clock;
788 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
789 }
790
791 void
792 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
793 struct drm_display_mode *adjusted_mode)
794 {
795 struct drm_device *dev = crtc->dev;
796 struct drm_mode_config *mode_config = &dev->mode_config;
797 struct drm_encoder *encoder;
798 struct drm_i915_private *dev_priv = dev->dev_private;
799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
800 int lane_count = 4;
801 struct intel_dp_m_n m_n;
802 int pipe = intel_crtc->pipe;
803
804 /*
805 * Find the lane count in the intel_encoder private
806 */
807 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
808 struct intel_dp *intel_dp;
809
810 if (encoder->crtc != crtc)
811 continue;
812
813 intel_dp = enc_to_intel_dp(encoder);
814 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
815 intel_dp->base.type == INTEL_OUTPUT_EDP)
816 {
817 lane_count = intel_dp->lane_count;
818 break;
819 }
820 }
821
822 /*
823 * Compute the GMCH and Link ratios. The '3' here is
824 * the number of bytes_per_pixel post-LUT, which we always
825 * set up for 8-bits of R/G/B, or 3 bytes total.
826 */
827 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
828 mode->clock, adjusted_mode->clock, &m_n);
829
830 if (HAS_PCH_SPLIT(dev)) {
831 I915_WRITE(TRANSDATA_M1(pipe),
832 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
833 m_n.gmch_m);
834 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
835 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
836 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
837 } else {
838 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
839 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
840 m_n.gmch_m);
841 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
842 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
843 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
844 }
845 }
846
847 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
848 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
849
850 static void
851 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
852 struct drm_display_mode *adjusted_mode)
853 {
854 struct drm_device *dev = encoder->dev;
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
857 struct drm_crtc *crtc = intel_dp->base.base.crtc;
858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
859
860 /* Turn on the eDP PLL if needed */
861 if (is_edp(intel_dp)) {
862 if (!is_pch_edp(intel_dp))
863 ironlake_edp_pll_on(encoder);
864 else
865 ironlake_edp_pll_off(encoder);
866 }
867
868 /*
869 * There are four kinds of DP registers:
870 *
871 * IBX PCH
872 * SNB CPU
873 * IVB CPU
874 * CPT PCH
875 *
876 * IBX PCH and CPU are the same for almost everything,
877 * except that the CPU DP PLL is configured in this
878 * register
879 *
880 * CPT PCH is quite different, having many bits moved
881 * to the TRANS_DP_CTL register instead. That
882 * configuration happens (oddly) in ironlake_pch_enable
883 */
884
885 /* Preserve the BIOS-computed detected bit. This is
886 * supposed to be read-only.
887 */
888 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
889 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
890
891 /* Handle DP bits in common between all three register formats */
892
893 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
894
895 switch (intel_dp->lane_count) {
896 case 1:
897 intel_dp->DP |= DP_PORT_WIDTH_1;
898 break;
899 case 2:
900 intel_dp->DP |= DP_PORT_WIDTH_2;
901 break;
902 case 4:
903 intel_dp->DP |= DP_PORT_WIDTH_4;
904 break;
905 }
906 if (intel_dp->has_audio) {
907 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
908 pipe_name(intel_crtc->pipe));
909 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
910 intel_write_eld(encoder, adjusted_mode);
911 }
912 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
913 intel_dp->link_configuration[0] = intel_dp->link_bw;
914 intel_dp->link_configuration[1] = intel_dp->lane_count;
915 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
916 /*
917 * Check for DPCD version > 1.1 and enhanced framing support
918 */
919 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
920 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
921 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
922 }
923
924 /* Split out the IBX/CPU vs CPT settings */
925
926 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
927 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
928 intel_dp->DP |= DP_SYNC_HS_HIGH;
929 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
930 intel_dp->DP |= DP_SYNC_VS_HIGH;
931 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
932
933 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
934 intel_dp->DP |= DP_ENHANCED_FRAMING;
935
936 intel_dp->DP |= intel_crtc->pipe << 29;
937
938 /* don't miss out required setting for eDP */
939 intel_dp->DP |= DP_PLL_ENABLE;
940 if (adjusted_mode->clock < 200000)
941 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
942 else
943 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
944 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
945 intel_dp->DP |= intel_dp->color_range;
946
947 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
948 intel_dp->DP |= DP_SYNC_HS_HIGH;
949 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
950 intel_dp->DP |= DP_SYNC_VS_HIGH;
951 intel_dp->DP |= DP_LINK_TRAIN_OFF;
952
953 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
954 intel_dp->DP |= DP_ENHANCED_FRAMING;
955
956 if (intel_crtc->pipe == 1)
957 intel_dp->DP |= DP_PIPEB_SELECT;
958
959 if (is_cpu_edp(intel_dp)) {
960 /* don't miss out required setting for eDP */
961 intel_dp->DP |= DP_PLL_ENABLE;
962 if (adjusted_mode->clock < 200000)
963 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
964 else
965 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
966 }
967 } else {
968 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
969 }
970 }
971
972 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
973 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
974
975 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
976 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
977
978 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
979 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
980
981 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
982 u32 mask,
983 u32 value)
984 {
985 struct drm_device *dev = intel_dp->base.base.dev;
986 struct drm_i915_private *dev_priv = dev->dev_private;
987
988 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
989 mask, value,
990 I915_READ(PCH_PP_STATUS),
991 I915_READ(PCH_PP_CONTROL));
992
993 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
994 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
995 I915_READ(PCH_PP_STATUS),
996 I915_READ(PCH_PP_CONTROL));
997 }
998 }
999
1000 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1001 {
1002 DRM_DEBUG_KMS("Wait for panel power on\n");
1003 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1004 }
1005
1006 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1007 {
1008 DRM_DEBUG_KMS("Wait for panel power off time\n");
1009 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1010 }
1011
1012 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1013 {
1014 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1015 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1016 }
1017
1018
1019 /* Read the current pp_control value, unlocking the register if it
1020 * is locked
1021 */
1022
1023 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1024 {
1025 u32 control = I915_READ(PCH_PP_CONTROL);
1026
1027 control &= ~PANEL_UNLOCK_MASK;
1028 control |= PANEL_UNLOCK_REGS;
1029 return control;
1030 }
1031
1032 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1033 {
1034 struct drm_device *dev = intel_dp->base.base.dev;
1035 struct drm_i915_private *dev_priv = dev->dev_private;
1036 u32 pp;
1037
1038 if (!is_edp(intel_dp))
1039 return;
1040 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1041
1042 WARN(intel_dp->want_panel_vdd,
1043 "eDP VDD already requested on\n");
1044
1045 intel_dp->want_panel_vdd = true;
1046
1047 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1048 DRM_DEBUG_KMS("eDP VDD already on\n");
1049 return;
1050 }
1051
1052 if (!ironlake_edp_have_panel_power(intel_dp))
1053 ironlake_wait_panel_power_cycle(intel_dp);
1054
1055 pp = ironlake_get_pp_control(dev_priv);
1056 pp |= EDP_FORCE_VDD;
1057 I915_WRITE(PCH_PP_CONTROL, pp);
1058 POSTING_READ(PCH_PP_CONTROL);
1059 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1060 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1061
1062 /*
1063 * If the panel wasn't on, delay before accessing aux channel
1064 */
1065 if (!ironlake_edp_have_panel_power(intel_dp)) {
1066 DRM_DEBUG_KMS("eDP was not running\n");
1067 msleep(intel_dp->panel_power_up_delay);
1068 }
1069 }
1070
1071 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1072 {
1073 struct drm_device *dev = intel_dp->base.base.dev;
1074 struct drm_i915_private *dev_priv = dev->dev_private;
1075 u32 pp;
1076
1077 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1078 pp = ironlake_get_pp_control(dev_priv);
1079 pp &= ~EDP_FORCE_VDD;
1080 I915_WRITE(PCH_PP_CONTROL, pp);
1081 POSTING_READ(PCH_PP_CONTROL);
1082
1083 /* Make sure sequencer is idle before allowing subsequent activity */
1084 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1085 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1086
1087 msleep(intel_dp->panel_power_down_delay);
1088 }
1089 }
1090
1091 static void ironlake_panel_vdd_work(struct work_struct *__work)
1092 {
1093 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1094 struct intel_dp, panel_vdd_work);
1095 struct drm_device *dev = intel_dp->base.base.dev;
1096
1097 mutex_lock(&dev->mode_config.mutex);
1098 ironlake_panel_vdd_off_sync(intel_dp);
1099 mutex_unlock(&dev->mode_config.mutex);
1100 }
1101
1102 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1103 {
1104 if (!is_edp(intel_dp))
1105 return;
1106
1107 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1108 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1109
1110 intel_dp->want_panel_vdd = false;
1111
1112 if (sync) {
1113 ironlake_panel_vdd_off_sync(intel_dp);
1114 } else {
1115 /*
1116 * Queue the timer to fire a long
1117 * time from now (relative to the power down delay)
1118 * to keep the panel power up across a sequence of operations
1119 */
1120 schedule_delayed_work(&intel_dp->panel_vdd_work,
1121 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1122 }
1123 }
1124
1125 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1126 {
1127 struct drm_device *dev = intel_dp->base.base.dev;
1128 struct drm_i915_private *dev_priv = dev->dev_private;
1129 u32 pp;
1130
1131 if (!is_edp(intel_dp))
1132 return;
1133
1134 DRM_DEBUG_KMS("Turn eDP power on\n");
1135
1136 if (ironlake_edp_have_panel_power(intel_dp)) {
1137 DRM_DEBUG_KMS("eDP power already on\n");
1138 return;
1139 }
1140
1141 ironlake_wait_panel_power_cycle(intel_dp);
1142
1143 pp = ironlake_get_pp_control(dev_priv);
1144 if (IS_GEN5(dev)) {
1145 /* ILK workaround: disable reset around power sequence */
1146 pp &= ~PANEL_POWER_RESET;
1147 I915_WRITE(PCH_PP_CONTROL, pp);
1148 POSTING_READ(PCH_PP_CONTROL);
1149 }
1150
1151 pp |= POWER_TARGET_ON;
1152 if (!IS_GEN5(dev))
1153 pp |= PANEL_POWER_RESET;
1154
1155 I915_WRITE(PCH_PP_CONTROL, pp);
1156 POSTING_READ(PCH_PP_CONTROL);
1157
1158 ironlake_wait_panel_on(intel_dp);
1159
1160 if (IS_GEN5(dev)) {
1161 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1162 I915_WRITE(PCH_PP_CONTROL, pp);
1163 POSTING_READ(PCH_PP_CONTROL);
1164 }
1165 }
1166
1167 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1168 {
1169 struct drm_device *dev = intel_dp->base.base.dev;
1170 struct drm_i915_private *dev_priv = dev->dev_private;
1171 u32 pp;
1172
1173 if (!is_edp(intel_dp))
1174 return;
1175
1176 DRM_DEBUG_KMS("Turn eDP power off\n");
1177
1178 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1179
1180 pp = ironlake_get_pp_control(dev_priv);
1181 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1182 I915_WRITE(PCH_PP_CONTROL, pp);
1183 POSTING_READ(PCH_PP_CONTROL);
1184
1185 ironlake_wait_panel_off(intel_dp);
1186 }
1187
1188 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1189 {
1190 struct drm_device *dev = intel_dp->base.base.dev;
1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 u32 pp;
1193
1194 if (!is_edp(intel_dp))
1195 return;
1196
1197 DRM_DEBUG_KMS("\n");
1198 /*
1199 * If we enable the backlight right away following a panel power
1200 * on, we may see slight flicker as the panel syncs with the eDP
1201 * link. So delay a bit to make sure the image is solid before
1202 * allowing it to appear.
1203 */
1204 msleep(intel_dp->backlight_on_delay);
1205 pp = ironlake_get_pp_control(dev_priv);
1206 pp |= EDP_BLC_ENABLE;
1207 I915_WRITE(PCH_PP_CONTROL, pp);
1208 POSTING_READ(PCH_PP_CONTROL);
1209 }
1210
1211 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1212 {
1213 struct drm_device *dev = intel_dp->base.base.dev;
1214 struct drm_i915_private *dev_priv = dev->dev_private;
1215 u32 pp;
1216
1217 if (!is_edp(intel_dp))
1218 return;
1219
1220 DRM_DEBUG_KMS("\n");
1221 pp = ironlake_get_pp_control(dev_priv);
1222 pp &= ~EDP_BLC_ENABLE;
1223 I915_WRITE(PCH_PP_CONTROL, pp);
1224 POSTING_READ(PCH_PP_CONTROL);
1225 msleep(intel_dp->backlight_off_delay);
1226 }
1227
1228 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1229 {
1230 struct drm_device *dev = encoder->dev;
1231 struct drm_i915_private *dev_priv = dev->dev_private;
1232 u32 dpa_ctl;
1233
1234 DRM_DEBUG_KMS("\n");
1235 dpa_ctl = I915_READ(DP_A);
1236 dpa_ctl |= DP_PLL_ENABLE;
1237 I915_WRITE(DP_A, dpa_ctl);
1238 POSTING_READ(DP_A);
1239 udelay(200);
1240 }
1241
1242 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1243 {
1244 struct drm_device *dev = encoder->dev;
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246 u32 dpa_ctl;
1247
1248 dpa_ctl = I915_READ(DP_A);
1249 dpa_ctl &= ~DP_PLL_ENABLE;
1250 I915_WRITE(DP_A, dpa_ctl);
1251 POSTING_READ(DP_A);
1252 udelay(200);
1253 }
1254
1255 /* If the sink supports it, try to set the power state appropriately */
1256 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1257 {
1258 int ret, i;
1259
1260 /* Should have a valid DPCD by this point */
1261 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1262 return;
1263
1264 if (mode != DRM_MODE_DPMS_ON) {
1265 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1266 DP_SET_POWER_D3);
1267 if (ret != 1)
1268 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1269 } else {
1270 /*
1271 * When turning on, we need to retry for 1ms to give the sink
1272 * time to wake up.
1273 */
1274 for (i = 0; i < 3; i++) {
1275 ret = intel_dp_aux_native_write_1(intel_dp,
1276 DP_SET_POWER,
1277 DP_SET_POWER_D0);
1278 if (ret == 1)
1279 break;
1280 msleep(1);
1281 }
1282 }
1283 }
1284
1285 static void intel_dp_prepare(struct drm_encoder *encoder)
1286 {
1287 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1288
1289
1290 /* Make sure the panel is off before trying to change the mode. But also
1291 * ensure that we have vdd while we switch off the panel. */
1292 ironlake_edp_panel_vdd_on(intel_dp);
1293 ironlake_edp_backlight_off(intel_dp);
1294 ironlake_edp_panel_off(intel_dp);
1295
1296 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1297 intel_dp_link_down(intel_dp);
1298 ironlake_edp_panel_vdd_off(intel_dp, false);
1299 }
1300
1301 static void intel_dp_commit(struct drm_encoder *encoder)
1302 {
1303 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1304 struct drm_device *dev = encoder->dev;
1305 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1306
1307 ironlake_edp_panel_vdd_on(intel_dp);
1308 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1309 intel_dp_start_link_train(intel_dp);
1310 ironlake_edp_panel_on(intel_dp);
1311 ironlake_edp_panel_vdd_off(intel_dp, true);
1312 intel_dp_complete_link_train(intel_dp);
1313 ironlake_edp_backlight_on(intel_dp);
1314
1315 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1316
1317 if (HAS_PCH_CPT(dev))
1318 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1319 }
1320
1321 static void
1322 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1323 {
1324 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1325 struct drm_device *dev = encoder->dev;
1326 struct drm_i915_private *dev_priv = dev->dev_private;
1327 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1328
1329 if (mode != DRM_MODE_DPMS_ON) {
1330 /* Switching the panel off requires vdd. */
1331 ironlake_edp_panel_vdd_on(intel_dp);
1332 ironlake_edp_backlight_off(intel_dp);
1333 ironlake_edp_panel_off(intel_dp);
1334
1335 intel_dp_sink_dpms(intel_dp, mode);
1336 intel_dp_link_down(intel_dp);
1337 ironlake_edp_panel_vdd_off(intel_dp, false);
1338
1339 if (is_cpu_edp(intel_dp))
1340 ironlake_edp_pll_off(encoder);
1341 } else {
1342 if (is_cpu_edp(intel_dp))
1343 ironlake_edp_pll_on(encoder);
1344
1345 ironlake_edp_panel_vdd_on(intel_dp);
1346 intel_dp_sink_dpms(intel_dp, mode);
1347 if (!(dp_reg & DP_PORT_EN)) {
1348 intel_dp_start_link_train(intel_dp);
1349 ironlake_edp_panel_on(intel_dp);
1350 ironlake_edp_panel_vdd_off(intel_dp, true);
1351 intel_dp_complete_link_train(intel_dp);
1352 } else
1353 ironlake_edp_panel_vdd_off(intel_dp, false);
1354 ironlake_edp_backlight_on(intel_dp);
1355 }
1356 intel_dp->dpms_mode = mode;
1357 }
1358
1359 /*
1360 * Native read with retry for link status and receiver capability reads for
1361 * cases where the sink may still be asleep.
1362 */
1363 static bool
1364 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1365 uint8_t *recv, int recv_bytes)
1366 {
1367 int ret, i;
1368
1369 /*
1370 * Sinks are *supposed* to come up within 1ms from an off state,
1371 * but we're also supposed to retry 3 times per the spec.
1372 */
1373 for (i = 0; i < 3; i++) {
1374 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1375 recv_bytes);
1376 if (ret == recv_bytes)
1377 return true;
1378 msleep(1);
1379 }
1380
1381 return false;
1382 }
1383
1384 /*
1385 * Fetch AUX CH registers 0x202 - 0x207 which contain
1386 * link status information
1387 */
1388 static bool
1389 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1390 {
1391 return intel_dp_aux_native_read_retry(intel_dp,
1392 DP_LANE0_1_STATUS,
1393 link_status,
1394 DP_LINK_STATUS_SIZE);
1395 }
1396
1397 static uint8_t
1398 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1399 int r)
1400 {
1401 return link_status[r - DP_LANE0_1_STATUS];
1402 }
1403
1404 static uint8_t
1405 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1406 int lane)
1407 {
1408 int s = ((lane & 1) ?
1409 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1410 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1411 uint8_t l = adjust_request[lane>>1];
1412
1413 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1414 }
1415
1416 static uint8_t
1417 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1418 int lane)
1419 {
1420 int s = ((lane & 1) ?
1421 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1422 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1423 uint8_t l = adjust_request[lane>>1];
1424
1425 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1426 }
1427
1428
1429 #if 0
1430 static char *voltage_names[] = {
1431 "0.4V", "0.6V", "0.8V", "1.2V"
1432 };
1433 static char *pre_emph_names[] = {
1434 "0dB", "3.5dB", "6dB", "9.5dB"
1435 };
1436 static char *link_train_names[] = {
1437 "pattern 1", "pattern 2", "idle", "off"
1438 };
1439 #endif
1440
1441 /*
1442 * These are source-specific values; current Intel hardware supports
1443 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1444 */
1445
1446 static uint8_t
1447 intel_dp_voltage_max(struct intel_dp *intel_dp)
1448 {
1449 struct drm_device *dev = intel_dp->base.base.dev;
1450
1451 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1452 return DP_TRAIN_VOLTAGE_SWING_800;
1453 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1454 return DP_TRAIN_VOLTAGE_SWING_1200;
1455 else
1456 return DP_TRAIN_VOLTAGE_SWING_800;
1457 }
1458
1459 static uint8_t
1460 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1461 {
1462 struct drm_device *dev = intel_dp->base.base.dev;
1463
1464 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1465 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1466 case DP_TRAIN_VOLTAGE_SWING_400:
1467 return DP_TRAIN_PRE_EMPHASIS_6;
1468 case DP_TRAIN_VOLTAGE_SWING_600:
1469 case DP_TRAIN_VOLTAGE_SWING_800:
1470 return DP_TRAIN_PRE_EMPHASIS_3_5;
1471 default:
1472 return DP_TRAIN_PRE_EMPHASIS_0;
1473 }
1474 } else {
1475 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1476 case DP_TRAIN_VOLTAGE_SWING_400:
1477 return DP_TRAIN_PRE_EMPHASIS_6;
1478 case DP_TRAIN_VOLTAGE_SWING_600:
1479 return DP_TRAIN_PRE_EMPHASIS_6;
1480 case DP_TRAIN_VOLTAGE_SWING_800:
1481 return DP_TRAIN_PRE_EMPHASIS_3_5;
1482 case DP_TRAIN_VOLTAGE_SWING_1200:
1483 default:
1484 return DP_TRAIN_PRE_EMPHASIS_0;
1485 }
1486 }
1487 }
1488
1489 static void
1490 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1491 {
1492 uint8_t v = 0;
1493 uint8_t p = 0;
1494 int lane;
1495 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1496 uint8_t voltage_max;
1497 uint8_t preemph_max;
1498
1499 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1500 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1501 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1502
1503 if (this_v > v)
1504 v = this_v;
1505 if (this_p > p)
1506 p = this_p;
1507 }
1508
1509 voltage_max = intel_dp_voltage_max(intel_dp);
1510 if (v >= voltage_max)
1511 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1512
1513 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1514 if (p >= preemph_max)
1515 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1516
1517 for (lane = 0; lane < 4; lane++)
1518 intel_dp->train_set[lane] = v | p;
1519 }
1520
1521 static uint32_t
1522 intel_dp_signal_levels(uint8_t train_set)
1523 {
1524 uint32_t signal_levels = 0;
1525
1526 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1527 case DP_TRAIN_VOLTAGE_SWING_400:
1528 default:
1529 signal_levels |= DP_VOLTAGE_0_4;
1530 break;
1531 case DP_TRAIN_VOLTAGE_SWING_600:
1532 signal_levels |= DP_VOLTAGE_0_6;
1533 break;
1534 case DP_TRAIN_VOLTAGE_SWING_800:
1535 signal_levels |= DP_VOLTAGE_0_8;
1536 break;
1537 case DP_TRAIN_VOLTAGE_SWING_1200:
1538 signal_levels |= DP_VOLTAGE_1_2;
1539 break;
1540 }
1541 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1542 case DP_TRAIN_PRE_EMPHASIS_0:
1543 default:
1544 signal_levels |= DP_PRE_EMPHASIS_0;
1545 break;
1546 case DP_TRAIN_PRE_EMPHASIS_3_5:
1547 signal_levels |= DP_PRE_EMPHASIS_3_5;
1548 break;
1549 case DP_TRAIN_PRE_EMPHASIS_6:
1550 signal_levels |= DP_PRE_EMPHASIS_6;
1551 break;
1552 case DP_TRAIN_PRE_EMPHASIS_9_5:
1553 signal_levels |= DP_PRE_EMPHASIS_9_5;
1554 break;
1555 }
1556 return signal_levels;
1557 }
1558
1559 /* Gen6's DP voltage swing and pre-emphasis control */
1560 static uint32_t
1561 intel_gen6_edp_signal_levels(uint8_t train_set)
1562 {
1563 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1564 DP_TRAIN_PRE_EMPHASIS_MASK);
1565 switch (signal_levels) {
1566 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1567 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1568 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1569 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1570 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1571 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1572 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1573 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1574 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1575 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1576 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1577 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1578 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1579 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1580 default:
1581 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1582 "0x%x\n", signal_levels);
1583 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1584 }
1585 }
1586
1587 /* Gen7's DP voltage swing and pre-emphasis control */
1588 static uint32_t
1589 intel_gen7_edp_signal_levels(uint8_t train_set)
1590 {
1591 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1592 DP_TRAIN_PRE_EMPHASIS_MASK);
1593 switch (signal_levels) {
1594 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1595 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1596 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1597 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1598 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1599 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1600
1601 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1602 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1603 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1604 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1605
1606 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1607 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1608 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1609 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1610
1611 default:
1612 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1613 "0x%x\n", signal_levels);
1614 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1615 }
1616 }
1617
1618 static uint8_t
1619 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1620 int lane)
1621 {
1622 int s = (lane & 1) * 4;
1623 uint8_t l = link_status[lane>>1];
1624
1625 return (l >> s) & 0xf;
1626 }
1627
1628 /* Check for clock recovery is done on all channels */
1629 static bool
1630 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1631 {
1632 int lane;
1633 uint8_t lane_status;
1634
1635 for (lane = 0; lane < lane_count; lane++) {
1636 lane_status = intel_get_lane_status(link_status, lane);
1637 if ((lane_status & DP_LANE_CR_DONE) == 0)
1638 return false;
1639 }
1640 return true;
1641 }
1642
1643 /* Check to see if channel eq is done on all channels */
1644 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1645 DP_LANE_CHANNEL_EQ_DONE|\
1646 DP_LANE_SYMBOL_LOCKED)
1647 static bool
1648 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1649 {
1650 uint8_t lane_align;
1651 uint8_t lane_status;
1652 int lane;
1653
1654 lane_align = intel_dp_link_status(link_status,
1655 DP_LANE_ALIGN_STATUS_UPDATED);
1656 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1657 return false;
1658 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1659 lane_status = intel_get_lane_status(link_status, lane);
1660 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1661 return false;
1662 }
1663 return true;
1664 }
1665
1666 static bool
1667 intel_dp_set_link_train(struct intel_dp *intel_dp,
1668 uint32_t dp_reg_value,
1669 uint8_t dp_train_pat)
1670 {
1671 struct drm_device *dev = intel_dp->base.base.dev;
1672 struct drm_i915_private *dev_priv = dev->dev_private;
1673 int ret;
1674
1675 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1676 POSTING_READ(intel_dp->output_reg);
1677
1678 intel_dp_aux_native_write_1(intel_dp,
1679 DP_TRAINING_PATTERN_SET,
1680 dp_train_pat);
1681
1682 ret = intel_dp_aux_native_write(intel_dp,
1683 DP_TRAINING_LANE0_SET,
1684 intel_dp->train_set,
1685 intel_dp->lane_count);
1686 if (ret != intel_dp->lane_count)
1687 return false;
1688
1689 return true;
1690 }
1691
1692 /* Enable corresponding port and start training pattern 1 */
1693 static void
1694 intel_dp_start_link_train(struct intel_dp *intel_dp)
1695 {
1696 struct drm_device *dev = intel_dp->base.base.dev;
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1699 int i;
1700 uint8_t voltage;
1701 bool clock_recovery = false;
1702 int voltage_tries, loop_tries;
1703 u32 reg;
1704 uint32_t DP = intel_dp->DP;
1705
1706 /*
1707 * On CPT we have to enable the port in training pattern 1, which
1708 * will happen below in intel_dp_set_link_train. Otherwise, enable
1709 * the port and wait for it to become active.
1710 */
1711 if (!HAS_PCH_CPT(dev)) {
1712 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1713 POSTING_READ(intel_dp->output_reg);
1714 intel_wait_for_vblank(dev, intel_crtc->pipe);
1715 }
1716
1717 /* Write the link configuration data */
1718 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1719 intel_dp->link_configuration,
1720 DP_LINK_CONFIGURATION_SIZE);
1721
1722 DP |= DP_PORT_EN;
1723
1724 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1725 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1726 else
1727 DP &= ~DP_LINK_TRAIN_MASK;
1728 memset(intel_dp->train_set, 0, 4);
1729 voltage = 0xff;
1730 voltage_tries = 0;
1731 loop_tries = 0;
1732 clock_recovery = false;
1733 for (;;) {
1734 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1735 uint8_t link_status[DP_LINK_STATUS_SIZE];
1736 uint32_t signal_levels;
1737
1738
1739 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1740 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1741 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1742 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1743 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1744 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1745 } else {
1746 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1747 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1748 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1749 }
1750
1751 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1752 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1753 else
1754 reg = DP | DP_LINK_TRAIN_PAT_1;
1755
1756 if (!intel_dp_set_link_train(intel_dp, reg,
1757 DP_TRAINING_PATTERN_1 |
1758 DP_LINK_SCRAMBLING_DISABLE))
1759 break;
1760 /* Set training pattern 1 */
1761
1762 udelay(100);
1763 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1764 DRM_ERROR("failed to get link status\n");
1765 break;
1766 }
1767
1768 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1769 DRM_DEBUG_KMS("clock recovery OK\n");
1770 clock_recovery = true;
1771 break;
1772 }
1773
1774 /* Check to see if we've tried the max voltage */
1775 for (i = 0; i < intel_dp->lane_count; i++)
1776 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1777 break;
1778 if (i == intel_dp->lane_count) {
1779 ++loop_tries;
1780 if (loop_tries == 5) {
1781 DRM_DEBUG_KMS("too many full retries, give up\n");
1782 break;
1783 }
1784 memset(intel_dp->train_set, 0, 4);
1785 voltage_tries = 0;
1786 continue;
1787 }
1788
1789 /* Check to see if we've tried the same voltage 5 times */
1790 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1791 ++voltage_tries;
1792 if (voltage_tries == 5) {
1793 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1794 break;
1795 }
1796 } else
1797 voltage_tries = 0;
1798 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1799
1800 /* Compute new intel_dp->train_set as requested by target */
1801 intel_get_adjust_train(intel_dp, link_status);
1802 }
1803
1804 intel_dp->DP = DP;
1805 }
1806
1807 static void
1808 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1809 {
1810 struct drm_device *dev = intel_dp->base.base.dev;
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 bool channel_eq = false;
1813 int tries, cr_tries;
1814 u32 reg;
1815 uint32_t DP = intel_dp->DP;
1816
1817 /* channel equalization */
1818 tries = 0;
1819 cr_tries = 0;
1820 channel_eq = false;
1821 for (;;) {
1822 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1823 uint32_t signal_levels;
1824 uint8_t link_status[DP_LINK_STATUS_SIZE];
1825
1826 if (cr_tries > 5) {
1827 DRM_ERROR("failed to train DP, aborting\n");
1828 intel_dp_link_down(intel_dp);
1829 break;
1830 }
1831
1832 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1833 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1834 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1835 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1836 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1837 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1838 } else {
1839 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1840 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1841 }
1842
1843 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1844 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1845 else
1846 reg = DP | DP_LINK_TRAIN_PAT_2;
1847
1848 /* channel eq pattern */
1849 if (!intel_dp_set_link_train(intel_dp, reg,
1850 DP_TRAINING_PATTERN_2 |
1851 DP_LINK_SCRAMBLING_DISABLE))
1852 break;
1853
1854 udelay(400);
1855 if (!intel_dp_get_link_status(intel_dp, link_status))
1856 break;
1857
1858 /* Make sure clock is still ok */
1859 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1860 intel_dp_start_link_train(intel_dp);
1861 cr_tries++;
1862 continue;
1863 }
1864
1865 if (intel_channel_eq_ok(intel_dp, link_status)) {
1866 channel_eq = true;
1867 break;
1868 }
1869
1870 /* Try 5 times, then try clock recovery if that fails */
1871 if (tries > 5) {
1872 intel_dp_link_down(intel_dp);
1873 intel_dp_start_link_train(intel_dp);
1874 tries = 0;
1875 cr_tries++;
1876 continue;
1877 }
1878
1879 /* Compute new intel_dp->train_set as requested by target */
1880 intel_get_adjust_train(intel_dp, link_status);
1881 ++tries;
1882 }
1883
1884 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1885 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1886 else
1887 reg = DP | DP_LINK_TRAIN_OFF;
1888
1889 I915_WRITE(intel_dp->output_reg, reg);
1890 POSTING_READ(intel_dp->output_reg);
1891 intel_dp_aux_native_write_1(intel_dp,
1892 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1893 }
1894
1895 static void
1896 intel_dp_link_down(struct intel_dp *intel_dp)
1897 {
1898 struct drm_device *dev = intel_dp->base.base.dev;
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1900 uint32_t DP = intel_dp->DP;
1901
1902 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1903 return;
1904
1905 DRM_DEBUG_KMS("\n");
1906
1907 if (is_edp(intel_dp)) {
1908 DP &= ~DP_PLL_ENABLE;
1909 I915_WRITE(intel_dp->output_reg, DP);
1910 POSTING_READ(intel_dp->output_reg);
1911 udelay(100);
1912 }
1913
1914 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1915 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1916 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1917 } else {
1918 DP &= ~DP_LINK_TRAIN_MASK;
1919 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1920 }
1921 POSTING_READ(intel_dp->output_reg);
1922
1923 msleep(17);
1924
1925 if (is_edp(intel_dp)) {
1926 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1927 DP |= DP_LINK_TRAIN_OFF_CPT;
1928 else
1929 DP |= DP_LINK_TRAIN_OFF;
1930 }
1931
1932 if (HAS_PCH_IBX(dev) &&
1933 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1934 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1935
1936 /* Hardware workaround: leaving our transcoder select
1937 * set to transcoder B while it's off will prevent the
1938 * corresponding HDMI output on transcoder A.
1939 *
1940 * Combine this with another hardware workaround:
1941 * transcoder select bit can only be cleared while the
1942 * port is enabled.
1943 */
1944 DP &= ~DP_PIPEB_SELECT;
1945 I915_WRITE(intel_dp->output_reg, DP);
1946
1947 /* Changes to enable or select take place the vblank
1948 * after being written.
1949 */
1950 if (crtc == NULL) {
1951 /* We can arrive here never having been attached
1952 * to a CRTC, for instance, due to inheriting
1953 * random state from the BIOS.
1954 *
1955 * If the pipe is not running, play safe and
1956 * wait for the clocks to stabilise before
1957 * continuing.
1958 */
1959 POSTING_READ(intel_dp->output_reg);
1960 msleep(50);
1961 } else
1962 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1963 }
1964
1965 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1966 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1967 POSTING_READ(intel_dp->output_reg);
1968 msleep(intel_dp->panel_power_down_delay);
1969 }
1970
1971 static bool
1972 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1973 {
1974 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1975 sizeof(intel_dp->dpcd)) &&
1976 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1977 return true;
1978 }
1979
1980 return false;
1981 }
1982
1983 static void
1984 intel_dp_probe_oui(struct intel_dp *intel_dp)
1985 {
1986 u8 buf[3];
1987
1988 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1989 return;
1990
1991 ironlake_edp_panel_vdd_on(intel_dp);
1992
1993 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1994 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1995 buf[0], buf[1], buf[2]);
1996
1997 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1998 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1999 buf[0], buf[1], buf[2]);
2000
2001 ironlake_edp_panel_vdd_off(intel_dp, false);
2002 }
2003
2004 static bool
2005 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2006 {
2007 int ret;
2008
2009 ret = intel_dp_aux_native_read_retry(intel_dp,
2010 DP_DEVICE_SERVICE_IRQ_VECTOR,
2011 sink_irq_vector, 1);
2012 if (!ret)
2013 return false;
2014
2015 return true;
2016 }
2017
2018 static void
2019 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2020 {
2021 /* NAK by default */
2022 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2023 }
2024
2025 /*
2026 * According to DP spec
2027 * 5.1.2:
2028 * 1. Read DPCD
2029 * 2. Configure link according to Receiver Capabilities
2030 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2031 * 4. Check link status on receipt of hot-plug interrupt
2032 */
2033
2034 static void
2035 intel_dp_check_link_status(struct intel_dp *intel_dp)
2036 {
2037 u8 sink_irq_vector;
2038 u8 link_status[DP_LINK_STATUS_SIZE];
2039
2040 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2041 return;
2042
2043 if (!intel_dp->base.base.crtc)
2044 return;
2045
2046 /* Try to read receiver status if the link appears to be up */
2047 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2048 intel_dp_link_down(intel_dp);
2049 return;
2050 }
2051
2052 /* Now read the DPCD to see if it's actually running */
2053 if (!intel_dp_get_dpcd(intel_dp)) {
2054 intel_dp_link_down(intel_dp);
2055 return;
2056 }
2057
2058 /* Try to read the source of the interrupt */
2059 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2060 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2061 /* Clear interrupt source */
2062 intel_dp_aux_native_write_1(intel_dp,
2063 DP_DEVICE_SERVICE_IRQ_VECTOR,
2064 sink_irq_vector);
2065
2066 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2067 intel_dp_handle_test_request(intel_dp);
2068 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2069 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2070 }
2071
2072 if (!intel_channel_eq_ok(intel_dp, link_status)) {
2073 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2074 drm_get_encoder_name(&intel_dp->base.base));
2075 intel_dp_start_link_train(intel_dp);
2076 intel_dp_complete_link_train(intel_dp);
2077 }
2078 }
2079
2080 static enum drm_connector_status
2081 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2082 {
2083 if (intel_dp_get_dpcd(intel_dp))
2084 return connector_status_connected;
2085 return connector_status_disconnected;
2086 }
2087
2088 static enum drm_connector_status
2089 ironlake_dp_detect(struct intel_dp *intel_dp)
2090 {
2091 enum drm_connector_status status;
2092
2093 /* Can't disconnect eDP, but you can close the lid... */
2094 if (is_edp(intel_dp)) {
2095 status = intel_panel_detect(intel_dp->base.base.dev);
2096 if (status == connector_status_unknown)
2097 status = connector_status_connected;
2098 return status;
2099 }
2100
2101 return intel_dp_detect_dpcd(intel_dp);
2102 }
2103
2104 static enum drm_connector_status
2105 g4x_dp_detect(struct intel_dp *intel_dp)
2106 {
2107 struct drm_device *dev = intel_dp->base.base.dev;
2108 struct drm_i915_private *dev_priv = dev->dev_private;
2109 uint32_t bit;
2110
2111 switch (intel_dp->output_reg) {
2112 case DP_B:
2113 bit = DPB_HOTPLUG_LIVE_STATUS;
2114 break;
2115 case DP_C:
2116 bit = DPC_HOTPLUG_LIVE_STATUS;
2117 break;
2118 case DP_D:
2119 bit = DPD_HOTPLUG_LIVE_STATUS;
2120 break;
2121 default:
2122 return connector_status_unknown;
2123 }
2124
2125 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2126 return connector_status_disconnected;
2127
2128 return intel_dp_detect_dpcd(intel_dp);
2129 }
2130
2131 static struct edid *
2132 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2133 {
2134 struct intel_dp *intel_dp = intel_attached_dp(connector);
2135 struct edid *edid;
2136 int size;
2137
2138 if (is_edp(intel_dp)) {
2139 if (!intel_dp->edid)
2140 return NULL;
2141
2142 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2143 edid = kmalloc(size, GFP_KERNEL);
2144 if (!edid)
2145 return NULL;
2146
2147 memcpy(edid, intel_dp->edid, size);
2148 return edid;
2149 }
2150
2151 edid = drm_get_edid(connector, adapter);
2152 return edid;
2153 }
2154
2155 static int
2156 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2157 {
2158 struct intel_dp *intel_dp = intel_attached_dp(connector);
2159 int ret;
2160
2161 if (is_edp(intel_dp)) {
2162 drm_mode_connector_update_edid_property(connector,
2163 intel_dp->edid);
2164 ret = drm_add_edid_modes(connector, intel_dp->edid);
2165 drm_edid_to_eld(connector,
2166 intel_dp->edid);
2167 connector->display_info.raw_edid = NULL;
2168 return intel_dp->edid_mode_count;
2169 }
2170
2171 ret = intel_ddc_get_modes(connector, adapter);
2172 return ret;
2173 }
2174
2175
2176 /**
2177 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2178 *
2179 * \return true if DP port is connected.
2180 * \return false if DP port is disconnected.
2181 */
2182 static enum drm_connector_status
2183 intel_dp_detect(struct drm_connector *connector, bool force)
2184 {
2185 struct intel_dp *intel_dp = intel_attached_dp(connector);
2186 struct drm_device *dev = intel_dp->base.base.dev;
2187 enum drm_connector_status status;
2188 struct edid *edid = NULL;
2189
2190 intel_dp->has_audio = false;
2191
2192 if (HAS_PCH_SPLIT(dev))
2193 status = ironlake_dp_detect(intel_dp);
2194 else
2195 status = g4x_dp_detect(intel_dp);
2196
2197 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2198 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2199 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2200 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2201
2202 if (status != connector_status_connected)
2203 return status;
2204
2205 intel_dp_probe_oui(intel_dp);
2206
2207 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2208 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2209 } else {
2210 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2211 if (edid) {
2212 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2213 connector->display_info.raw_edid = NULL;
2214 kfree(edid);
2215 }
2216 }
2217
2218 return connector_status_connected;
2219 }
2220
2221 static int intel_dp_get_modes(struct drm_connector *connector)
2222 {
2223 struct intel_dp *intel_dp = intel_attached_dp(connector);
2224 struct drm_device *dev = intel_dp->base.base.dev;
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226 int ret;
2227
2228 /* We should parse the EDID data and find out if it has an audio sink
2229 */
2230
2231 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2232 if (ret) {
2233 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2234 struct drm_display_mode *newmode;
2235 list_for_each_entry(newmode, &connector->probed_modes,
2236 head) {
2237 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2238 intel_dp->panel_fixed_mode =
2239 drm_mode_duplicate(dev, newmode);
2240 break;
2241 }
2242 }
2243 }
2244 return ret;
2245 }
2246
2247 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2248 if (is_edp(intel_dp)) {
2249 /* initialize panel mode from VBT if available for eDP */
2250 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2251 intel_dp->panel_fixed_mode =
2252 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2253 if (intel_dp->panel_fixed_mode) {
2254 intel_dp->panel_fixed_mode->type |=
2255 DRM_MODE_TYPE_PREFERRED;
2256 }
2257 }
2258 if (intel_dp->panel_fixed_mode) {
2259 struct drm_display_mode *mode;
2260 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2261 drm_mode_probed_add(connector, mode);
2262 return 1;
2263 }
2264 }
2265 return 0;
2266 }
2267
2268 static bool
2269 intel_dp_detect_audio(struct drm_connector *connector)
2270 {
2271 struct intel_dp *intel_dp = intel_attached_dp(connector);
2272 struct edid *edid;
2273 bool has_audio = false;
2274
2275 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2276 if (edid) {
2277 has_audio = drm_detect_monitor_audio(edid);
2278
2279 connector->display_info.raw_edid = NULL;
2280 kfree(edid);
2281 }
2282
2283 return has_audio;
2284 }
2285
2286 static int
2287 intel_dp_set_property(struct drm_connector *connector,
2288 struct drm_property *property,
2289 uint64_t val)
2290 {
2291 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2292 struct intel_dp *intel_dp = intel_attached_dp(connector);
2293 int ret;
2294
2295 ret = drm_connector_property_set_value(connector, property, val);
2296 if (ret)
2297 return ret;
2298
2299 if (property == dev_priv->force_audio_property) {
2300 int i = val;
2301 bool has_audio;
2302
2303 if (i == intel_dp->force_audio)
2304 return 0;
2305
2306 intel_dp->force_audio = i;
2307
2308 if (i == HDMI_AUDIO_AUTO)
2309 has_audio = intel_dp_detect_audio(connector);
2310 else
2311 has_audio = (i == HDMI_AUDIO_ON);
2312
2313 if (has_audio == intel_dp->has_audio)
2314 return 0;
2315
2316 intel_dp->has_audio = has_audio;
2317 goto done;
2318 }
2319
2320 if (property == dev_priv->broadcast_rgb_property) {
2321 if (val == !!intel_dp->color_range)
2322 return 0;
2323
2324 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2325 goto done;
2326 }
2327
2328 return -EINVAL;
2329
2330 done:
2331 if (intel_dp->base.base.crtc) {
2332 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2333 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2334 crtc->x, crtc->y,
2335 crtc->fb);
2336 }
2337
2338 return 0;
2339 }
2340
2341 static void
2342 intel_dp_destroy(struct drm_connector *connector)
2343 {
2344 struct drm_device *dev = connector->dev;
2345
2346 if (intel_dpd_is_edp(dev))
2347 intel_panel_destroy_backlight(dev);
2348
2349 drm_sysfs_connector_remove(connector);
2350 drm_connector_cleanup(connector);
2351 kfree(connector);
2352 }
2353
2354 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2355 {
2356 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2357
2358 i2c_del_adapter(&intel_dp->adapter);
2359 drm_encoder_cleanup(encoder);
2360 if (is_edp(intel_dp)) {
2361 kfree(intel_dp->edid);
2362 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2363 ironlake_panel_vdd_off_sync(intel_dp);
2364 }
2365 kfree(intel_dp);
2366 }
2367
2368 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2369 .dpms = intel_dp_dpms,
2370 .mode_fixup = intel_dp_mode_fixup,
2371 .prepare = intel_dp_prepare,
2372 .mode_set = intel_dp_mode_set,
2373 .commit = intel_dp_commit,
2374 };
2375
2376 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2377 .dpms = drm_helper_connector_dpms,
2378 .detect = intel_dp_detect,
2379 .fill_modes = drm_helper_probe_single_connector_modes,
2380 .set_property = intel_dp_set_property,
2381 .destroy = intel_dp_destroy,
2382 };
2383
2384 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2385 .get_modes = intel_dp_get_modes,
2386 .mode_valid = intel_dp_mode_valid,
2387 .best_encoder = intel_best_encoder,
2388 };
2389
2390 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2391 .destroy = intel_dp_encoder_destroy,
2392 };
2393
2394 static void
2395 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2396 {
2397 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2398
2399 intel_dp_check_link_status(intel_dp);
2400 }
2401
2402 /* Return which DP Port should be selected for Transcoder DP control */
2403 int
2404 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2405 {
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_mode_config *mode_config = &dev->mode_config;
2408 struct drm_encoder *encoder;
2409
2410 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2411 struct intel_dp *intel_dp;
2412
2413 if (encoder->crtc != crtc)
2414 continue;
2415
2416 intel_dp = enc_to_intel_dp(encoder);
2417 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2418 intel_dp->base.type == INTEL_OUTPUT_EDP)
2419 return intel_dp->output_reg;
2420 }
2421
2422 return -1;
2423 }
2424
2425 /* check the VBT to see whether the eDP is on DP-D port */
2426 bool intel_dpd_is_edp(struct drm_device *dev)
2427 {
2428 struct drm_i915_private *dev_priv = dev->dev_private;
2429 struct child_device_config *p_child;
2430 int i;
2431
2432 if (!dev_priv->child_dev_num)
2433 return false;
2434
2435 for (i = 0; i < dev_priv->child_dev_num; i++) {
2436 p_child = dev_priv->child_dev + i;
2437
2438 if (p_child->dvo_port == PORT_IDPD &&
2439 p_child->device_type == DEVICE_TYPE_eDP)
2440 return true;
2441 }
2442 return false;
2443 }
2444
2445 static void
2446 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2447 {
2448 intel_attach_force_audio_property(connector);
2449 intel_attach_broadcast_rgb_property(connector);
2450 }
2451
2452 void
2453 intel_dp_init(struct drm_device *dev, int output_reg)
2454 {
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct drm_connector *connector;
2457 struct intel_dp *intel_dp;
2458 struct intel_encoder *intel_encoder;
2459 struct intel_connector *intel_connector;
2460 const char *name = NULL;
2461 int type;
2462
2463 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2464 if (!intel_dp)
2465 return;
2466
2467 intel_dp->output_reg = output_reg;
2468 intel_dp->dpms_mode = -1;
2469
2470 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2471 if (!intel_connector) {
2472 kfree(intel_dp);
2473 return;
2474 }
2475 intel_encoder = &intel_dp->base;
2476
2477 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2478 if (intel_dpd_is_edp(dev))
2479 intel_dp->is_pch_edp = true;
2480
2481 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2482 type = DRM_MODE_CONNECTOR_eDP;
2483 intel_encoder->type = INTEL_OUTPUT_EDP;
2484 } else {
2485 type = DRM_MODE_CONNECTOR_DisplayPort;
2486 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2487 }
2488
2489 connector = &intel_connector->base;
2490 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2491 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2492
2493 connector->polled = DRM_CONNECTOR_POLL_HPD;
2494
2495 if (output_reg == DP_B || output_reg == PCH_DP_B)
2496 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2497 else if (output_reg == DP_C || output_reg == PCH_DP_C)
2498 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2499 else if (output_reg == DP_D || output_reg == PCH_DP_D)
2500 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2501
2502 if (is_edp(intel_dp)) {
2503 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2504 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2505 ironlake_panel_vdd_work);
2506 }
2507
2508 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2509
2510 connector->interlace_allowed = true;
2511 connector->doublescan_allowed = 0;
2512
2513 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2514 DRM_MODE_ENCODER_TMDS);
2515 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2516
2517 intel_connector_attach_encoder(intel_connector, intel_encoder);
2518 drm_sysfs_connector_add(connector);
2519
2520 /* Set up the DDC bus. */
2521 switch (output_reg) {
2522 case DP_A:
2523 name = "DPDDC-A";
2524 break;
2525 case DP_B:
2526 case PCH_DP_B:
2527 dev_priv->hotplug_supported_mask |=
2528 DPB_HOTPLUG_INT_STATUS;
2529 name = "DPDDC-B";
2530 break;
2531 case DP_C:
2532 case PCH_DP_C:
2533 dev_priv->hotplug_supported_mask |=
2534 DPC_HOTPLUG_INT_STATUS;
2535 name = "DPDDC-C";
2536 break;
2537 case DP_D:
2538 case PCH_DP_D:
2539 dev_priv->hotplug_supported_mask |=
2540 DPD_HOTPLUG_INT_STATUS;
2541 name = "DPDDC-D";
2542 break;
2543 }
2544
2545 intel_dp_i2c_init(intel_dp, intel_connector, name);
2546
2547 /* Cache some DPCD data in the eDP case */
2548 if (is_edp(intel_dp)) {
2549 bool ret;
2550 struct edp_power_seq cur, vbt;
2551 u32 pp_on, pp_off, pp_div;
2552 struct edid *edid;
2553
2554 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2555 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2556 pp_div = I915_READ(PCH_PP_DIVISOR);
2557
2558 if (!pp_on || !pp_off || !pp_div) {
2559 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2560 intel_dp_encoder_destroy(&intel_dp->base.base);
2561 intel_dp_destroy(&intel_connector->base);
2562 return;
2563 }
2564
2565 /* Pull timing values out of registers */
2566 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2567 PANEL_POWER_UP_DELAY_SHIFT;
2568
2569 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2570 PANEL_LIGHT_ON_DELAY_SHIFT;
2571
2572 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2573 PANEL_LIGHT_OFF_DELAY_SHIFT;
2574
2575 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2576 PANEL_POWER_DOWN_DELAY_SHIFT;
2577
2578 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2579 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2580
2581 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2582 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2583
2584 vbt = dev_priv->edp.pps;
2585
2586 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2587 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2588
2589 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2590
2591 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2592 intel_dp->backlight_on_delay = get_delay(t8);
2593 intel_dp->backlight_off_delay = get_delay(t9);
2594 intel_dp->panel_power_down_delay = get_delay(t10);
2595 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2596
2597 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2598 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2599 intel_dp->panel_power_cycle_delay);
2600
2601 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2602 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2603
2604 ironlake_edp_panel_vdd_on(intel_dp);
2605 ret = intel_dp_get_dpcd(intel_dp);
2606 ironlake_edp_panel_vdd_off(intel_dp, false);
2607
2608 if (ret) {
2609 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2610 dev_priv->no_aux_handshake =
2611 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2612 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2613 } else {
2614 /* if this fails, presume the device is a ghost */
2615 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2616 intel_dp_encoder_destroy(&intel_dp->base.base);
2617 intel_dp_destroy(&intel_connector->base);
2618 return;
2619 }
2620
2621 ironlake_edp_panel_vdd_on(intel_dp);
2622 edid = drm_get_edid(connector, &intel_dp->adapter);
2623 if (edid) {
2624 drm_mode_connector_update_edid_property(connector,
2625 edid);
2626 intel_dp->edid_mode_count =
2627 drm_add_edid_modes(connector, edid);
2628 drm_edid_to_eld(connector, edid);
2629 intel_dp->edid = edid;
2630 }
2631 ironlake_edp_panel_vdd_off(intel_dp, false);
2632 }
2633
2634 intel_encoder->hot_plug = intel_dp_hot_plug;
2635
2636 if (is_edp(intel_dp)) {
2637 dev_priv->int_edp_connector = connector;
2638 intel_panel_setup_backlight(dev);
2639 }
2640
2641 intel_dp_add_properties(intel_dp, connector);
2642
2643 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2644 * 0xd. Failure to do so will result in spurious interrupts being
2645 * generated on the port when a cable is not attached.
2646 */
2647 if (IS_G4X(dev) && !IS_GM45(dev)) {
2648 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2649 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2650 }
2651 }
Linux 2.6 libata-dev (mirror)