include/media/omap3isp.h

   1 /*
   2  * omap3isp.h
   3  *
   4  * TI OMAP3 ISP - Platform data
   5  *
   6  * Copyright (C) 2011 Nokia Corporation
   7  *
   8  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   9  *           Sakari Ailus <sakari.ailus@iki.fi>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23  * 02110-1301 USA
  24  */
  25
  26 #ifndef __MEDIA_OMAP3ISP_H__
  27 #define __MEDIA_OMAP3ISP_H__
  28
  29 struct i2c_board_info;
  30 struct isp_device;
  31
  32 #define ISP_XCLK_NONE                   0
  33 #define ISP_XCLK_A                      1
  34 #define ISP_XCLK_B                      2
  35
  36 enum isp_interface_type {
  37         ISP_INTERFACE_PARALLEL,
  38         ISP_INTERFACE_CSI2A_PHY2,
  39         ISP_INTERFACE_CCP2B_PHY1,
  40         ISP_INTERFACE_CCP2B_PHY2,
  41         ISP_INTERFACE_CSI2C_PHY1,
  42 };
  43
  44 enum {
  45         ISP_BRIDGE_DISABLE = 0,
  46         ISP_BRIDGE_LITTLE_ENDIAN = 2,
  47         ISP_BRIDGE_BIG_ENDIAN = 3,
  48 };
  49
  50 enum {
  51         ISP_LANE_SHIFT_0 = 0,
  52         ISP_LANE_SHIFT_2 = 1,
  53         ISP_LANE_SHIFT_4 = 2,
  54         ISP_LANE_SHIFT_6 = 3,
  55 };
  56
  57 /**
  58  * struct isp_parallel_platform_data - Parallel interface platform data
  59  * @data_lane_shift: Data lane shifter
  60  *              ISP_LANE_SHIFT_0 - CAMEXT[13:0] -> CAM[13:0]
  61  *              ISP_LANE_SHIFT_2 - CAMEXT[13:2] -> CAM[11:0]
  62  *              ISP_LANE_SHIFT_4 - CAMEXT[13:4] -> CAM[9:0]
  63  *              ISP_LANE_SHIFT_6 - CAMEXT[13:6] -> CAM[7:0]
  64  * @clk_pol: Pixel clock polarity
  65  *              0 - Sample on rising edge, 1 - Sample on falling edge
  66  * @hs_pol: Horizontal synchronization polarity
  67  *              0 - Active high, 1 - Active low
  68  * @vs_pol: Vertical synchronization polarity
  69  *              0 - Active high, 1 - Active low
  70  * @data_pol: Data polarity
  71  *              0 - Normal, 1 - One's complement
  72  * @bridge: CCDC Bridge input control
  73  *              ISP_BRIDGE_DISABLE - Disable
  74  *              ISP_BRIDGE_LITTLE_ENDIAN - Little endian
  75  *              ISP_BRIDGE_BIG_ENDIAN - Big endian
  76  */
  77 struct isp_parallel_platform_data {
  78         unsigned int data_lane_shift:2;
  79         unsigned int clk_pol:1;
  80         unsigned int hs_pol:1;
  81         unsigned int vs_pol:1;
  82         unsigned int data_pol:1;
  83         unsigned int bridge:2;
  84 };
  85
  86 enum {
  87         ISP_CCP2_PHY_DATA_CLOCK = 0,
  88         ISP_CCP2_PHY_DATA_STROBE = 1,
  89 };
  90
  91 enum {
  92         ISP_CCP2_MODE_MIPI = 0,
  93         ISP_CCP2_MODE_CCP2 = 1,
  94 };
  95
  96 /**
  97  * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
  98  * @pos: position of the lane
  99  * @pol: polarity of the lane
 100  */
 101 struct isp_csiphy_lane {
 102         u8 pos;
 103         u8 pol;
 104 };
 105
 106 #define ISP_CSIPHY1_NUM_DATA_LANES      1
 107 #define ISP_CSIPHY2_NUM_DATA_LANES      2
 108
 109 /**
 110  * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
 111  * @data: Configuration of one or two data lanes
 112  * @clk: Clock lane configuration
 113  */
 114 struct isp_csiphy_lanes_cfg {
 115         struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES];
 116         struct isp_csiphy_lane clk;
 117 };
 118
 119 /**
 120  * struct isp_ccp2_platform_data - CCP2 interface platform data
 121  * @strobe_clk_pol: Strobe/clock polarity
 122  *              0 - Non Inverted, 1 - Inverted
 123  * @crc: Enable the cyclic redundancy check
 124  * @ccp2_mode: Enable CCP2 compatibility mode
 125  *              ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode
 126  *              ISP_CCP2_MODE_CCP2 - CCP2 mode
 127  * @phy_layer: Physical layer selection
 128  *              ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer
 129  *              ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer
 130  * @vpclk_div: Video port output clock control
 131  */
 132 struct isp_ccp2_platform_data {
 133         unsigned int strobe_clk_pol:1;
 134         unsigned int crc:1;
 135         unsigned int ccp2_mode:1;
 136         unsigned int phy_layer:1;
 137         unsigned int vpclk_div:2;
 138         struct isp_csiphy_lanes_cfg lanecfg;
 139 };
 140
 141 /**
 142  * struct isp_csi2_platform_data - CSI2 interface platform data
 143  * @crc: Enable the cyclic redundancy check
 144  * @vpclk_div: Video port output clock control
 145  */
 146 struct isp_csi2_platform_data {
 147         unsigned crc:1;
 148         unsigned vpclk_div:2;
 149         struct isp_csiphy_lanes_cfg lanecfg;
 150 };
 151
 152 struct isp_subdev_i2c_board_info {
 153         struct i2c_board_info *board_info;
 154         int i2c_adapter_id;
 155 };
 156
 157 struct isp_v4l2_subdevs_group {
 158         struct isp_subdev_i2c_board_info *subdevs;
 159         enum isp_interface_type interface;
 160         union {
 161                 struct isp_parallel_platform_data parallel;
 162                 struct isp_ccp2_platform_data ccp2;
 163                 struct isp_csi2_platform_data csi2;
 164         } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
 165 };
 166
 167 struct isp_platform_data {
 168         struct isp_v4l2_subdevs_group *subdevs;
 169         void (*set_constraints)(struct isp_device *isp, bool enable);
 170 };
 171
 172 #endif  /* __MEDIA_OMAP3ISP_H__ */