?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
KVM: Emulate hlt on real mode for Intel
[linux-2.6/libata-dev.git] / drivers / kvm / x86_emulate.c
bloba4a84817b27481cdea6d42bd0a6679f484a0a3a0
1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privieged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf( _f , ## _a )
27 #else
28 #include "kvm.h"
29 #define DPRINTF(x...) do {} while (0)
30 #endif
31 #include "x86_emulate.h"
32 #include <linux/module.h>
33
34 /*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43 /* Operand sizes: 8-bit operands or specified/overridden size. */
44 #define ByteOp (1<<0) /* 8-bit operands. */
45 /* Destination operand type. */
46 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47 #define DstReg (2<<1) /* Register operand. */
48 #define DstMem (3<<1) /* Memory operand. */
49 #define DstMask (3<<1)
50 /* Source operand type. */
51 #define SrcNone (0<<3) /* No source operand. */
52 #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53 #define SrcReg (1<<3) /* Register operand. */
54 #define SrcMem (2<<3) /* Memory operand. */
55 #define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57 #define SrcImm (5<<3) /* Immediate operand. */
58 #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59 #define SrcMask (7<<3)
60 /* Generic ModRM decode. */
61 #define ModRM (1<<6)
62 /* Destination is only written; never read. */
63 #define Mov (1<<7)
64 #define BitOp (1<<8)
65
66 static u8 opcode_table[256] = {
67 /* 0x00 - 0x07 */
68 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
69 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
70 0, 0, 0, 0,
71 /* 0x08 - 0x0F */
72 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
73 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
74 0, 0, 0, 0,
75 /* 0x10 - 0x17 */
76 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
77 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
78 0, 0, 0, 0,
79 /* 0x18 - 0x1F */
80 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
81 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
82 0, 0, 0, 0,
83 /* 0x20 - 0x27 */
84 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
85 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
86 0, 0, 0, 0,
87 /* 0x28 - 0x2F */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 0, 0, 0, 0,
91 /* 0x30 - 0x37 */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x38 - 0x3F */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 0, 0, 0, 0,
99 /* 0x40 - 0x4F */
100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
101 /* 0x50 - 0x5F */
102 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
103 /* 0x60 - 0x6F */
104 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
105 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
106 /* 0x70 - 0x7F */
107 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
108 /* 0x80 - 0x87 */
109 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
110 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
111 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
112 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
113 /* 0x88 - 0x8F */
114 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
115 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
116 0, 0, 0, DstMem | SrcNone | ModRM | Mov,
117 /* 0x90 - 0x9F */
118 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
119 /* 0xA0 - 0xA7 */
120 ByteOp | DstReg | SrcMem | Mov, DstReg | SrcMem | Mov,
121 ByteOp | DstMem | SrcReg | Mov, DstMem | SrcReg | Mov,
122 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
123 ByteOp | ImplicitOps, ImplicitOps,
124 /* 0xA8 - 0xAF */
125 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
126 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
127 ByteOp | ImplicitOps, ImplicitOps,
128 /* 0xB0 - 0xBF */
129 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
130 /* 0xC0 - 0xC7 */
131 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, 0, 0,
132 0, 0, ByteOp | DstMem | SrcImm | ModRM | Mov,
133 DstMem | SrcImm | ModRM | Mov,
134 /* 0xC8 - 0xCF */
135 0, 0, 0, 0, 0, 0, 0, 0,
136 /* 0xD0 - 0xD7 */
137 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
138 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
139 0, 0, 0, 0,
140 /* 0xD8 - 0xDF */
141 0, 0, 0, 0, 0, 0, 0, 0,
142 /* 0xE0 - 0xEF */
143 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
144 /* 0xF0 - 0xF7 */
145 0, 0, 0, 0,
146 ImplicitOps, 0,
147 ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
148 /* 0xF8 - 0xFF */
149 0, 0, 0, 0,
150 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
151 };
152
153 static u16 twobyte_table[256] = {
154 /* 0x00 - 0x0F */
155 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
156 0, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
157 /* 0x10 - 0x1F */
158 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
159 /* 0x20 - 0x2F */
160 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
161 0, 0, 0, 0, 0, 0, 0, 0,
162 /* 0x30 - 0x3F */
163 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
164 /* 0x40 - 0x47 */
165 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
166 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
167 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
168 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
169 /* 0x48 - 0x4F */
170 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
171 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
172 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
173 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
174 /* 0x50 - 0x5F */
175 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
176 /* 0x60 - 0x6F */
177 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
178 /* 0x70 - 0x7F */
179 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
180 /* 0x80 - 0x8F */
181 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
182 /* 0x90 - 0x9F */
183 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
184 /* 0xA0 - 0xA7 */
185 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
186 /* 0xA8 - 0xAF */
187 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
188 /* 0xB0 - 0xB7 */
189 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
190 DstMem | SrcReg | ModRM | BitOp,
191 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
192 DstReg | SrcMem16 | ModRM | Mov,
193 /* 0xB8 - 0xBF */
194 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
195 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
196 DstReg | SrcMem16 | ModRM | Mov,
197 /* 0xC0 - 0xCF */
198 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, 0,
199 /* 0xD0 - 0xDF */
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
201 /* 0xE0 - 0xEF */
202 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
203 /* 0xF0 - 0xFF */
204 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
205 };
206
207 /*
208 * Tell the emulator that of the Group 7 instructions (sgdt, lidt, etc.) we
209 * are interested only in invlpg and not in any of the rest.
210 *
211 * invlpg is a special instruction in that the data it references may not
212 * be mapped.
213 */
214 void kvm_emulator_want_group7_invlpg(void)
215 {
216 twobyte_table[1] &= ~SrcMem;
217 }
218 EXPORT_SYMBOL_GPL(kvm_emulator_want_group7_invlpg);
219
220 /* Type, address-of, and value of an instruction's operand. */
221 struct operand {
222 enum { OP_REG, OP_MEM, OP_IMM } type;
223 unsigned int bytes;
224 unsigned long val, orig_val, *ptr;
225 };
226
227 /* EFLAGS bit definitions. */
228 #define EFLG_OF (1<<11)
229 #define EFLG_DF (1<<10)
230 #define EFLG_SF (1<<7)
231 #define EFLG_ZF (1<<6)
232 #define EFLG_AF (1<<4)
233 #define EFLG_PF (1<<2)
234 #define EFLG_CF (1<<0)
235
236 /*
237 * Instruction emulation:
238 * Most instructions are emulated directly via a fragment of inline assembly
239 * code. This allows us to save/restore EFLAGS and thus very easily pick up
240 * any modified flags.
241 */
242
243 #if defined(CONFIG_X86_64)
244 #define _LO32 "k" /* force 32-bit operand */
245 #define _STK "%%rsp" /* stack pointer */
246 #elif defined(__i386__)
247 #define _LO32 "" /* force 32-bit operand */
248 #define _STK "%%esp" /* stack pointer */
249 #endif
250
251 /*
252 * These EFLAGS bits are restored from saved value during emulation, and
253 * any changes are written back to the saved value after emulation.
254 */
255 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
256
257 /* Before executing instruction: restore necessary bits in EFLAGS. */
258 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
259 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \
260 "push %"_sav"; " \
261 "movl %"_msk",%"_LO32 _tmp"; " \
262 "andl %"_LO32 _tmp",("_STK"); " \
263 "pushf; " \
264 "notl %"_LO32 _tmp"; " \
265 "andl %"_LO32 _tmp",("_STK"); " \
266 "pop %"_tmp"; " \
267 "orl %"_LO32 _tmp",("_STK"); " \
268 "popf; " \
269 /* _sav &= ~msk; */ \
270 "movl %"_msk",%"_LO32 _tmp"; " \
271 "notl %"_LO32 _tmp"; " \
272 "andl %"_LO32 _tmp",%"_sav"; "
273
274 /* After executing instruction: write-back necessary bits in EFLAGS. */
275 #define _POST_EFLAGS(_sav, _msk, _tmp) \
276 /* _sav |= EFLAGS & _msk; */ \
277 "pushf; " \
278 "pop %"_tmp"; " \
279 "andl %"_msk",%"_LO32 _tmp"; " \
280 "orl %"_LO32 _tmp",%"_sav"; "
281
282 /* Raw emulation: instruction has two explicit operands. */
283 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
284 do { \
285 unsigned long _tmp; \
286 \
287 switch ((_dst).bytes) { \
288 case 2: \
289 __asm__ __volatile__ ( \
290 _PRE_EFLAGS("0","4","2") \
291 _op"w %"_wx"3,%1; " \
292 _POST_EFLAGS("0","4","2") \
293 : "=m" (_eflags), "=m" ((_dst).val), \
294 "=&r" (_tmp) \
295 : _wy ((_src).val), "i" (EFLAGS_MASK) ); \
296 break; \
297 case 4: \
298 __asm__ __volatile__ ( \
299 _PRE_EFLAGS("0","4","2") \
300 _op"l %"_lx"3,%1; " \
301 _POST_EFLAGS("0","4","2") \
302 : "=m" (_eflags), "=m" ((_dst).val), \
303 "=&r" (_tmp) \
304 : _ly ((_src).val), "i" (EFLAGS_MASK) ); \
305 break; \
306 case 8: \
307 __emulate_2op_8byte(_op, _src, _dst, \
308 _eflags, _qx, _qy); \
309 break; \
310 } \
311 } while (0)
312
313 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
314 do { \
315 unsigned long _tmp; \
316 switch ( (_dst).bytes ) \
317 { \
318 case 1: \
319 __asm__ __volatile__ ( \
320 _PRE_EFLAGS("0","4","2") \
321 _op"b %"_bx"3,%1; " \
322 _POST_EFLAGS("0","4","2") \
323 : "=m" (_eflags), "=m" ((_dst).val), \
324 "=&r" (_tmp) \
325 : _by ((_src).val), "i" (EFLAGS_MASK) ); \
326 break; \
327 default: \
328 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
329 _wx, _wy, _lx, _ly, _qx, _qy); \
330 break; \
331 } \
332 } while (0)
333
334 /* Source operand is byte-sized and may be restricted to just %cl. */
335 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
336 __emulate_2op(_op, _src, _dst, _eflags, \
337 "b", "c", "b", "c", "b", "c", "b", "c")
338
339 /* Source operand is byte, word, long or quad sized. */
340 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
341 __emulate_2op(_op, _src, _dst, _eflags, \
342 "b", "q", "w", "r", _LO32, "r", "", "r")
343
344 /* Source operand is word, long or quad sized. */
345 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
346 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
347 "w", "r", _LO32, "r", "", "r")
348
349 /* Instruction has only one explicit operand (no source operand). */
350 #define emulate_1op(_op, _dst, _eflags) \
351 do { \
352 unsigned long _tmp; \
353 \
354 switch ( (_dst).bytes ) \
355 { \
356 case 1: \
357 __asm__ __volatile__ ( \
358 _PRE_EFLAGS("0","3","2") \
359 _op"b %1; " \
360 _POST_EFLAGS("0","3","2") \
361 : "=m" (_eflags), "=m" ((_dst).val), \
362 "=&r" (_tmp) \
363 : "i" (EFLAGS_MASK) ); \
364 break; \
365 case 2: \
366 __asm__ __volatile__ ( \
367 _PRE_EFLAGS("0","3","2") \
368 _op"w %1; " \
369 _POST_EFLAGS("0","3","2") \
370 : "=m" (_eflags), "=m" ((_dst).val), \
371 "=&r" (_tmp) \
372 : "i" (EFLAGS_MASK) ); \
373 break; \
374 case 4: \
375 __asm__ __volatile__ ( \
376 _PRE_EFLAGS("0","3","2") \
377 _op"l %1; " \
378 _POST_EFLAGS("0","3","2") \
379 : "=m" (_eflags), "=m" ((_dst).val), \
380 "=&r" (_tmp) \
381 : "i" (EFLAGS_MASK) ); \
382 break; \
383 case 8: \
384 __emulate_1op_8byte(_op, _dst, _eflags); \
385 break; \
386 } \
387 } while (0)
388
389 /* Emulate an instruction with quadword operands (x86/64 only). */
390 #if defined(CONFIG_X86_64)
391 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
392 do { \
393 __asm__ __volatile__ ( \
394 _PRE_EFLAGS("0","4","2") \
395 _op"q %"_qx"3,%1; " \
396 _POST_EFLAGS("0","4","2") \
397 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
398 : _qy ((_src).val), "i" (EFLAGS_MASK) ); \
399 } while (0)
400
401 #define __emulate_1op_8byte(_op, _dst, _eflags) \
402 do { \
403 __asm__ __volatile__ ( \
404 _PRE_EFLAGS("0","3","2") \
405 _op"q %1; " \
406 _POST_EFLAGS("0","3","2") \
407 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
408 : "i" (EFLAGS_MASK) ); \
409 } while (0)
410
411 #elif defined(__i386__)
412 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
413 #define __emulate_1op_8byte(_op, _dst, _eflags)
414 #endif /* __i386__ */
415
416 /* Fetch next part of the instruction being emulated. */
417 #define insn_fetch(_type, _size, _eip) \
418 ({ unsigned long _x; \
419 rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x, \
420 (_size), ctxt); \
421 if ( rc != 0 ) \
422 goto done; \
423 (_eip) += (_size); \
424 (_type)_x; \
425 })
426
427 /* Access/update address held in a register, based on addressing mode. */
428 #define register_address(base, reg) \
429 ((base) + ((ad_bytes == sizeof(unsigned long)) ? (reg) : \
430 ((reg) & ((1UL << (ad_bytes << 3)) - 1))))
431
432 #define register_address_increment(reg, inc) \
433 do { \
434 /* signed type ensures sign extension to long */ \
435 int _inc = (inc); \
436 if ( ad_bytes == sizeof(unsigned long) ) \
437 (reg) += _inc; \
438 else \
439 (reg) = ((reg) & ~((1UL << (ad_bytes << 3)) - 1)) | \
440 (((reg) + _inc) & ((1UL << (ad_bytes << 3)) - 1)); \
441 } while (0)
442
443 void *decode_register(u8 modrm_reg, unsigned long *regs,
444 int highbyte_regs)
445 {
446 void *p;
447
448 p = &regs[modrm_reg];
449 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
450 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
451 return p;
452 }
453
454 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
455 struct x86_emulate_ops *ops,
456 void *ptr,
457 u16 *size, unsigned long *address, int op_bytes)
458 {
459 int rc;
460
461 if (op_bytes == 2)
462 op_bytes = 3;
463 *address = 0;
464 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, ctxt);
465 if (rc)
466 return rc;
467 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, ctxt);
468 return rc;
469 }
470
471 int
472 x86_emulate_memop(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
473 {
474 unsigned d;
475 u8 b, sib, twobyte = 0, rex_prefix = 0;
476 u8 modrm, modrm_mod = 0, modrm_reg = 0, modrm_rm = 0;
477 unsigned long *override_base = NULL;
478 unsigned int op_bytes, ad_bytes, lock_prefix = 0, rep_prefix = 0, i;
479 int rc = 0;
480 struct operand src, dst;
481 unsigned long cr2 = ctxt->cr2;
482 int mode = ctxt->mode;
483 unsigned long modrm_ea;
484 int use_modrm_ea, index_reg = 0, base_reg = 0, scale, rip_relative = 0;
485
486 /* Shadow copy of register state. Committed on successful emulation. */
487 unsigned long _regs[NR_VCPU_REGS];
488 unsigned long _eip = ctxt->vcpu->rip, _eflags = ctxt->eflags;
489 unsigned long modrm_val = 0;
490
491 memcpy(_regs, ctxt->vcpu->regs, sizeof _regs);
492
493 switch (mode) {
494 case X86EMUL_MODE_REAL:
495 case X86EMUL_MODE_PROT16:
496 op_bytes = ad_bytes = 2;
497 break;
498 case X86EMUL_MODE_PROT32:
499 op_bytes = ad_bytes = 4;
500 break;
501 #ifdef CONFIG_X86_64
502 case X86EMUL_MODE_PROT64:
503 op_bytes = 4;
504 ad_bytes = 8;
505 break;
506 #endif
507 default:
508 return -1;
509 }
510
511 /* Legacy prefixes. */
512 for (i = 0; i < 8; i++) {
513 switch (b = insn_fetch(u8, 1, _eip)) {
514 case 0x66: /* operand-size override */
515 op_bytes ^= 6; /* switch between 2/4 bytes */
516 break;
517 case 0x67: /* address-size override */
518 if (mode == X86EMUL_MODE_PROT64)
519 ad_bytes ^= 12; /* switch between 4/8 bytes */
520 else
521 ad_bytes ^= 6; /* switch between 2/4 bytes */
522 break;
523 case 0x2e: /* CS override */
524 override_base = &ctxt->cs_base;
525 break;
526 case 0x3e: /* DS override */
527 override_base = &ctxt->ds_base;
528 break;
529 case 0x26: /* ES override */
530 override_base = &ctxt->es_base;
531 break;
532 case 0x64: /* FS override */
533 override_base = &ctxt->fs_base;
534 break;
535 case 0x65: /* GS override */
536 override_base = &ctxt->gs_base;
537 break;
538 case 0x36: /* SS override */
539 override_base = &ctxt->ss_base;
540 break;
541 case 0xf0: /* LOCK */
542 lock_prefix = 1;
543 break;
544 case 0xf3: /* REP/REPE/REPZ */
545 rep_prefix = 1;
546 break;
547 case 0xf2: /* REPNE/REPNZ */
548 break;
549 default:
550 goto done_prefixes;
551 }
552 }
553
554 done_prefixes:
555
556 /* REX prefix. */
557 if ((mode == X86EMUL_MODE_PROT64) && ((b & 0xf0) == 0x40)) {
558 rex_prefix = b;
559 if (b & 8)
560 op_bytes = 8; /* REX.W */
561 modrm_reg = (b & 4) << 1; /* REX.R */
562 index_reg = (b & 2) << 2; /* REX.X */
563 modrm_rm = base_reg = (b & 1) << 3; /* REG.B */
564 b = insn_fetch(u8, 1, _eip);
565 }
566
567 /* Opcode byte(s). */
568 d = opcode_table[b];
569 if (d == 0) {
570 /* Two-byte opcode? */
571 if (b == 0x0f) {
572 twobyte = 1;
573 b = insn_fetch(u8, 1, _eip);
574 d = twobyte_table[b];
575 }
576
577 /* Unrecognised? */
578 if (d == 0)
579 goto cannot_emulate;
580 }
581
582 /* ModRM and SIB bytes. */
583 if (d & ModRM) {
584 modrm = insn_fetch(u8, 1, _eip);
585 modrm_mod |= (modrm & 0xc0) >> 6;
586 modrm_reg |= (modrm & 0x38) >> 3;
587 modrm_rm |= (modrm & 0x07);
588 modrm_ea = 0;
589 use_modrm_ea = 1;
590
591 if (modrm_mod == 3) {
592 modrm_val = *(unsigned long *)
593 decode_register(modrm_rm, _regs, d & ByteOp);
594 goto modrm_done;
595 }
596
597 if (ad_bytes == 2) {
598 unsigned bx = _regs[VCPU_REGS_RBX];
599 unsigned bp = _regs[VCPU_REGS_RBP];
600 unsigned si = _regs[VCPU_REGS_RSI];
601 unsigned di = _regs[VCPU_REGS_RDI];
602
603 /* 16-bit ModR/M decode. */
604 switch (modrm_mod) {
605 case 0:
606 if (modrm_rm == 6)
607 modrm_ea += insn_fetch(u16, 2, _eip);
608 break;
609 case 1:
610 modrm_ea += insn_fetch(s8, 1, _eip);
611 break;
612 case 2:
613 modrm_ea += insn_fetch(u16, 2, _eip);
614 break;
615 }
616 switch (modrm_rm) {
617 case 0:
618 modrm_ea += bx + si;
619 break;
620 case 1:
621 modrm_ea += bx + di;
622 break;
623 case 2:
624 modrm_ea += bp + si;
625 break;
626 case 3:
627 modrm_ea += bp + di;
628 break;
629 case 4:
630 modrm_ea += si;
631 break;
632 case 5:
633 modrm_ea += di;
634 break;
635 case 6:
636 if (modrm_mod != 0)
637 modrm_ea += bp;
638 break;
639 case 7:
640 modrm_ea += bx;
641 break;
642 }
643 if (modrm_rm == 2 || modrm_rm == 3 ||
644 (modrm_rm == 6 && modrm_mod != 0))
645 if (!override_base)
646 override_base = &ctxt->ss_base;
647 modrm_ea = (u16)modrm_ea;
648 } else {
649 /* 32/64-bit ModR/M decode. */
650 switch (modrm_rm) {
651 case 4:
652 case 12:
653 sib = insn_fetch(u8, 1, _eip);
654 index_reg |= (sib >> 3) & 7;
655 base_reg |= sib & 7;
656 scale = sib >> 6;
657
658 switch (base_reg) {
659 case 5:
660 if (modrm_mod != 0)
661 modrm_ea += _regs[base_reg];
662 else
663 modrm_ea += insn_fetch(s32, 4, _eip);
664 break;
665 default:
666 modrm_ea += _regs[base_reg];
667 }
668 switch (index_reg) {
669 case 4:
670 break;
671 default:
672 modrm_ea += _regs[index_reg] << scale;
673
674 }
675 break;
676 case 5:
677 if (modrm_mod != 0)
678 modrm_ea += _regs[modrm_rm];
679 else if (mode == X86EMUL_MODE_PROT64)
680 rip_relative = 1;
681 break;
682 default:
683 modrm_ea += _regs[modrm_rm];
684 break;
685 }
686 switch (modrm_mod) {
687 case 0:
688 if (modrm_rm == 5)
689 modrm_ea += insn_fetch(s32, 4, _eip);
690 break;
691 case 1:
692 modrm_ea += insn_fetch(s8, 1, _eip);
693 break;
694 case 2:
695 modrm_ea += insn_fetch(s32, 4, _eip);
696 break;
697 }
698 }
699 if (!override_base)
700 override_base = &ctxt->ds_base;
701 if (mode == X86EMUL_MODE_PROT64 &&
702 override_base != &ctxt->fs_base &&
703 override_base != &ctxt->gs_base)
704 override_base = NULL;
705
706 if (override_base)
707 modrm_ea += *override_base;
708
709 if (rip_relative) {
710 modrm_ea += _eip;
711 switch (d & SrcMask) {
712 case SrcImmByte:
713 modrm_ea += 1;
714 break;
715 case SrcImm:
716 if (d & ByteOp)
717 modrm_ea += 1;
718 else
719 if (op_bytes == 8)
720 modrm_ea += 4;
721 else
722 modrm_ea += op_bytes;
723 }
724 }
725 if (ad_bytes != 8)
726 modrm_ea = (u32)modrm_ea;
727 cr2 = modrm_ea;
728 modrm_done:
729 ;
730 }
731
732 /*
733 * Decode and fetch the source operand: register, memory
734 * or immediate.
735 */
736 switch (d & SrcMask) {
737 case SrcNone:
738 break;
739 case SrcReg:
740 src.type = OP_REG;
741 if (d & ByteOp) {
742 src.ptr = decode_register(modrm_reg, _regs,
743 (rex_prefix == 0));
744 src.val = src.orig_val = *(u8 *) src.ptr;
745 src.bytes = 1;
746 } else {
747 src.ptr = decode_register(modrm_reg, _regs, 0);
748 switch ((src.bytes = op_bytes)) {
749 case 2:
750 src.val = src.orig_val = *(u16 *) src.ptr;
751 break;
752 case 4:
753 src.val = src.orig_val = *(u32 *) src.ptr;
754 break;
755 case 8:
756 src.val = src.orig_val = *(u64 *) src.ptr;
757 break;
758 }
759 }
760 break;
761 case SrcMem16:
762 src.bytes = 2;
763 goto srcmem_common;
764 case SrcMem32:
765 src.bytes = 4;
766 goto srcmem_common;
767 case SrcMem:
768 src.bytes = (d & ByteOp) ? 1 : op_bytes;
769 srcmem_common:
770 src.type = OP_MEM;
771 src.ptr = (unsigned long *)cr2;
772 if ((rc = ops->read_emulated((unsigned long)src.ptr,
773 &src.val, src.bytes, ctxt)) != 0)
774 goto done;
775 src.orig_val = src.val;
776 break;
777 case SrcImm:
778 src.type = OP_IMM;
779 src.ptr = (unsigned long *)_eip;
780 src.bytes = (d & ByteOp) ? 1 : op_bytes;
781 if (src.bytes == 8)
782 src.bytes = 4;
783 /* NB. Immediates are sign-extended as necessary. */
784 switch (src.bytes) {
785 case 1:
786 src.val = insn_fetch(s8, 1, _eip);
787 break;
788 case 2:
789 src.val = insn_fetch(s16, 2, _eip);
790 break;
791 case 4:
792 src.val = insn_fetch(s32, 4, _eip);
793 break;
794 }
795 break;
796 case SrcImmByte:
797 src.type = OP_IMM;
798 src.ptr = (unsigned long *)_eip;
799 src.bytes = 1;
800 src.val = insn_fetch(s8, 1, _eip);
801 break;
802 }
803
804 /* Decode and fetch the destination operand: register or memory. */
805 switch (d & DstMask) {
806 case ImplicitOps:
807 /* Special instructions do their own operand decoding. */
808 goto special_insn;
809 case DstReg:
810 dst.type = OP_REG;
811 if ((d & ByteOp)
812 && !(twobyte_table && (b == 0xb6 || b == 0xb7))) {
813 dst.ptr = decode_register(modrm_reg, _regs,
814 (rex_prefix == 0));
815 dst.val = *(u8 *) dst.ptr;
816 dst.bytes = 1;
817 } else {
818 dst.ptr = decode_register(modrm_reg, _regs, 0);
819 switch ((dst.bytes = op_bytes)) {
820 case 2:
821 dst.val = *(u16 *)dst.ptr;
822 break;
823 case 4:
824 dst.val = *(u32 *)dst.ptr;
825 break;
826 case 8:
827 dst.val = *(u64 *)dst.ptr;
828 break;
829 }
830 }
831 break;
832 case DstMem:
833 dst.type = OP_MEM;
834 dst.ptr = (unsigned long *)cr2;
835 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
836 if (d & BitOp) {
837 unsigned long mask = ~(dst.bytes * 8 - 1);
838
839 dst.ptr = (void *)dst.ptr + (src.val & mask) / 8;
840 }
841 if (!(d & Mov) && /* optimisation - avoid slow emulated read */
842 ((rc = ops->read_emulated((unsigned long)dst.ptr,
843 &dst.val, dst.bytes, ctxt)) != 0))
844 goto done;
845 break;
846 }
847 dst.orig_val = dst.val;
848
849 if (twobyte)
850 goto twobyte_insn;
851
852 switch (b) {
853 case 0x00 ... 0x05:
854 add: /* add */
855 emulate_2op_SrcV("add", src, dst, _eflags);
856 break;
857 case 0x08 ... 0x0d:
858 or: /* or */
859 emulate_2op_SrcV("or", src, dst, _eflags);
860 break;
861 case 0x10 ... 0x15:
862 adc: /* adc */
863 emulate_2op_SrcV("adc", src, dst, _eflags);
864 break;
865 case 0x18 ... 0x1d:
866 sbb: /* sbb */
867 emulate_2op_SrcV("sbb", src, dst, _eflags);
868 break;
869 case 0x20 ... 0x25:
870 and: /* and */
871 emulate_2op_SrcV("and", src, dst, _eflags);
872 break;
873 case 0x28 ... 0x2d:
874 sub: /* sub */
875 emulate_2op_SrcV("sub", src, dst, _eflags);
876 break;
877 case 0x30 ... 0x35:
878 xor: /* xor */
879 emulate_2op_SrcV("xor", src, dst, _eflags);
880 break;
881 case 0x38 ... 0x3d:
882 cmp: /* cmp */
883 emulate_2op_SrcV("cmp", src, dst, _eflags);
884 break;
885 case 0x63: /* movsxd */
886 if (mode != X86EMUL_MODE_PROT64)
887 goto cannot_emulate;
888 dst.val = (s32) src.val;
889 break;
890 case 0x80 ... 0x83: /* Grp1 */
891 switch (modrm_reg) {
892 case 0:
893 goto add;
894 case 1:
895 goto or;
896 case 2:
897 goto adc;
898 case 3:
899 goto sbb;
900 case 4:
901 goto and;
902 case 5:
903 goto sub;
904 case 6:
905 goto xor;
906 case 7:
907 goto cmp;
908 }
909 break;
910 case 0x84 ... 0x85:
911 test: /* test */
912 emulate_2op_SrcV("test", src, dst, _eflags);
913 break;
914 case 0x86 ... 0x87: /* xchg */
915 /* Write back the register source. */
916 switch (dst.bytes) {
917 case 1:
918 *(u8 *) src.ptr = (u8) dst.val;
919 break;
920 case 2:
921 *(u16 *) src.ptr = (u16) dst.val;
922 break;
923 case 4:
924 *src.ptr = (u32) dst.val;
925 break; /* 64b reg: zero-extend */
926 case 8:
927 *src.ptr = dst.val;
928 break;
929 }
930 /*
931 * Write back the memory destination with implicit LOCK
932 * prefix.
933 */
934 dst.val = src.val;
935 lock_prefix = 1;
936 break;
937 case 0xa0 ... 0xa1: /* mov */
938 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
939 dst.val = src.val;
940 _eip += ad_bytes; /* skip src displacement */
941 break;
942 case 0xa2 ... 0xa3: /* mov */
943 dst.val = (unsigned long)_regs[VCPU_REGS_RAX];
944 _eip += ad_bytes; /* skip dst displacement */
945 break;
946 case 0x88 ... 0x8b: /* mov */
947 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
948 dst.val = src.val;
949 break;
950 case 0x8f: /* pop (sole member of Grp1a) */
951 /* 64-bit mode: POP always pops a 64-bit operand. */
952 if (mode == X86EMUL_MODE_PROT64)
953 dst.bytes = 8;
954 if ((rc = ops->read_std(register_address(ctxt->ss_base,
955 _regs[VCPU_REGS_RSP]),
956 &dst.val, dst.bytes, ctxt)) != 0)
957 goto done;
958 register_address_increment(_regs[VCPU_REGS_RSP], dst.bytes);
959 break;
960 case 0xc0 ... 0xc1:
961 grp2: /* Grp2 */
962 switch (modrm_reg) {
963 case 0: /* rol */
964 emulate_2op_SrcB("rol", src, dst, _eflags);
965 break;
966 case 1: /* ror */
967 emulate_2op_SrcB("ror", src, dst, _eflags);
968 break;
969 case 2: /* rcl */
970 emulate_2op_SrcB("rcl", src, dst, _eflags);
971 break;
972 case 3: /* rcr */
973 emulate_2op_SrcB("rcr", src, dst, _eflags);
974 break;
975 case 4: /* sal/shl */
976 case 6: /* sal/shl */
977 emulate_2op_SrcB("sal", src, dst, _eflags);
978 break;
979 case 5: /* shr */
980 emulate_2op_SrcB("shr", src, dst, _eflags);
981 break;
982 case 7: /* sar */
983 emulate_2op_SrcB("sar", src, dst, _eflags);
984 break;
985 }
986 break;
987 case 0xd0 ... 0xd1: /* Grp2 */
988 src.val = 1;
989 goto grp2;
990 case 0xd2 ... 0xd3: /* Grp2 */
991 src.val = _regs[VCPU_REGS_RCX];
992 goto grp2;
993 case 0xf6 ... 0xf7: /* Grp3 */
994 switch (modrm_reg) {
995 case 0 ... 1: /* test */
996 /*
997 * Special case in Grp3: test has an immediate
998 * source operand.
999 */
1000 src.type = OP_IMM;
1001 src.ptr = (unsigned long *)_eip;
1002 src.bytes = (d & ByteOp) ? 1 : op_bytes;
1003 if (src.bytes == 8)
1004 src.bytes = 4;
1005 switch (src.bytes) {
1006 case 1:
1007 src.val = insn_fetch(s8, 1, _eip);
1008 break;
1009 case 2:
1010 src.val = insn_fetch(s16, 2, _eip);
1011 break;
1012 case 4:
1013 src.val = insn_fetch(s32, 4, _eip);
1014 break;
1015 }
1016 goto test;
1017 case 2: /* not */
1018 dst.val = ~dst.val;
1019 break;
1020 case 3: /* neg */
1021 emulate_1op("neg", dst, _eflags);
1022 break;
1023 default:
1024 goto cannot_emulate;
1025 }
1026 break;
1027 case 0xfe ... 0xff: /* Grp4/Grp5 */
1028 switch (modrm_reg) {
1029 case 0: /* inc */
1030 emulate_1op("inc", dst, _eflags);
1031 break;
1032 case 1: /* dec */
1033 emulate_1op("dec", dst, _eflags);
1034 break;
1035 case 6: /* push */
1036 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1037 if (mode == X86EMUL_MODE_PROT64) {
1038 dst.bytes = 8;
1039 if ((rc = ops->read_std((unsigned long)dst.ptr,
1040 &dst.val, 8,
1041 ctxt)) != 0)
1042 goto done;
1043 }
1044 register_address_increment(_regs[VCPU_REGS_RSP],
1045 -dst.bytes);
1046 if ((rc = ops->write_std(
1047 register_address(ctxt->ss_base,
1048 _regs[VCPU_REGS_RSP]),
1049 &dst.val, dst.bytes, ctxt)) != 0)
1050 goto done;
1051 dst.val = dst.orig_val; /* skanky: disable writeback */
1052 break;
1053 default:
1054 goto cannot_emulate;
1055 }
1056 break;
1057 }
1058
1059 writeback:
1060 if ((d & Mov) || (dst.orig_val != dst.val)) {
1061 switch (dst.type) {
1062 case OP_REG:
1063 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1064 switch (dst.bytes) {
1065 case 1:
1066 *(u8 *)dst.ptr = (u8)dst.val;
1067 break;
1068 case 2:
1069 *(u16 *)dst.ptr = (u16)dst.val;
1070 break;
1071 case 4:
1072 *dst.ptr = (u32)dst.val;
1073 break; /* 64b: zero-ext */
1074 case 8:
1075 *dst.ptr = dst.val;
1076 break;
1077 }
1078 break;
1079 case OP_MEM:
1080 if (lock_prefix)
1081 rc = ops->cmpxchg_emulated((unsigned long)dst.
1082 ptr, &dst.orig_val,
1083 &dst.val, dst.bytes,
1084 ctxt);
1085 else
1086 rc = ops->write_emulated((unsigned long)dst.ptr,
1087 &dst.val, dst.bytes,
1088 ctxt);
1089 if (rc != 0)
1090 goto done;
1091 default:
1092 break;
1093 }
1094 }
1095
1096 /* Commit shadow register state. */
1097 memcpy(ctxt->vcpu->regs, _regs, sizeof _regs);
1098 ctxt->eflags = _eflags;
1099 ctxt->vcpu->rip = _eip;
1100
1101 done:
1102 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1103
1104 special_insn:
1105 if (twobyte)
1106 goto twobyte_special_insn;
1107 if (rep_prefix) {
1108 if (_regs[VCPU_REGS_RCX] == 0) {
1109 ctxt->vcpu->rip = _eip;
1110 goto done;
1111 }
1112 _regs[VCPU_REGS_RCX]--;
1113 _eip = ctxt->vcpu->rip;
1114 }
1115 switch (b) {
1116 case 0xa4 ... 0xa5: /* movs */
1117 dst.type = OP_MEM;
1118 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1119 dst.ptr = (unsigned long *)register_address(ctxt->es_base,
1120 _regs[VCPU_REGS_RDI]);
1121 if ((rc = ops->read_emulated(register_address(
1122 override_base ? *override_base : ctxt->ds_base,
1123 _regs[VCPU_REGS_RSI]), &dst.val, dst.bytes, ctxt)) != 0)
1124 goto done;
1125 register_address_increment(_regs[VCPU_REGS_RSI],
1126 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1127 register_address_increment(_regs[VCPU_REGS_RDI],
1128 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1129 break;
1130 case 0xa6 ... 0xa7: /* cmps */
1131 DPRINTF("Urk! I don't handle CMPS.\n");
1132 goto cannot_emulate;
1133 case 0xaa ... 0xab: /* stos */
1134 dst.type = OP_MEM;
1135 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1136 dst.ptr = (unsigned long *)cr2;
1137 dst.val = _regs[VCPU_REGS_RAX];
1138 register_address_increment(_regs[VCPU_REGS_RDI],
1139 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1140 break;
1141 case 0xac ... 0xad: /* lods */
1142 dst.type = OP_REG;
1143 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1144 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1145 if ((rc = ops->read_emulated(cr2, &dst.val, dst.bytes, ctxt)) != 0)
1146 goto done;
1147 register_address_increment(_regs[VCPU_REGS_RSI],
1148 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1149 break;
1150 case 0xae ... 0xaf: /* scas */
1151 DPRINTF("Urk! I don't handle SCAS.\n");
1152 goto cannot_emulate;
1153 case 0xf4: /* hlt */
1154 ctxt->vcpu->halt_request = 1;
1155 goto done;
1156 }
1157 goto writeback;
1158
1159 twobyte_insn:
1160 switch (b) {
1161 case 0x01: /* lgdt, lidt, lmsw */
1162 switch (modrm_reg) {
1163 u16 size;
1164 unsigned long address;
1165
1166 case 2: /* lgdt */
1167 rc = read_descriptor(ctxt, ops, src.ptr,
1168 &size, &address, op_bytes);
1169 if (rc)
1170 goto done;
1171 realmode_lgdt(ctxt->vcpu, size, address);
1172 break;
1173 case 3: /* lidt */
1174 rc = read_descriptor(ctxt, ops, src.ptr,
1175 &size, &address, op_bytes);
1176 if (rc)
1177 goto done;
1178 realmode_lidt(ctxt->vcpu, size, address);
1179 break;
1180 case 4: /* smsw */
1181 if (modrm_mod != 3)
1182 goto cannot_emulate;
1183 *(u16 *)&_regs[modrm_rm]
1184 = realmode_get_cr(ctxt->vcpu, 0);
1185 break;
1186 case 6: /* lmsw */
1187 if (modrm_mod != 3)
1188 goto cannot_emulate;
1189 realmode_lmsw(ctxt->vcpu, (u16)modrm_val, &_eflags);
1190 break;
1191 case 7: /* invlpg*/
1192 emulate_invlpg(ctxt->vcpu, cr2);
1193 break;
1194 default:
1195 goto cannot_emulate;
1196 }
1197 break;
1198 case 0x21: /* mov from dr to reg */
1199 if (modrm_mod != 3)
1200 goto cannot_emulate;
1201 rc = emulator_get_dr(ctxt, modrm_reg, &_regs[modrm_rm]);
1202 break;
1203 case 0x23: /* mov from reg to dr */
1204 if (modrm_mod != 3)
1205 goto cannot_emulate;
1206 rc = emulator_set_dr(ctxt, modrm_reg, _regs[modrm_rm]);
1207 break;
1208 case 0x40 ... 0x4f: /* cmov */
1209 dst.val = dst.orig_val = src.val;
1210 d &= ~Mov; /* default to no move */
1211 /*
1212 * First, assume we're decoding an even cmov opcode
1213 * (lsb == 0).
1214 */
1215 switch ((b & 15) >> 1) {
1216 case 0: /* cmovo */
1217 d |= (_eflags & EFLG_OF) ? Mov : 0;
1218 break;
1219 case 1: /* cmovb/cmovc/cmovnae */
1220 d |= (_eflags & EFLG_CF) ? Mov : 0;
1221 break;
1222 case 2: /* cmovz/cmove */
1223 d |= (_eflags & EFLG_ZF) ? Mov : 0;
1224 break;
1225 case 3: /* cmovbe/cmovna */
1226 d |= (_eflags & (EFLG_CF | EFLG_ZF)) ? Mov : 0;
1227 break;
1228 case 4: /* cmovs */
1229 d |= (_eflags & EFLG_SF) ? Mov : 0;
1230 break;
1231 case 5: /* cmovp/cmovpe */
1232 d |= (_eflags & EFLG_PF) ? Mov : 0;
1233 break;
1234 case 7: /* cmovle/cmovng */
1235 d |= (_eflags & EFLG_ZF) ? Mov : 0;
1236 /* fall through */
1237 case 6: /* cmovl/cmovnge */
1238 d |= (!(_eflags & EFLG_SF) !=
1239 !(_eflags & EFLG_OF)) ? Mov : 0;
1240 break;
1241 }
1242 /* Odd cmov opcodes (lsb == 1) have inverted sense. */
1243 d ^= (b & 1) ? Mov : 0;
1244 break;
1245 case 0xb0 ... 0xb1: /* cmpxchg */
1246 /*
1247 * Save real source value, then compare EAX against
1248 * destination.
1249 */
1250 src.orig_val = src.val;
1251 src.val = _regs[VCPU_REGS_RAX];
1252 emulate_2op_SrcV("cmp", src, dst, _eflags);
1253 /* Always write back. The question is: where to? */
1254 d |= Mov;
1255 if (_eflags & EFLG_ZF) {
1256 /* Success: write back to memory. */
1257 dst.val = src.orig_val;
1258 } else {
1259 /* Failure: write the value we saw to EAX. */
1260 dst.type = OP_REG;
1261 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1262 }
1263 break;
1264 case 0xa3:
1265 bt: /* bt */
1266 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1267 emulate_2op_SrcV_nobyte("bt", src, dst, _eflags);
1268 break;
1269 case 0xb3:
1270 btr: /* btr */
1271 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1272 emulate_2op_SrcV_nobyte("btr", src, dst, _eflags);
1273 break;
1274 case 0xab:
1275 bts: /* bts */
1276 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1277 emulate_2op_SrcV_nobyte("bts", src, dst, _eflags);
1278 break;
1279 case 0xb6 ... 0xb7: /* movzx */
1280 dst.bytes = op_bytes;
1281 dst.val = (d & ByteOp) ? (u8) src.val : (u16) src.val;
1282 break;
1283 case 0xbb:
1284 btc: /* btc */
1285 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1286 emulate_2op_SrcV_nobyte("btc", src, dst, _eflags);
1287 break;
1288 case 0xba: /* Grp8 */
1289 switch (modrm_reg & 3) {
1290 case 0:
1291 goto bt;
1292 case 1:
1293 goto bts;
1294 case 2:
1295 goto btr;
1296 case 3:
1297 goto btc;
1298 }
1299 break;
1300 case 0xbe ... 0xbf: /* movsx */
1301 dst.bytes = op_bytes;
1302 dst.val = (d & ByteOp) ? (s8) src.val : (s16) src.val;
1303 break;
1304 }
1305 goto writeback;
1306
1307 twobyte_special_insn:
1308 /* Disable writeback. */
1309 dst.orig_val = dst.val;
1310 switch (b) {
1311 case 0x09: /* wbinvd */
1312 break;
1313 case 0x0d: /* GrpP (prefetch) */
1314 case 0x18: /* Grp16 (prefetch/nop) */
1315 break;
1316 case 0x06:
1317 emulate_clts(ctxt->vcpu);
1318 break;
1319 case 0x20: /* mov cr, reg */
1320 if (modrm_mod != 3)
1321 goto cannot_emulate;
1322 _regs[modrm_rm] = realmode_get_cr(ctxt->vcpu, modrm_reg);
1323 break;
1324 case 0x22: /* mov reg, cr */
1325 if (modrm_mod != 3)
1326 goto cannot_emulate;
1327 realmode_set_cr(ctxt->vcpu, modrm_reg, modrm_val, &_eflags);
1328 break;
1329 case 0xc7: /* Grp9 (cmpxchg8b) */
1330 {
1331 u64 old, new;
1332 if ((rc = ops->read_emulated(cr2, &old, 8, ctxt)) != 0)
1333 goto done;
1334 if (((u32) (old >> 0) != (u32) _regs[VCPU_REGS_RAX]) ||
1335 ((u32) (old >> 32) != (u32) _regs[VCPU_REGS_RDX])) {
1336 _regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1337 _regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1338 _eflags &= ~EFLG_ZF;
1339 } else {
1340 new = ((u64)_regs[VCPU_REGS_RCX] << 32)
1341 | (u32) _regs[VCPU_REGS_RBX];
1342 if ((rc = ops->cmpxchg_emulated(cr2, &old,
1343 &new, 8, ctxt)) != 0)
1344 goto done;
1345 _eflags |= EFLG_ZF;
1346 }
1347 break;
1348 }
1349 }
1350 goto writeback;
1351
1352 cannot_emulate:
1353 DPRINTF("Cannot emulate %02x\n", b);
1354 return -1;
1355 }
1356
1357 #ifdef __XEN__
1358
1359 #include <asm/mm.h>
1360 #include <asm/uaccess.h>
1361
1362 int
1363 x86_emulate_read_std(unsigned long addr,
1364 unsigned long *val,
1365 unsigned int bytes, struct x86_emulate_ctxt *ctxt)
1366 {
1367 unsigned int rc;
1368
1369 *val = 0;
1370
1371 if ((rc = copy_from_user((void *)val, (void *)addr, bytes)) != 0) {
1372 propagate_page_fault(addr + bytes - rc, 0); /* read fault */
1373 return X86EMUL_PROPAGATE_FAULT;
1374 }
1375
1376 return X86EMUL_CONTINUE;
1377 }
1378
1379 int
1380 x86_emulate_write_std(unsigned long addr,
1381 unsigned long val,
1382 unsigned int bytes, struct x86_emulate_ctxt *ctxt)
1383 {
1384 unsigned int rc;
1385
1386 if ((rc = copy_to_user((void *)addr, (void *)&val, bytes)) != 0) {
1387 propagate_page_fault(addr + bytes - rc, PGERR_write_access);
1388 return X86EMUL_PROPAGATE_FAULT;
1389 }
1390
1391 return X86EMUL_CONTINUE;
1392 }
1393
1394 #endif
Linux 2.6 libata-dev (mirror)