2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
38 #include <linux/init.h>
40 #include <rdma/ib_verbs.h>
41 #include <rdma/ib_cache.h>
42 #include <rdma/ib_pack.h>
44 #include "mthca_dev.h"
45 #include "mthca_cmd.h"
46 #include "mthca_memfree.h"
47 #include "mthca_wqe.h"
50 MTHCA_MAX_DIRECT_QP_SIZE
= 4 * PAGE_SIZE
,
51 MTHCA_ACK_REQ_FREQ
= 10,
52 MTHCA_FLIGHT_LIMIT
= 9,
53 MTHCA_UD_HEADER_SIZE
= 72, /* largest UD header possible */
54 MTHCA_INLINE_HEADER_SIZE
= 4, /* data segment overhead for inline */
55 MTHCA_INLINE_CHUNK_SIZE
= 16 /* inline data segment chunk */
59 MTHCA_QP_STATE_RST
= 0,
60 MTHCA_QP_STATE_INIT
= 1,
61 MTHCA_QP_STATE_RTR
= 2,
62 MTHCA_QP_STATE_RTS
= 3,
63 MTHCA_QP_STATE_SQE
= 4,
64 MTHCA_QP_STATE_SQD
= 5,
65 MTHCA_QP_STATE_ERR
= 6,
66 MTHCA_QP_STATE_DRAINING
= 7
78 MTHCA_QP_PM_MIGRATED
= 0x3,
79 MTHCA_QP_PM_ARMED
= 0x0,
80 MTHCA_QP_PM_REARM
= 0x1
84 /* qp_context flags */
85 MTHCA_QP_BIT_DE
= 1 << 8,
87 MTHCA_QP_BIT_SRE
= 1 << 15,
88 MTHCA_QP_BIT_SWE
= 1 << 14,
89 MTHCA_QP_BIT_SAE
= 1 << 13,
90 MTHCA_QP_BIT_SIC
= 1 << 4,
91 MTHCA_QP_BIT_SSC
= 1 << 3,
93 MTHCA_QP_BIT_RRE
= 1 << 15,
94 MTHCA_QP_BIT_RWE
= 1 << 14,
95 MTHCA_QP_BIT_RAE
= 1 << 13,
96 MTHCA_QP_BIT_RIC
= 1 << 4,
97 MTHCA_QP_BIT_RSC
= 1 << 3
100 struct mthca_qp_path
{
109 __be32 sl_tclass_flowlabel
;
111 } __attribute__((packed
));
113 struct mthca_qp_context
{
115 __be32 tavor_sched_queue
; /* Reserved on Arbel */
117 u8 rq_size_stride
; /* Reserved on Tavor */
118 u8 sq_size_stride
; /* Reserved on Tavor */
119 u8 rlkey_arbel_sched_queue
; /* Reserved on Tavor */
124 struct mthca_qp_path pri_path
;
125 struct mthca_qp_path alt_path
;
132 __be32 next_send_psn
;
134 __be32 snd_wqe_base_l
; /* Next send WQE on Tavor */
135 __be32 snd_db_index
; /* (debugging only entries) */
136 __be32 last_acked_psn
;
139 __be32 rnr_nextrecvpsn
;
142 __be32 rcv_wqe_base_l
; /* Next recv WQE on Tavor */
143 __be32 rcv_db_index
; /* (debugging only entries) */
147 __be16 rq_wqe_counter
; /* reserved on Tavor */
148 __be16 sq_wqe_counter
; /* reserved on Tavor */
150 } __attribute__((packed
));
152 struct mthca_qp_param
{
153 __be32 opt_param_mask
;
155 struct mthca_qp_context context
;
157 } __attribute__((packed
));
160 MTHCA_QP_OPTPAR_ALT_ADDR_PATH
= 1 << 0,
161 MTHCA_QP_OPTPAR_RRE
= 1 << 1,
162 MTHCA_QP_OPTPAR_RAE
= 1 << 2,
163 MTHCA_QP_OPTPAR_RWE
= 1 << 3,
164 MTHCA_QP_OPTPAR_PKEY_INDEX
= 1 << 4,
165 MTHCA_QP_OPTPAR_Q_KEY
= 1 << 5,
166 MTHCA_QP_OPTPAR_RNR_TIMEOUT
= 1 << 6,
167 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
= 1 << 7,
168 MTHCA_QP_OPTPAR_SRA_MAX
= 1 << 8,
169 MTHCA_QP_OPTPAR_RRA_MAX
= 1 << 9,
170 MTHCA_QP_OPTPAR_PM_STATE
= 1 << 10,
171 MTHCA_QP_OPTPAR_PORT_NUM
= 1 << 11,
172 MTHCA_QP_OPTPAR_RETRY_COUNT
= 1 << 12,
173 MTHCA_QP_OPTPAR_ALT_RNR_RETRY
= 1 << 13,
174 MTHCA_QP_OPTPAR_ACK_TIMEOUT
= 1 << 14,
175 MTHCA_QP_OPTPAR_RNR_RETRY
= 1 << 15,
176 MTHCA_QP_OPTPAR_SCHED_QUEUE
= 1 << 16
179 static const u8 mthca_opcode
[] = {
180 [IB_WR_SEND
] = MTHCA_OPCODE_SEND
,
181 [IB_WR_SEND_WITH_IMM
] = MTHCA_OPCODE_SEND_IMM
,
182 [IB_WR_RDMA_WRITE
] = MTHCA_OPCODE_RDMA_WRITE
,
183 [IB_WR_RDMA_WRITE_WITH_IMM
] = MTHCA_OPCODE_RDMA_WRITE_IMM
,
184 [IB_WR_RDMA_READ
] = MTHCA_OPCODE_RDMA_READ
,
185 [IB_WR_ATOMIC_CMP_AND_SWP
] = MTHCA_OPCODE_ATOMIC_CS
,
186 [IB_WR_ATOMIC_FETCH_AND_ADD
] = MTHCA_OPCODE_ATOMIC_FA
,
189 static int is_sqp(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
191 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
192 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 3;
195 static int is_qp0(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
197 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
198 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 1;
201 static void *get_recv_wqe(struct mthca_qp
*qp
, int n
)
204 return qp
->queue
.direct
.buf
+ (n
<< qp
->rq
.wqe_shift
);
206 return qp
->queue
.page_list
[(n
<< qp
->rq
.wqe_shift
) >> PAGE_SHIFT
].buf
+
207 ((n
<< qp
->rq
.wqe_shift
) & (PAGE_SIZE
- 1));
210 static void *get_send_wqe(struct mthca_qp
*qp
, int n
)
213 return qp
->queue
.direct
.buf
+ qp
->send_wqe_offset
+
214 (n
<< qp
->sq
.wqe_shift
);
216 return qp
->queue
.page_list
[(qp
->send_wqe_offset
+
217 (n
<< qp
->sq
.wqe_shift
)) >>
219 ((qp
->send_wqe_offset
+ (n
<< qp
->sq
.wqe_shift
)) &
223 static void mthca_wq_init(struct mthca_wq
*wq
)
225 spin_lock_init(&wq
->lock
);
227 wq
->last_comp
= wq
->max
- 1;
232 void mthca_qp_event(struct mthca_dev
*dev
, u32 qpn
,
233 enum ib_event_type event_type
)
236 struct ib_event event
;
238 spin_lock(&dev
->qp_table
.lock
);
239 qp
= mthca_array_get(&dev
->qp_table
.qp
, qpn
& (dev
->limits
.num_qps
- 1));
241 atomic_inc(&qp
->refcount
);
242 spin_unlock(&dev
->qp_table
.lock
);
245 mthca_warn(dev
, "Async event for bogus QP %08x\n", qpn
);
249 event
.device
= &dev
->ib_dev
;
250 event
.event
= event_type
;
251 event
.element
.qp
= &qp
->ibqp
;
252 if (qp
->ibqp
.event_handler
)
253 qp
->ibqp
.event_handler(&event
, qp
->ibqp
.qp_context
);
255 if (atomic_dec_and_test(&qp
->refcount
))
259 static int to_mthca_state(enum ib_qp_state ib_state
)
262 case IB_QPS_RESET
: return MTHCA_QP_STATE_RST
;
263 case IB_QPS_INIT
: return MTHCA_QP_STATE_INIT
;
264 case IB_QPS_RTR
: return MTHCA_QP_STATE_RTR
;
265 case IB_QPS_RTS
: return MTHCA_QP_STATE_RTS
;
266 case IB_QPS_SQD
: return MTHCA_QP_STATE_SQD
;
267 case IB_QPS_SQE
: return MTHCA_QP_STATE_SQE
;
268 case IB_QPS_ERR
: return MTHCA_QP_STATE_ERR
;
273 enum { RC
, UC
, UD
, RD
, RDEE
, MLX
, NUM_TRANS
};
275 static int to_mthca_st(int transport
)
278 case RC
: return MTHCA_QP_ST_RC
;
279 case UC
: return MTHCA_QP_ST_UC
;
280 case UD
: return MTHCA_QP_ST_UD
;
281 case RD
: return MTHCA_QP_ST_RD
;
282 case MLX
: return MTHCA_QP_ST_MLX
;
287 static const struct {
289 u32 req_param
[NUM_TRANS
];
290 u32 opt_param
[NUM_TRANS
];
291 } state_table
[IB_QPS_ERR
+ 1][IB_QPS_ERR
+ 1] = {
293 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
294 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
296 .trans
= MTHCA_TRANS_RST2INIT
,
298 [UD
] = (IB_QP_PKEY_INDEX
|
301 [UC
] = (IB_QP_PKEY_INDEX
|
304 [RC
] = (IB_QP_PKEY_INDEX
|
307 [MLX
] = (IB_QP_PKEY_INDEX
|
310 /* bug-for-bug compatibility with VAPI: */
317 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
318 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
320 .trans
= MTHCA_TRANS_INIT2INIT
,
322 [UD
] = (IB_QP_PKEY_INDEX
|
325 [UC
] = (IB_QP_PKEY_INDEX
|
328 [RC
] = (IB_QP_PKEY_INDEX
|
331 [MLX
] = (IB_QP_PKEY_INDEX
|
336 .trans
= MTHCA_TRANS_INIT2RTR
,
342 IB_QP_MAX_DEST_RD_ATOMIC
),
347 IB_QP_MAX_DEST_RD_ATOMIC
|
348 IB_QP_MIN_RNR_TIMER
),
351 [UD
] = (IB_QP_PKEY_INDEX
|
353 [UC
] = (IB_QP_ALT_PATH
|
356 [RC
] = (IB_QP_ALT_PATH
|
359 [MLX
] = (IB_QP_PKEY_INDEX
|
365 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
366 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
368 .trans
= MTHCA_TRANS_RTR2RTS
,
371 [UC
] = (IB_QP_SQ_PSN
|
372 IB_QP_MAX_QP_RD_ATOMIC
),
373 [RC
] = (IB_QP_TIMEOUT
|
377 IB_QP_MAX_QP_RD_ATOMIC
),
378 [MLX
] = IB_QP_SQ_PSN
,
381 [UD
] = (IB_QP_CUR_STATE
|
383 [UC
] = (IB_QP_CUR_STATE
|
387 IB_QP_PATH_MIG_STATE
),
388 [RC
] = (IB_QP_CUR_STATE
|
392 IB_QP_MIN_RNR_TIMER
|
393 IB_QP_PATH_MIG_STATE
),
394 [MLX
] = (IB_QP_CUR_STATE
|
400 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
401 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
403 .trans
= MTHCA_TRANS_RTS2RTS
,
405 [UD
] = (IB_QP_CUR_STATE
|
407 [UC
] = (IB_QP_ACCESS_FLAGS
|
409 IB_QP_PATH_MIG_STATE
),
410 [RC
] = (IB_QP_ACCESS_FLAGS
|
412 IB_QP_PATH_MIG_STATE
|
413 IB_QP_MIN_RNR_TIMER
),
414 [MLX
] = (IB_QP_CUR_STATE
|
419 .trans
= MTHCA_TRANS_RTS2SQD
,
423 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
424 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
426 .trans
= MTHCA_TRANS_SQD2RTS
,
428 [UD
] = (IB_QP_CUR_STATE
|
430 [UC
] = (IB_QP_CUR_STATE
|
433 IB_QP_PATH_MIG_STATE
),
434 [RC
] = (IB_QP_CUR_STATE
|
437 IB_QP_MIN_RNR_TIMER
|
438 IB_QP_PATH_MIG_STATE
),
439 [MLX
] = (IB_QP_CUR_STATE
|
444 .trans
= MTHCA_TRANS_SQD2SQD
,
446 [UD
] = (IB_QP_PKEY_INDEX
|
449 IB_QP_MAX_QP_RD_ATOMIC
|
450 IB_QP_MAX_DEST_RD_ATOMIC
|
455 IB_QP_PATH_MIG_STATE
),
460 IB_QP_MAX_QP_RD_ATOMIC
|
461 IB_QP_MAX_DEST_RD_ATOMIC
|
466 IB_QP_MIN_RNR_TIMER
|
467 IB_QP_PATH_MIG_STATE
),
468 [MLX
] = (IB_QP_PKEY_INDEX
|
474 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
475 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
477 .trans
= MTHCA_TRANS_SQERR2RTS
,
479 [UD
] = (IB_QP_CUR_STATE
|
481 [UC
] = (IB_QP_CUR_STATE
),
482 [RC
] = (IB_QP_CUR_STATE
|
483 IB_QP_MIN_RNR_TIMER
),
484 [MLX
] = (IB_QP_CUR_STATE
|
490 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
491 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
}
495 static void store_attrs(struct mthca_sqp
*sqp
, struct ib_qp_attr
*attr
,
498 if (attr_mask
& IB_QP_PKEY_INDEX
)
499 sqp
->pkey_index
= attr
->pkey_index
;
500 if (attr_mask
& IB_QP_QKEY
)
501 sqp
->qkey
= attr
->qkey
;
502 if (attr_mask
& IB_QP_SQ_PSN
)
503 sqp
->send_psn
= attr
->sq_psn
;
506 static void init_port(struct mthca_dev
*dev
, int port
)
510 struct mthca_init_ib_param param
;
512 memset(¶m
, 0, sizeof param
);
514 param
.port_width
= dev
->limits
.port_width_cap
;
515 param
.vl_cap
= dev
->limits
.vl_cap
;
516 param
.mtu_cap
= dev
->limits
.mtu_cap
;
517 param
.gid_cap
= dev
->limits
.gid_table_len
;
518 param
.pkey_cap
= dev
->limits
.pkey_table_len
;
520 err
= mthca_INIT_IB(dev
, ¶m
, port
, &status
);
522 mthca_warn(dev
, "INIT_IB failed, return code %d.\n", err
);
524 mthca_warn(dev
, "INIT_IB returned status %02x.\n", status
);
527 int mthca_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
, int attr_mask
)
529 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
530 struct mthca_qp
*qp
= to_mqp(ibqp
);
531 enum ib_qp_state cur_state
, new_state
;
532 struct mthca_mailbox
*mailbox
;
533 struct mthca_qp_param
*qp_param
;
534 struct mthca_qp_context
*qp_context
;
535 u32 req_param
, opt_param
;
539 if (attr_mask
& IB_QP_CUR_STATE
) {
540 if (attr
->cur_qp_state
!= IB_QPS_RTR
&&
541 attr
->cur_qp_state
!= IB_QPS_RTS
&&
542 attr
->cur_qp_state
!= IB_QPS_SQD
&&
543 attr
->cur_qp_state
!= IB_QPS_SQE
)
546 cur_state
= attr
->cur_qp_state
;
548 spin_lock_irq(&qp
->sq
.lock
);
549 spin_lock(&qp
->rq
.lock
);
550 cur_state
= qp
->state
;
551 spin_unlock(&qp
->rq
.lock
);
552 spin_unlock_irq(&qp
->sq
.lock
);
555 if (attr_mask
& IB_QP_STATE
) {
556 if (attr
->qp_state
< 0 || attr
->qp_state
> IB_QPS_ERR
)
558 new_state
= attr
->qp_state
;
560 new_state
= cur_state
;
562 if (state_table
[cur_state
][new_state
].trans
== MTHCA_TRANS_INVALID
) {
563 mthca_dbg(dev
, "Illegal QP transition "
564 "%d->%d\n", cur_state
, new_state
);
568 req_param
= state_table
[cur_state
][new_state
].req_param
[qp
->transport
];
569 opt_param
= state_table
[cur_state
][new_state
].opt_param
[qp
->transport
];
571 if ((req_param
& attr_mask
) != req_param
) {
572 mthca_dbg(dev
, "QP transition "
573 "%d->%d missing req attr 0x%08x\n",
574 cur_state
, new_state
,
575 req_param
& ~attr_mask
);
579 if (attr_mask
& ~(req_param
| opt_param
| IB_QP_STATE
)) {
580 mthca_dbg(dev
, "QP transition (transport %d) "
581 "%d->%d has extra attr 0x%08x\n",
583 cur_state
, new_state
,
584 attr_mask
& ~(req_param
| opt_param
|
589 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
591 return PTR_ERR(mailbox
);
592 qp_param
= mailbox
->buf
;
593 qp_context
= &qp_param
->context
;
594 memset(qp_param
, 0, sizeof *qp_param
);
596 qp_context
->flags
= cpu_to_be32((to_mthca_state(new_state
) << 28) |
597 (to_mthca_st(qp
->transport
) << 16));
598 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_BIT_DE
);
599 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
))
600 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
602 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE
);
603 switch (attr
->path_mig_state
) {
604 case IB_MIG_MIGRATED
:
605 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
608 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_REARM
<< 11);
611 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_ARMED
<< 11);
616 /* leave tavor_sched_queue as 0 */
618 if (qp
->transport
== MLX
|| qp
->transport
== UD
)
619 qp_context
->mtu_msgmax
= (IB_MTU_2048
<< 5) | 11;
620 else if (attr_mask
& IB_QP_PATH_MTU
)
621 qp_context
->mtu_msgmax
= (attr
->path_mtu
<< 5) | 31;
623 if (mthca_is_memfree(dev
)) {
625 qp_context
->rq_size_stride
= long_log2(qp
->rq
.max
) << 3;
626 qp_context
->rq_size_stride
|= qp
->rq
.wqe_shift
- 4;
629 qp_context
->sq_size_stride
= long_log2(qp
->sq
.max
) << 3;
630 qp_context
->sq_size_stride
|= qp
->sq
.wqe_shift
- 4;
633 /* leave arbel_sched_queue as 0 */
635 if (qp
->ibqp
.uobject
)
636 qp_context
->usr_page
=
637 cpu_to_be32(to_mucontext(qp
->ibqp
.uobject
->context
)->uar
.index
);
639 qp_context
->usr_page
= cpu_to_be32(dev
->driver_uar
.index
);
640 qp_context
->local_qpn
= cpu_to_be32(qp
->qpn
);
641 if (attr_mask
& IB_QP_DEST_QPN
) {
642 qp_context
->remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
645 if (qp
->transport
== MLX
)
646 qp_context
->pri_path
.port_pkey
|=
647 cpu_to_be32(to_msqp(qp
)->port
<< 24);
649 if (attr_mask
& IB_QP_PORT
) {
650 qp_context
->pri_path
.port_pkey
|=
651 cpu_to_be32(attr
->port_num
<< 24);
652 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM
);
656 if (attr_mask
& IB_QP_PKEY_INDEX
) {
657 qp_context
->pri_path
.port_pkey
|=
658 cpu_to_be32(attr
->pkey_index
);
659 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX
);
662 if (attr_mask
& IB_QP_RNR_RETRY
) {
663 qp_context
->pri_path
.rnr_retry
= attr
->rnr_retry
<< 5;
664 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY
);
667 if (attr_mask
& IB_QP_AV
) {
668 qp_context
->pri_path
.g_mylmc
= attr
->ah_attr
.src_path_bits
& 0x7f;
669 qp_context
->pri_path
.rlid
= cpu_to_be16(attr
->ah_attr
.dlid
);
670 qp_context
->pri_path
.static_rate
= !!attr
->ah_attr
.static_rate
;
671 if (attr
->ah_attr
.ah_flags
& IB_AH_GRH
) {
672 qp_context
->pri_path
.g_mylmc
|= 1 << 7;
673 qp_context
->pri_path
.mgid_index
= attr
->ah_attr
.grh
.sgid_index
;
674 qp_context
->pri_path
.hop_limit
= attr
->ah_attr
.grh
.hop_limit
;
675 qp_context
->pri_path
.sl_tclass_flowlabel
=
676 cpu_to_be32((attr
->ah_attr
.sl
<< 28) |
677 (attr
->ah_attr
.grh
.traffic_class
<< 20) |
678 (attr
->ah_attr
.grh
.flow_label
));
679 memcpy(qp_context
->pri_path
.rgid
,
680 attr
->ah_attr
.grh
.dgid
.raw
, 16);
682 qp_context
->pri_path
.sl_tclass_flowlabel
=
683 cpu_to_be32(attr
->ah_attr
.sl
<< 28);
685 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
);
688 if (attr_mask
& IB_QP_TIMEOUT
) {
689 qp_context
->pri_path
.ackto
= attr
->timeout
<< 3;
690 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT
);
696 qp_context
->pd
= cpu_to_be32(to_mpd(ibqp
->pd
)->pd_num
);
697 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
698 qp_context
->wqe_lkey
= cpu_to_be32(qp
->mr
.ibmr
.lkey
);
699 qp_context
->params1
= cpu_to_be32((MTHCA_ACK_REQ_FREQ
<< 28) |
700 (MTHCA_FLIGHT_LIMIT
<< 24) |
704 if (qp
->sq_policy
== IB_SIGNAL_ALL_WR
)
705 qp_context
->params1
|= cpu_to_be32(MTHCA_QP_BIT_SSC
);
706 if (attr_mask
& IB_QP_RETRY_CNT
) {
707 qp_context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
708 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT
);
711 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
712 qp_context
->params1
|= cpu_to_be32(min(attr
->max_rd_atomic
?
713 ffs(attr
->max_rd_atomic
) - 1 : 0,
715 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX
);
718 if (attr_mask
& IB_QP_SQ_PSN
)
719 qp_context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
720 qp_context
->cqn_snd
= cpu_to_be32(to_mcq(ibqp
->send_cq
)->cqn
);
722 if (mthca_is_memfree(dev
)) {
723 qp_context
->snd_wqe_base_l
= cpu_to_be32(qp
->send_wqe_offset
);
724 qp_context
->snd_db_index
= cpu_to_be32(qp
->sq
.db_index
);
727 if (attr_mask
& IB_QP_ACCESS_FLAGS
) {
729 * Only enable RDMA/atomics if we have responder
730 * resources set to a non-zero value.
732 if (qp
->resp_depth
) {
733 qp_context
->params2
|=
734 cpu_to_be32(attr
->qp_access_flags
& IB_ACCESS_REMOTE_WRITE
?
735 MTHCA_QP_BIT_RWE
: 0);
736 qp_context
->params2
|=
737 cpu_to_be32(attr
->qp_access_flags
& IB_ACCESS_REMOTE_READ
?
738 MTHCA_QP_BIT_RRE
: 0);
739 qp_context
->params2
|=
740 cpu_to_be32(attr
->qp_access_flags
& IB_ACCESS_REMOTE_ATOMIC
?
741 MTHCA_QP_BIT_RAE
: 0);
744 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RWE
|
745 MTHCA_QP_OPTPAR_RRE
|
746 MTHCA_QP_OPTPAR_RAE
);
748 qp
->atomic_rd_en
= attr
->qp_access_flags
;
751 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
754 if (qp
->resp_depth
&& !attr
->max_dest_rd_atomic
) {
756 * Lowering our responder resources to zero.
757 * Turn off RDMA/atomics as responder.
758 * (RWE/RRE/RAE in params2 already zero)
760 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RWE
|
761 MTHCA_QP_OPTPAR_RRE
|
762 MTHCA_QP_OPTPAR_RAE
);
765 if (!qp
->resp_depth
&& attr
->max_dest_rd_atomic
) {
767 * Increasing our responder resources from
768 * zero. Turn on RDMA/atomics as appropriate.
770 qp_context
->params2
|=
771 cpu_to_be32(qp
->atomic_rd_en
& IB_ACCESS_REMOTE_WRITE
?
772 MTHCA_QP_BIT_RWE
: 0);
773 qp_context
->params2
|=
774 cpu_to_be32(qp
->atomic_rd_en
& IB_ACCESS_REMOTE_READ
?
775 MTHCA_QP_BIT_RRE
: 0);
776 qp_context
->params2
|=
777 cpu_to_be32(qp
->atomic_rd_en
& IB_ACCESS_REMOTE_ATOMIC
?
778 MTHCA_QP_BIT_RAE
: 0);
780 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RWE
|
781 MTHCA_QP_OPTPAR_RRE
|
782 MTHCA_QP_OPTPAR_RAE
);
786 1 << rra_max
< attr
->max_dest_rd_atomic
&&
787 rra_max
< dev
->qp_table
.rdb_shift
;
791 qp_context
->params2
|= cpu_to_be32(rra_max
<< 21);
792 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX
);
794 qp
->resp_depth
= attr
->max_dest_rd_atomic
;
797 qp_context
->params2
|= cpu_to_be32(MTHCA_QP_BIT_RSC
);
800 qp_context
->params2
|= cpu_to_be32(MTHCA_QP_BIT_RIC
);
802 if (attr_mask
& IB_QP_MIN_RNR_TIMER
) {
803 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
804 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT
);
806 if (attr_mask
& IB_QP_RQ_PSN
)
807 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
809 qp_context
->ra_buff_indx
=
810 cpu_to_be32(dev
->qp_table
.rdb_base
+
811 ((qp
->qpn
& (dev
->limits
.num_qps
- 1)) * MTHCA_RDB_ENTRY_SIZE
<<
812 dev
->qp_table
.rdb_shift
));
814 qp_context
->cqn_rcv
= cpu_to_be32(to_mcq(ibqp
->recv_cq
)->cqn
);
816 if (mthca_is_memfree(dev
))
817 qp_context
->rcv_db_index
= cpu_to_be32(qp
->rq
.db_index
);
819 if (attr_mask
& IB_QP_QKEY
) {
820 qp_context
->qkey
= cpu_to_be32(attr
->qkey
);
821 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY
);
825 qp_context
->srqn
= cpu_to_be32(1 << 24 |
826 to_msrq(ibqp
->srq
)->srqn
);
828 err
= mthca_MODIFY_QP(dev
, state_table
[cur_state
][new_state
].trans
,
829 qp
->qpn
, 0, mailbox
, 0, &status
);
831 mthca_warn(dev
, "modify QP %d returned status %02x.\n",
832 state_table
[cur_state
][new_state
].trans
, status
);
837 qp
->state
= new_state
;
839 mthca_free_mailbox(dev
, mailbox
);
842 store_attrs(to_msqp(qp
), attr
, attr_mask
);
845 * If we moved QP0 to RTR, bring the IB link up; if we moved
846 * QP0 to RESET or ERROR, bring the link back down.
848 if (is_qp0(dev
, qp
)) {
849 if (cur_state
!= IB_QPS_RTR
&&
850 new_state
== IB_QPS_RTR
)
851 init_port(dev
, to_msqp(qp
)->port
);
853 if (cur_state
!= IB_QPS_RESET
&&
854 cur_state
!= IB_QPS_ERR
&&
855 (new_state
== IB_QPS_RESET
||
856 new_state
== IB_QPS_ERR
))
857 mthca_CLOSE_IB(dev
, to_msqp(qp
)->port
, &status
);
861 * If we moved a kernel QP to RESET, clean up all old CQ
862 * entries and reinitialize the QP.
864 if (!err
&& new_state
== IB_QPS_RESET
&& !qp
->ibqp
.uobject
) {
865 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.send_cq
)->cqn
, qp
->qpn
,
866 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
867 if (qp
->ibqp
.send_cq
!= qp
->ibqp
.recv_cq
)
868 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.recv_cq
)->cqn
, qp
->qpn
,
869 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
871 mthca_wq_init(&qp
->sq
);
872 mthca_wq_init(&qp
->rq
);
874 if (mthca_is_memfree(dev
)) {
884 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
885 * rq.max_gs and sq.max_gs must all be assigned.
886 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
887 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
890 static int mthca_alloc_wqe_buf(struct mthca_dev
*dev
,
897 size
= sizeof (struct mthca_next_seg
) +
898 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
);
900 for (qp
->rq
.wqe_shift
= 6; 1 << qp
->rq
.wqe_shift
< size
;
904 size
= sizeof (struct mthca_next_seg
) +
905 qp
->sq
.max_gs
* sizeof (struct mthca_data_seg
);
906 switch (qp
->transport
) {
908 size
+= 2 * sizeof (struct mthca_data_seg
);
911 if (mthca_is_memfree(dev
))
912 size
+= sizeof (struct mthca_arbel_ud_seg
);
914 size
+= sizeof (struct mthca_tavor_ud_seg
);
917 /* bind seg is as big as atomic + raddr segs */
918 size
+= sizeof (struct mthca_bind_seg
);
921 for (qp
->sq
.wqe_shift
= 6; 1 << qp
->sq
.wqe_shift
< size
;
925 qp
->send_wqe_offset
= ALIGN(qp
->rq
.max
<< qp
->rq
.wqe_shift
,
926 1 << qp
->sq
.wqe_shift
);
929 * If this is a userspace QP, we don't actually have to
930 * allocate anything. All we need is to calculate the WQE
931 * sizes and the send_wqe_offset, so we're done now.
933 if (pd
->ibpd
.uobject
)
936 size
= PAGE_ALIGN(qp
->send_wqe_offset
+
937 (qp
->sq
.max
<< qp
->sq
.wqe_shift
));
939 qp
->wrid
= kmalloc((qp
->rq
.max
+ qp
->sq
.max
) * sizeof (u64
),
944 err
= mthca_buf_alloc(dev
, size
, MTHCA_MAX_DIRECT_QP_SIZE
,
945 &qp
->queue
, &qp
->is_direct
, pd
, 0, &qp
->mr
);
956 static void mthca_free_wqe_buf(struct mthca_dev
*dev
,
959 mthca_buf_free(dev
, PAGE_ALIGN(qp
->send_wqe_offset
+
960 (qp
->sq
.max
<< qp
->sq
.wqe_shift
)),
961 &qp
->queue
, qp
->is_direct
, &qp
->mr
);
965 static int mthca_map_memfree(struct mthca_dev
*dev
,
970 if (mthca_is_memfree(dev
)) {
971 ret
= mthca_table_get(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
975 ret
= mthca_table_get(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
979 ret
= mthca_table_get(dev
, dev
->qp_table
.rdb_table
,
980 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
989 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
992 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
997 static void mthca_unmap_memfree(struct mthca_dev
*dev
,
1000 mthca_table_put(dev
, dev
->qp_table
.rdb_table
,
1001 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
1002 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1003 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1006 static int mthca_alloc_memfree(struct mthca_dev
*dev
,
1007 struct mthca_qp
*qp
)
1011 if (mthca_is_memfree(dev
)) {
1012 qp
->rq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_RQ
,
1013 qp
->qpn
, &qp
->rq
.db
);
1014 if (qp
->rq
.db_index
< 0)
1017 qp
->sq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_SQ
,
1018 qp
->qpn
, &qp
->sq
.db
);
1019 if (qp
->sq
.db_index
< 0)
1020 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1026 static void mthca_free_memfree(struct mthca_dev
*dev
,
1027 struct mthca_qp
*qp
)
1029 if (mthca_is_memfree(dev
)) {
1030 mthca_free_db(dev
, MTHCA_DB_TYPE_SQ
, qp
->sq
.db_index
);
1031 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1035 static int mthca_alloc_qp_common(struct mthca_dev
*dev
,
1036 struct mthca_pd
*pd
,
1037 struct mthca_cq
*send_cq
,
1038 struct mthca_cq
*recv_cq
,
1039 enum ib_sig_type send_policy
,
1040 struct mthca_qp
*qp
)
1045 atomic_set(&qp
->refcount
, 1);
1046 init_waitqueue_head(&qp
->wait
);
1047 qp
->state
= IB_QPS_RESET
;
1048 qp
->atomic_rd_en
= 0;
1050 qp
->sq_policy
= send_policy
;
1051 mthca_wq_init(&qp
->sq
);
1052 mthca_wq_init(&qp
->rq
);
1054 ret
= mthca_map_memfree(dev
, qp
);
1058 ret
= mthca_alloc_wqe_buf(dev
, pd
, qp
);
1060 mthca_unmap_memfree(dev
, qp
);
1065 * If this is a userspace QP, we're done now. The doorbells
1066 * will be allocated and buffers will be initialized in
1069 if (pd
->ibpd
.uobject
)
1072 ret
= mthca_alloc_memfree(dev
, qp
);
1074 mthca_free_wqe_buf(dev
, qp
);
1075 mthca_unmap_memfree(dev
, qp
);
1079 if (mthca_is_memfree(dev
)) {
1080 struct mthca_next_seg
*next
;
1081 struct mthca_data_seg
*scatter
;
1082 int size
= (sizeof (struct mthca_next_seg
) +
1083 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
)) / 16;
1085 for (i
= 0; i
< qp
->rq
.max
; ++i
) {
1086 next
= get_recv_wqe(qp
, i
);
1087 next
->nda_op
= cpu_to_be32(((i
+ 1) & (qp
->rq
.max
- 1)) <<
1089 next
->ee_nds
= cpu_to_be32(size
);
1091 for (scatter
= (void *) (next
+ 1);
1092 (void *) scatter
< (void *) next
+ (1 << qp
->rq
.wqe_shift
);
1094 scatter
->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
1097 for (i
= 0; i
< qp
->sq
.max
; ++i
) {
1098 next
= get_send_wqe(qp
, i
);
1099 next
->nda_op
= cpu_to_be32((((i
+ 1) & (qp
->sq
.max
- 1)) <<
1101 qp
->send_wqe_offset
);
1105 qp
->sq
.last
= get_send_wqe(qp
, qp
->sq
.max
- 1);
1106 qp
->rq
.last
= get_recv_wqe(qp
, qp
->rq
.max
- 1);
1111 static int mthca_set_qp_size(struct mthca_dev
*dev
, struct ib_qp_cap
*cap
,
1112 struct mthca_qp
*qp
)
1114 /* Sanity check QP size before proceeding */
1115 if (cap
->max_send_wr
> 65536 || cap
->max_recv_wr
> 65536 ||
1116 cap
->max_send_sge
> 64 || cap
->max_recv_sge
> 64)
1119 if (mthca_is_memfree(dev
)) {
1120 qp
->rq
.max
= cap
->max_recv_wr
?
1121 roundup_pow_of_two(cap
->max_recv_wr
) : 0;
1122 qp
->sq
.max
= cap
->max_send_wr
?
1123 roundup_pow_of_two(cap
->max_send_wr
) : 0;
1125 qp
->rq
.max
= cap
->max_recv_wr
;
1126 qp
->sq
.max
= cap
->max_send_wr
;
1129 qp
->rq
.max_gs
= cap
->max_recv_sge
;
1130 qp
->sq
.max_gs
= max_t(int, cap
->max_send_sge
,
1131 ALIGN(cap
->max_inline_data
+ MTHCA_INLINE_HEADER_SIZE
,
1132 MTHCA_INLINE_CHUNK_SIZE
) /
1133 sizeof (struct mthca_data_seg
));
1136 * For MLX transport we need 2 extra S/G entries:
1137 * one for the header and one for the checksum at the end
1139 if ((qp
->transport
== MLX
&& qp
->sq
.max_gs
+ 2 > dev
->limits
.max_sg
) ||
1140 qp
->sq
.max_gs
> dev
->limits
.max_sg
|| qp
->rq
.max_gs
> dev
->limits
.max_sg
)
1146 int mthca_alloc_qp(struct mthca_dev
*dev
,
1147 struct mthca_pd
*pd
,
1148 struct mthca_cq
*send_cq
,
1149 struct mthca_cq
*recv_cq
,
1150 enum ib_qp_type type
,
1151 enum ib_sig_type send_policy
,
1152 struct ib_qp_cap
*cap
,
1153 struct mthca_qp
*qp
)
1157 err
= mthca_set_qp_size(dev
, cap
, qp
);
1162 case IB_QPT_RC
: qp
->transport
= RC
; break;
1163 case IB_QPT_UC
: qp
->transport
= UC
; break;
1164 case IB_QPT_UD
: qp
->transport
= UD
; break;
1165 default: return -EINVAL
;
1168 qp
->qpn
= mthca_alloc(&dev
->qp_table
.alloc
);
1172 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1175 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1179 spin_lock_irq(&dev
->qp_table
.lock
);
1180 mthca_array_set(&dev
->qp_table
.qp
,
1181 qp
->qpn
& (dev
->limits
.num_qps
- 1), qp
);
1182 spin_unlock_irq(&dev
->qp_table
.lock
);
1187 int mthca_alloc_sqp(struct mthca_dev
*dev
,
1188 struct mthca_pd
*pd
,
1189 struct mthca_cq
*send_cq
,
1190 struct mthca_cq
*recv_cq
,
1191 enum ib_sig_type send_policy
,
1192 struct ib_qp_cap
*cap
,
1195 struct mthca_sqp
*sqp
)
1197 u32 mqpn
= qpn
* 2 + dev
->qp_table
.sqp_start
+ port
- 1;
1200 err
= mthca_set_qp_size(dev
, cap
, &sqp
->qp
);
1204 sqp
->header_buf_size
= sqp
->qp
.sq
.max
* MTHCA_UD_HEADER_SIZE
;
1205 sqp
->header_buf
= dma_alloc_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1206 &sqp
->header_dma
, GFP_KERNEL
);
1207 if (!sqp
->header_buf
)
1210 spin_lock_irq(&dev
->qp_table
.lock
);
1211 if (mthca_array_get(&dev
->qp_table
.qp
, mqpn
))
1214 mthca_array_set(&dev
->qp_table
.qp
, mqpn
, sqp
);
1215 spin_unlock_irq(&dev
->qp_table
.lock
);
1222 sqp
->qp
.transport
= MLX
;
1224 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1225 send_policy
, &sqp
->qp
);
1229 atomic_inc(&pd
->sqp_count
);
1235 * Lock CQs here, so that CQ polling code can do QP lookup
1236 * without taking a lock.
1238 spin_lock_irq(&send_cq
->lock
);
1239 if (send_cq
!= recv_cq
)
1240 spin_lock(&recv_cq
->lock
);
1242 spin_lock(&dev
->qp_table
.lock
);
1243 mthca_array_clear(&dev
->qp_table
.qp
, mqpn
);
1244 spin_unlock(&dev
->qp_table
.lock
);
1246 if (send_cq
!= recv_cq
)
1247 spin_unlock(&recv_cq
->lock
);
1248 spin_unlock_irq(&send_cq
->lock
);
1251 dma_free_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1252 sqp
->header_buf
, sqp
->header_dma
);
1257 void mthca_free_qp(struct mthca_dev
*dev
,
1258 struct mthca_qp
*qp
)
1261 struct mthca_cq
*send_cq
;
1262 struct mthca_cq
*recv_cq
;
1264 send_cq
= to_mcq(qp
->ibqp
.send_cq
);
1265 recv_cq
= to_mcq(qp
->ibqp
.recv_cq
);
1268 * Lock CQs here, so that CQ polling code can do QP lookup
1269 * without taking a lock.
1271 spin_lock_irq(&send_cq
->lock
);
1272 if (send_cq
!= recv_cq
)
1273 spin_lock(&recv_cq
->lock
);
1275 spin_lock(&dev
->qp_table
.lock
);
1276 mthca_array_clear(&dev
->qp_table
.qp
,
1277 qp
->qpn
& (dev
->limits
.num_qps
- 1));
1278 spin_unlock(&dev
->qp_table
.lock
);
1280 if (send_cq
!= recv_cq
)
1281 spin_unlock(&recv_cq
->lock
);
1282 spin_unlock_irq(&send_cq
->lock
);
1284 atomic_dec(&qp
->refcount
);
1285 wait_event(qp
->wait
, !atomic_read(&qp
->refcount
));
1287 if (qp
->state
!= IB_QPS_RESET
)
1288 mthca_MODIFY_QP(dev
, MTHCA_TRANS_ANY2RST
, qp
->qpn
, 0, NULL
, 0, &status
);
1291 * If this is a userspace QP, the buffers, MR, CQs and so on
1292 * will be cleaned up in userspace, so all we have to do is
1293 * unref the mem-free tables and free the QPN in our table.
1295 if (!qp
->ibqp
.uobject
) {
1296 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.send_cq
)->cqn
, qp
->qpn
,
1297 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
1298 if (qp
->ibqp
.send_cq
!= qp
->ibqp
.recv_cq
)
1299 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.recv_cq
)->cqn
, qp
->qpn
,
1300 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
1302 mthca_free_memfree(dev
, qp
);
1303 mthca_free_wqe_buf(dev
, qp
);
1306 mthca_unmap_memfree(dev
, qp
);
1308 if (is_sqp(dev
, qp
)) {
1309 atomic_dec(&(to_mpd(qp
->ibqp
.pd
)->sqp_count
));
1310 dma_free_coherent(&dev
->pdev
->dev
,
1311 to_msqp(qp
)->header_buf_size
,
1312 to_msqp(qp
)->header_buf
,
1313 to_msqp(qp
)->header_dma
);
1315 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1318 /* Create UD header for an MLX send and build a data segment for it */
1319 static int build_mlx_header(struct mthca_dev
*dev
, struct mthca_sqp
*sqp
,
1320 int ind
, struct ib_send_wr
*wr
,
1321 struct mthca_mlx_seg
*mlx
,
1322 struct mthca_data_seg
*data
)
1328 ib_ud_header_init(256, /* assume a MAD */
1329 sqp
->ud_header
.grh_present
,
1332 err
= mthca_read_ah(dev
, to_mah(wr
->wr
.ud
.ah
), &sqp
->ud_header
);
1335 mlx
->flags
&= ~cpu_to_be32(MTHCA_NEXT_SOLICIT
| 1);
1336 mlx
->flags
|= cpu_to_be32((!sqp
->qp
.ibqp
.qp_num
? MTHCA_MLX_VL15
: 0) |
1337 (sqp
->ud_header
.lrh
.destination_lid
==
1338 IB_LID_PERMISSIVE
? MTHCA_MLX_SLR
: 0) |
1339 (sqp
->ud_header
.lrh
.service_level
<< 8));
1340 mlx
->rlid
= sqp
->ud_header
.lrh
.destination_lid
;
1343 switch (wr
->opcode
) {
1345 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY
;
1346 sqp
->ud_header
.immediate_present
= 0;
1348 case IB_WR_SEND_WITH_IMM
:
1349 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE
;
1350 sqp
->ud_header
.immediate_present
= 1;
1351 sqp
->ud_header
.immediate_data
= wr
->imm_data
;
1357 sqp
->ud_header
.lrh
.virtual_lane
= !sqp
->qp
.ibqp
.qp_num
? 15 : 0;
1358 if (sqp
->ud_header
.lrh
.destination_lid
== IB_LID_PERMISSIVE
)
1359 sqp
->ud_header
.lrh
.source_lid
= IB_LID_PERMISSIVE
;
1360 sqp
->ud_header
.bth
.solicited_event
= !!(wr
->send_flags
& IB_SEND_SOLICITED
);
1361 if (!sqp
->qp
.ibqp
.qp_num
)
1362 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->port
,
1363 sqp
->pkey_index
, &pkey
);
1365 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->port
,
1366 wr
->wr
.ud
.pkey_index
, &pkey
);
1367 sqp
->ud_header
.bth
.pkey
= cpu_to_be16(pkey
);
1368 sqp
->ud_header
.bth
.destination_qpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1369 sqp
->ud_header
.bth
.psn
= cpu_to_be32((sqp
->send_psn
++) & ((1 << 24) - 1));
1370 sqp
->ud_header
.deth
.qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
& 0x80000000 ?
1371 sqp
->qkey
: wr
->wr
.ud
.remote_qkey
);
1372 sqp
->ud_header
.deth
.source_qpn
= cpu_to_be32(sqp
->qp
.ibqp
.qp_num
);
1374 header_size
= ib_ud_header_pack(&sqp
->ud_header
,
1376 ind
* MTHCA_UD_HEADER_SIZE
);
1378 data
->byte_count
= cpu_to_be32(header_size
);
1379 data
->lkey
= cpu_to_be32(to_mpd(sqp
->qp
.ibqp
.pd
)->ntmr
.ibmr
.lkey
);
1380 data
->addr
= cpu_to_be64(sqp
->header_dma
+
1381 ind
* MTHCA_UD_HEADER_SIZE
);
1386 static inline int mthca_wq_overflow(struct mthca_wq
*wq
, int nreq
,
1387 struct ib_cq
*ib_cq
)
1390 struct mthca_cq
*cq
;
1392 cur
= wq
->head
- wq
->tail
;
1393 if (likely(cur
+ nreq
< wq
->max
))
1397 spin_lock(&cq
->lock
);
1398 cur
= wq
->head
- wq
->tail
;
1399 spin_unlock(&cq
->lock
);
1401 return cur
+ nreq
>= wq
->max
;
1404 int mthca_tavor_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1405 struct ib_send_wr
**bad_wr
)
1407 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1408 struct mthca_qp
*qp
= to_mqp(ibqp
);
1411 unsigned long flags
;
1421 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1423 /* XXX check that state is OK to post send */
1425 ind
= qp
->sq
.next_ind
;
1427 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1428 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1429 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1430 " %d max, %d nreq)\n", qp
->qpn
,
1431 qp
->sq
.head
, qp
->sq
.tail
,
1438 wqe
= get_send_wqe(qp
, ind
);
1439 prev_wqe
= qp
->sq
.last
;
1442 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1443 ((struct mthca_next_seg
*) wqe
)->ee_nds
= 0;
1444 ((struct mthca_next_seg
*) wqe
)->flags
=
1445 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
1446 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
1447 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
1448 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
1450 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
1451 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
1452 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
1454 wqe
+= sizeof (struct mthca_next_seg
);
1455 size
= sizeof (struct mthca_next_seg
) / 16;
1457 switch (qp
->transport
) {
1459 switch (wr
->opcode
) {
1460 case IB_WR_ATOMIC_CMP_AND_SWP
:
1461 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1462 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1463 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
1464 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1465 cpu_to_be32(wr
->wr
.atomic
.rkey
);
1466 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1468 wqe
+= sizeof (struct mthca_raddr_seg
);
1470 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1471 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1472 cpu_to_be64(wr
->wr
.atomic
.swap
);
1473 ((struct mthca_atomic_seg
*) wqe
)->compare
=
1474 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1476 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1477 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1478 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
1481 wqe
+= sizeof (struct mthca_atomic_seg
);
1482 size
+= sizeof (struct mthca_raddr_seg
) / 16 +
1483 sizeof (struct mthca_atomic_seg
);
1486 case IB_WR_RDMA_WRITE
:
1487 case IB_WR_RDMA_WRITE_WITH_IMM
:
1488 case IB_WR_RDMA_READ
:
1489 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1490 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1491 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1492 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1493 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1494 wqe
+= sizeof (struct mthca_raddr_seg
);
1495 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1499 /* No extra segments required for sends */
1506 switch (wr
->opcode
) {
1507 case IB_WR_RDMA_WRITE
:
1508 case IB_WR_RDMA_WRITE_WITH_IMM
:
1509 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1510 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1511 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1512 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1513 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1514 wqe
+= sizeof (struct mthca_raddr_seg
);
1515 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1519 /* No extra segments required for sends */
1526 ((struct mthca_tavor_ud_seg
*) wqe
)->lkey
=
1527 cpu_to_be32(to_mah(wr
->wr
.ud
.ah
)->key
);
1528 ((struct mthca_tavor_ud_seg
*) wqe
)->av_addr
=
1529 cpu_to_be64(to_mah(wr
->wr
.ud
.ah
)->avdma
);
1530 ((struct mthca_tavor_ud_seg
*) wqe
)->dqpn
=
1531 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1532 ((struct mthca_tavor_ud_seg
*) wqe
)->qkey
=
1533 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1535 wqe
+= sizeof (struct mthca_tavor_ud_seg
);
1536 size
+= sizeof (struct mthca_tavor_ud_seg
) / 16;
1540 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
1541 wqe
- sizeof (struct mthca_next_seg
),
1547 wqe
+= sizeof (struct mthca_data_seg
);
1548 size
+= sizeof (struct mthca_data_seg
) / 16;
1552 if (wr
->num_sge
> qp
->sq
.max_gs
) {
1553 mthca_err(dev
, "too many gathers\n");
1559 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1560 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1561 cpu_to_be32(wr
->sg_list
[i
].length
);
1562 ((struct mthca_data_seg
*) wqe
)->lkey
=
1563 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1564 ((struct mthca_data_seg
*) wqe
)->addr
=
1565 cpu_to_be64(wr
->sg_list
[i
].addr
);
1566 wqe
+= sizeof (struct mthca_data_seg
);
1567 size
+= sizeof (struct mthca_data_seg
) / 16;
1570 /* Add one more inline data segment for ICRC */
1571 if (qp
->transport
== MLX
) {
1572 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1573 cpu_to_be32((1 << 31) | 4);
1574 ((u32
*) wqe
)[1] = 0;
1575 wqe
+= sizeof (struct mthca_data_seg
);
1576 size
+= sizeof (struct mthca_data_seg
) / 16;
1579 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
1581 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
1582 mthca_err(dev
, "opcode invalid\n");
1588 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1589 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
1590 qp
->send_wqe_offset
) |
1591 mthca_opcode
[wr
->opcode
]);
1593 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1594 cpu_to_be32((size0
? 0 : MTHCA_NEXT_DBD
) | size
);
1598 op0
= mthca_opcode
[wr
->opcode
];
1602 if (unlikely(ind
>= qp
->sq
.max
))
1610 doorbell
[0] = cpu_to_be32(((qp
->sq
.next_ind
<< qp
->sq
.wqe_shift
) +
1611 qp
->send_wqe_offset
) | f0
| op0
);
1612 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
1616 mthca_write64(doorbell
,
1617 dev
->kar
+ MTHCA_SEND_DOORBELL
,
1618 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1621 qp
->sq
.next_ind
= ind
;
1622 qp
->sq
.head
+= nreq
;
1624 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
1628 int mthca_tavor_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
1629 struct ib_recv_wr
**bad_wr
)
1631 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1632 struct mthca_qp
*qp
= to_mqp(ibqp
);
1633 unsigned long flags
;
1643 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
1645 /* XXX check that state is OK to post receive */
1647 ind
= qp
->rq
.next_ind
;
1649 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1650 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
1651 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
1652 " %d max, %d nreq)\n", qp
->qpn
,
1653 qp
->rq
.head
, qp
->rq
.tail
,
1660 wqe
= get_recv_wqe(qp
, ind
);
1661 prev_wqe
= qp
->rq
.last
;
1664 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1665 ((struct mthca_next_seg
*) wqe
)->ee_nds
=
1666 cpu_to_be32(MTHCA_NEXT_DBD
);
1667 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
1669 wqe
+= sizeof (struct mthca_next_seg
);
1670 size
= sizeof (struct mthca_next_seg
) / 16;
1672 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
1678 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1679 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1680 cpu_to_be32(wr
->sg_list
[i
].length
);
1681 ((struct mthca_data_seg
*) wqe
)->lkey
=
1682 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1683 ((struct mthca_data_seg
*) wqe
)->addr
=
1684 cpu_to_be64(wr
->sg_list
[i
].addr
);
1685 wqe
+= sizeof (struct mthca_data_seg
);
1686 size
+= sizeof (struct mthca_data_seg
) / 16;
1689 qp
->wrid
[ind
] = wr
->wr_id
;
1691 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1692 cpu_to_be32((ind
<< qp
->rq
.wqe_shift
) | 1);
1694 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1695 cpu_to_be32(MTHCA_NEXT_DBD
| size
);
1701 if (unlikely(ind
>= qp
->rq
.max
))
1709 doorbell
[0] = cpu_to_be32((qp
->rq
.next_ind
<< qp
->rq
.wqe_shift
) | size0
);
1710 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | nreq
);
1714 mthca_write64(doorbell
,
1715 dev
->kar
+ MTHCA_RECEIVE_DOORBELL
,
1716 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1719 qp
->rq
.next_ind
= ind
;
1720 qp
->rq
.head
+= nreq
;
1722 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
1726 int mthca_arbel_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1727 struct ib_send_wr
**bad_wr
)
1729 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1730 struct mthca_qp
*qp
= to_mqp(ibqp
);
1733 unsigned long flags
;
1743 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1745 /* XXX check that state is OK to post send */
1747 ind
= qp
->sq
.head
& (qp
->sq
.max
- 1);
1749 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1750 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1751 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1752 " %d max, %d nreq)\n", qp
->qpn
,
1753 qp
->sq
.head
, qp
->sq
.tail
,
1760 wqe
= get_send_wqe(qp
, ind
);
1761 prev_wqe
= qp
->sq
.last
;
1764 ((struct mthca_next_seg
*) wqe
)->flags
=
1765 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
1766 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
1767 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
1768 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
1770 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
1771 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
1772 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
1774 wqe
+= sizeof (struct mthca_next_seg
);
1775 size
= sizeof (struct mthca_next_seg
) / 16;
1777 switch (qp
->transport
) {
1779 switch (wr
->opcode
) {
1780 case IB_WR_ATOMIC_CMP_AND_SWP
:
1781 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1782 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1783 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
1784 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1785 cpu_to_be32(wr
->wr
.atomic
.rkey
);
1786 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1788 wqe
+= sizeof (struct mthca_raddr_seg
);
1790 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1791 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1792 cpu_to_be64(wr
->wr
.atomic
.swap
);
1793 ((struct mthca_atomic_seg
*) wqe
)->compare
=
1794 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1796 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1797 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1798 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
1801 wqe
+= sizeof (struct mthca_atomic_seg
);
1802 size
+= sizeof (struct mthca_raddr_seg
) / 16 +
1803 sizeof (struct mthca_atomic_seg
);
1806 case IB_WR_RDMA_READ
:
1807 case IB_WR_RDMA_WRITE
:
1808 case IB_WR_RDMA_WRITE_WITH_IMM
:
1809 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1810 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1811 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1812 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1813 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1814 wqe
+= sizeof (struct mthca_raddr_seg
);
1815 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1819 /* No extra segments required for sends */
1826 switch (wr
->opcode
) {
1827 case IB_WR_RDMA_WRITE
:
1828 case IB_WR_RDMA_WRITE_WITH_IMM
:
1829 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1830 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1831 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1832 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1833 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1834 wqe
+= sizeof (struct mthca_raddr_seg
);
1835 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1839 /* No extra segments required for sends */
1846 memcpy(((struct mthca_arbel_ud_seg
*) wqe
)->av
,
1847 to_mah(wr
->wr
.ud
.ah
)->av
, MTHCA_AV_SIZE
);
1848 ((struct mthca_arbel_ud_seg
*) wqe
)->dqpn
=
1849 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1850 ((struct mthca_arbel_ud_seg
*) wqe
)->qkey
=
1851 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1853 wqe
+= sizeof (struct mthca_arbel_ud_seg
);
1854 size
+= sizeof (struct mthca_arbel_ud_seg
) / 16;
1858 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
1859 wqe
- sizeof (struct mthca_next_seg
),
1865 wqe
+= sizeof (struct mthca_data_seg
);
1866 size
+= sizeof (struct mthca_data_seg
) / 16;
1870 if (wr
->num_sge
> qp
->sq
.max_gs
) {
1871 mthca_err(dev
, "too many gathers\n");
1877 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1878 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1879 cpu_to_be32(wr
->sg_list
[i
].length
);
1880 ((struct mthca_data_seg
*) wqe
)->lkey
=
1881 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1882 ((struct mthca_data_seg
*) wqe
)->addr
=
1883 cpu_to_be64(wr
->sg_list
[i
].addr
);
1884 wqe
+= sizeof (struct mthca_data_seg
);
1885 size
+= sizeof (struct mthca_data_seg
) / 16;
1888 /* Add one more inline data segment for ICRC */
1889 if (qp
->transport
== MLX
) {
1890 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1891 cpu_to_be32((1 << 31) | 4);
1892 ((u32
*) wqe
)[1] = 0;
1893 wqe
+= sizeof (struct mthca_data_seg
);
1894 size
+= sizeof (struct mthca_data_seg
) / 16;
1897 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
1899 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
1900 mthca_err(dev
, "opcode invalid\n");
1906 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1907 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
1908 qp
->send_wqe_offset
) |
1909 mthca_opcode
[wr
->opcode
]);
1911 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1912 cpu_to_be32(MTHCA_NEXT_DBD
| size
);
1916 op0
= mthca_opcode
[wr
->opcode
];
1920 if (unlikely(ind
>= qp
->sq
.max
))
1928 doorbell
[0] = cpu_to_be32((nreq
<< 24) |
1929 ((qp
->sq
.head
& 0xffff) << 8) |
1931 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
1933 qp
->sq
.head
+= nreq
;
1936 * Make sure that descriptors are written before
1940 *qp
->sq
.db
= cpu_to_be32(qp
->sq
.head
& 0xffff);
1943 * Make sure doorbell record is written before we
1944 * write MMIO send doorbell.
1947 mthca_write64(doorbell
,
1948 dev
->kar
+ MTHCA_SEND_DOORBELL
,
1949 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1952 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
1956 int mthca_arbel_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
1957 struct ib_recv_wr
**bad_wr
)
1959 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1960 struct mthca_qp
*qp
= to_mqp(ibqp
);
1961 unsigned long flags
;
1968 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
1970 /* XXX check that state is OK to post receive */
1972 ind
= qp
->rq
.head
& (qp
->rq
.max
- 1);
1974 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1975 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
1976 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
1977 " %d max, %d nreq)\n", qp
->qpn
,
1978 qp
->rq
.head
, qp
->rq
.tail
,
1985 wqe
= get_recv_wqe(qp
, ind
);
1987 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
1989 wqe
+= sizeof (struct mthca_next_seg
);
1991 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
1997 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1998 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1999 cpu_to_be32(wr
->sg_list
[i
].length
);
2000 ((struct mthca_data_seg
*) wqe
)->lkey
=
2001 cpu_to_be32(wr
->sg_list
[i
].lkey
);
2002 ((struct mthca_data_seg
*) wqe
)->addr
=
2003 cpu_to_be64(wr
->sg_list
[i
].addr
);
2004 wqe
+= sizeof (struct mthca_data_seg
);
2007 if (i
< qp
->rq
.max_gs
) {
2008 ((struct mthca_data_seg
*) wqe
)->byte_count
= 0;
2009 ((struct mthca_data_seg
*) wqe
)->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
2010 ((struct mthca_data_seg
*) wqe
)->addr
= 0;
2013 qp
->wrid
[ind
] = wr
->wr_id
;
2016 if (unlikely(ind
>= qp
->rq
.max
))
2021 qp
->rq
.head
+= nreq
;
2024 * Make sure that descriptors are written before
2028 *qp
->rq
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
2031 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
2035 int mthca_free_err_wqe(struct mthca_dev
*dev
, struct mthca_qp
*qp
, int is_send
,
2036 int index
, int *dbd
, __be32
*new_wqe
)
2038 struct mthca_next_seg
*next
;
2041 * For SRQs, all WQEs generate a CQE, so we're always at the
2042 * end of the doorbell chain.
2050 next
= get_send_wqe(qp
, index
);
2052 next
= get_recv_wqe(qp
, index
);
2054 *dbd
= !!(next
->ee_nds
& cpu_to_be32(MTHCA_NEXT_DBD
));
2055 if (next
->ee_nds
& cpu_to_be32(0x3f))
2056 *new_wqe
= (next
->nda_op
& cpu_to_be32(~0x3f)) |
2057 (next
->ee_nds
& cpu_to_be32(0x3f));
2064 int __devinit
mthca_init_qp_table(struct mthca_dev
*dev
)
2070 spin_lock_init(&dev
->qp_table
.lock
);
2073 * We reserve 2 extra QPs per port for the special QPs. The
2074 * special QP for port 1 has to be even, so round up.
2076 dev
->qp_table
.sqp_start
= (dev
->limits
.reserved_qps
+ 1) & ~1UL;
2077 err
= mthca_alloc_init(&dev
->qp_table
.alloc
,
2078 dev
->limits
.num_qps
,
2080 dev
->qp_table
.sqp_start
+
2081 MTHCA_MAX_PORTS
* 2);
2085 err
= mthca_array_init(&dev
->qp_table
.qp
,
2086 dev
->limits
.num_qps
);
2088 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2092 for (i
= 0; i
< 2; ++i
) {
2093 err
= mthca_CONF_SPECIAL_QP(dev
, i
? IB_QPT_GSI
: IB_QPT_SMI
,
2094 dev
->qp_table
.sqp_start
+ i
* 2,
2099 mthca_warn(dev
, "CONF_SPECIAL_QP returned "
2100 "status %02x, aborting.\n",
2109 for (i
= 0; i
< 2; ++i
)
2110 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2112 mthca_array_cleanup(&dev
->qp_table
.qp
, dev
->limits
.num_qps
);
2113 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2118 void __devexit
mthca_cleanup_qp_table(struct mthca_dev
*dev
)
2123 for (i
= 0; i
< 2; ++i
)
2124 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2126 mthca_array_cleanup(&dev
->qp_table
.qp
, dev
->limits
.num_qps
);
2127 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);