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mmc: tmio_mmc: handle missing HW interrupts
[linux-2.6/libata-dev.git] / drivers / mmc / host / tmio_mmc.c
blob689a3692242eddad16df2cf90e712f66e6a35471
1 /*
2 * linux/drivers/mmc/tmio_mmc.c
3 *
4 * Copyright (C) 2004 Ian Molton
5 * Copyright (C) 2007 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Driver for the MMC / SD / SDIO cell found in:
12 *
13 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
14 *
15 * This driver draws mainly on scattered spec sheets, Reverse engineering
16 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
17 * support). (Further 4 bit support from a later datasheet).
18 *
19 * TODO:
20 * Investigate using a workqueue for PIO transfers
21 * Eliminate FIXMEs
22 * SDIO support
23 * Better Power management
24 * Handle MMC errors better
25 * double buffer support
26 *
27 */
28
29 #include <linux/delay.h>
30 #include <linux/device.h>
31 #include <linux/dmaengine.h>
32 #include <linux/highmem.h>
33 #include <linux/interrupt.h>
34 #include <linux/io.h>
35 #include <linux/irq.h>
36 #include <linux/mfd/core.h>
37 #include <linux/mfd/tmio.h>
38 #include <linux/mmc/host.h>
39 #include <linux/module.h>
40 #include <linux/pagemap.h>
41 #include <linux/scatterlist.h>
42 #include <linux/workqueue.h>
43 #include <linux/spinlock.h>
44
45 #define CTL_SD_CMD 0x00
46 #define CTL_ARG_REG 0x04
47 #define CTL_STOP_INTERNAL_ACTION 0x08
48 #define CTL_XFER_BLK_COUNT 0xa
49 #define CTL_RESPONSE 0x0c
50 #define CTL_STATUS 0x1c
51 #define CTL_IRQ_MASK 0x20
52 #define CTL_SD_CARD_CLK_CTL 0x24
53 #define CTL_SD_XFER_LEN 0x26
54 #define CTL_SD_MEM_CARD_OPT 0x28
55 #define CTL_SD_ERROR_DETAIL_STATUS 0x2c
56 #define CTL_SD_DATA_PORT 0x30
57 #define CTL_TRANSACTION_CTL 0x34
58 #define CTL_SDIO_STATUS 0x36
59 #define CTL_SDIO_IRQ_MASK 0x38
60 #define CTL_RESET_SD 0xe0
61 #define CTL_SDIO_REGS 0x100
62 #define CTL_CLK_AND_WAIT_CTL 0x138
63 #define CTL_RESET_SDIO 0x1e0
64
65 /* Definitions for values the CTRL_STATUS register can take. */
66 #define TMIO_STAT_CMDRESPEND 0x00000001
67 #define TMIO_STAT_DATAEND 0x00000004
68 #define TMIO_STAT_CARD_REMOVE 0x00000008
69 #define TMIO_STAT_CARD_INSERT 0x00000010
70 #define TMIO_STAT_SIGSTATE 0x00000020
71 #define TMIO_STAT_WRPROTECT 0x00000080
72 #define TMIO_STAT_CARD_REMOVE_A 0x00000100
73 #define TMIO_STAT_CARD_INSERT_A 0x00000200
74 #define TMIO_STAT_SIGSTATE_A 0x00000400
75 #define TMIO_STAT_CMD_IDX_ERR 0x00010000
76 #define TMIO_STAT_CRCFAIL 0x00020000
77 #define TMIO_STAT_STOPBIT_ERR 0x00040000
78 #define TMIO_STAT_DATATIMEOUT 0x00080000
79 #define TMIO_STAT_RXOVERFLOW 0x00100000
80 #define TMIO_STAT_TXUNDERRUN 0x00200000
81 #define TMIO_STAT_CMDTIMEOUT 0x00400000
82 #define TMIO_STAT_RXRDY 0x01000000
83 #define TMIO_STAT_TXRQ 0x02000000
84 #define TMIO_STAT_ILL_FUNC 0x20000000
85 #define TMIO_STAT_CMD_BUSY 0x40000000
86 #define TMIO_STAT_ILL_ACCESS 0x80000000
87
88 /* Definitions for values the CTRL_SDIO_STATUS register can take. */
89 #define TMIO_SDIO_STAT_IOIRQ 0x0001
90 #define TMIO_SDIO_STAT_EXPUB52 0x4000
91 #define TMIO_SDIO_STAT_EXWT 0x8000
92 #define TMIO_SDIO_MASK_ALL 0xc007
93
94 /* Define some IRQ masks */
95 /* This is the mask used at reset by the chip */
96 #define TMIO_MASK_ALL 0x837f031d
97 #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
98 #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
99 #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
100 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
101 #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
102
103 #define enable_mmc_irqs(host, i) \
104 do { \
105 u32 mask;\
106 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \
107 mask &= ~((i) & TMIO_MASK_IRQ); \
108 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
109 } while (0)
110
111 #define disable_mmc_irqs(host, i) \
112 do { \
113 u32 mask;\
114 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \
115 mask |= ((i) & TMIO_MASK_IRQ); \
116 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
117 } while (0)
118
119 #define ack_mmc_irqs(host, i) \
120 do { \
121 sd_ctrl_write32((host), CTL_STATUS, ~(i)); \
122 } while (0)
123
124 /* This is arbitrary, just noone needed any higher alignment yet */
125 #define MAX_ALIGN 4
126
127 struct tmio_mmc_host {
128 void __iomem *ctl;
129 unsigned long bus_shift;
130 struct mmc_command *cmd;
131 struct mmc_request *mrq;
132 struct mmc_data *data;
133 struct mmc_host *mmc;
134 int irq;
135 unsigned int sdio_irq_enabled;
136
137 /* Callbacks for clock / power control */
138 void (*set_pwr)(struct platform_device *host, int state);
139 void (*set_clk_div)(struct platform_device *host, int state);
140
141 /* pio related stuff */
142 struct scatterlist *sg_ptr;
143 struct scatterlist *sg_orig;
144 unsigned int sg_len;
145 unsigned int sg_off;
146
147 struct platform_device *pdev;
148
149 /* DMA support */
150 struct dma_chan *chan_rx;
151 struct dma_chan *chan_tx;
152 struct tasklet_struct dma_complete;
153 struct tasklet_struct dma_issue;
154 #ifdef CONFIG_TMIO_MMC_DMA
155 unsigned int dma_sglen;
156 u8 bounce_buf[PAGE_CACHE_SIZE] __attribute__((aligned(MAX_ALIGN)));
157 struct scatterlist bounce_sg;
158 #endif
159
160 /* Track lost interrupts */
161 struct delayed_work delayed_reset_work;
162 spinlock_t lock;
163 unsigned long last_req_ts;
164 };
165
166 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host);
167
168 static u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
169 {
170 return readw(host->ctl + (addr << host->bus_shift));
171 }
172
173 static void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
174 u16 *buf, int count)
175 {
176 readsw(host->ctl + (addr << host->bus_shift), buf, count);
177 }
178
179 static u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)
180 {
181 return readw(host->ctl + (addr << host->bus_shift)) |
182 readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
183 }
184
185 static void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
186 {
187 writew(val, host->ctl + (addr << host->bus_shift));
188 }
189
190 static void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
191 u16 *buf, int count)
192 {
193 writesw(host->ctl + (addr << host->bus_shift), buf, count);
194 }
195
196 static void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
197 {
198 writew(val, host->ctl + (addr << host->bus_shift));
199 writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
200 }
201
202 static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
203 {
204 host->sg_len = data->sg_len;
205 host->sg_ptr = data->sg;
206 host->sg_orig = data->sg;
207 host->sg_off = 0;
208 }
209
210 static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
211 {
212 host->sg_ptr = sg_next(host->sg_ptr);
213 host->sg_off = 0;
214 return --host->sg_len;
215 }
216
217 static char *tmio_mmc_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
218 {
219 local_irq_save(*flags);
220 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
221 }
222
223 static void tmio_mmc_kunmap_atomic(void *virt, unsigned long *flags)
224 {
225 kunmap_atomic(virt, KM_BIO_SRC_IRQ);
226 local_irq_restore(*flags);
227 }
228
229 #ifdef CONFIG_MMC_DEBUG
230
231 #define STATUS_TO_TEXT(a) \
232 do { \
233 if (status & TMIO_STAT_##a) \
234 printk(#a); \
235 } while (0)
236
237 void pr_debug_status(u32 status)
238 {
239 printk(KERN_DEBUG "status: %08x = ", status);
240 STATUS_TO_TEXT(CARD_REMOVE);
241 STATUS_TO_TEXT(CARD_INSERT);
242 STATUS_TO_TEXT(SIGSTATE);
243 STATUS_TO_TEXT(WRPROTECT);
244 STATUS_TO_TEXT(CARD_REMOVE_A);
245 STATUS_TO_TEXT(CARD_INSERT_A);
246 STATUS_TO_TEXT(SIGSTATE_A);
247 STATUS_TO_TEXT(CMD_IDX_ERR);
248 STATUS_TO_TEXT(STOPBIT_ERR);
249 STATUS_TO_TEXT(ILL_FUNC);
250 STATUS_TO_TEXT(CMD_BUSY);
251 STATUS_TO_TEXT(CMDRESPEND);
252 STATUS_TO_TEXT(DATAEND);
253 STATUS_TO_TEXT(CRCFAIL);
254 STATUS_TO_TEXT(DATATIMEOUT);
255 STATUS_TO_TEXT(CMDTIMEOUT);
256 STATUS_TO_TEXT(RXOVERFLOW);
257 STATUS_TO_TEXT(TXUNDERRUN);
258 STATUS_TO_TEXT(RXRDY);
259 STATUS_TO_TEXT(TXRQ);
260 STATUS_TO_TEXT(ILL_ACCESS);
261 printk("\n");
262 }
263
264 #else
265 #define pr_debug_status(s) do { } while (0)
266 #endif
267
268 static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
269 {
270 struct tmio_mmc_host *host = mmc_priv(mmc);
271
272 if (enable) {
273 host->sdio_irq_enabled = 1;
274 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
275 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK,
276 (TMIO_SDIO_MASK_ALL & ~TMIO_SDIO_STAT_IOIRQ));
277 } else {
278 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, TMIO_SDIO_MASK_ALL);
279 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
280 host->sdio_irq_enabled = 0;
281 }
282 }
283
284 static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
285 {
286 u32 clk = 0, clock;
287
288 if (new_clock) {
289 for (clock = host->mmc->f_min, clk = 0x80000080;
290 new_clock >= (clock<<1); clk >>= 1)
291 clock <<= 1;
292 clk |= 0x100;
293 }
294
295 if (host->set_clk_div)
296 host->set_clk_div(host->pdev, (clk>>22) & 1);
297
298 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
299 }
300
301 static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
302 {
303 struct mfd_cell *cell = host->pdev->dev.platform_data;
304 struct tmio_mmc_data *pdata = cell->driver_data;
305
306 /*
307 * Testing on sh-mobile showed that SDIO IRQs are unmasked when
308 * CTL_CLK_AND_WAIT_CTL gets written, so we have to disable the
309 * device IRQ here and restore the SDIO IRQ mask before
310 * re-enabling the device IRQ.
311 */
312 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
313 disable_irq(host->irq);
314 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
315 msleep(10);
316 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
317 tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled);
318 enable_irq(host->irq);
319 }
320 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
321 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
322 msleep(10);
323 }
324
325 static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
326 {
327 struct mfd_cell *cell = host->pdev->dev.platform_data;
328 struct tmio_mmc_data *pdata = cell->driver_data;
329
330 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
331 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
332 msleep(10);
333 /* see comment in tmio_mmc_clk_stop above */
334 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
335 disable_irq(host->irq);
336 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
337 msleep(10);
338 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
339 tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled);
340 enable_irq(host->irq);
341 }
342 }
343
344 static void reset(struct tmio_mmc_host *host)
345 {
346 /* FIXME - should we set stop clock reg here */
347 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
348 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
349 msleep(10);
350 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
351 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
352 msleep(10);
353 }
354
355 static void tmio_mmc_reset_work(struct work_struct *work)
356 {
357 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
358 delayed_reset_work.work);
359 struct mmc_request *mrq;
360 unsigned long flags;
361
362 spin_lock_irqsave(&host->lock, flags);
363 mrq = host->mrq;
364
365 /* request already finished */
366 if (!mrq
367 || time_is_after_jiffies(host->last_req_ts +
368 msecs_to_jiffies(2000))) {
369 spin_unlock_irqrestore(&host->lock, flags);
370 return;
371 }
372
373 dev_warn(&host->pdev->dev,
374 "timeout waiting for hardware interrupt (CMD%u)\n",
375 mrq->cmd->opcode);
376
377 if (host->data)
378 host->data->error = -ETIMEDOUT;
379 else if (host->cmd)
380 host->cmd->error = -ETIMEDOUT;
381 else
382 mrq->cmd->error = -ETIMEDOUT;
383
384 host->cmd = NULL;
385 host->data = NULL;
386 host->mrq = NULL;
387
388 spin_unlock_irqrestore(&host->lock, flags);
389
390 reset(host);
391
392 mmc_request_done(host->mmc, mrq);
393 }
394
395 static void
396 tmio_mmc_finish_request(struct tmio_mmc_host *host)
397 {
398 struct mmc_request *mrq = host->mrq;
399
400 if (!mrq)
401 return;
402
403 host->mrq = NULL;
404 host->cmd = NULL;
405 host->data = NULL;
406
407 cancel_delayed_work(&host->delayed_reset_work);
408
409 mmc_request_done(host->mmc, mrq);
410 }
411
412 /* These are the bitmasks the tmio chip requires to implement the MMC response
413 * types. Note that R1 and R6 are the same in this scheme. */
414 #define APP_CMD 0x0040
415 #define RESP_NONE 0x0300
416 #define RESP_R1 0x0400
417 #define RESP_R1B 0x0500
418 #define RESP_R2 0x0600
419 #define RESP_R3 0x0700
420 #define DATA_PRESENT 0x0800
421 #define TRANSFER_READ 0x1000
422 #define TRANSFER_MULTI 0x2000
423 #define SECURITY_CMD 0x4000
424
425 static int
426 tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
427 {
428 struct mmc_data *data = host->data;
429 int c = cmd->opcode;
430
431 /* Command 12 is handled by hardware */
432 if (cmd->opcode == 12 && !cmd->arg) {
433 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
434 return 0;
435 }
436
437 switch (mmc_resp_type(cmd)) {
438 case MMC_RSP_NONE: c |= RESP_NONE; break;
439 case MMC_RSP_R1: c |= RESP_R1; break;
440 case MMC_RSP_R1B: c |= RESP_R1B; break;
441 case MMC_RSP_R2: c |= RESP_R2; break;
442 case MMC_RSP_R3: c |= RESP_R3; break;
443 default:
444 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
445 return -EINVAL;
446 }
447
448 host->cmd = cmd;
449
450 /* FIXME - this seems to be ok commented out but the spec suggest this bit
451 * should be set when issuing app commands.
452 * if(cmd->flags & MMC_FLAG_ACMD)
453 * c |= APP_CMD;
454 */
455 if (data) {
456 c |= DATA_PRESENT;
457 if (data->blocks > 1) {
458 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
459 c |= TRANSFER_MULTI;
460 }
461 if (data->flags & MMC_DATA_READ)
462 c |= TRANSFER_READ;
463 }
464
465 enable_mmc_irqs(host, TMIO_MASK_CMD);
466
467 /* Fire off the command */
468 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
469 sd_ctrl_write16(host, CTL_SD_CMD, c);
470
471 return 0;
472 }
473
474 /*
475 * This chip always returns (at least?) as much data as you ask for.
476 * I'm unsure what happens if you ask for less than a block. This should be
477 * looked into to ensure that a funny length read doesnt hose the controller.
478 */
479 static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
480 {
481 struct mmc_data *data = host->data;
482 void *sg_virt;
483 unsigned short *buf;
484 unsigned int count;
485 unsigned long flags;
486
487 if (!data) {
488 pr_debug("Spurious PIO IRQ\n");
489 return;
490 }
491
492 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
493 buf = (unsigned short *)(sg_virt + host->sg_off);
494
495 count = host->sg_ptr->length - host->sg_off;
496 if (count > data->blksz)
497 count = data->blksz;
498
499 pr_debug("count: %08x offset: %08x flags %08x\n",
500 count, host->sg_off, data->flags);
501
502 /* Transfer the data */
503 if (data->flags & MMC_DATA_READ)
504 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
505 else
506 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
507
508 host->sg_off += count;
509
510 tmio_mmc_kunmap_atomic(sg_virt, &flags);
511
512 if (host->sg_off == host->sg_ptr->length)
513 tmio_mmc_next_sg(host);
514
515 return;
516 }
517
518 /* needs to be called with host->lock held */
519 static void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
520 {
521 struct mmc_data *data = host->data;
522 struct mmc_command *stop;
523
524 host->data = NULL;
525
526 if (!data) {
527 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
528 return;
529 }
530 stop = data->stop;
531
532 /* FIXME - return correct transfer count on errors */
533 if (!data->error)
534 data->bytes_xfered = data->blocks * data->blksz;
535 else
536 data->bytes_xfered = 0;
537
538 pr_debug("Completed data request\n");
539
540 /*
541 * FIXME: other drivers allow an optional stop command of any given type
542 * which we dont do, as the chip can auto generate them.
543 * Perhaps we can be smarter about when to use auto CMD12 and
544 * only issue the auto request when we know this is the desired
545 * stop command, allowing fallback to the stop command the
546 * upper layers expect. For now, we do what works.
547 */
548
549 if (data->flags & MMC_DATA_READ) {
550 if (!host->chan_rx)
551 disable_mmc_irqs(host, TMIO_MASK_READOP);
552 else
553 tmio_check_bounce_buffer(host);
554 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
555 host->mrq);
556 } else {
557 if (!host->chan_tx)
558 disable_mmc_irqs(host, TMIO_MASK_WRITEOP);
559 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
560 host->mrq);
561 }
562
563 if (stop) {
564 if (stop->opcode == 12 && !stop->arg)
565 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
566 else
567 BUG();
568 }
569
570 tmio_mmc_finish_request(host);
571 }
572
573 static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
574 {
575 struct mmc_data *data;
576 spin_lock(&host->lock);
577 data = host->data;
578
579 if (!data)
580 goto out;
581
582 if (host->chan_tx && (data->flags & MMC_DATA_WRITE)) {
583 /*
584 * Has all data been written out yet? Testing on SuperH showed,
585 * that in most cases the first interrupt comes already with the
586 * BUSY status bit clear, but on some operations, like mount or
587 * in the beginning of a write / sync / umount, there is one
588 * DATAEND interrupt with the BUSY bit set, in this cases
589 * waiting for one more interrupt fixes the problem.
590 */
591 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
592 disable_mmc_irqs(host, TMIO_STAT_DATAEND);
593 tasklet_schedule(&host->dma_complete);
594 }
595 } else if (host->chan_rx && (data->flags & MMC_DATA_READ)) {
596 disable_mmc_irqs(host, TMIO_STAT_DATAEND);
597 tasklet_schedule(&host->dma_complete);
598 } else {
599 tmio_mmc_do_data_irq(host);
600 }
601 out:
602 spin_unlock(&host->lock);
603 }
604
605 static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
606 unsigned int stat)
607 {
608 struct mmc_command *cmd = host->cmd;
609 int i, addr;
610
611 spin_lock(&host->lock);
612
613 if (!host->cmd) {
614 pr_debug("Spurious CMD irq\n");
615 goto out;
616 }
617
618 host->cmd = NULL;
619
620 /* This controller is sicker than the PXA one. Not only do we need to
621 * drop the top 8 bits of the first response word, we also need to
622 * modify the order of the response for short response command types.
623 */
624
625 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
626 cmd->resp[i] = sd_ctrl_read32(host, addr);
627
628 if (cmd->flags & MMC_RSP_136) {
629 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
630 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
631 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
632 cmd->resp[3] <<= 8;
633 } else if (cmd->flags & MMC_RSP_R3) {
634 cmd->resp[0] = cmd->resp[3];
635 }
636
637 if (stat & TMIO_STAT_CMDTIMEOUT)
638 cmd->error = -ETIMEDOUT;
639 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
640 cmd->error = -EILSEQ;
641
642 /* If there is data to handle we enable data IRQs here, and
643 * we will ultimatley finish the request in the data_end handler.
644 * If theres no data or we encountered an error, finish now.
645 */
646 if (host->data && !cmd->error) {
647 if (host->data->flags & MMC_DATA_READ) {
648 if (!host->chan_rx)
649 enable_mmc_irqs(host, TMIO_MASK_READOP);
650 } else {
651 if (!host->chan_tx)
652 enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
653 else
654 tasklet_schedule(&host->dma_issue);
655 }
656 } else {
657 tmio_mmc_finish_request(host);
658 }
659
660 out:
661 spin_unlock(&host->lock);
662
663 return;
664 }
665
666 static irqreturn_t tmio_mmc_irq(int irq, void *devid)
667 {
668 struct tmio_mmc_host *host = devid;
669 struct mfd_cell *cell = host->pdev->dev.platform_data;
670 struct tmio_mmc_data *pdata = cell->driver_data;
671 unsigned int ireg, irq_mask, status;
672 unsigned int sdio_ireg, sdio_irq_mask, sdio_status;
673
674 pr_debug("MMC IRQ begin\n");
675
676 status = sd_ctrl_read32(host, CTL_STATUS);
677 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
678 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
679
680 sdio_ireg = 0;
681 if (!ireg && pdata->flags & TMIO_MMC_SDIO_IRQ) {
682 sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
683 sdio_irq_mask = sd_ctrl_read16(host, CTL_SDIO_IRQ_MASK);
684 sdio_ireg = sdio_status & TMIO_SDIO_MASK_ALL & ~sdio_irq_mask;
685
686 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status & ~TMIO_SDIO_MASK_ALL);
687
688 if (sdio_ireg && !host->sdio_irq_enabled) {
689 pr_warning("tmio_mmc: Spurious SDIO IRQ, disabling! 0x%04x 0x%04x 0x%04x\n",
690 sdio_status, sdio_irq_mask, sdio_ireg);
691 tmio_mmc_enable_sdio_irq(host->mmc, 0);
692 goto out;
693 }
694
695 if (host->mmc->caps & MMC_CAP_SDIO_IRQ &&
696 sdio_ireg & TMIO_SDIO_STAT_IOIRQ)
697 mmc_signal_sdio_irq(host->mmc);
698
699 if (sdio_ireg)
700 goto out;
701 }
702
703 pr_debug_status(status);
704 pr_debug_status(ireg);
705
706 if (!ireg) {
707 disable_mmc_irqs(host, status & ~irq_mask);
708
709 pr_warning("tmio_mmc: Spurious irq, disabling! "
710 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg);
711 pr_debug_status(status);
712
713 goto out;
714 }
715
716 while (ireg) {
717 /* Card insert / remove attempts */
718 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
719 ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
720 TMIO_STAT_CARD_REMOVE);
721 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
722 }
723
724 /* CRC and other errors */
725 /* if (ireg & TMIO_STAT_ERR_IRQ)
726 * handled |= tmio_error_irq(host, irq, stat);
727 */
728
729 /* Command completion */
730 if (ireg & TMIO_MASK_CMD) {
731 ack_mmc_irqs(host, TMIO_MASK_CMD);
732 tmio_mmc_cmd_irq(host, status);
733 }
734
735 /* Data transfer */
736 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
737 ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
738 tmio_mmc_pio_irq(host);
739 }
740
741 /* Data transfer completion */
742 if (ireg & TMIO_STAT_DATAEND) {
743 ack_mmc_irqs(host, TMIO_STAT_DATAEND);
744 tmio_mmc_data_irq(host);
745 }
746
747 /* Check status - keep going until we've handled it all */
748 status = sd_ctrl_read32(host, CTL_STATUS);
749 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
750 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
751
752 pr_debug("Status at end of loop: %08x\n", status);
753 pr_debug_status(status);
754 }
755 pr_debug("MMC IRQ end\n");
756
757 out:
758 return IRQ_HANDLED;
759 }
760
761 #ifdef CONFIG_TMIO_MMC_DMA
762 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host)
763 {
764 if (host->sg_ptr == &host->bounce_sg) {
765 unsigned long flags;
766 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
767 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
768 tmio_mmc_kunmap_atomic(sg_vaddr, &flags);
769 }
770 }
771
772 static void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable)
773 {
774 #if defined(CONFIG_SUPERH) || defined(CONFIG_ARCH_SHMOBILE)
775 /* Switch DMA mode on or off - SuperH specific? */
776 sd_ctrl_write16(host, 0xd8, enable ? 2 : 0);
777 #endif
778 }
779
780 static void tmio_dma_complete(void *arg)
781 {
782 struct tmio_mmc_host *host = arg;
783
784 dev_dbg(&host->pdev->dev, "Command completed\n");
785
786 if (!host->data)
787 dev_warn(&host->pdev->dev, "NULL data in DMA completion!\n");
788 else
789 enable_mmc_irqs(host, TMIO_STAT_DATAEND);
790 }
791
792 static void tmio_mmc_start_dma_rx(struct tmio_mmc_host *host)
793 {
794 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
795 struct dma_async_tx_descriptor *desc = NULL;
796 struct dma_chan *chan = host->chan_rx;
797 struct mfd_cell *cell = host->pdev->dev.platform_data;
798 struct tmio_mmc_data *pdata = cell->driver_data;
799 dma_cookie_t cookie;
800 int ret, i;
801 bool aligned = true, multiple = true;
802 unsigned int align = (1 << pdata->dma->alignment_shift) - 1;
803
804 for_each_sg(sg, sg_tmp, host->sg_len, i) {
805 if (sg_tmp->offset & align)
806 aligned = false;
807 if (sg_tmp->length & align) {
808 multiple = false;
809 break;
810 }
811 }
812
813 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE ||
814 align >= MAX_ALIGN)) || !multiple) {
815 ret = -EINVAL;
816 goto pio;
817 }
818
819 /* The only sg element can be unaligned, use our bounce buffer then */
820 if (!aligned) {
821 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
822 host->sg_ptr = &host->bounce_sg;
823 sg = host->sg_ptr;
824 }
825
826 ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, DMA_FROM_DEVICE);
827 if (ret > 0) {
828 host->dma_sglen = ret;
829 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
830 DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
831 }
832
833 if (desc) {
834 desc->callback = tmio_dma_complete;
835 desc->callback_param = host;
836 cookie = desc->tx_submit(desc);
837 if (cookie < 0) {
838 desc = NULL;
839 ret = cookie;
840 } else {
841 chan->device->device_issue_pending(chan);
842 }
843 }
844 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
845 __func__, host->sg_len, ret, cookie, host->mrq);
846
847 pio:
848 if (!desc) {
849 /* DMA failed, fall back to PIO */
850 if (ret >= 0)
851 ret = -EIO;
852 host->chan_rx = NULL;
853 dma_release_channel(chan);
854 /* Free the Tx channel too */
855 chan = host->chan_tx;
856 if (chan) {
857 host->chan_tx = NULL;
858 dma_release_channel(chan);
859 }
860 dev_warn(&host->pdev->dev,
861 "DMA failed: %d, falling back to PIO\n", ret);
862 tmio_mmc_enable_dma(host, false);
863 }
864
865 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
866 desc, cookie, host->sg_len);
867 }
868
869 static void tmio_mmc_start_dma_tx(struct tmio_mmc_host *host)
870 {
871 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
872 struct dma_async_tx_descriptor *desc = NULL;
873 struct dma_chan *chan = host->chan_tx;
874 struct mfd_cell *cell = host->pdev->dev.platform_data;
875 struct tmio_mmc_data *pdata = cell->driver_data;
876 dma_cookie_t cookie;
877 int ret, i;
878 bool aligned = true, multiple = true;
879 unsigned int align = (1 << pdata->dma->alignment_shift) - 1;
880
881 for_each_sg(sg, sg_tmp, host->sg_len, i) {
882 if (sg_tmp->offset & align)
883 aligned = false;
884 if (sg_tmp->length & align) {
885 multiple = false;
886 break;
887 }
888 }
889
890 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE ||
891 align >= MAX_ALIGN)) || !multiple) {
892 ret = -EINVAL;
893 goto pio;
894 }
895
896 /* The only sg element can be unaligned, use our bounce buffer then */
897 if (!aligned) {
898 unsigned long flags;
899 void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);
900 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
901 memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
902 tmio_mmc_kunmap_atomic(sg_vaddr, &flags);
903 host->sg_ptr = &host->bounce_sg;
904 sg = host->sg_ptr;
905 }
906
907 ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, DMA_TO_DEVICE);
908 if (ret > 0) {
909 host->dma_sglen = ret;
910 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
911 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
912 }
913
914 if (desc) {
915 desc->callback = tmio_dma_complete;
916 desc->callback_param = host;
917 cookie = desc->tx_submit(desc);
918 if (cookie < 0) {
919 desc = NULL;
920 ret = cookie;
921 }
922 }
923 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
924 __func__, host->sg_len, ret, cookie, host->mrq);
925
926 pio:
927 if (!desc) {
928 /* DMA failed, fall back to PIO */
929 if (ret >= 0)
930 ret = -EIO;
931 host->chan_tx = NULL;
932 dma_release_channel(chan);
933 /* Free the Rx channel too */
934 chan = host->chan_rx;
935 if (chan) {
936 host->chan_rx = NULL;
937 dma_release_channel(chan);
938 }
939 dev_warn(&host->pdev->dev,
940 "DMA failed: %d, falling back to PIO\n", ret);
941 tmio_mmc_enable_dma(host, false);
942 }
943
944 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d\n", __func__,
945 desc, cookie);
946 }
947
948 static void tmio_mmc_start_dma(struct tmio_mmc_host *host,
949 struct mmc_data *data)
950 {
951 if (data->flags & MMC_DATA_READ) {
952 if (host->chan_rx)
953 tmio_mmc_start_dma_rx(host);
954 } else {
955 if (host->chan_tx)
956 tmio_mmc_start_dma_tx(host);
957 }
958 }
959
960 static void tmio_issue_tasklet_fn(unsigned long priv)
961 {
962 struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
963 struct dma_chan *chan = host->chan_tx;
964
965 chan->device->device_issue_pending(chan);
966 }
967
968 static void tmio_tasklet_fn(unsigned long arg)
969 {
970 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
971 unsigned long flags;
972
973 spin_lock_irqsave(&host->lock, flags);
974
975 if (!host->data)
976 goto out;
977
978 if (host->data->flags & MMC_DATA_READ)
979 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->dma_sglen,
980 DMA_FROM_DEVICE);
981 else
982 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->dma_sglen,
983 DMA_TO_DEVICE);
984
985 tmio_mmc_do_data_irq(host);
986 out:
987 spin_unlock_irqrestore(&host->lock, flags);
988 }
989
990 /* It might be necessary to make filter MFD specific */
991 static bool tmio_mmc_filter(struct dma_chan *chan, void *arg)
992 {
993 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
994 chan->private = arg;
995 return true;
996 }
997
998 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
999 struct tmio_mmc_data *pdata)
1000 {
1001 /* We can only either use DMA for both Tx and Rx or not use it at all */
1002 if (pdata->dma) {
1003 dma_cap_mask_t mask;
1004
1005 dma_cap_zero(mask);
1006 dma_cap_set(DMA_SLAVE, mask);
1007
1008 host->chan_tx = dma_request_channel(mask, tmio_mmc_filter,
1009 pdata->dma->chan_priv_tx);
1010 dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
1011 host->chan_tx);
1012
1013 if (!host->chan_tx)
1014 return;
1015
1016 host->chan_rx = dma_request_channel(mask, tmio_mmc_filter,
1017 pdata->dma->chan_priv_rx);
1018 dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
1019 host->chan_rx);
1020
1021 if (!host->chan_rx) {
1022 dma_release_channel(host->chan_tx);
1023 host->chan_tx = NULL;
1024 return;
1025 }
1026
1027 tasklet_init(&host->dma_complete, tmio_tasklet_fn, (unsigned long)host);
1028 tasklet_init(&host->dma_issue, tmio_issue_tasklet_fn, (unsigned long)host);
1029
1030 tmio_mmc_enable_dma(host, true);
1031 }
1032 }
1033
1034 static void tmio_mmc_release_dma(struct tmio_mmc_host *host)
1035 {
1036 if (host->chan_tx) {
1037 struct dma_chan *chan = host->chan_tx;
1038 host->chan_tx = NULL;
1039 dma_release_channel(chan);
1040 }
1041 if (host->chan_rx) {
1042 struct dma_chan *chan = host->chan_rx;
1043 host->chan_rx = NULL;
1044 dma_release_channel(chan);
1045 }
1046 }
1047 #else
1048 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host)
1049 {
1050 }
1051
1052 static void tmio_mmc_start_dma(struct tmio_mmc_host *host,
1053 struct mmc_data *data)
1054 {
1055 }
1056
1057 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
1058 struct tmio_mmc_data *pdata)
1059 {
1060 host->chan_tx = NULL;
1061 host->chan_rx = NULL;
1062 }
1063
1064 static void tmio_mmc_release_dma(struct tmio_mmc_host *host)
1065 {
1066 }
1067 #endif
1068
1069 static int tmio_mmc_start_data(struct tmio_mmc_host *host,
1070 struct mmc_data *data)
1071 {
1072 struct mfd_cell *cell = host->pdev->dev.platform_data;
1073 struct tmio_mmc_data *pdata = cell->driver_data;
1074
1075 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
1076 data->blksz, data->blocks);
1077
1078 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
1079 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1080 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
1081
1082 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
1083 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
1084 mmc_hostname(host->mmc), data->blksz);
1085 return -EINVAL;
1086 }
1087 }
1088
1089 tmio_mmc_init_sg(host, data);
1090 host->data = data;
1091
1092 /* Set transfer length / blocksize */
1093 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
1094 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
1095
1096 tmio_mmc_start_dma(host, data);
1097
1098 return 0;
1099 }
1100
1101 /* Process requests from the MMC layer */
1102 static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
1103 {
1104 struct tmio_mmc_host *host = mmc_priv(mmc);
1105 int ret;
1106
1107 if (host->mrq)
1108 pr_debug("request not null\n");
1109
1110 host->last_req_ts = jiffies;
1111 wmb();
1112 host->mrq = mrq;
1113
1114 if (mrq->data) {
1115 ret = tmio_mmc_start_data(host, mrq->data);
1116 if (ret)
1117 goto fail;
1118 }
1119
1120 ret = tmio_mmc_start_command(host, mrq->cmd);
1121 if (!ret) {
1122 schedule_delayed_work(&host->delayed_reset_work,
1123 msecs_to_jiffies(2000));
1124 return;
1125 }
1126
1127 fail:
1128 host->mrq = NULL;
1129 mrq->cmd->error = ret;
1130 mmc_request_done(mmc, mrq);
1131 }
1132
1133 /* Set MMC clock / power.
1134 * Note: This controller uses a simple divider scheme therefore it cannot
1135 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
1136 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
1137 * slowest setting.
1138 */
1139 static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1140 {
1141 struct tmio_mmc_host *host = mmc_priv(mmc);
1142
1143 if (ios->clock)
1144 tmio_mmc_set_clock(host, ios->clock);
1145
1146 /* Power sequence - OFF -> ON -> UP */
1147 switch (ios->power_mode) {
1148 case MMC_POWER_OFF: /* power down SD bus */
1149 if (host->set_pwr)
1150 host->set_pwr(host->pdev, 0);
1151 tmio_mmc_clk_stop(host);
1152 break;
1153 case MMC_POWER_ON: /* power up SD bus */
1154 if (host->set_pwr)
1155 host->set_pwr(host->pdev, 1);
1156 break;
1157 case MMC_POWER_UP: /* start bus clock */
1158 tmio_mmc_clk_start(host);
1159 break;
1160 }
1161
1162 switch (ios->bus_width) {
1163 case MMC_BUS_WIDTH_1:
1164 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
1165 break;
1166 case MMC_BUS_WIDTH_4:
1167 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
1168 break;
1169 }
1170
1171 /* Let things settle. delay taken from winCE driver */
1172 udelay(140);
1173 }
1174
1175 static int tmio_mmc_get_ro(struct mmc_host *mmc)
1176 {
1177 struct tmio_mmc_host *host = mmc_priv(mmc);
1178 struct mfd_cell *cell = host->pdev->dev.platform_data;
1179 struct tmio_mmc_data *pdata = cell->driver_data;
1180
1181 return ((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
1182 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)) ? 0 : 1;
1183 }
1184
1185 static int tmio_mmc_get_cd(struct mmc_host *mmc)
1186 {
1187 struct tmio_mmc_host *host = mmc_priv(mmc);
1188 struct mfd_cell *cell = host->pdev->dev.platform_data;
1189 struct tmio_mmc_data *pdata = cell->driver_data;
1190
1191 if (!pdata->get_cd)
1192 return -ENOSYS;
1193 else
1194 return pdata->get_cd(host->pdev);
1195 }
1196
1197 static const struct mmc_host_ops tmio_mmc_ops = {
1198 .request = tmio_mmc_request,
1199 .set_ios = tmio_mmc_set_ios,
1200 .get_ro = tmio_mmc_get_ro,
1201 .get_cd = tmio_mmc_get_cd,
1202 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
1203 };
1204
1205 #ifdef CONFIG_PM
1206 static int tmio_mmc_suspend(struct platform_device *dev, pm_message_t state)
1207 {
1208 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1209 struct mmc_host *mmc = platform_get_drvdata(dev);
1210 int ret;
1211
1212 ret = mmc_suspend_host(mmc);
1213
1214 /* Tell MFD core it can disable us now.*/
1215 if (!ret && cell->disable)
1216 cell->disable(dev);
1217
1218 return ret;
1219 }
1220
1221 static int tmio_mmc_resume(struct platform_device *dev)
1222 {
1223 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1224 struct mmc_host *mmc = platform_get_drvdata(dev);
1225 int ret = 0;
1226
1227 /* Tell the MFD core we are ready to be enabled */
1228 if (cell->resume) {
1229 ret = cell->resume(dev);
1230 if (ret)
1231 goto out;
1232 }
1233
1234 mmc_resume_host(mmc);
1235
1236 out:
1237 return ret;
1238 }
1239 #else
1240 #define tmio_mmc_suspend NULL
1241 #define tmio_mmc_resume NULL
1242 #endif
1243
1244 static int __devinit tmio_mmc_probe(struct platform_device *dev)
1245 {
1246 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1247 struct tmio_mmc_data *pdata;
1248 struct resource *res_ctl;
1249 struct tmio_mmc_host *host;
1250 struct mmc_host *mmc;
1251 int ret = -EINVAL;
1252 u32 irq_mask = TMIO_MASK_CMD;
1253
1254 if (dev->num_resources != 2)
1255 goto out;
1256
1257 res_ctl = platform_get_resource(dev, IORESOURCE_MEM, 0);
1258 if (!res_ctl)
1259 goto out;
1260
1261 pdata = cell->driver_data;
1262 if (!pdata || !pdata->hclk)
1263 goto out;
1264
1265 ret = -ENOMEM;
1266
1267 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev);
1268 if (!mmc)
1269 goto out;
1270
1271 host = mmc_priv(mmc);
1272 host->mmc = mmc;
1273 host->pdev = dev;
1274 platform_set_drvdata(dev, mmc);
1275
1276 host->set_pwr = pdata->set_pwr;
1277 host->set_clk_div = pdata->set_clk_div;
1278
1279 /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
1280 host->bus_shift = resource_size(res_ctl) >> 10;
1281
1282 host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
1283 if (!host->ctl)
1284 goto host_free;
1285
1286 mmc->ops = &tmio_mmc_ops;
1287 mmc->caps = MMC_CAP_4_BIT_DATA | pdata->capabilities;
1288 mmc->f_max = pdata->hclk;
1289 mmc->f_min = mmc->f_max / 512;
1290 mmc->max_segs = 32;
1291 mmc->max_blk_size = 512;
1292 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
1293 mmc->max_segs;
1294 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1295 mmc->max_seg_size = mmc->max_req_size;
1296 if (pdata->ocr_mask)
1297 mmc->ocr_avail = pdata->ocr_mask;
1298 else
1299 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1300
1301 /* Tell the MFD core we are ready to be enabled */
1302 if (cell->enable) {
1303 ret = cell->enable(dev);
1304 if (ret)
1305 goto unmap_ctl;
1306 }
1307
1308 tmio_mmc_clk_stop(host);
1309 reset(host);
1310
1311 ret = platform_get_irq(dev, 0);
1312 if (ret >= 0)
1313 host->irq = ret;
1314 else
1315 goto cell_disable;
1316
1317 disable_mmc_irqs(host, TMIO_MASK_ALL);
1318 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
1319 tmio_mmc_enable_sdio_irq(mmc, 0);
1320
1321 ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED |
1322 IRQF_TRIGGER_FALLING, dev_name(&dev->dev), host);
1323 if (ret)
1324 goto cell_disable;
1325
1326 spin_lock_init(&host->lock);
1327
1328 /* Init delayed work for request timeouts */
1329 INIT_DELAYED_WORK(&host->delayed_reset_work, tmio_mmc_reset_work);
1330
1331 /* See if we also get DMA */
1332 tmio_mmc_request_dma(host, pdata);
1333
1334 mmc_add_host(mmc);
1335
1336 pr_info("%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc),
1337 (unsigned long)host->ctl, host->irq);
1338
1339 /* Unmask the IRQs we want to know about */
1340 if (!host->chan_rx)
1341 irq_mask |= TMIO_MASK_READOP;
1342 if (!host->chan_tx)
1343 irq_mask |= TMIO_MASK_WRITEOP;
1344 enable_mmc_irqs(host, irq_mask);
1345
1346 return 0;
1347
1348 cell_disable:
1349 if (cell->disable)
1350 cell->disable(dev);
1351 unmap_ctl:
1352 iounmap(host->ctl);
1353 host_free:
1354 mmc_free_host(mmc);
1355 out:
1356 return ret;
1357 }
1358
1359 static int __devexit tmio_mmc_remove(struct platform_device *dev)
1360 {
1361 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1362 struct mmc_host *mmc = platform_get_drvdata(dev);
1363
1364 platform_set_drvdata(dev, NULL);
1365
1366 if (mmc) {
1367 struct tmio_mmc_host *host = mmc_priv(mmc);
1368 mmc_remove_host(mmc);
1369 cancel_delayed_work_sync(&host->delayed_reset_work);
1370 tmio_mmc_release_dma(host);
1371 free_irq(host->irq, host);
1372 if (cell->disable)
1373 cell->disable(dev);
1374 iounmap(host->ctl);
1375 mmc_free_host(mmc);
1376 }
1377
1378 return 0;
1379 }
1380
1381 /* ------------------- device registration ----------------------- */
1382
1383 static struct platform_driver tmio_mmc_driver = {
1384 .driver = {
1385 .name = "tmio-mmc",
1386 .owner = THIS_MODULE,
1387 },
1388 .probe = tmio_mmc_probe,
1389 .remove = __devexit_p(tmio_mmc_remove),
1390 .suspend = tmio_mmc_suspend,
1391 .resume = tmio_mmc_resume,
1392 };
1393
1394
1395 static int __init tmio_mmc_init(void)
1396 {
1397 return platform_driver_register(&tmio_mmc_driver);
1398 }
1399
1400 static void __exit tmio_mmc_exit(void)
1401 {
1402 platform_driver_unregister(&tmio_mmc_driver);
1403 }
1404
1405 module_init(tmio_mmc_init);
1406 module_exit(tmio_mmc_exit);
1407
1408 MODULE_DESCRIPTION("Toshiba TMIO SD/MMC driver");
1409 MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
1410 MODULE_LICENSE("GPL v2");
1411 MODULE_ALIAS("platform:tmio-mmc");
Linux 2.6 libata-dev (mirror)