?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sky2: fix shutdown synchronization
[linux-2.6/libata-dev.git] / drivers / net / sky2.c
blobfd7accf8f30571c7aa3917d4c916ea3a31ec48e8
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
33 #include <linux/ip.h>
34 #include <net/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.22"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66
67 #define TX_RING_SIZE 512
68 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
69 #define TX_MIN_PENDING 64
70 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
71
72 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
73 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
74 #define TX_WATCHDOG (5 * HZ)
75 #define NAPI_WEIGHT 64
76 #define PHY_RETRIES 1000
77
78 #define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
83 static const u32 default_msg =
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
87
88 static int debug = -1; /* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
100 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
140 { 0 }
141 };
142
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149
150 static void sky2_set_multicast(struct net_device *dev);
151
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
154 {
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
167 return 0;
168
169 udelay(10);
170 }
171
172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
173 return -ETIMEDOUT;
174
175 io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
178 }
179
180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
181 {
182 int i;
183
184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
197 udelay(10);
198 }
199
200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
201 return -ETIMEDOUT;
202 io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
205 }
206
207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
208 {
209 u16 v;
210 __gm_phy_read(hw, port, reg, &v);
211 return v;
212 }
213
214
215 static void sky2_power_on(struct sky2_hw *hw)
216 {
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232
233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
234 u32 reg;
235
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237
238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
242
243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
247
248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
254
255 sky2_read32(hw, B2_GP_IO);
256 }
257 }
258
259 static void sky2_power_aux(struct sky2_hw *hw)
260 {
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
275 }
276
277 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
278 {
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
283
284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292 }
293
294 /* flow control to advertise bits */
295 static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300 };
301
302 /* flow control to advertise bits when using 1000BaseX */
303 static const u16 fiber_fc_adv[] = {
304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
308 };
309
310 /* flow control to GMA disable bits */
311 static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316 };
317
318
319 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320 {
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
323
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
329 PHY_M_EC_MAC_S_MSK);
330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
333 if (hw->chip_id == CHIP_ID_YUKON_EC)
334 /* set downshift counter to 3x and enable downshift */
335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 if (sky2_is_copper(hw)) {
345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
365 /* downshift on PHY 88E1112 and 88E1149 is changed */
366 if (sky2->autoneg == AUTONEG_ENABLE
367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
368 /* set downshift counter to 3x and enable downshift */
369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
378 }
379
380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
385
386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401 }
402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
404 }
405
406 ctrl = PHY_CT_RESET;
407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
409 reg = 0;
410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
412 if (sky2_is_copper(hw)) {
413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
425
426 adv |= copper_fc_adv[sky2->flow_mode];
427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
432
433 adv |= fiber_fc_adv[sky2->flow_mode];
434 }
435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
448 reg |= GM_GPCR_SPEED_1000;
449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
452 reg |= GM_GPCR_SPEED_100;
453 break;
454 }
455
456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
461
462
463 reg |= gm_fc_disable[sky2->flow_mode];
464
465 /* Forward pause packets to GMAC? */
466 if (sky2->flow_mode & FC_RX)
467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
470 }
471
472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
474 if (hw->flags & SKY2_HW_GIGABIT)
475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
515 case CHIP_ID_YUKON_XL:
516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
536
537 /* restore page register */
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
539 break;
540
541 case CHIP_ID_YUKON_EC_U:
542 case CHIP_ID_YUKON_EX:
543 case CHIP_ID_YUKON_SUPR:
544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
566
567 /* turn off the Rx LED (LED_RX) */
568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
569 }
570
571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
572 /* apply fixes in PHY AFE */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
575 /* increase differential signal amplitude in 10BASE-T */
576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
578
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
584
585 /* set page register to 0 */
586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
594 /* no effect on Yukon-XL */
595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
596
597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
600 }
601
602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
606
607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612 }
613
614 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
618 {
619 u32 reg1;
620
621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
623 reg1 &= ~phy_power[port];
624
625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
626 reg1 |= coma_mode[port];
627
628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
636 }
637
638 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639 {
640 u32 reg1;
641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
670
671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
689 }
690
691 /* Force a renegotiation */
692 static void sky2_phy_reinit(struct sky2_port *sky2)
693 {
694 spin_lock_bh(&sky2->phy_lock);
695 sky2_phy_init(sky2->hw, sky2->port);
696 spin_unlock_bh(&sky2->phy_lock);
697 }
698
699 /* Put device in state to listen for Wake On Lan */
700 static void sky2_wol_init(struct sky2_port *sky2)
701 {
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
759 reg1 |= PCI_Y2_PME_LEGACY;
760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765 }
766
767 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768 {
769 struct net_device *dev = hw->dev[port];
770
771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
777
778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
781
782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
792
793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
798 }
799 }
800
801 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802 {
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
805 u32 rx_reg;
806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
827
828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
831 spin_lock_bh(&sky2->phy_lock);
832 sky2_phy_power_up(hw, port);
833 sky2_phy_init(hw, port);
834 spin_unlock_bh(&sky2->phy_lock);
835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
864
865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
886 rx_reg |= GMF_RX_OVER_ON;
887
888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
889
890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
897
898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
909
910 /* On chips without ram buffer, pause is controled by MAC level */
911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
914
915 sky2_set_tx_stfwd(hw, port);
916 }
917
918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
925 }
926
927 /* Assign Ram Buffer allocation to queue */
928 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
929 {
930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
936
937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
944 u32 tp = space - space/4;
945
946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
952
953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
965 }
966
967 /* Setup Bus Memory Interface */
968 static void sky2_qset(struct sky2_hw *hw, u16 q)
969 {
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
974 }
975
976 /* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
979 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
980 u64 addr, u32 last)
981 {
982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
990 }
991
992 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
993 {
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
995
996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
997 le->ctrl = 0;
998 return le;
999 }
1000
1001 static void tx_init(struct sky2_port *sky2)
1002 {
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
1009 le = get_tx_le(sky2);
1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
1012 }
1013
1014 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016 {
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018 }
1019
1020 /* Update chip's next pointer */
1021 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1022 {
1023 /* Make sure write' to descriptors are complete before we tell hardware */
1024 wmb();
1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
1029 }
1030
1031
1032 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033 {
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1036 le->ctrl = 0;
1037 return le;
1038 }
1039
1040 /* Build description to hardware for one receive segment */
1041 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
1043 {
1044 struct sky2_rx_le *le;
1045
1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
1047 le = sky2_next_rx(sky2);
1048 le->addr = cpu_to_le32(upper_32_bits(map));
1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
1051
1052 le = sky2_next_rx(sky2);
1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
1055 le->opcode = op | HW_OWNER;
1056 }
1057
1058 /* Build description to hardware for one possibly fragmented skb */
1059 static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061 {
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068 }
1069
1070
1071 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1072 unsigned size)
1073 {
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1079 return -EIO;
1080
1081 pci_unmap_len_set(re, data_size, size);
1082
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
1089 return 0;
1090 }
1091
1092 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1093 {
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1099
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1104 }
1105
1106 /* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1108 * order problems.
1109 */
1110 static void rx_set_checksum(struct sky2_port *sky2)
1111 {
1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
1113
1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1115 le->ctrl = 0;
1116 le->opcode = OP_TCPSTART | HW_OWNER;
1117
1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1121 }
1122
1123 /*
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1131 * will be reset.
1132 */
1133 static void sky2_rx_stop(struct sky2_port *sky2)
1134 {
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1137 int i;
1138
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1141
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1145 goto stopped;
1146
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1149 stopped:
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1151
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1154
1155 /* Reset the RAM Buffer receive queue */
1156 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_RST_SET);
1157
1158 /* Reset Rx MAC FIFO */
1159 sky2_write8(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), GMF_RST_SET);
1160
1161 sky2_read8(hw, B0_CTST);
1162 }
1163
1164 /* Clean out receive buffer area, assumes receiver hardware stopped */
1165 static void sky2_rx_clean(struct sky2_port *sky2)
1166 {
1167 unsigned i;
1168
1169 memset(sky2->rx_le, 0, RX_LE_BYTES);
1170 for (i = 0; i < sky2->rx_pending; i++) {
1171 struct rx_ring_info *re = sky2->rx_ring + i;
1172
1173 if (re->skb) {
1174 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1175 kfree_skb(re->skb);
1176 re->skb = NULL;
1177 }
1178 }
1179 }
1180
1181 /* Basic MII support */
1182 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1183 {
1184 struct mii_ioctl_data *data = if_mii(ifr);
1185 struct sky2_port *sky2 = netdev_priv(dev);
1186 struct sky2_hw *hw = sky2->hw;
1187 int err = -EOPNOTSUPP;
1188
1189 if (!netif_running(dev))
1190 return -ENODEV; /* Phy still in reset */
1191
1192 switch (cmd) {
1193 case SIOCGMIIPHY:
1194 data->phy_id = PHY_ADDR_MARV;
1195
1196 /* fallthru */
1197 case SIOCGMIIREG: {
1198 u16 val = 0;
1199
1200 spin_lock_bh(&sky2->phy_lock);
1201 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1202 spin_unlock_bh(&sky2->phy_lock);
1203
1204 data->val_out = val;
1205 break;
1206 }
1207
1208 case SIOCSMIIREG:
1209 if (!capable(CAP_NET_ADMIN))
1210 return -EPERM;
1211
1212 spin_lock_bh(&sky2->phy_lock);
1213 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1214 data->val_in);
1215 spin_unlock_bh(&sky2->phy_lock);
1216 break;
1217 }
1218 return err;
1219 }
1220
1221 #ifdef SKY2_VLAN_TAG_USED
1222 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1223 {
1224 if (onoff) {
1225 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1226 RX_VLAN_STRIP_ON);
1227 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1228 TX_VLAN_TAG_ON);
1229 } else {
1230 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1231 RX_VLAN_STRIP_OFF);
1232 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1233 TX_VLAN_TAG_OFF);
1234 }
1235 }
1236
1237 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1238 {
1239 struct sky2_port *sky2 = netdev_priv(dev);
1240 struct sky2_hw *hw = sky2->hw;
1241 u16 port = sky2->port;
1242
1243 netif_tx_lock_bh(dev);
1244 napi_disable(&hw->napi);
1245
1246 sky2->vlgrp = grp;
1247 sky2_set_vlan_mode(hw, port, grp != NULL);
1248
1249 sky2_read32(hw, B0_Y2_SP_LISR);
1250 napi_enable(&hw->napi);
1251 netif_tx_unlock_bh(dev);
1252 }
1253 #endif
1254
1255 /*
1256 * Allocate an skb for receiving. If the MTU is large enough
1257 * make the skb non-linear with a fragment list of pages.
1258 */
1259 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1260 {
1261 struct sk_buff *skb;
1262 int i;
1263
1264 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1265 unsigned char *start;
1266 /*
1267 * Workaround for a bug in FIFO that cause hang
1268 * if the FIFO if the receive buffer is not 64 byte aligned.
1269 * The buffer returned from netdev_alloc_skb is
1270 * aligned except if slab debugging is enabled.
1271 */
1272 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1273 if (!skb)
1274 goto nomem;
1275 start = PTR_ALIGN(skb->data, 8);
1276 skb_reserve(skb, start - skb->data);
1277 } else {
1278 skb = netdev_alloc_skb(sky2->netdev,
1279 sky2->rx_data_size + NET_IP_ALIGN);
1280 if (!skb)
1281 goto nomem;
1282 skb_reserve(skb, NET_IP_ALIGN);
1283 }
1284
1285 for (i = 0; i < sky2->rx_nfrags; i++) {
1286 struct page *page = alloc_page(GFP_ATOMIC);
1287
1288 if (!page)
1289 goto free_partial;
1290 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1291 }
1292
1293 return skb;
1294 free_partial:
1295 kfree_skb(skb);
1296 nomem:
1297 return NULL;
1298 }
1299
1300 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1301 {
1302 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1303 }
1304
1305 /*
1306 * Allocate and setup receiver buffer pool.
1307 * Normal case this ends up creating one list element for skb
1308 * in the receive ring. Worst case if using large MTU and each
1309 * allocation falls on a different 64 bit region, that results
1310 * in 6 list elements per ring entry.
1311 * One element is used for checksum enable/disable, and one
1312 * extra to avoid wrap.
1313 */
1314 static int sky2_rx_start(struct sky2_port *sky2)
1315 {
1316 struct sky2_hw *hw = sky2->hw;
1317 struct rx_ring_info *re;
1318 unsigned rxq = rxqaddr[sky2->port];
1319 unsigned i, size, thresh;
1320
1321 sky2->rx_put = sky2->rx_next = 0;
1322 sky2_qset(hw, rxq);
1323
1324 /* On PCI express lowering the watermark gives better performance */
1325 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1326 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1327
1328 /* These chips have no ram buffer?
1329 * MAC Rx RAM Read is controlled by hardware */
1330 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1331 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1332 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1333 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1334
1335 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1336
1337 if (!(hw->flags & SKY2_HW_NEW_LE))
1338 rx_set_checksum(sky2);
1339
1340 /* Space needed for frame data + headers rounded up */
1341 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1342
1343 /* Stopping point for hardware truncation */
1344 thresh = (size - 8) / sizeof(u32);
1345
1346 sky2->rx_nfrags = size >> PAGE_SHIFT;
1347 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1348
1349 /* Compute residue after pages */
1350 size -= sky2->rx_nfrags << PAGE_SHIFT;
1351
1352 /* Optimize to handle small packets and headers */
1353 if (size < copybreak)
1354 size = copybreak;
1355 if (size < ETH_HLEN)
1356 size = ETH_HLEN;
1357
1358 sky2->rx_data_size = size;
1359
1360 /* Fill Rx ring */
1361 for (i = 0; i < sky2->rx_pending; i++) {
1362 re = sky2->rx_ring + i;
1363
1364 re->skb = sky2_rx_alloc(sky2);
1365 if (!re->skb)
1366 goto nomem;
1367
1368 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1369 dev_kfree_skb(re->skb);
1370 re->skb = NULL;
1371 goto nomem;
1372 }
1373
1374 sky2_rx_submit(sky2, re);
1375 }
1376
1377 /*
1378 * The receiver hangs if it receives frames larger than the
1379 * packet buffer. As a workaround, truncate oversize frames, but
1380 * the register is limited to 9 bits, so if you do frames > 2052
1381 * you better get the MTU right!
1382 */
1383 if (thresh > 0x1ff)
1384 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1385 else {
1386 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1387 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1388 }
1389
1390 /* Tell chip about available buffers */
1391 sky2_rx_update(sky2, rxq);
1392 return 0;
1393 nomem:
1394 sky2_rx_clean(sky2);
1395 return -ENOMEM;
1396 }
1397
1398 /* Bring up network interface. */
1399 static int sky2_up(struct net_device *dev)
1400 {
1401 struct sky2_port *sky2 = netdev_priv(dev);
1402 struct sky2_hw *hw = sky2->hw;
1403 unsigned port = sky2->port;
1404 u32 imask, ramsize;
1405 int cap, err = -ENOMEM;
1406 struct net_device *otherdev = hw->dev[sky2->port^1];
1407
1408 /*
1409 * On dual port PCI-X card, there is an problem where status
1410 * can be received out of order due to split transactions
1411 */
1412 if (otherdev && netif_running(otherdev) &&
1413 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1414 u16 cmd;
1415
1416 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1417 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1418 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1419
1420 }
1421
1422 netif_carrier_off(dev);
1423
1424 /* must be power of 2 */
1425 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1426 TX_RING_SIZE *
1427 sizeof(struct sky2_tx_le),
1428 &sky2->tx_le_map);
1429 if (!sky2->tx_le)
1430 goto err_out;
1431
1432 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1433 GFP_KERNEL);
1434 if (!sky2->tx_ring)
1435 goto err_out;
1436
1437 tx_init(sky2);
1438
1439 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1440 &sky2->rx_le_map);
1441 if (!sky2->rx_le)
1442 goto err_out;
1443 memset(sky2->rx_le, 0, RX_LE_BYTES);
1444
1445 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1446 GFP_KERNEL);
1447 if (!sky2->rx_ring)
1448 goto err_out;
1449
1450 sky2_mac_init(hw, port);
1451
1452 /* Register is number of 4K blocks on internal RAM buffer. */
1453 ramsize = sky2_read8(hw, B2_E_0) * 4;
1454 if (ramsize > 0) {
1455 u32 rxspace;
1456
1457 hw->flags |= SKY2_HW_RAM_BUFFER;
1458 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1459 if (ramsize < 16)
1460 rxspace = ramsize / 2;
1461 else
1462 rxspace = 8 + (2*(ramsize - 16))/3;
1463
1464 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1465 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1466
1467 /* Make sure SyncQ is disabled */
1468 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1469 RB_RST_SET);
1470 }
1471
1472 sky2_qset(hw, txqaddr[port]);
1473
1474 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1475 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1476 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1477
1478 /* Set almost empty threshold */
1479 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1480 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1481 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1482
1483 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1484 TX_RING_SIZE - 1);
1485
1486 #ifdef SKY2_VLAN_TAG_USED
1487 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1488 #endif
1489
1490 err = sky2_rx_start(sky2);
1491 if (err)
1492 goto err_out;
1493
1494 /* Enable interrupts from phy/mac for port */
1495 imask = sky2_read32(hw, B0_IMSK);
1496 imask |= portirq_msk[port];
1497 sky2_write32(hw, B0_IMSK, imask);
1498 sky2_read32(hw, B0_IMSK);
1499
1500 sky2_set_multicast(dev);
1501
1502 if (netif_msg_ifup(sky2))
1503 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1504 return 0;
1505
1506 err_out:
1507 if (sky2->rx_le) {
1508 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1509 sky2->rx_le, sky2->rx_le_map);
1510 sky2->rx_le = NULL;
1511 }
1512 if (sky2->tx_le) {
1513 pci_free_consistent(hw->pdev,
1514 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1515 sky2->tx_le, sky2->tx_le_map);
1516 sky2->tx_le = NULL;
1517 }
1518 kfree(sky2->tx_ring);
1519 kfree(sky2->rx_ring);
1520
1521 sky2->tx_ring = NULL;
1522 sky2->rx_ring = NULL;
1523 return err;
1524 }
1525
1526 /* Modular subtraction in ring */
1527 static inline int tx_dist(unsigned tail, unsigned head)
1528 {
1529 return (head - tail) & (TX_RING_SIZE - 1);
1530 }
1531
1532 /* Number of list elements available for next tx */
1533 static inline int tx_avail(const struct sky2_port *sky2)
1534 {
1535 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1536 }
1537
1538 /* Estimate of number of transmit list elements required */
1539 static unsigned tx_le_req(const struct sk_buff *skb)
1540 {
1541 unsigned count;
1542
1543 count = sizeof(dma_addr_t) / sizeof(u32);
1544 count += skb_shinfo(skb)->nr_frags * count;
1545
1546 if (skb_is_gso(skb))
1547 ++count;
1548
1549 if (skb->ip_summed == CHECKSUM_PARTIAL)
1550 ++count;
1551
1552 return count;
1553 }
1554
1555 /*
1556 * Put one packet in ring for transmit.
1557 * A single packet can generate multiple list elements, and
1558 * the number of ring elements will probably be less than the number
1559 * of list elements used.
1560 */
1561 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1562 {
1563 struct sky2_port *sky2 = netdev_priv(dev);
1564 struct sky2_hw *hw = sky2->hw;
1565 struct sky2_tx_le *le = NULL;
1566 struct tx_ring_info *re;
1567 unsigned i, len, first_slot;
1568 dma_addr_t mapping;
1569 u16 mss;
1570 u8 ctrl;
1571
1572 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1573 return NETDEV_TX_BUSY;
1574
1575 len = skb_headlen(skb);
1576 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1577
1578 if (pci_dma_mapping_error(hw->pdev, mapping))
1579 goto mapping_error;
1580
1581 first_slot = sky2->tx_prod;
1582 if (unlikely(netif_msg_tx_queued(sky2)))
1583 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1584 dev->name, first_slot, skb->len);
1585
1586 /* Send high bits if needed */
1587 if (sizeof(dma_addr_t) > sizeof(u32)) {
1588 le = get_tx_le(sky2);
1589 le->addr = cpu_to_le32(upper_32_bits(mapping));
1590 le->opcode = OP_ADDR64 | HW_OWNER;
1591 }
1592
1593 /* Check for TCP Segmentation Offload */
1594 mss = skb_shinfo(skb)->gso_size;
1595 if (mss != 0) {
1596
1597 if (!(hw->flags & SKY2_HW_NEW_LE))
1598 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1599
1600 if (mss != sky2->tx_last_mss) {
1601 le = get_tx_le(sky2);
1602 le->addr = cpu_to_le32(mss);
1603
1604 if (hw->flags & SKY2_HW_NEW_LE)
1605 le->opcode = OP_MSS | HW_OWNER;
1606 else
1607 le->opcode = OP_LRGLEN | HW_OWNER;
1608 sky2->tx_last_mss = mss;
1609 }
1610 }
1611
1612 ctrl = 0;
1613 #ifdef SKY2_VLAN_TAG_USED
1614 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1615 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1616 if (!le) {
1617 le = get_tx_le(sky2);
1618 le->addr = 0;
1619 le->opcode = OP_VLAN|HW_OWNER;
1620 } else
1621 le->opcode |= OP_VLAN;
1622 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1623 ctrl |= INS_VLAN;
1624 }
1625 #endif
1626
1627 /* Handle TCP checksum offload */
1628 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1629 /* On Yukon EX (some versions) encoding change. */
1630 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1631 ctrl |= CALSUM; /* auto checksum */
1632 else {
1633 const unsigned offset = skb_transport_offset(skb);
1634 u32 tcpsum;
1635
1636 tcpsum = offset << 16; /* sum start */
1637 tcpsum |= offset + skb->csum_offset; /* sum write */
1638
1639 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1640 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1641 ctrl |= UDPTCP;
1642
1643 if (tcpsum != sky2->tx_tcpsum) {
1644 sky2->tx_tcpsum = tcpsum;
1645
1646 le = get_tx_le(sky2);
1647 le->addr = cpu_to_le32(tcpsum);
1648 le->length = 0; /* initial checksum value */
1649 le->ctrl = 1; /* one packet */
1650 le->opcode = OP_TCPLISW | HW_OWNER;
1651 }
1652 }
1653 }
1654
1655 le = get_tx_le(sky2);
1656 le->addr = cpu_to_le32((u32) mapping);
1657 le->length = cpu_to_le16(len);
1658 le->ctrl = ctrl;
1659 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1660
1661 re = tx_le_re(sky2, le);
1662 re->skb = skb;
1663 pci_unmap_addr_set(re, mapaddr, mapping);
1664 pci_unmap_len_set(re, maplen, len);
1665
1666 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1667 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1668
1669 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1670 frag->size, PCI_DMA_TODEVICE);
1671
1672 if (pci_dma_mapping_error(hw->pdev, mapping))
1673 goto mapping_unwind;
1674
1675 if (sizeof(dma_addr_t) > sizeof(u32)) {
1676 le = get_tx_le(sky2);
1677 le->addr = cpu_to_le32(upper_32_bits(mapping));
1678 le->ctrl = 0;
1679 le->opcode = OP_ADDR64 | HW_OWNER;
1680 }
1681
1682 le = get_tx_le(sky2);
1683 le->addr = cpu_to_le32((u32) mapping);
1684 le->length = cpu_to_le16(frag->size);
1685 le->ctrl = ctrl;
1686 le->opcode = OP_BUFFER | HW_OWNER;
1687
1688 re = tx_le_re(sky2, le);
1689 re->skb = skb;
1690 pci_unmap_addr_set(re, mapaddr, mapping);
1691 pci_unmap_len_set(re, maplen, frag->size);
1692 }
1693
1694 le->ctrl |= EOP;
1695
1696 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1697 netif_stop_queue(dev);
1698
1699 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1700
1701 return NETDEV_TX_OK;
1702
1703 mapping_unwind:
1704 for (i = first_slot; i != sky2->tx_prod; i = RING_NEXT(i, TX_RING_SIZE)) {
1705 le = sky2->tx_le + i;
1706 re = sky2->tx_ring + i;
1707
1708 switch(le->opcode & ~HW_OWNER) {
1709 case OP_LARGESEND:
1710 case OP_PACKET:
1711 pci_unmap_single(hw->pdev,
1712 pci_unmap_addr(re, mapaddr),
1713 pci_unmap_len(re, maplen),
1714 PCI_DMA_TODEVICE);
1715 break;
1716 case OP_BUFFER:
1717 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1718 pci_unmap_len(re, maplen),
1719 PCI_DMA_TODEVICE);
1720 break;
1721 }
1722 }
1723
1724 sky2->tx_prod = first_slot;
1725 mapping_error:
1726 if (net_ratelimit())
1727 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1728 dev_kfree_skb(skb);
1729 return NETDEV_TX_OK;
1730 }
1731
1732 /*
1733 * Free ring elements from starting at tx_cons until "done"
1734 *
1735 * NB: the hardware will tell us about partial completion of multi-part
1736 * buffers so make sure not to free skb to early.
1737 */
1738 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1739 {
1740 struct net_device *dev = sky2->netdev;
1741 struct pci_dev *pdev = sky2->hw->pdev;
1742 unsigned idx;
1743
1744 BUG_ON(done >= TX_RING_SIZE);
1745
1746 for (idx = sky2->tx_cons; idx != done;
1747 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1748 struct sky2_tx_le *le = sky2->tx_le + idx;
1749 struct tx_ring_info *re = sky2->tx_ring + idx;
1750
1751 switch(le->opcode & ~HW_OWNER) {
1752 case OP_LARGESEND:
1753 case OP_PACKET:
1754 pci_unmap_single(pdev,
1755 pci_unmap_addr(re, mapaddr),
1756 pci_unmap_len(re, maplen),
1757 PCI_DMA_TODEVICE);
1758 break;
1759 case OP_BUFFER:
1760 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1761 pci_unmap_len(re, maplen),
1762 PCI_DMA_TODEVICE);
1763 break;
1764 }
1765
1766 if (le->ctrl & EOP) {
1767 if (unlikely(netif_msg_tx_done(sky2)))
1768 printk(KERN_DEBUG "%s: tx done %u\n",
1769 dev->name, idx);
1770
1771 dev->stats.tx_packets++;
1772 dev->stats.tx_bytes += re->skb->len;
1773
1774 dev_kfree_skb_any(re->skb);
1775 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1776 }
1777 }
1778
1779 sky2->tx_cons = idx;
1780 smp_mb();
1781
1782 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1783 netif_wake_queue(dev);
1784 }
1785
1786 /* Cleanup all untransmitted buffers, assume transmitter not running */
1787 static void sky2_tx_clean(struct net_device *dev)
1788 {
1789 struct sky2_port *sky2 = netdev_priv(dev);
1790
1791 netif_tx_lock_bh(dev);
1792 sky2_tx_complete(sky2, sky2->tx_prod);
1793 netif_tx_unlock_bh(dev);
1794 }
1795
1796 /* Network shutdown */
1797 static int sky2_down(struct net_device *dev)
1798 {
1799 struct sky2_port *sky2 = netdev_priv(dev);
1800 struct sky2_hw *hw = sky2->hw;
1801 unsigned port = sky2->port;
1802 u16 ctrl;
1803 u32 imask;
1804
1805 /* Never really got started! */
1806 if (!sky2->tx_le)
1807 return 0;
1808
1809 if (netif_msg_ifdown(sky2))
1810 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1811
1812 /* Disable port IRQ */
1813 imask = sky2_read32(hw, B0_IMSK);
1814 imask &= ~portirq_msk[port];
1815 sky2_write32(hw, B0_IMSK, imask);
1816 sky2_read32(hw, B0_IMSK);
1817
1818 /* Force flow control off */
1819 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1820
1821 /* Stop transmitter */
1822 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1823 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1824
1825 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1826 RB_RST_SET | RB_DIS_OP_MD);
1827
1828 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1829 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1830 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1831
1832 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1833
1834 /* Workaround shared GMAC reset */
1835 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1836 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1837 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1838
1839 /* Disable Force Sync bit and Enable Alloc bit */
1840 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1841 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1842
1843 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1844 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1845 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1846
1847 /* Reset the PCI FIFO of the async Tx queue */
1848 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1849 BMU_RST_SET | BMU_FIFO_RST);
1850
1851 /* Reset the Tx prefetch units */
1852 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1853 PREF_UNIT_RST_SET);
1854
1855 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1856
1857 sky2_rx_stop(sky2);
1858
1859 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1860 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1861
1862 /* Force any delayed status interrrupt and NAPI */
1863 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1864 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1865 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1866 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1867
1868 synchronize_irq(hw->pdev->irq);
1869 napi_synchronize(&hw->napi);
1870
1871 sky2_phy_power_down(hw, port);
1872
1873 /* turn off LED's */
1874 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1875
1876 sky2_tx_clean(dev);
1877 sky2_rx_clean(sky2);
1878
1879 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1880 sky2->rx_le, sky2->rx_le_map);
1881 kfree(sky2->rx_ring);
1882
1883 pci_free_consistent(hw->pdev,
1884 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1885 sky2->tx_le, sky2->tx_le_map);
1886 kfree(sky2->tx_ring);
1887
1888 sky2->tx_le = NULL;
1889 sky2->rx_le = NULL;
1890
1891 sky2->rx_ring = NULL;
1892 sky2->tx_ring = NULL;
1893
1894 return 0;
1895 }
1896
1897 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1898 {
1899 if (hw->flags & SKY2_HW_FIBRE_PHY)
1900 return SPEED_1000;
1901
1902 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1903 if (aux & PHY_M_PS_SPEED_100)
1904 return SPEED_100;
1905 else
1906 return SPEED_10;
1907 }
1908
1909 switch (aux & PHY_M_PS_SPEED_MSK) {
1910 case PHY_M_PS_SPEED_1000:
1911 return SPEED_1000;
1912 case PHY_M_PS_SPEED_100:
1913 return SPEED_100;
1914 default:
1915 return SPEED_10;
1916 }
1917 }
1918
1919 static void sky2_link_up(struct sky2_port *sky2)
1920 {
1921 struct sky2_hw *hw = sky2->hw;
1922 unsigned port = sky2->port;
1923 u16 reg;
1924 static const char *fc_name[] = {
1925 [FC_NONE] = "none",
1926 [FC_TX] = "tx",
1927 [FC_RX] = "rx",
1928 [FC_BOTH] = "both",
1929 };
1930
1931 /* enable Rx/Tx */
1932 reg = gma_read16(hw, port, GM_GP_CTRL);
1933 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1934 gma_write16(hw, port, GM_GP_CTRL, reg);
1935
1936 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1937
1938 netif_carrier_on(sky2->netdev);
1939
1940 mod_timer(&hw->watchdog_timer, jiffies + 1);
1941
1942 /* Turn on link LED */
1943 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1944 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1945
1946 if (netif_msg_link(sky2))
1947 printk(KERN_INFO PFX
1948 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1949 sky2->netdev->name, sky2->speed,
1950 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1951 fc_name[sky2->flow_status]);
1952 }
1953
1954 static void sky2_link_down(struct sky2_port *sky2)
1955 {
1956 struct sky2_hw *hw = sky2->hw;
1957 unsigned port = sky2->port;
1958 u16 reg;
1959
1960 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1961
1962 reg = gma_read16(hw, port, GM_GP_CTRL);
1963 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1964 gma_write16(hw, port, GM_GP_CTRL, reg);
1965
1966 netif_carrier_off(sky2->netdev);
1967
1968 /* Turn on link LED */
1969 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1970
1971 if (netif_msg_link(sky2))
1972 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1973
1974 sky2_phy_init(hw, port);
1975 }
1976
1977 static enum flow_control sky2_flow(int rx, int tx)
1978 {
1979 if (rx)
1980 return tx ? FC_BOTH : FC_RX;
1981 else
1982 return tx ? FC_TX : FC_NONE;
1983 }
1984
1985 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1986 {
1987 struct sky2_hw *hw = sky2->hw;
1988 unsigned port = sky2->port;
1989 u16 advert, lpa;
1990
1991 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1992 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1993 if (lpa & PHY_M_AN_RF) {
1994 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1995 return -1;
1996 }
1997
1998 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1999 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2000 sky2->netdev->name);
2001 return -1;
2002 }
2003
2004 sky2->speed = sky2_phy_speed(hw, aux);
2005 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2006
2007 /* Since the pause result bits seem to in different positions on
2008 * different chips. look at registers.
2009 */
2010 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2011 /* Shift for bits in fiber PHY */
2012 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2013 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2014
2015 if (advert & ADVERTISE_1000XPAUSE)
2016 advert |= ADVERTISE_PAUSE_CAP;
2017 if (advert & ADVERTISE_1000XPSE_ASYM)
2018 advert |= ADVERTISE_PAUSE_ASYM;
2019 if (lpa & LPA_1000XPAUSE)
2020 lpa |= LPA_PAUSE_CAP;
2021 if (lpa & LPA_1000XPAUSE_ASYM)
2022 lpa |= LPA_PAUSE_ASYM;
2023 }
2024
2025 sky2->flow_status = FC_NONE;
2026 if (advert & ADVERTISE_PAUSE_CAP) {
2027 if (lpa & LPA_PAUSE_CAP)
2028 sky2->flow_status = FC_BOTH;
2029 else if (advert & ADVERTISE_PAUSE_ASYM)
2030 sky2->flow_status = FC_RX;
2031 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2032 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2033 sky2->flow_status = FC_TX;
2034 }
2035
2036 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2037 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2038 sky2->flow_status = FC_NONE;
2039
2040 if (sky2->flow_status & FC_TX)
2041 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2042 else
2043 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2044
2045 return 0;
2046 }
2047
2048 /* Interrupt from PHY */
2049 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2050 {
2051 struct net_device *dev = hw->dev[port];
2052 struct sky2_port *sky2 = netdev_priv(dev);
2053 u16 istatus, phystat;
2054
2055 if (!netif_running(dev))
2056 return;
2057
2058 spin_lock(&sky2->phy_lock);
2059 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2060 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2061
2062 if (netif_msg_intr(sky2))
2063 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2064 sky2->netdev->name, istatus, phystat);
2065
2066 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2067 if (sky2_autoneg_done(sky2, phystat) == 0)
2068 sky2_link_up(sky2);
2069 goto out;
2070 }
2071
2072 if (istatus & PHY_M_IS_LSP_CHANGE)
2073 sky2->speed = sky2_phy_speed(hw, phystat);
2074
2075 if (istatus & PHY_M_IS_DUP_CHANGE)
2076 sky2->duplex =
2077 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2078
2079 if (istatus & PHY_M_IS_LST_CHANGE) {
2080 if (phystat & PHY_M_PS_LINK_UP)
2081 sky2_link_up(sky2);
2082 else
2083 sky2_link_down(sky2);
2084 }
2085 out:
2086 spin_unlock(&sky2->phy_lock);
2087 }
2088
2089 /* Transmit timeout is only called if we are running, carrier is up
2090 * and tx queue is full (stopped).
2091 */
2092 static void sky2_tx_timeout(struct net_device *dev)
2093 {
2094 struct sky2_port *sky2 = netdev_priv(dev);
2095 struct sky2_hw *hw = sky2->hw;
2096
2097 if (netif_msg_timer(sky2))
2098 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2099
2100 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2101 dev->name, sky2->tx_cons, sky2->tx_prod,
2102 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2103 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2104
2105 /* can't restart safely under softirq */
2106 schedule_work(&hw->restart_work);
2107 }
2108
2109 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2110 {
2111 struct sky2_port *sky2 = netdev_priv(dev);
2112 struct sky2_hw *hw = sky2->hw;
2113 unsigned port = sky2->port;
2114 int err;
2115 u16 ctl, mode;
2116 u32 imask;
2117
2118 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2119 return -EINVAL;
2120
2121 if (new_mtu > ETH_DATA_LEN &&
2122 (hw->chip_id == CHIP_ID_YUKON_FE ||
2123 hw->chip_id == CHIP_ID_YUKON_FE_P))
2124 return -EINVAL;
2125
2126 if (!netif_running(dev)) {
2127 dev->mtu = new_mtu;
2128 return 0;
2129 }
2130
2131 imask = sky2_read32(hw, B0_IMSK);
2132 sky2_write32(hw, B0_IMSK, 0);
2133
2134 dev->trans_start = jiffies; /* prevent tx timeout */
2135 netif_stop_queue(dev);
2136 napi_disable(&hw->napi);
2137
2138 synchronize_irq(hw->pdev->irq);
2139
2140 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2141 sky2_set_tx_stfwd(hw, port);
2142
2143 ctl = gma_read16(hw, port, GM_GP_CTRL);
2144 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2145 sky2_rx_stop(sky2);
2146 sky2_rx_clean(sky2);
2147
2148 dev->mtu = new_mtu;
2149
2150 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2151 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2152
2153 if (dev->mtu > ETH_DATA_LEN)
2154 mode |= GM_SMOD_JUMBO_ENA;
2155
2156 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2157
2158 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2159
2160 err = sky2_rx_start(sky2);
2161 sky2_write32(hw, B0_IMSK, imask);
2162
2163 sky2_read32(hw, B0_Y2_SP_LISR);
2164 napi_enable(&hw->napi);
2165
2166 if (err)
2167 dev_close(dev);
2168 else {
2169 gma_write16(hw, port, GM_GP_CTRL, ctl);
2170
2171 netif_wake_queue(dev);
2172 }
2173
2174 return err;
2175 }
2176
2177 /* For small just reuse existing skb for next receive */
2178 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2179 const struct rx_ring_info *re,
2180 unsigned length)
2181 {
2182 struct sk_buff *skb;
2183
2184 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2185 if (likely(skb)) {
2186 skb_reserve(skb, 2);
2187 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2188 length, PCI_DMA_FROMDEVICE);
2189 skb_copy_from_linear_data(re->skb, skb->data, length);
2190 skb->ip_summed = re->skb->ip_summed;
2191 skb->csum = re->skb->csum;
2192 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2193 length, PCI_DMA_FROMDEVICE);
2194 re->skb->ip_summed = CHECKSUM_NONE;
2195 skb_put(skb, length);
2196 }
2197 return skb;
2198 }
2199
2200 /* Adjust length of skb with fragments to match received data */
2201 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2202 unsigned int length)
2203 {
2204 int i, num_frags;
2205 unsigned int size;
2206
2207 /* put header into skb */
2208 size = min(length, hdr_space);
2209 skb->tail += size;
2210 skb->len += size;
2211 length -= size;
2212
2213 num_frags = skb_shinfo(skb)->nr_frags;
2214 for (i = 0; i < num_frags; i++) {
2215 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2216
2217 if (length == 0) {
2218 /* don't need this page */
2219 __free_page(frag->page);
2220 --skb_shinfo(skb)->nr_frags;
2221 } else {
2222 size = min(length, (unsigned) PAGE_SIZE);
2223
2224 frag->size = size;
2225 skb->data_len += size;
2226 skb->truesize += size;
2227 skb->len += size;
2228 length -= size;
2229 }
2230 }
2231 }
2232
2233 /* Normal packet - take skb from ring element and put in a new one */
2234 static struct sk_buff *receive_new(struct sky2_port *sky2,
2235 struct rx_ring_info *re,
2236 unsigned int length)
2237 {
2238 struct sk_buff *skb, *nskb;
2239 unsigned hdr_space = sky2->rx_data_size;
2240
2241 /* Don't be tricky about reusing pages (yet) */
2242 nskb = sky2_rx_alloc(sky2);
2243 if (unlikely(!nskb))
2244 return NULL;
2245
2246 skb = re->skb;
2247 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2248
2249 prefetch(skb->data);
2250 re->skb = nskb;
2251 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2252 dev_kfree_skb(nskb);
2253 re->skb = skb;
2254 return NULL;
2255 }
2256
2257 if (skb_shinfo(skb)->nr_frags)
2258 skb_put_frags(skb, hdr_space, length);
2259 else
2260 skb_put(skb, length);
2261 return skb;
2262 }
2263
2264 /*
2265 * Receive one packet.
2266 * For larger packets, get new buffer.
2267 */
2268 static struct sk_buff *sky2_receive(struct net_device *dev,
2269 u16 length, u32 status)
2270 {
2271 struct sky2_port *sky2 = netdev_priv(dev);
2272 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2273 struct sk_buff *skb = NULL;
2274 u16 count = (status & GMR_FS_LEN) >> 16;
2275
2276 #ifdef SKY2_VLAN_TAG_USED
2277 /* Account for vlan tag */
2278 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2279 count -= VLAN_HLEN;
2280 #endif
2281
2282 if (unlikely(netif_msg_rx_status(sky2)))
2283 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2284 dev->name, sky2->rx_next, status, length);
2285
2286 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2287 prefetch(sky2->rx_ring + sky2->rx_next);
2288
2289 /* This chip has hardware problems that generates bogus status.
2290 * So do only marginal checking and expect higher level protocols
2291 * to handle crap frames.
2292 */
2293 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2294 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2295 length != count)
2296 goto okay;
2297
2298 if (status & GMR_FS_ANY_ERR)
2299 goto error;
2300
2301 if (!(status & GMR_FS_RX_OK))
2302 goto resubmit;
2303
2304 /* if length reported by DMA does not match PHY, packet was truncated */
2305 if (length != count)
2306 goto len_error;
2307
2308 okay:
2309 if (length < copybreak)
2310 skb = receive_copy(sky2, re, length);
2311 else
2312 skb = receive_new(sky2, re, length);
2313 resubmit:
2314 sky2_rx_submit(sky2, re);
2315
2316 return skb;
2317
2318 len_error:
2319 /* Truncation of overlength packets
2320 causes PHY length to not match MAC length */
2321 ++dev->stats.rx_length_errors;
2322 if (netif_msg_rx_err(sky2) && net_ratelimit())
2323 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2324 dev->name, status, length);
2325 goto resubmit;
2326
2327 error:
2328 ++dev->stats.rx_errors;
2329 if (status & GMR_FS_RX_FF_OV) {
2330 dev->stats.rx_over_errors++;
2331 goto resubmit;
2332 }
2333
2334 if (netif_msg_rx_err(sky2) && net_ratelimit())
2335 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2336 dev->name, status, length);
2337
2338 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2339 dev->stats.rx_length_errors++;
2340 if (status & GMR_FS_FRAGMENT)
2341 dev->stats.rx_frame_errors++;
2342 if (status & GMR_FS_CRC_ERR)
2343 dev->stats.rx_crc_errors++;
2344
2345 goto resubmit;
2346 }
2347
2348 /* Transmit complete */
2349 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2350 {
2351 struct sky2_port *sky2 = netdev_priv(dev);
2352
2353 if (netif_running(dev)) {
2354 netif_tx_lock(dev);
2355 sky2_tx_complete(sky2, last);
2356 netif_tx_unlock(dev);
2357 }
2358 }
2359
2360 /* Process status response ring */
2361 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2362 {
2363 int work_done = 0;
2364 unsigned rx[2] = { 0, 0 };
2365
2366 rmb();
2367 do {
2368 struct sky2_port *sky2;
2369 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2370 unsigned port;
2371 struct net_device *dev;
2372 struct sk_buff *skb;
2373 u32 status;
2374 u16 length;
2375 u8 opcode = le->opcode;
2376
2377 if (!(opcode & HW_OWNER))
2378 break;
2379
2380 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2381
2382 port = le->css & CSS_LINK_BIT;
2383 dev = hw->dev[port];
2384 sky2 = netdev_priv(dev);
2385 length = le16_to_cpu(le->length);
2386 status = le32_to_cpu(le->status);
2387
2388 le->opcode = 0;
2389 switch (opcode & ~HW_OWNER) {
2390 case OP_RXSTAT:
2391 ++rx[port];
2392 skb = sky2_receive(dev, length, status);
2393 if (unlikely(!skb)) {
2394 dev->stats.rx_dropped++;
2395 break;
2396 }
2397
2398 /* This chip reports checksum status differently */
2399 if (hw->flags & SKY2_HW_NEW_LE) {
2400 if (sky2->rx_csum &&
2401 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2402 (le->css & CSS_TCPUDPCSOK))
2403 skb->ip_summed = CHECKSUM_UNNECESSARY;
2404 else
2405 skb->ip_summed = CHECKSUM_NONE;
2406 }
2407
2408 skb->protocol = eth_type_trans(skb, dev);
2409 dev->stats.rx_packets++;
2410 dev->stats.rx_bytes += skb->len;
2411 dev->last_rx = jiffies;
2412
2413 #ifdef SKY2_VLAN_TAG_USED
2414 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2415 vlan_hwaccel_receive_skb(skb,
2416 sky2->vlgrp,
2417 be16_to_cpu(sky2->rx_tag));
2418 } else
2419 #endif
2420 netif_receive_skb(skb);
2421
2422 /* Stop after net poll weight */
2423 if (++work_done >= to_do)
2424 goto exit_loop;
2425 break;
2426
2427 #ifdef SKY2_VLAN_TAG_USED
2428 case OP_RXVLAN:
2429 sky2->rx_tag = length;
2430 break;
2431
2432 case OP_RXCHKSVLAN:
2433 sky2->rx_tag = length;
2434 /* fall through */
2435 #endif
2436 case OP_RXCHKS:
2437 if (!sky2->rx_csum)
2438 break;
2439
2440 /* If this happens then driver assuming wrong format */
2441 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2442 if (net_ratelimit())
2443 printk(KERN_NOTICE "%s: unexpected"
2444 " checksum status\n",
2445 dev->name);
2446 break;
2447 }
2448
2449 /* Both checksum counters are programmed to start at
2450 * the same offset, so unless there is a problem they
2451 * should match. This failure is an early indication that
2452 * hardware receive checksumming won't work.
2453 */
2454 if (likely(status >> 16 == (status & 0xffff))) {
2455 skb = sky2->rx_ring[sky2->rx_next].skb;
2456 skb->ip_summed = CHECKSUM_COMPLETE;
2457 skb->csum = status & 0xffff;
2458 } else {
2459 printk(KERN_NOTICE PFX "%s: hardware receive "
2460 "checksum problem (status = %#x)\n",
2461 dev->name, status);
2462 sky2->rx_csum = 0;
2463 sky2_write32(sky2->hw,
2464 Q_ADDR(rxqaddr[port], Q_CSR),
2465 BMU_DIS_RX_CHKSUM);
2466 }
2467 break;
2468
2469 case OP_TXINDEXLE:
2470 /* TX index reports status for both ports */
2471 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2472 sky2_tx_done(hw->dev[0], status & 0xfff);
2473 if (hw->dev[1])
2474 sky2_tx_done(hw->dev[1],
2475 ((status >> 24) & 0xff)
2476 | (u16)(length & 0xf) << 8);
2477 break;
2478
2479 default:
2480 if (net_ratelimit())
2481 printk(KERN_WARNING PFX
2482 "unknown status opcode 0x%x\n", opcode);
2483 }
2484 } while (hw->st_idx != idx);
2485
2486 /* Fully processed status ring so clear irq */
2487 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2488
2489 exit_loop:
2490 if (rx[0])
2491 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2492
2493 if (rx[1])
2494 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2495
2496 return work_done;
2497 }
2498
2499 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2500 {
2501 struct net_device *dev = hw->dev[port];
2502
2503 if (net_ratelimit())
2504 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2505 dev->name, status);
2506
2507 if (status & Y2_IS_PAR_RD1) {
2508 if (net_ratelimit())
2509 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2510 dev->name);
2511 /* Clear IRQ */
2512 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2513 }
2514
2515 if (status & Y2_IS_PAR_WR1) {
2516 if (net_ratelimit())
2517 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2518 dev->name);
2519
2520 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2521 }
2522
2523 if (status & Y2_IS_PAR_MAC1) {
2524 if (net_ratelimit())
2525 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2526 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2527 }
2528
2529 if (status & Y2_IS_PAR_RX1) {
2530 if (net_ratelimit())
2531 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2532 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2533 }
2534
2535 if (status & Y2_IS_TCP_TXA1) {
2536 if (net_ratelimit())
2537 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2538 dev->name);
2539 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2540 }
2541 }
2542
2543 static void sky2_hw_intr(struct sky2_hw *hw)
2544 {
2545 struct pci_dev *pdev = hw->pdev;
2546 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2547 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2548
2549 status &= hwmsk;
2550
2551 if (status & Y2_IS_TIST_OV)
2552 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2553
2554 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2555 u16 pci_err;
2556
2557 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2558 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2559 if (net_ratelimit())
2560 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2561 pci_err);
2562
2563 sky2_pci_write16(hw, PCI_STATUS,
2564 pci_err | PCI_STATUS_ERROR_BITS);
2565 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2566 }
2567
2568 if (status & Y2_IS_PCI_EXP) {
2569 /* PCI-Express uncorrectable Error occurred */
2570 u32 err;
2571
2572 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2573 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2574 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2575 0xfffffffful);
2576 if (net_ratelimit())
2577 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2578
2579 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2580 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2581 }
2582
2583 if (status & Y2_HWE_L1_MASK)
2584 sky2_hw_error(hw, 0, status);
2585 status >>= 8;
2586 if (status & Y2_HWE_L1_MASK)
2587 sky2_hw_error(hw, 1, status);
2588 }
2589
2590 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2591 {
2592 struct net_device *dev = hw->dev[port];
2593 struct sky2_port *sky2 = netdev_priv(dev);
2594 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2595
2596 if (netif_msg_intr(sky2))
2597 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2598 dev->name, status);
2599
2600 if (status & GM_IS_RX_CO_OV)
2601 gma_read16(hw, port, GM_RX_IRQ_SRC);
2602
2603 if (status & GM_IS_TX_CO_OV)
2604 gma_read16(hw, port, GM_TX_IRQ_SRC);
2605
2606 if (status & GM_IS_RX_FF_OR) {
2607 ++dev->stats.rx_fifo_errors;
2608 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2609 }
2610
2611 if (status & GM_IS_TX_FF_UR) {
2612 ++dev->stats.tx_fifo_errors;
2613 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2614 }
2615 }
2616
2617 /* This should never happen it is a bug. */
2618 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2619 u16 q, unsigned ring_size)
2620 {
2621 struct net_device *dev = hw->dev[port];
2622 struct sky2_port *sky2 = netdev_priv(dev);
2623 unsigned idx;
2624 const u64 *le = (q == Q_R1 || q == Q_R2)
2625 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2626
2627 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2628 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2629 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2630 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2631
2632 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2633 }
2634
2635 static int sky2_rx_hung(struct net_device *dev)
2636 {
2637 struct sky2_port *sky2 = netdev_priv(dev);
2638 struct sky2_hw *hw = sky2->hw;
2639 unsigned port = sky2->port;
2640 unsigned rxq = rxqaddr[port];
2641 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2642 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2643 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2644 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2645
2646 /* If idle and MAC or PCI is stuck */
2647 if (sky2->check.last == dev->last_rx &&
2648 ((mac_rp == sky2->check.mac_rp &&
2649 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2650 /* Check if the PCI RX hang */
2651 (fifo_rp == sky2->check.fifo_rp &&
2652 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2653 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2654 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2655 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2656 return 1;
2657 } else {
2658 sky2->check.last = dev->last_rx;
2659 sky2->check.mac_rp = mac_rp;
2660 sky2->check.mac_lev = mac_lev;
2661 sky2->check.fifo_rp = fifo_rp;
2662 sky2->check.fifo_lev = fifo_lev;
2663 return 0;
2664 }
2665 }
2666
2667 static void sky2_watchdog(unsigned long arg)
2668 {
2669 struct sky2_hw *hw = (struct sky2_hw *) arg;
2670
2671 /* Check for lost IRQ once a second */
2672 if (sky2_read32(hw, B0_ISRC)) {
2673 napi_schedule(&hw->napi);
2674 } else {
2675 int i, active = 0;
2676
2677 for (i = 0; i < hw->ports; i++) {
2678 struct net_device *dev = hw->dev[i];
2679 if (!netif_running(dev))
2680 continue;
2681 ++active;
2682
2683 /* For chips with Rx FIFO, check if stuck */
2684 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2685 sky2_rx_hung(dev)) {
2686 pr_info(PFX "%s: receiver hang detected\n",
2687 dev->name);
2688 schedule_work(&hw->restart_work);
2689 return;
2690 }
2691 }
2692
2693 if (active == 0)
2694 return;
2695 }
2696
2697 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2698 }
2699
2700 /* Hardware/software error handling */
2701 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2702 {
2703 if (net_ratelimit())
2704 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2705
2706 if (status & Y2_IS_HW_ERR)
2707 sky2_hw_intr(hw);
2708
2709 if (status & Y2_IS_IRQ_MAC1)
2710 sky2_mac_intr(hw, 0);
2711
2712 if (status & Y2_IS_IRQ_MAC2)
2713 sky2_mac_intr(hw, 1);
2714
2715 if (status & Y2_IS_CHK_RX1)
2716 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2717
2718 if (status & Y2_IS_CHK_RX2)
2719 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2720
2721 if (status & Y2_IS_CHK_TXA1)
2722 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2723
2724 if (status & Y2_IS_CHK_TXA2)
2725 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2726 }
2727
2728 static int sky2_poll(struct napi_struct *napi, int work_limit)
2729 {
2730 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2731 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2732 int work_done = 0;
2733 u16 idx;
2734
2735 if (unlikely(status & Y2_IS_ERROR))
2736 sky2_err_intr(hw, status);
2737
2738 if (status & Y2_IS_IRQ_PHY1)
2739 sky2_phy_intr(hw, 0);
2740
2741 if (status & Y2_IS_IRQ_PHY2)
2742 sky2_phy_intr(hw, 1);
2743
2744 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2745 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2746
2747 if (work_done >= work_limit)
2748 goto done;
2749 }
2750
2751 napi_complete(napi);
2752 sky2_read32(hw, B0_Y2_SP_LISR);
2753 done:
2754
2755 return work_done;
2756 }
2757
2758 static irqreturn_t sky2_intr(int irq, void *dev_id)
2759 {
2760 struct sky2_hw *hw = dev_id;
2761 u32 status;
2762
2763 /* Reading this mask interrupts as side effect */
2764 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2765 if (status == 0 || status == ~0)
2766 return IRQ_NONE;
2767
2768 prefetch(&hw->st_le[hw->st_idx]);
2769
2770 napi_schedule(&hw->napi);
2771
2772 return IRQ_HANDLED;
2773 }
2774
2775 #ifdef CONFIG_NET_POLL_CONTROLLER
2776 static void sky2_netpoll(struct net_device *dev)
2777 {
2778 struct sky2_port *sky2 = netdev_priv(dev);
2779
2780 napi_schedule(&sky2->hw->napi);
2781 }
2782 #endif
2783
2784 /* Chip internal frequency for clock calculations */
2785 static u32 sky2_mhz(const struct sky2_hw *hw)
2786 {
2787 switch (hw->chip_id) {
2788 case CHIP_ID_YUKON_EC:
2789 case CHIP_ID_YUKON_EC_U:
2790 case CHIP_ID_YUKON_EX:
2791 case CHIP_ID_YUKON_SUPR:
2792 case CHIP_ID_YUKON_UL_2:
2793 return 125;
2794
2795 case CHIP_ID_YUKON_FE:
2796 return 100;
2797
2798 case CHIP_ID_YUKON_FE_P:
2799 return 50;
2800
2801 case CHIP_ID_YUKON_XL:
2802 return 156;
2803
2804 default:
2805 BUG();
2806 }
2807 }
2808
2809 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2810 {
2811 return sky2_mhz(hw) * us;
2812 }
2813
2814 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2815 {
2816 return clk / sky2_mhz(hw);
2817 }
2818
2819
2820 static int __devinit sky2_init(struct sky2_hw *hw)
2821 {
2822 u8 t8;
2823
2824 /* Enable all clocks and check for bad PCI access */
2825 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2826
2827 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2828
2829 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2830 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2831
2832 switch(hw->chip_id) {
2833 case CHIP_ID_YUKON_XL:
2834 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2835 break;
2836
2837 case CHIP_ID_YUKON_EC_U:
2838 hw->flags = SKY2_HW_GIGABIT
2839 | SKY2_HW_NEWER_PHY
2840 | SKY2_HW_ADV_POWER_CTL;
2841 break;
2842
2843 case CHIP_ID_YUKON_EX:
2844 hw->flags = SKY2_HW_GIGABIT
2845 | SKY2_HW_NEWER_PHY
2846 | SKY2_HW_NEW_LE
2847 | SKY2_HW_ADV_POWER_CTL;
2848
2849 /* New transmit checksum */
2850 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2851 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2852 break;
2853
2854 case CHIP_ID_YUKON_EC:
2855 /* This rev is really old, and requires untested workarounds */
2856 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2857 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2858 return -EOPNOTSUPP;
2859 }
2860 hw->flags = SKY2_HW_GIGABIT;
2861 break;
2862
2863 case CHIP_ID_YUKON_FE:
2864 break;
2865
2866 case CHIP_ID_YUKON_FE_P:
2867 hw->flags = SKY2_HW_NEWER_PHY
2868 | SKY2_HW_NEW_LE
2869 | SKY2_HW_AUTO_TX_SUM
2870 | SKY2_HW_ADV_POWER_CTL;
2871 break;
2872
2873 case CHIP_ID_YUKON_SUPR:
2874 hw->flags = SKY2_HW_GIGABIT
2875 | SKY2_HW_NEWER_PHY
2876 | SKY2_HW_NEW_LE
2877 | SKY2_HW_AUTO_TX_SUM
2878 | SKY2_HW_ADV_POWER_CTL;
2879 break;
2880
2881 case CHIP_ID_YUKON_UL_2:
2882 hw->flags = SKY2_HW_GIGABIT
2883 | SKY2_HW_ADV_POWER_CTL;
2884 break;
2885
2886 default:
2887 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2888 hw->chip_id);
2889 return -EOPNOTSUPP;
2890 }
2891
2892 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2893 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2894 hw->flags |= SKY2_HW_FIBRE_PHY;
2895
2896 hw->ports = 1;
2897 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2898 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2899 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2900 ++hw->ports;
2901 }
2902
2903 return 0;
2904 }
2905
2906 static void sky2_reset(struct sky2_hw *hw)
2907 {
2908 struct pci_dev *pdev = hw->pdev;
2909 u16 status;
2910 int i, cap;
2911 u32 hwe_mask = Y2_HWE_ALL_MASK;
2912
2913 /* disable ASF */
2914 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2915 status = sky2_read16(hw, HCU_CCSR);
2916 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2917 HCU_CCSR_UC_STATE_MSK);
2918 sky2_write16(hw, HCU_CCSR, status);
2919 } else
2920 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2921 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2922
2923 /* do a SW reset */
2924 sky2_write8(hw, B0_CTST, CS_RST_SET);
2925 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2926
2927 /* allow writes to PCI config */
2928 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2929
2930 /* clear PCI errors, if any */
2931 status = sky2_pci_read16(hw, PCI_STATUS);
2932 status |= PCI_STATUS_ERROR_BITS;
2933 sky2_pci_write16(hw, PCI_STATUS, status);
2934
2935 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2936
2937 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2938 if (cap) {
2939 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2940 0xfffffffful);
2941
2942 /* If error bit is stuck on ignore it */
2943 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2944 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2945 else
2946 hwe_mask |= Y2_IS_PCI_EXP;
2947 }
2948
2949 sky2_power_on(hw);
2950 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2951
2952 for (i = 0; i < hw->ports; i++) {
2953 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2954 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2955
2956 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2957 hw->chip_id == CHIP_ID_YUKON_SUPR)
2958 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2959 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2960 | GMC_BYP_RETR_ON);
2961 }
2962
2963 /* Clear I2C IRQ noise */
2964 sky2_write32(hw, B2_I2C_IRQ, 1);
2965
2966 /* turn off hardware timer (unused) */
2967 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2968 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2969
2970 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2971
2972 /* Turn off descriptor polling */
2973 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2974
2975 /* Turn off receive timestamp */
2976 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2977 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2978
2979 /* enable the Tx Arbiters */
2980 for (i = 0; i < hw->ports; i++)
2981 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2982
2983 /* Initialize ram interface */
2984 for (i = 0; i < hw->ports; i++) {
2985 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2986
2987 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2988 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2989 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2990 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2991 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2992 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2993 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2994 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2995 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2996 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2997 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2998 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2999 }
3000
3001 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3002
3003 for (i = 0; i < hw->ports; i++)
3004 sky2_gmac_reset(hw, i);
3005
3006 memset(hw->st_le, 0, STATUS_LE_BYTES);
3007 hw->st_idx = 0;
3008
3009 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3010 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3011
3012 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3013 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3014
3015 /* Set the list last index */
3016 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3017
3018 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3019 sky2_write8(hw, STAT_FIFO_WM, 16);
3020
3021 /* set Status-FIFO ISR watermark */
3022 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3023 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3024 else
3025 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3026
3027 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3028 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3029 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3030
3031 /* enable status unit */
3032 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3033
3034 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3035 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3036 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3037 }
3038
3039 static void sky2_restart(struct work_struct *work)
3040 {
3041 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3042 struct net_device *dev;
3043 int i, err;
3044
3045 rtnl_lock();
3046 for (i = 0; i < hw->ports; i++) {
3047 dev = hw->dev[i];
3048 if (netif_running(dev))
3049 sky2_down(dev);
3050 }
3051
3052 napi_disable(&hw->napi);
3053 sky2_write32(hw, B0_IMSK, 0);
3054 sky2_reset(hw);
3055 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3056 napi_enable(&hw->napi);
3057
3058 for (i = 0; i < hw->ports; i++) {
3059 dev = hw->dev[i];
3060 if (netif_running(dev)) {
3061 err = sky2_up(dev);
3062 if (err) {
3063 printk(KERN_INFO PFX "%s: could not restart %d\n",
3064 dev->name, err);
3065 dev_close(dev);
3066 }
3067 }
3068 }
3069
3070 rtnl_unlock();
3071 }
3072
3073 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3074 {
3075 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3076 }
3077
3078 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3079 {
3080 const struct sky2_port *sky2 = netdev_priv(dev);
3081
3082 wol->supported = sky2_wol_supported(sky2->hw);
3083 wol->wolopts = sky2->wol;
3084 }
3085
3086 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3087 {
3088 struct sky2_port *sky2 = netdev_priv(dev);
3089 struct sky2_hw *hw = sky2->hw;
3090
3091 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3092 || !device_can_wakeup(&hw->pdev->dev))
3093 return -EOPNOTSUPP;
3094
3095 sky2->wol = wol->wolopts;
3096
3097 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3098 hw->chip_id == CHIP_ID_YUKON_EX ||
3099 hw->chip_id == CHIP_ID_YUKON_FE_P)
3100 sky2_write32(hw, B0_CTST, sky2->wol
3101 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3102
3103 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3104
3105 if (!netif_running(dev))
3106 sky2_wol_init(sky2);
3107 return 0;
3108 }
3109
3110 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3111 {
3112 if (sky2_is_copper(hw)) {
3113 u32 modes = SUPPORTED_10baseT_Half
3114 | SUPPORTED_10baseT_Full
3115 | SUPPORTED_100baseT_Half
3116 | SUPPORTED_100baseT_Full
3117 | SUPPORTED_Autoneg | SUPPORTED_TP;
3118
3119 if (hw->flags & SKY2_HW_GIGABIT)
3120 modes |= SUPPORTED_1000baseT_Half
3121 | SUPPORTED_1000baseT_Full;
3122 return modes;
3123 } else
3124 return SUPPORTED_1000baseT_Half
3125 | SUPPORTED_1000baseT_Full
3126 | SUPPORTED_Autoneg
3127 | SUPPORTED_FIBRE;
3128 }
3129
3130 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3131 {
3132 struct sky2_port *sky2 = netdev_priv(dev);
3133 struct sky2_hw *hw = sky2->hw;
3134
3135 ecmd->transceiver = XCVR_INTERNAL;
3136 ecmd->supported = sky2_supported_modes(hw);
3137 ecmd->phy_address = PHY_ADDR_MARV;
3138 if (sky2_is_copper(hw)) {
3139 ecmd->port = PORT_TP;
3140 ecmd->speed = sky2->speed;
3141 } else {
3142 ecmd->speed = SPEED_1000;
3143 ecmd->port = PORT_FIBRE;
3144 }
3145
3146 ecmd->advertising = sky2->advertising;
3147 ecmd->autoneg = sky2->autoneg;
3148 ecmd->duplex = sky2->duplex;
3149 return 0;
3150 }
3151
3152 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3153 {
3154 struct sky2_port *sky2 = netdev_priv(dev);
3155 const struct sky2_hw *hw = sky2->hw;
3156 u32 supported = sky2_supported_modes(hw);
3157
3158 if (ecmd->autoneg == AUTONEG_ENABLE) {
3159 ecmd->advertising = supported;
3160 sky2->duplex = -1;
3161 sky2->speed = -1;
3162 } else {
3163 u32 setting;
3164
3165 switch (ecmd->speed) {
3166 case SPEED_1000:
3167 if (ecmd->duplex == DUPLEX_FULL)
3168 setting = SUPPORTED_1000baseT_Full;
3169 else if (ecmd->duplex == DUPLEX_HALF)
3170 setting = SUPPORTED_1000baseT_Half;
3171 else
3172 return -EINVAL;
3173 break;
3174 case SPEED_100:
3175 if (ecmd->duplex == DUPLEX_FULL)
3176 setting = SUPPORTED_100baseT_Full;
3177 else if (ecmd->duplex == DUPLEX_HALF)
3178 setting = SUPPORTED_100baseT_Half;
3179 else
3180 return -EINVAL;
3181 break;
3182
3183 case SPEED_10:
3184 if (ecmd->duplex == DUPLEX_FULL)
3185 setting = SUPPORTED_10baseT_Full;
3186 else if (ecmd->duplex == DUPLEX_HALF)
3187 setting = SUPPORTED_10baseT_Half;
3188 else
3189 return -EINVAL;
3190 break;
3191 default:
3192 return -EINVAL;
3193 }
3194
3195 if ((setting & supported) == 0)
3196 return -EINVAL;
3197
3198 sky2->speed = ecmd->speed;
3199 sky2->duplex = ecmd->duplex;
3200 }
3201
3202 sky2->autoneg = ecmd->autoneg;
3203 sky2->advertising = ecmd->advertising;
3204
3205 if (netif_running(dev)) {
3206 sky2_phy_reinit(sky2);
3207 sky2_set_multicast(dev);
3208 }
3209
3210 return 0;
3211 }
3212
3213 static void sky2_get_drvinfo(struct net_device *dev,
3214 struct ethtool_drvinfo *info)
3215 {
3216 struct sky2_port *sky2 = netdev_priv(dev);
3217
3218 strcpy(info->driver, DRV_NAME);
3219 strcpy(info->version, DRV_VERSION);
3220 strcpy(info->fw_version, "N/A");
3221 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3222 }
3223
3224 static const struct sky2_stat {
3225 char name[ETH_GSTRING_LEN];
3226 u16 offset;
3227 } sky2_stats[] = {
3228 { "tx_bytes", GM_TXO_OK_HI },
3229 { "rx_bytes", GM_RXO_OK_HI },
3230 { "tx_broadcast", GM_TXF_BC_OK },
3231 { "rx_broadcast", GM_RXF_BC_OK },
3232 { "tx_multicast", GM_TXF_MC_OK },
3233 { "rx_multicast", GM_RXF_MC_OK },
3234 { "tx_unicast", GM_TXF_UC_OK },
3235 { "rx_unicast", GM_RXF_UC_OK },
3236 { "tx_mac_pause", GM_TXF_MPAUSE },
3237 { "rx_mac_pause", GM_RXF_MPAUSE },
3238 { "collisions", GM_TXF_COL },
3239 { "late_collision",GM_TXF_LAT_COL },
3240 { "aborted", GM_TXF_ABO_COL },
3241 { "single_collisions", GM_TXF_SNG_COL },
3242 { "multi_collisions", GM_TXF_MUL_COL },
3243
3244 { "rx_short", GM_RXF_SHT },
3245 { "rx_runt", GM_RXE_FRAG },
3246 { "rx_64_byte_packets", GM_RXF_64B },
3247 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3248 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3249 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3250 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3251 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3252 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3253 { "rx_too_long", GM_RXF_LNG_ERR },
3254 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3255 { "rx_jabber", GM_RXF_JAB_PKT },
3256 { "rx_fcs_error", GM_RXF_FCS_ERR },
3257
3258 { "tx_64_byte_packets", GM_TXF_64B },
3259 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3260 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3261 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3262 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3263 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3264 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3265 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3266 };
3267
3268 static u32 sky2_get_rx_csum(struct net_device *dev)
3269 {
3270 struct sky2_port *sky2 = netdev_priv(dev);
3271
3272 return sky2->rx_csum;
3273 }
3274
3275 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3276 {
3277 struct sky2_port *sky2 = netdev_priv(dev);
3278
3279 sky2->rx_csum = data;
3280
3281 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3282 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3283
3284 return 0;
3285 }
3286
3287 static u32 sky2_get_msglevel(struct net_device *netdev)
3288 {
3289 struct sky2_port *sky2 = netdev_priv(netdev);
3290 return sky2->msg_enable;
3291 }
3292
3293 static int sky2_nway_reset(struct net_device *dev)
3294 {
3295 struct sky2_port *sky2 = netdev_priv(dev);
3296
3297 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3298 return -EINVAL;
3299
3300 sky2_phy_reinit(sky2);
3301 sky2_set_multicast(dev);
3302
3303 return 0;
3304 }
3305
3306 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3307 {
3308 struct sky2_hw *hw = sky2->hw;
3309 unsigned port = sky2->port;
3310 int i;
3311
3312 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3313 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3314 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3315 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3316
3317 for (i = 2; i < count; i++)
3318 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3319 }
3320
3321 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3322 {
3323 struct sky2_port *sky2 = netdev_priv(netdev);
3324 sky2->msg_enable = value;
3325 }
3326
3327 static int sky2_get_sset_count(struct net_device *dev, int sset)
3328 {
3329 switch (sset) {
3330 case ETH_SS_STATS:
3331 return ARRAY_SIZE(sky2_stats);
3332 default:
3333 return -EOPNOTSUPP;
3334 }
3335 }
3336
3337 static void sky2_get_ethtool_stats(struct net_device *dev,
3338 struct ethtool_stats *stats, u64 * data)
3339 {
3340 struct sky2_port *sky2 = netdev_priv(dev);
3341
3342 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3343 }
3344
3345 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3346 {
3347 int i;
3348
3349 switch (stringset) {
3350 case ETH_SS_STATS:
3351 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3352 memcpy(data + i * ETH_GSTRING_LEN,
3353 sky2_stats[i].name, ETH_GSTRING_LEN);
3354 break;
3355 }
3356 }
3357
3358 static int sky2_set_mac_address(struct net_device *dev, void *p)
3359 {
3360 struct sky2_port *sky2 = netdev_priv(dev);
3361 struct sky2_hw *hw = sky2->hw;
3362 unsigned port = sky2->port;
3363 const struct sockaddr *addr = p;
3364
3365 if (!is_valid_ether_addr(addr->sa_data))
3366 return -EADDRNOTAVAIL;
3367
3368 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3369 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3370 dev->dev_addr, ETH_ALEN);
3371 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3372 dev->dev_addr, ETH_ALEN);
3373
3374 /* virtual address for data */
3375 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3376
3377 /* physical address: used for pause frames */
3378 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3379
3380 return 0;
3381 }
3382
3383 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3384 {
3385 u32 bit;
3386
3387 bit = ether_crc(ETH_ALEN, addr) & 63;
3388 filter[bit >> 3] |= 1 << (bit & 7);
3389 }
3390
3391 static void sky2_set_multicast(struct net_device *dev)
3392 {
3393 struct sky2_port *sky2 = netdev_priv(dev);
3394 struct sky2_hw *hw = sky2->hw;
3395 unsigned port = sky2->port;
3396 struct dev_mc_list *list = dev->mc_list;
3397 u16 reg;
3398 u8 filter[8];
3399 int rx_pause;
3400 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3401
3402 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3403 memset(filter, 0, sizeof(filter));
3404
3405 reg = gma_read16(hw, port, GM_RX_CTRL);
3406 reg |= GM_RXCR_UCF_ENA;
3407
3408 if (dev->flags & IFF_PROMISC) /* promiscuous */
3409 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3410 else if (dev->flags & IFF_ALLMULTI)
3411 memset(filter, 0xff, sizeof(filter));
3412 else if (dev->mc_count == 0 && !rx_pause)
3413 reg &= ~GM_RXCR_MCF_ENA;
3414 else {
3415 int i;
3416 reg |= GM_RXCR_MCF_ENA;
3417
3418 if (rx_pause)
3419 sky2_add_filter(filter, pause_mc_addr);
3420
3421 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3422 sky2_add_filter(filter, list->dmi_addr);
3423 }
3424
3425 gma_write16(hw, port, GM_MC_ADDR_H1,
3426 (u16) filter[0] | ((u16) filter[1] << 8));
3427 gma_write16(hw, port, GM_MC_ADDR_H2,
3428 (u16) filter[2] | ((u16) filter[3] << 8));
3429 gma_write16(hw, port, GM_MC_ADDR_H3,
3430 (u16) filter[4] | ((u16) filter[5] << 8));
3431 gma_write16(hw, port, GM_MC_ADDR_H4,
3432 (u16) filter[6] | ((u16) filter[7] << 8));
3433
3434 gma_write16(hw, port, GM_RX_CTRL, reg);
3435 }
3436
3437 /* Can have one global because blinking is controlled by
3438 * ethtool and that is always under RTNL mutex
3439 */
3440 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3441 {
3442 struct sky2_hw *hw = sky2->hw;
3443 unsigned port = sky2->port;
3444
3445 spin_lock_bh(&sky2->phy_lock);
3446 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3447 hw->chip_id == CHIP_ID_YUKON_EX ||
3448 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3449 u16 pg;
3450 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3451 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3452
3453 switch (mode) {
3454 case MO_LED_OFF:
3455 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3456 PHY_M_LEDC_LOS_CTRL(8) |
3457 PHY_M_LEDC_INIT_CTRL(8) |
3458 PHY_M_LEDC_STA1_CTRL(8) |
3459 PHY_M_LEDC_STA0_CTRL(8));
3460 break;
3461 case MO_LED_ON:
3462 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3463 PHY_M_LEDC_LOS_CTRL(9) |
3464 PHY_M_LEDC_INIT_CTRL(9) |
3465 PHY_M_LEDC_STA1_CTRL(9) |
3466 PHY_M_LEDC_STA0_CTRL(9));
3467 break;
3468 case MO_LED_BLINK:
3469 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3470 PHY_M_LEDC_LOS_CTRL(0xa) |
3471 PHY_M_LEDC_INIT_CTRL(0xa) |
3472 PHY_M_LEDC_STA1_CTRL(0xa) |
3473 PHY_M_LEDC_STA0_CTRL(0xa));
3474 break;
3475 case MO_LED_NORM:
3476 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3477 PHY_M_LEDC_LOS_CTRL(1) |
3478 PHY_M_LEDC_INIT_CTRL(8) |
3479 PHY_M_LEDC_STA1_CTRL(7) |
3480 PHY_M_LEDC_STA0_CTRL(7));
3481 }
3482
3483 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3484 } else
3485 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3486 PHY_M_LED_MO_DUP(mode) |
3487 PHY_M_LED_MO_10(mode) |
3488 PHY_M_LED_MO_100(mode) |
3489 PHY_M_LED_MO_1000(mode) |
3490 PHY_M_LED_MO_RX(mode) |
3491 PHY_M_LED_MO_TX(mode));
3492
3493 spin_unlock_bh(&sky2->phy_lock);
3494 }
3495
3496 /* blink LED's for finding board */
3497 static int sky2_phys_id(struct net_device *dev, u32 data)
3498 {
3499 struct sky2_port *sky2 = netdev_priv(dev);
3500 unsigned int i;
3501
3502 if (data == 0)
3503 data = UINT_MAX;
3504
3505 for (i = 0; i < data; i++) {
3506 sky2_led(sky2, MO_LED_ON);
3507 if (msleep_interruptible(500))
3508 break;
3509 sky2_led(sky2, MO_LED_OFF);
3510 if (msleep_interruptible(500))
3511 break;
3512 }
3513 sky2_led(sky2, MO_LED_NORM);
3514
3515 return 0;
3516 }
3517
3518 static void sky2_get_pauseparam(struct net_device *dev,
3519 struct ethtool_pauseparam *ecmd)
3520 {
3521 struct sky2_port *sky2 = netdev_priv(dev);
3522
3523 switch (sky2->flow_mode) {
3524 case FC_NONE:
3525 ecmd->tx_pause = ecmd->rx_pause = 0;
3526 break;
3527 case FC_TX:
3528 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3529 break;
3530 case FC_RX:
3531 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3532 break;
3533 case FC_BOTH:
3534 ecmd->tx_pause = ecmd->rx_pause = 1;
3535 }
3536
3537 ecmd->autoneg = sky2->autoneg;
3538 }
3539
3540 static int sky2_set_pauseparam(struct net_device *dev,
3541 struct ethtool_pauseparam *ecmd)
3542 {
3543 struct sky2_port *sky2 = netdev_priv(dev);
3544
3545 sky2->autoneg = ecmd->autoneg;
3546 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3547
3548 if (netif_running(dev))
3549 sky2_phy_reinit(sky2);
3550
3551 return 0;
3552 }
3553
3554 static int sky2_get_coalesce(struct net_device *dev,
3555 struct ethtool_coalesce *ecmd)
3556 {
3557 struct sky2_port *sky2 = netdev_priv(dev);
3558 struct sky2_hw *hw = sky2->hw;
3559
3560 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3561 ecmd->tx_coalesce_usecs = 0;
3562 else {
3563 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3564 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3565 }
3566 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3567
3568 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3569 ecmd->rx_coalesce_usecs = 0;
3570 else {
3571 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3572 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3573 }
3574 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3575
3576 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3577 ecmd->rx_coalesce_usecs_irq = 0;
3578 else {
3579 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3580 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3581 }
3582
3583 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3584
3585 return 0;
3586 }
3587
3588 /* Note: this affect both ports */
3589 static int sky2_set_coalesce(struct net_device *dev,
3590 struct ethtool_coalesce *ecmd)
3591 {
3592 struct sky2_port *sky2 = netdev_priv(dev);
3593 struct sky2_hw *hw = sky2->hw;
3594 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3595
3596 if (ecmd->tx_coalesce_usecs > tmax ||
3597 ecmd->rx_coalesce_usecs > tmax ||
3598 ecmd->rx_coalesce_usecs_irq > tmax)
3599 return -EINVAL;
3600
3601 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3602 return -EINVAL;
3603 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3604 return -EINVAL;
3605 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3606 return -EINVAL;
3607
3608 if (ecmd->tx_coalesce_usecs == 0)
3609 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3610 else {
3611 sky2_write32(hw, STAT_TX_TIMER_INI,
3612 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3613 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3614 }
3615 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3616
3617 if (ecmd->rx_coalesce_usecs == 0)
3618 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3619 else {
3620 sky2_write32(hw, STAT_LEV_TIMER_INI,
3621 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3622 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3623 }
3624 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3625
3626 if (ecmd->rx_coalesce_usecs_irq == 0)
3627 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3628 else {
3629 sky2_write32(hw, STAT_ISR_TIMER_INI,
3630 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3631 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3632 }
3633 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3634 return 0;
3635 }
3636
3637 static void sky2_get_ringparam(struct net_device *dev,
3638 struct ethtool_ringparam *ering)
3639 {
3640 struct sky2_port *sky2 = netdev_priv(dev);
3641
3642 ering->rx_max_pending = RX_MAX_PENDING;
3643 ering->rx_mini_max_pending = 0;
3644 ering->rx_jumbo_max_pending = 0;
3645 ering->tx_max_pending = TX_RING_SIZE - 1;
3646
3647 ering->rx_pending = sky2->rx_pending;
3648 ering->rx_mini_pending = 0;
3649 ering->rx_jumbo_pending = 0;
3650 ering->tx_pending = sky2->tx_pending;
3651 }
3652
3653 static int sky2_set_ringparam(struct net_device *dev,
3654 struct ethtool_ringparam *ering)
3655 {
3656 struct sky2_port *sky2 = netdev_priv(dev);
3657 int err = 0;
3658
3659 if (ering->rx_pending > RX_MAX_PENDING ||
3660 ering->rx_pending < 8 ||
3661 ering->tx_pending < MAX_SKB_TX_LE ||
3662 ering->tx_pending > TX_RING_SIZE - 1)
3663 return -EINVAL;
3664
3665 if (netif_running(dev))
3666 sky2_down(dev);
3667
3668 sky2->rx_pending = ering->rx_pending;
3669 sky2->tx_pending = ering->tx_pending;
3670
3671 if (netif_running(dev)) {
3672 err = sky2_up(dev);
3673 if (err)
3674 dev_close(dev);
3675 }
3676
3677 return err;
3678 }
3679
3680 static int sky2_get_regs_len(struct net_device *dev)
3681 {
3682 return 0x4000;
3683 }
3684
3685 /*
3686 * Returns copy of control register region
3687 * Note: ethtool_get_regs always provides full size (16k) buffer
3688 */
3689 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3690 void *p)
3691 {
3692 const struct sky2_port *sky2 = netdev_priv(dev);
3693 const void __iomem *io = sky2->hw->regs;
3694 unsigned int b;
3695
3696 regs->version = 1;
3697
3698 for (b = 0; b < 128; b++) {
3699 /* This complicated switch statement is to make sure and
3700 * only access regions that are unreserved.
3701 * Some blocks are only valid on dual port cards.
3702 * and block 3 has some special diagnostic registers that
3703 * are poison.
3704 */
3705 switch (b) {
3706 case 3:
3707 /* skip diagnostic ram region */
3708 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3709 break;
3710
3711 /* dual port cards only */
3712 case 5: /* Tx Arbiter 2 */
3713 case 9: /* RX2 */
3714 case 14 ... 15: /* TX2 */
3715 case 17: case 19: /* Ram Buffer 2 */
3716 case 22 ... 23: /* Tx Ram Buffer 2 */
3717 case 25: /* Rx MAC Fifo 1 */
3718 case 27: /* Tx MAC Fifo 2 */
3719 case 31: /* GPHY 2 */
3720 case 40 ... 47: /* Pattern Ram 2 */
3721 case 52: case 54: /* TCP Segmentation 2 */
3722 case 112 ... 116: /* GMAC 2 */
3723 if (sky2->hw->ports == 1)
3724 goto reserved;
3725 /* fall through */
3726 case 0: /* Control */
3727 case 2: /* Mac address */
3728 case 4: /* Tx Arbiter 1 */
3729 case 7: /* PCI express reg */
3730 case 8: /* RX1 */
3731 case 12 ... 13: /* TX1 */
3732 case 16: case 18:/* Rx Ram Buffer 1 */
3733 case 20 ... 21: /* Tx Ram Buffer 1 */
3734 case 24: /* Rx MAC Fifo 1 */
3735 case 26: /* Tx MAC Fifo 1 */
3736 case 28 ... 29: /* Descriptor and status unit */
3737 case 30: /* GPHY 1*/
3738 case 32 ... 39: /* Pattern Ram 1 */
3739 case 48: case 50: /* TCP Segmentation 1 */
3740 case 56 ... 60: /* PCI space */
3741 case 80 ... 84: /* GMAC 1 */
3742 memcpy_fromio(p, io, 128);
3743 break;
3744 default:
3745 reserved:
3746 memset(p, 0, 128);
3747 }
3748
3749 p += 128;
3750 io += 128;
3751 }
3752 }
3753
3754 /* In order to do Jumbo packets on these chips, need to turn off the
3755 * transmit store/forward. Therefore checksum offload won't work.
3756 */
3757 static int no_tx_offload(struct net_device *dev)
3758 {
3759 const struct sky2_port *sky2 = netdev_priv(dev);
3760 const struct sky2_hw *hw = sky2->hw;
3761
3762 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3763 }
3764
3765 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3766 {
3767 if (data && no_tx_offload(dev))
3768 return -EINVAL;
3769
3770 return ethtool_op_set_tx_csum(dev, data);
3771 }
3772
3773
3774 static int sky2_set_tso(struct net_device *dev, u32 data)
3775 {
3776 if (data && no_tx_offload(dev))
3777 return -EINVAL;
3778
3779 return ethtool_op_set_tso(dev, data);
3780 }
3781
3782 static int sky2_get_eeprom_len(struct net_device *dev)
3783 {
3784 struct sky2_port *sky2 = netdev_priv(dev);
3785 struct sky2_hw *hw = sky2->hw;
3786 u16 reg2;
3787
3788 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3789 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3790 }
3791
3792 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3793 {
3794 unsigned long start = jiffies;
3795
3796 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3797 /* Can take up to 10.6 ms for write */
3798 if (time_after(jiffies, start + HZ/4)) {
3799 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3800 return -ETIMEDOUT;
3801 }
3802 mdelay(1);
3803 }
3804
3805 return 0;
3806 }
3807
3808 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3809 u16 offset, size_t length)
3810 {
3811 int rc = 0;
3812
3813 while (length > 0) {
3814 u32 val;
3815
3816 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3817 rc = sky2_vpd_wait(hw, cap, 0);
3818 if (rc)
3819 break;
3820
3821 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3822
3823 memcpy(data, &val, min(sizeof(val), length));
3824 offset += sizeof(u32);
3825 data += sizeof(u32);
3826 length -= sizeof(u32);
3827 }
3828
3829 return rc;
3830 }
3831
3832 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3833 u16 offset, unsigned int length)
3834 {
3835 unsigned int i;
3836 int rc = 0;
3837
3838 for (i = 0; i < length; i += sizeof(u32)) {
3839 u32 val = *(u32 *)(data + i);
3840
3841 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3842 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3843
3844 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3845 if (rc)
3846 break;
3847 }
3848 return rc;
3849 }
3850
3851 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3852 u8 *data)
3853 {
3854 struct sky2_port *sky2 = netdev_priv(dev);
3855 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3856
3857 if (!cap)
3858 return -EINVAL;
3859
3860 eeprom->magic = SKY2_EEPROM_MAGIC;
3861
3862 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3863 }
3864
3865 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3866 u8 *data)
3867 {
3868 struct sky2_port *sky2 = netdev_priv(dev);
3869 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3870
3871 if (!cap)
3872 return -EINVAL;
3873
3874 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3875 return -EINVAL;
3876
3877 /* Partial writes not supported */
3878 if ((eeprom->offset & 3) || (eeprom->len & 3))
3879 return -EINVAL;
3880
3881 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3882 }
3883
3884
3885 static const struct ethtool_ops sky2_ethtool_ops = {
3886 .get_settings = sky2_get_settings,
3887 .set_settings = sky2_set_settings,
3888 .get_drvinfo = sky2_get_drvinfo,
3889 .get_wol = sky2_get_wol,
3890 .set_wol = sky2_set_wol,
3891 .get_msglevel = sky2_get_msglevel,
3892 .set_msglevel = sky2_set_msglevel,
3893 .nway_reset = sky2_nway_reset,
3894 .get_regs_len = sky2_get_regs_len,
3895 .get_regs = sky2_get_regs,
3896 .get_link = ethtool_op_get_link,
3897 .get_eeprom_len = sky2_get_eeprom_len,
3898 .get_eeprom = sky2_get_eeprom,
3899 .set_eeprom = sky2_set_eeprom,
3900 .set_sg = ethtool_op_set_sg,
3901 .set_tx_csum = sky2_set_tx_csum,
3902 .set_tso = sky2_set_tso,
3903 .get_rx_csum = sky2_get_rx_csum,
3904 .set_rx_csum = sky2_set_rx_csum,
3905 .get_strings = sky2_get_strings,
3906 .get_coalesce = sky2_get_coalesce,
3907 .set_coalesce = sky2_set_coalesce,
3908 .get_ringparam = sky2_get_ringparam,
3909 .set_ringparam = sky2_set_ringparam,
3910 .get_pauseparam = sky2_get_pauseparam,
3911 .set_pauseparam = sky2_set_pauseparam,
3912 .phys_id = sky2_phys_id,
3913 .get_sset_count = sky2_get_sset_count,
3914 .get_ethtool_stats = sky2_get_ethtool_stats,
3915 };
3916
3917 #ifdef CONFIG_SKY2_DEBUG
3918
3919 static struct dentry *sky2_debug;
3920
3921
3922 /*
3923 * Read and parse the first part of Vital Product Data
3924 */
3925 #define VPD_SIZE 128
3926 #define VPD_MAGIC 0x82
3927
3928 static const struct vpd_tag {
3929 char tag[2];
3930 char *label;
3931 } vpd_tags[] = {
3932 { "PN", "Part Number" },
3933 { "EC", "Engineering Level" },
3934 { "MN", "Manufacturer" },
3935 { "SN", "Serial Number" },
3936 { "YA", "Asset Tag" },
3937 { "VL", "First Error Log Message" },
3938 { "VF", "Second Error Log Message" },
3939 { "VB", "Boot Agent ROM Configuration" },
3940 { "VE", "EFI UNDI Configuration" },
3941 };
3942
3943 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3944 {
3945 size_t vpd_size;
3946 loff_t offs;
3947 u8 len;
3948 unsigned char *buf;
3949 u16 reg2;
3950
3951 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3952 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3953
3954 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3955 buf = kmalloc(vpd_size, GFP_KERNEL);
3956 if (!buf) {
3957 seq_puts(seq, "no memory!\n");
3958 return;
3959 }
3960
3961 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
3962 seq_puts(seq, "VPD read failed\n");
3963 goto out;
3964 }
3965
3966 if (buf[0] != VPD_MAGIC) {
3967 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
3968 goto out;
3969 }
3970 len = buf[1];
3971 if (len == 0 || len > vpd_size - 4) {
3972 seq_printf(seq, "Invalid id length: %d\n", len);
3973 goto out;
3974 }
3975
3976 seq_printf(seq, "%.*s\n", len, buf + 3);
3977 offs = len + 3;
3978
3979 while (offs < vpd_size - 4) {
3980 int i;
3981
3982 if (!memcmp("RW", buf + offs, 2)) /* end marker */
3983 break;
3984 len = buf[offs + 2];
3985 if (offs + len + 3 >= vpd_size)
3986 break;
3987
3988 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
3989 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
3990 seq_printf(seq, " %s: %.*s\n",
3991 vpd_tags[i].label, len, buf + offs + 3);
3992 break;
3993 }
3994 }
3995 offs += len + 3;
3996 }
3997 out:
3998 kfree(buf);
3999 }
4000
4001 static int sky2_debug_show(struct seq_file *seq, void *v)
4002 {
4003 struct net_device *dev = seq->private;
4004 const struct sky2_port *sky2 = netdev_priv(dev);
4005 struct sky2_hw *hw = sky2->hw;
4006 unsigned port = sky2->port;
4007 unsigned idx, last;
4008 int sop;
4009
4010 sky2_show_vpd(seq, hw);
4011
4012 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4013 sky2_read32(hw, B0_ISRC),
4014 sky2_read32(hw, B0_IMSK),
4015 sky2_read32(hw, B0_Y2_SP_ICR));
4016
4017 if (!netif_running(dev)) {
4018 seq_printf(seq, "network not running\n");
4019 return 0;
4020 }
4021
4022 napi_disable(&hw->napi);
4023 last = sky2_read16(hw, STAT_PUT_IDX);
4024
4025 if (hw->st_idx == last)
4026 seq_puts(seq, "Status ring (empty)\n");
4027 else {
4028 seq_puts(seq, "Status ring\n");
4029 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4030 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4031 const struct sky2_status_le *le = hw->st_le + idx;
4032 seq_printf(seq, "[%d] %#x %d %#x\n",
4033 idx, le->opcode, le->length, le->status);
4034 }
4035 seq_puts(seq, "\n");
4036 }
4037
4038 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4039 sky2->tx_cons, sky2->tx_prod,
4040 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4041 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4042
4043 /* Dump contents of tx ring */
4044 sop = 1;
4045 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4046 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4047 const struct sky2_tx_le *le = sky2->tx_le + idx;
4048 u32 a = le32_to_cpu(le->addr);
4049
4050 if (sop)
4051 seq_printf(seq, "%u:", idx);
4052 sop = 0;
4053
4054 switch(le->opcode & ~HW_OWNER) {
4055 case OP_ADDR64:
4056 seq_printf(seq, " %#x:", a);
4057 break;
4058 case OP_LRGLEN:
4059 seq_printf(seq, " mtu=%d", a);
4060 break;
4061 case OP_VLAN:
4062 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4063 break;
4064 case OP_TCPLISW:
4065 seq_printf(seq, " csum=%#x", a);
4066 break;
4067 case OP_LARGESEND:
4068 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4069 break;
4070 case OP_PACKET:
4071 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4072 break;
4073 case OP_BUFFER:
4074 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4075 break;
4076 default:
4077 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4078 a, le16_to_cpu(le->length));
4079 }
4080
4081 if (le->ctrl & EOP) {
4082 seq_putc(seq, '\n');
4083 sop = 1;
4084 }
4085 }
4086
4087 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4088 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4089 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4090 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4091
4092 sky2_read32(hw, B0_Y2_SP_LISR);
4093 napi_enable(&hw->napi);
4094 return 0;
4095 }
4096
4097 static int sky2_debug_open(struct inode *inode, struct file *file)
4098 {
4099 return single_open(file, sky2_debug_show, inode->i_private);
4100 }
4101
4102 static const struct file_operations sky2_debug_fops = {
4103 .owner = THIS_MODULE,
4104 .open = sky2_debug_open,
4105 .read = seq_read,
4106 .llseek = seq_lseek,
4107 .release = single_release,
4108 };
4109
4110 /*
4111 * Use network device events to create/remove/rename
4112 * debugfs file entries
4113 */
4114 static int sky2_device_event(struct notifier_block *unused,
4115 unsigned long event, void *ptr)
4116 {
4117 struct net_device *dev = ptr;
4118 struct sky2_port *sky2 = netdev_priv(dev);
4119
4120 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4121 return NOTIFY_DONE;
4122
4123 switch(event) {
4124 case NETDEV_CHANGENAME:
4125 if (sky2->debugfs) {
4126 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4127 sky2_debug, dev->name);
4128 }
4129 break;
4130
4131 case NETDEV_GOING_DOWN:
4132 if (sky2->debugfs) {
4133 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4134 dev->name);
4135 debugfs_remove(sky2->debugfs);
4136 sky2->debugfs = NULL;
4137 }
4138 break;
4139
4140 case NETDEV_UP:
4141 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4142 sky2_debug, dev,
4143 &sky2_debug_fops);
4144 if (IS_ERR(sky2->debugfs))
4145 sky2->debugfs = NULL;
4146 }
4147
4148 return NOTIFY_DONE;
4149 }
4150
4151 static struct notifier_block sky2_notifier = {
4152 .notifier_call = sky2_device_event,
4153 };
4154
4155
4156 static __init void sky2_debug_init(void)
4157 {
4158 struct dentry *ent;
4159
4160 ent = debugfs_create_dir("sky2", NULL);
4161 if (!ent || IS_ERR(ent))
4162 return;
4163
4164 sky2_debug = ent;
4165 register_netdevice_notifier(&sky2_notifier);
4166 }
4167
4168 static __exit void sky2_debug_cleanup(void)
4169 {
4170 if (sky2_debug) {
4171 unregister_netdevice_notifier(&sky2_notifier);
4172 debugfs_remove(sky2_debug);
4173 sky2_debug = NULL;
4174 }
4175 }
4176
4177 #else
4178 #define sky2_debug_init()
4179 #define sky2_debug_cleanup()
4180 #endif
4181
4182 /* Two copies of network device operations to handle special case of
4183 not allowing netpoll on second port */
4184 static const struct net_device_ops sky2_netdev_ops[2] = {
4185 {
4186 .ndo_open = sky2_up,
4187 .ndo_stop = sky2_down,
4188 .ndo_start_xmit = sky2_xmit_frame,
4189 .ndo_do_ioctl = sky2_ioctl,
4190 .ndo_validate_addr = eth_validate_addr,
4191 .ndo_set_mac_address = sky2_set_mac_address,
4192 .ndo_set_multicast_list = sky2_set_multicast,
4193 .ndo_change_mtu = sky2_change_mtu,
4194 .ndo_tx_timeout = sky2_tx_timeout,
4195 #ifdef SKY2_VLAN_TAG_USED
4196 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4197 #endif
4198 #ifdef CONFIG_NET_POLL_CONTROLLER
4199 .ndo_poll_controller = sky2_netpoll,
4200 #endif
4201 },
4202 {
4203 .ndo_open = sky2_up,
4204 .ndo_stop = sky2_down,
4205 .ndo_start_xmit = sky2_xmit_frame,
4206 .ndo_do_ioctl = sky2_ioctl,
4207 .ndo_validate_addr = eth_validate_addr,
4208 .ndo_set_mac_address = sky2_set_mac_address,
4209 .ndo_set_multicast_list = sky2_set_multicast,
4210 .ndo_change_mtu = sky2_change_mtu,
4211 .ndo_tx_timeout = sky2_tx_timeout,
4212 #ifdef SKY2_VLAN_TAG_USED
4213 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4214 #endif
4215 },
4216 };
4217
4218 /* Initialize network device */
4219 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4220 unsigned port,
4221 int highmem, int wol)
4222 {
4223 struct sky2_port *sky2;
4224 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4225
4226 if (!dev) {
4227 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4228 return NULL;
4229 }
4230
4231 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4232 dev->irq = hw->pdev->irq;
4233 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4234 dev->watchdog_timeo = TX_WATCHDOG;
4235 dev->netdev_ops = &sky2_netdev_ops[port];
4236
4237 sky2 = netdev_priv(dev);
4238 sky2->netdev = dev;
4239 sky2->hw = hw;
4240 sky2->msg_enable = netif_msg_init(debug, default_msg);
4241
4242 /* Auto speed and flow control */
4243 sky2->autoneg = AUTONEG_ENABLE;
4244 sky2->flow_mode = FC_BOTH;
4245
4246 sky2->duplex = -1;
4247 sky2->speed = -1;
4248 sky2->advertising = sky2_supported_modes(hw);
4249 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4250 sky2->wol = wol;
4251
4252 spin_lock_init(&sky2->phy_lock);
4253 sky2->tx_pending = TX_DEF_PENDING;
4254 sky2->rx_pending = RX_DEF_PENDING;
4255
4256 hw->dev[port] = dev;
4257
4258 sky2->port = port;
4259
4260 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4261 if (highmem)
4262 dev->features |= NETIF_F_HIGHDMA;
4263
4264 #ifdef SKY2_VLAN_TAG_USED
4265 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4266 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4267 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4268 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4269 }
4270 #endif
4271
4272 /* read the mac address */
4273 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4274 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4275
4276 return dev;
4277 }
4278
4279 static void __devinit sky2_show_addr(struct net_device *dev)
4280 {
4281 const struct sky2_port *sky2 = netdev_priv(dev);
4282
4283 if (netif_msg_probe(sky2))
4284 printk(KERN_INFO PFX "%s: addr %pM\n",
4285 dev->name, dev->dev_addr);
4286 }
4287
4288 /* Handle software interrupt used during MSI test */
4289 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4290 {
4291 struct sky2_hw *hw = dev_id;
4292 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4293
4294 if (status == 0)
4295 return IRQ_NONE;
4296
4297 if (status & Y2_IS_IRQ_SW) {
4298 hw->flags |= SKY2_HW_USE_MSI;
4299 wake_up(&hw->msi_wait);
4300 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4301 }
4302 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4303
4304 return IRQ_HANDLED;
4305 }
4306
4307 /* Test interrupt path by forcing a a software IRQ */
4308 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4309 {
4310 struct pci_dev *pdev = hw->pdev;
4311 int err;
4312
4313 init_waitqueue_head (&hw->msi_wait);
4314
4315 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4316
4317 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4318 if (err) {
4319 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4320 return err;
4321 }
4322
4323 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4324 sky2_read8(hw, B0_CTST);
4325
4326 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4327
4328 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4329 /* MSI test failed, go back to INTx mode */
4330 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4331 "switching to INTx mode.\n");
4332
4333 err = -EOPNOTSUPP;
4334 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4335 }
4336
4337 sky2_write32(hw, B0_IMSK, 0);
4338 sky2_read32(hw, B0_IMSK);
4339
4340 free_irq(pdev->irq, hw);
4341
4342 return err;
4343 }
4344
4345 /* This driver supports yukon2 chipset only */
4346 static const char *sky2_name(u8 chipid, char *buf, int sz)
4347 {
4348 const char *name[] = {
4349 "XL", /* 0xb3 */
4350 "EC Ultra", /* 0xb4 */
4351 "Extreme", /* 0xb5 */
4352 "EC", /* 0xb6 */
4353 "FE", /* 0xb7 */
4354 "FE+", /* 0xb8 */
4355 "Supreme", /* 0xb9 */
4356 "UL 2", /* 0xba */
4357 };
4358
4359 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4360 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4361 else
4362 snprintf(buf, sz, "(chip %#x)", chipid);
4363 return buf;
4364 }
4365
4366 static int __devinit sky2_probe(struct pci_dev *pdev,
4367 const struct pci_device_id *ent)
4368 {
4369 struct net_device *dev;
4370 struct sky2_hw *hw;
4371 int err, using_dac = 0, wol_default;
4372 u32 reg;
4373 char buf1[16];
4374
4375 err = pci_enable_device(pdev);
4376 if (err) {
4377 dev_err(&pdev->dev, "cannot enable PCI device\n");
4378 goto err_out;
4379 }
4380
4381 /* Get configuration information
4382 * Note: only regular PCI config access once to test for HW issues
4383 * other PCI access through shared memory for speed and to
4384 * avoid MMCONFIG problems.
4385 */
4386 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4387 if (err) {
4388 dev_err(&pdev->dev, "PCI read config failed\n");
4389 goto err_out;
4390 }
4391
4392 if (~reg == 0) {
4393 dev_err(&pdev->dev, "PCI configuration read error\n");
4394 goto err_out;
4395 }
4396
4397 err = pci_request_regions(pdev, DRV_NAME);
4398 if (err) {
4399 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4400 goto err_out_disable;
4401 }
4402
4403 pci_set_master(pdev);
4404
4405 if (sizeof(dma_addr_t) > sizeof(u32) &&
4406 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4407 using_dac = 1;
4408 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4409 if (err < 0) {
4410 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4411 "for consistent allocations\n");
4412 goto err_out_free_regions;
4413 }
4414 } else {
4415 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4416 if (err) {
4417 dev_err(&pdev->dev, "no usable DMA configuration\n");
4418 goto err_out_free_regions;
4419 }
4420 }
4421
4422
4423 #ifdef __BIG_ENDIAN
4424 /* The sk98lin vendor driver uses hardware byte swapping but
4425 * this driver uses software swapping.
4426 */
4427 reg &= ~PCI_REV_DESC;
4428 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4429 if (err) {
4430 dev_err(&pdev->dev, "PCI write config failed\n");
4431 goto err_out_free_regions;
4432 }
4433 #endif
4434
4435 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4436
4437 err = -ENOMEM;
4438 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4439 if (!hw) {
4440 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4441 goto err_out_free_regions;
4442 }
4443
4444 hw->pdev = pdev;
4445
4446 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4447 if (!hw->regs) {
4448 dev_err(&pdev->dev, "cannot map device registers\n");
4449 goto err_out_free_hw;
4450 }
4451
4452 /* ring for status responses */
4453 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4454 if (!hw->st_le)
4455 goto err_out_iounmap;
4456
4457 err = sky2_init(hw);
4458 if (err)
4459 goto err_out_iounmap;
4460
4461 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4462 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4463
4464 sky2_reset(hw);
4465
4466 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4467 if (!dev) {
4468 err = -ENOMEM;
4469 goto err_out_free_pci;
4470 }
4471
4472 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4473 err = sky2_test_msi(hw);
4474 if (err == -EOPNOTSUPP)
4475 pci_disable_msi(pdev);
4476 else if (err)
4477 goto err_out_free_netdev;
4478 }
4479
4480 err = register_netdev(dev);
4481 if (err) {
4482 dev_err(&pdev->dev, "cannot register net device\n");
4483 goto err_out_free_netdev;
4484 }
4485
4486 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4487
4488 err = request_irq(pdev->irq, sky2_intr,
4489 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4490 dev->name, hw);
4491 if (err) {
4492 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4493 goto err_out_unregister;
4494 }
4495 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4496 napi_enable(&hw->napi);
4497
4498 sky2_show_addr(dev);
4499
4500 if (hw->ports > 1) {
4501 struct net_device *dev1;
4502
4503 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4504 if (!dev1)
4505 dev_warn(&pdev->dev, "allocation for second device failed\n");
4506 else if ((err = register_netdev(dev1))) {
4507 dev_warn(&pdev->dev,
4508 "register of second port failed (%d)\n", err);
4509 hw->dev[1] = NULL;
4510 free_netdev(dev1);
4511 } else
4512 sky2_show_addr(dev1);
4513 }
4514
4515 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4516 INIT_WORK(&hw->restart_work, sky2_restart);
4517
4518 pci_set_drvdata(pdev, hw);
4519
4520 return 0;
4521
4522 err_out_unregister:
4523 if (hw->flags & SKY2_HW_USE_MSI)
4524 pci_disable_msi(pdev);
4525 unregister_netdev(dev);
4526 err_out_free_netdev:
4527 free_netdev(dev);
4528 err_out_free_pci:
4529 sky2_write8(hw, B0_CTST, CS_RST_SET);
4530 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4531 err_out_iounmap:
4532 iounmap(hw->regs);
4533 err_out_free_hw:
4534 kfree(hw);
4535 err_out_free_regions:
4536 pci_release_regions(pdev);
4537 err_out_disable:
4538 pci_disable_device(pdev);
4539 err_out:
4540 pci_set_drvdata(pdev, NULL);
4541 return err;
4542 }
4543
4544 static void __devexit sky2_remove(struct pci_dev *pdev)
4545 {
4546 struct sky2_hw *hw = pci_get_drvdata(pdev);
4547 int i;
4548
4549 if (!hw)
4550 return;
4551
4552 del_timer_sync(&hw->watchdog_timer);
4553 cancel_work_sync(&hw->restart_work);
4554
4555 for (i = hw->ports-1; i >= 0; --i)
4556 unregister_netdev(hw->dev[i]);
4557
4558 sky2_write32(hw, B0_IMSK, 0);
4559
4560 sky2_power_aux(hw);
4561
4562 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4563 sky2_write8(hw, B0_CTST, CS_RST_SET);
4564 sky2_read8(hw, B0_CTST);
4565
4566 free_irq(pdev->irq, hw);
4567 if (hw->flags & SKY2_HW_USE_MSI)
4568 pci_disable_msi(pdev);
4569 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4570 pci_release_regions(pdev);
4571 pci_disable_device(pdev);
4572
4573 for (i = hw->ports-1; i >= 0; --i)
4574 free_netdev(hw->dev[i]);
4575
4576 iounmap(hw->regs);
4577 kfree(hw);
4578
4579 pci_set_drvdata(pdev, NULL);
4580 }
4581
4582 #ifdef CONFIG_PM
4583 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4584 {
4585 struct sky2_hw *hw = pci_get_drvdata(pdev);
4586 int i, wol = 0;
4587
4588 if (!hw)
4589 return 0;
4590
4591 del_timer_sync(&hw->watchdog_timer);
4592 cancel_work_sync(&hw->restart_work);
4593
4594 for (i = 0; i < hw->ports; i++) {
4595 struct net_device *dev = hw->dev[i];
4596 struct sky2_port *sky2 = netdev_priv(dev);
4597
4598 netif_device_detach(dev);
4599 if (netif_running(dev))
4600 sky2_down(dev);
4601
4602 if (sky2->wol)
4603 sky2_wol_init(sky2);
4604
4605 wol |= sky2->wol;
4606 }
4607
4608 sky2_write32(hw, B0_IMSK, 0);
4609 napi_disable(&hw->napi);
4610 sky2_power_aux(hw);
4611
4612 pci_save_state(pdev);
4613 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4614 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4615
4616 return 0;
4617 }
4618
4619 static int sky2_resume(struct pci_dev *pdev)
4620 {
4621 struct sky2_hw *hw = pci_get_drvdata(pdev);
4622 int i, err;
4623
4624 if (!hw)
4625 return 0;
4626
4627 err = pci_set_power_state(pdev, PCI_D0);
4628 if (err)
4629 goto out;
4630
4631 err = pci_restore_state(pdev);
4632 if (err)
4633 goto out;
4634
4635 pci_enable_wake(pdev, PCI_D0, 0);
4636
4637 /* Re-enable all clocks */
4638 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4639 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4640 hw->chip_id == CHIP_ID_YUKON_FE_P)
4641 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4642
4643 sky2_reset(hw);
4644 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4645 napi_enable(&hw->napi);
4646
4647 for (i = 0; i < hw->ports; i++) {
4648 struct net_device *dev = hw->dev[i];
4649
4650 netif_device_attach(dev);
4651 if (netif_running(dev)) {
4652 err = sky2_up(dev);
4653 if (err) {
4654 printk(KERN_ERR PFX "%s: could not up: %d\n",
4655 dev->name, err);
4656 rtnl_lock();
4657 dev_close(dev);
4658 rtnl_unlock();
4659 goto out;
4660 }
4661 }
4662 }
4663
4664 return 0;
4665 out:
4666 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4667 pci_disable_device(pdev);
4668 return err;
4669 }
4670 #endif
4671
4672 static void sky2_shutdown(struct pci_dev *pdev)
4673 {
4674 struct sky2_hw *hw = pci_get_drvdata(pdev);
4675 int i, wol = 0;
4676
4677 if (!hw)
4678 return;
4679
4680 del_timer_sync(&hw->watchdog_timer);
4681
4682 for (i = 0; i < hw->ports; i++) {
4683 struct net_device *dev = hw->dev[i];
4684 struct sky2_port *sky2 = netdev_priv(dev);
4685
4686 if (sky2->wol) {
4687 wol = 1;
4688 sky2_wol_init(sky2);
4689 }
4690 }
4691
4692 if (wol)
4693 sky2_power_aux(hw);
4694
4695 pci_enable_wake(pdev, PCI_D3hot, wol);
4696 pci_enable_wake(pdev, PCI_D3cold, wol);
4697
4698 pci_disable_device(pdev);
4699 pci_set_power_state(pdev, PCI_D3hot);
4700 }
4701
4702 static struct pci_driver sky2_driver = {
4703 .name = DRV_NAME,
4704 .id_table = sky2_id_table,
4705 .probe = sky2_probe,
4706 .remove = __devexit_p(sky2_remove),
4707 #ifdef CONFIG_PM
4708 .suspend = sky2_suspend,
4709 .resume = sky2_resume,
4710 #endif
4711 .shutdown = sky2_shutdown,
4712 };
4713
4714 static int __init sky2_init_module(void)
4715 {
4716 pr_info(PFX "driver version " DRV_VERSION "\n");
4717
4718 sky2_debug_init();
4719 return pci_register_driver(&sky2_driver);
4720 }
4721
4722 static void __exit sky2_cleanup_module(void)
4723 {
4724 pci_unregister_driver(&sky2_driver);
4725 sky2_debug_cleanup();
4726 }
4727
4728 module_init(sky2_init_module);
4729 module_exit(sky2_cleanup_module);
4730
4731 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4732 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4733 MODULE_LICENSE("GPL");
4734 MODULE_VERSION(DRV_VERSION);
Linux 2.6 libata-dev (mirror)