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rt2x00: RF3052 is a valid RF chipset for USB devices as well.
[linux-2.6/libata-dev.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
blobd300ff84b71797b74713bbcee9ea406fe088a8a2
1 /*
2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
3 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
4
5 Based on the original rt2800pci.c and rt2800usb.c.
6 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31 /*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38
39 #include "rt2x00.h"
40 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
41 #include "rt2x00usb.h"
42 #endif
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45 #include "rt2800usb.h"
46
47 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
48 MODULE_DESCRIPTION("rt2800 library");
49 MODULE_LICENSE("GPL");
50
51 /*
52 * Register access.
53 * All access to the CSR registers will go through the methods
54 * rt2800_register_read and rt2800_register_write.
55 * BBP and RF register require indirect register access,
56 * and use the CSR registers BBPCSR and RFCSR to achieve this.
57 * These indirect registers work with busy bits,
58 * and we will try maximal REGISTER_BUSY_COUNT times to access
59 * the register while taking a REGISTER_BUSY_DELAY us delay
60 * between each attampt. When the busy bit is still set at that time,
61 * the access attempt is considered to have failed,
62 * and we will print an error.
63 * The _lock versions must be used if you already hold the csr_mutex
64 */
65 #define WAIT_FOR_BBP(__dev, __reg) \
66 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
67 #define WAIT_FOR_RFCSR(__dev, __reg) \
68 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
69 #define WAIT_FOR_RF(__dev, __reg) \
70 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
71 #define WAIT_FOR_MCU(__dev, __reg) \
72 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
73 H2M_MAILBOX_CSR_OWNER, (__reg))
74
75 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
76 const unsigned int word, const u8 value)
77 {
78 u32 reg;
79
80 mutex_lock(&rt2x00dev->csr_mutex);
81
82 /*
83 * Wait until the BBP becomes available, afterwards we
84 * can safely write the new data into the register.
85 */
86 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
87 reg = 0;
88 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
89 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
90 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
91 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
92 if (rt2x00_intf_is_pci(rt2x00dev))
93 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
94
95 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
96 }
97
98 mutex_unlock(&rt2x00dev->csr_mutex);
99 }
100
101 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
102 const unsigned int word, u8 *value)
103 {
104 u32 reg;
105
106 mutex_lock(&rt2x00dev->csr_mutex);
107
108 /*
109 * Wait until the BBP becomes available, afterwards we
110 * can safely write the read request into the register.
111 * After the data has been written, we wait until hardware
112 * returns the correct value, if at any time the register
113 * doesn't become available in time, reg will be 0xffffffff
114 * which means we return 0xff to the caller.
115 */
116 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
117 reg = 0;
118 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
119 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
120 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
121 if (rt2x00_intf_is_pci(rt2x00dev))
122 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
123
124 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
125
126 WAIT_FOR_BBP(rt2x00dev, &reg);
127 }
128
129 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
130
131 mutex_unlock(&rt2x00dev->csr_mutex);
132 }
133
134 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
135 const unsigned int word, const u8 value)
136 {
137 u32 reg;
138
139 mutex_lock(&rt2x00dev->csr_mutex);
140
141 /*
142 * Wait until the RFCSR becomes available, afterwards we
143 * can safely write the new data into the register.
144 */
145 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
146 reg = 0;
147 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
148 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
149 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
150 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
151
152 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
153 }
154
155 mutex_unlock(&rt2x00dev->csr_mutex);
156 }
157
158 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
159 const unsigned int word, u8 *value)
160 {
161 u32 reg;
162
163 mutex_lock(&rt2x00dev->csr_mutex);
164
165 /*
166 * Wait until the RFCSR becomes available, afterwards we
167 * can safely write the read request into the register.
168 * After the data has been written, we wait until hardware
169 * returns the correct value, if at any time the register
170 * doesn't become available in time, reg will be 0xffffffff
171 * which means we return 0xff to the caller.
172 */
173 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
174 reg = 0;
175 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
176 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
177 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
178
179 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
180
181 WAIT_FOR_RFCSR(rt2x00dev, &reg);
182 }
183
184 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
185
186 mutex_unlock(&rt2x00dev->csr_mutex);
187 }
188
189 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
190 const unsigned int word, const u32 value)
191 {
192 u32 reg;
193
194 mutex_lock(&rt2x00dev->csr_mutex);
195
196 /*
197 * Wait until the RF becomes available, afterwards we
198 * can safely write the new data into the register.
199 */
200 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
201 reg = 0;
202 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
203 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
204 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
205 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
206
207 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
208 rt2x00_rf_write(rt2x00dev, word, value);
209 }
210
211 mutex_unlock(&rt2x00dev->csr_mutex);
212 }
213
214 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
215 const u8 command, const u8 token,
216 const u8 arg0, const u8 arg1)
217 {
218 u32 reg;
219
220 /*
221 * RT2880 and RT3052 don't support MCU requests.
222 */
223 if (rt2x00_rt(rt2x00dev, RT2880) || rt2x00_rt(rt2x00dev, RT3052))
224 return;
225
226 mutex_lock(&rt2x00dev->csr_mutex);
227
228 /*
229 * Wait until the MCU becomes available, afterwards we
230 * can safely write the new data into the register.
231 */
232 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
233 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
234 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
235 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
236 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
237 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
238
239 reg = 0;
240 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
241 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
242 }
243
244 mutex_unlock(&rt2x00dev->csr_mutex);
245 }
246 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
247
248 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
249 const struct rt2x00debug rt2800_rt2x00debug = {
250 .owner = THIS_MODULE,
251 .csr = {
252 .read = rt2800_register_read,
253 .write = rt2800_register_write,
254 .flags = RT2X00DEBUGFS_OFFSET,
255 .word_base = CSR_REG_BASE,
256 .word_size = sizeof(u32),
257 .word_count = CSR_REG_SIZE / sizeof(u32),
258 },
259 .eeprom = {
260 .read = rt2x00_eeprom_read,
261 .write = rt2x00_eeprom_write,
262 .word_base = EEPROM_BASE,
263 .word_size = sizeof(u16),
264 .word_count = EEPROM_SIZE / sizeof(u16),
265 },
266 .bbp = {
267 .read = rt2800_bbp_read,
268 .write = rt2800_bbp_write,
269 .word_base = BBP_BASE,
270 .word_size = sizeof(u8),
271 .word_count = BBP_SIZE / sizeof(u8),
272 },
273 .rf = {
274 .read = rt2x00_rf_read,
275 .write = rt2800_rf_write,
276 .word_base = RF_BASE,
277 .word_size = sizeof(u32),
278 .word_count = RF_SIZE / sizeof(u32),
279 },
280 };
281 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
282 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
283
284 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
285 {
286 u32 reg;
287
288 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
289 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
290 }
291 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
292
293 #ifdef CONFIG_RT2X00_LIB_LEDS
294 static void rt2800_brightness_set(struct led_classdev *led_cdev,
295 enum led_brightness brightness)
296 {
297 struct rt2x00_led *led =
298 container_of(led_cdev, struct rt2x00_led, led_dev);
299 unsigned int enabled = brightness != LED_OFF;
300 unsigned int bg_mode =
301 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
302 unsigned int polarity =
303 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
304 EEPROM_FREQ_LED_POLARITY);
305 unsigned int ledmode =
306 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
307 EEPROM_FREQ_LED_MODE);
308
309 if (led->type == LED_TYPE_RADIO) {
310 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
311 enabled ? 0x20 : 0);
312 } else if (led->type == LED_TYPE_ASSOC) {
313 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
314 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
315 } else if (led->type == LED_TYPE_QUALITY) {
316 /*
317 * The brightness is divided into 6 levels (0 - 5),
318 * The specs tell us the following levels:
319 * 0, 1 ,3, 7, 15, 31
320 * to determine the level in a simple way we can simply
321 * work with bitshifting:
322 * (1 << level) - 1
323 */
324 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
325 (1 << brightness / (LED_FULL / 6)) - 1,
326 polarity);
327 }
328 }
329
330 static int rt2800_blink_set(struct led_classdev *led_cdev,
331 unsigned long *delay_on, unsigned long *delay_off)
332 {
333 struct rt2x00_led *led =
334 container_of(led_cdev, struct rt2x00_led, led_dev);
335 u32 reg;
336
337 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
338 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
339 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
340 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
341 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
342 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
343 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
344 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
345 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
346
347 return 0;
348 }
349
350 void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
351 struct rt2x00_led *led, enum led_type type)
352 {
353 led->rt2x00dev = rt2x00dev;
354 led->type = type;
355 led->led_dev.brightness_set = rt2800_brightness_set;
356 led->led_dev.blink_set = rt2800_blink_set;
357 led->flags = LED_INITIALIZED;
358 }
359 EXPORT_SYMBOL_GPL(rt2800_init_led);
360 #endif /* CONFIG_RT2X00_LIB_LEDS */
361
362 /*
363 * Configuration handlers.
364 */
365 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
366 struct rt2x00lib_crypto *crypto,
367 struct ieee80211_key_conf *key)
368 {
369 struct mac_wcid_entry wcid_entry;
370 struct mac_iveiv_entry iveiv_entry;
371 u32 offset;
372 u32 reg;
373
374 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
375
376 rt2800_register_read(rt2x00dev, offset, &reg);
377 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
378 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
379 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
380 (crypto->cmd == SET_KEY) * crypto->cipher);
381 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
382 (crypto->cmd == SET_KEY) * crypto->bssidx);
383 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
384 rt2800_register_write(rt2x00dev, offset, reg);
385
386 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
387
388 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
389 if ((crypto->cipher == CIPHER_TKIP) ||
390 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
391 (crypto->cipher == CIPHER_AES))
392 iveiv_entry.iv[3] |= 0x20;
393 iveiv_entry.iv[3] |= key->keyidx << 6;
394 rt2800_register_multiwrite(rt2x00dev, offset,
395 &iveiv_entry, sizeof(iveiv_entry));
396
397 offset = MAC_WCID_ENTRY(key->hw_key_idx);
398
399 memset(&wcid_entry, 0, sizeof(wcid_entry));
400 if (crypto->cmd == SET_KEY)
401 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
402 rt2800_register_multiwrite(rt2x00dev, offset,
403 &wcid_entry, sizeof(wcid_entry));
404 }
405
406 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
407 struct rt2x00lib_crypto *crypto,
408 struct ieee80211_key_conf *key)
409 {
410 struct hw_key_entry key_entry;
411 struct rt2x00_field32 field;
412 u32 offset;
413 u32 reg;
414
415 if (crypto->cmd == SET_KEY) {
416 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
417
418 memcpy(key_entry.key, crypto->key,
419 sizeof(key_entry.key));
420 memcpy(key_entry.tx_mic, crypto->tx_mic,
421 sizeof(key_entry.tx_mic));
422 memcpy(key_entry.rx_mic, crypto->rx_mic,
423 sizeof(key_entry.rx_mic));
424
425 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
426 rt2800_register_multiwrite(rt2x00dev, offset,
427 &key_entry, sizeof(key_entry));
428 }
429
430 /*
431 * The cipher types are stored over multiple registers
432 * starting with SHARED_KEY_MODE_BASE each word will have
433 * 32 bits and contains the cipher types for 2 bssidx each.
434 * Using the correct defines correctly will cause overhead,
435 * so just calculate the correct offset.
436 */
437 field.bit_offset = 4 * (key->hw_key_idx % 8);
438 field.bit_mask = 0x7 << field.bit_offset;
439
440 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
441
442 rt2800_register_read(rt2x00dev, offset, &reg);
443 rt2x00_set_field32(&reg, field,
444 (crypto->cmd == SET_KEY) * crypto->cipher);
445 rt2800_register_write(rt2x00dev, offset, reg);
446
447 /*
448 * Update WCID information
449 */
450 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
451
452 return 0;
453 }
454 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
455
456 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
457 struct rt2x00lib_crypto *crypto,
458 struct ieee80211_key_conf *key)
459 {
460 struct hw_key_entry key_entry;
461 u32 offset;
462
463 if (crypto->cmd == SET_KEY) {
464 /*
465 * 1 pairwise key is possible per AID, this means that the AID
466 * equals our hw_key_idx. Make sure the WCID starts _after_ the
467 * last possible shared key entry.
468 */
469 if (crypto->aid > (256 - 32))
470 return -ENOSPC;
471
472 key->hw_key_idx = 32 + crypto->aid;
473
474 memcpy(key_entry.key, crypto->key,
475 sizeof(key_entry.key));
476 memcpy(key_entry.tx_mic, crypto->tx_mic,
477 sizeof(key_entry.tx_mic));
478 memcpy(key_entry.rx_mic, crypto->rx_mic,
479 sizeof(key_entry.rx_mic));
480
481 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
482 rt2800_register_multiwrite(rt2x00dev, offset,
483 &key_entry, sizeof(key_entry));
484 }
485
486 /*
487 * Update WCID information
488 */
489 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
490
491 return 0;
492 }
493 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
494
495 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
496 const unsigned int filter_flags)
497 {
498 u32 reg;
499
500 /*
501 * Start configuration steps.
502 * Note that the version error will always be dropped
503 * and broadcast frames will always be accepted since
504 * there is no filter for it at this time.
505 */
506 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
507 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
508 !(filter_flags & FIF_FCSFAIL));
509 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
510 !(filter_flags & FIF_PLCPFAIL));
511 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
512 !(filter_flags & FIF_PROMISC_IN_BSS));
513 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
515 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
516 !(filter_flags & FIF_ALLMULTI));
517 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
519 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
520 !(filter_flags & FIF_CONTROL));
521 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
522 !(filter_flags & FIF_CONTROL));
523 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
524 !(filter_flags & FIF_CONTROL));
525 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
526 !(filter_flags & FIF_CONTROL));
527 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
528 !(filter_flags & FIF_CONTROL));
529 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
530 !(filter_flags & FIF_PSPOLL));
531 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
532 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
533 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
534 !(filter_flags & FIF_CONTROL));
535 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
536 }
537 EXPORT_SYMBOL_GPL(rt2800_config_filter);
538
539 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
540 struct rt2x00intf_conf *conf, const unsigned int flags)
541 {
542 unsigned int beacon_base;
543 u32 reg;
544
545 if (flags & CONFIG_UPDATE_TYPE) {
546 /*
547 * Clear current synchronisation setup.
548 * For the Beacon base registers we only need to clear
549 * the first byte since that byte contains the VALID and OWNER
550 * bits which (when set to 0) will invalidate the entire beacon.
551 */
552 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
553 rt2800_register_write(rt2x00dev, beacon_base, 0);
554
555 /*
556 * Enable synchronisation.
557 */
558 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
559 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
560 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
561 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
562 (conf->sync == TSF_SYNC_BEACON));
563 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
564 }
565
566 if (flags & CONFIG_UPDATE_MAC) {
567 reg = le32_to_cpu(conf->mac[1]);
568 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
569 conf->mac[1] = cpu_to_le32(reg);
570
571 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
572 conf->mac, sizeof(conf->mac));
573 }
574
575 if (flags & CONFIG_UPDATE_BSSID) {
576 reg = le32_to_cpu(conf->bssid[1]);
577 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
578 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
579 conf->bssid[1] = cpu_to_le32(reg);
580
581 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
582 conf->bssid, sizeof(conf->bssid));
583 }
584 }
585 EXPORT_SYMBOL_GPL(rt2800_config_intf);
586
587 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
588 {
589 u32 reg;
590
591 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
592 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
593 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
594
595 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
596 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
597 !!erp->short_preamble);
598 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
599 !!erp->short_preamble);
600 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
601
602 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
603 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
604 erp->cts_protection ? 2 : 0);
605 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
606
607 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
608 erp->basic_rates);
609 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
610
611 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
612 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
613 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
614 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
615
616 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
617 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
618 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
619 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
620 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
621 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
622 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
623
624 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
625 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
626 erp->beacon_int * 16);
627 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
628 }
629 EXPORT_SYMBOL_GPL(rt2800_config_erp);
630
631 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
632 {
633 u8 r1;
634 u8 r3;
635
636 rt2800_bbp_read(rt2x00dev, 1, &r1);
637 rt2800_bbp_read(rt2x00dev, 3, &r3);
638
639 /*
640 * Configure the TX antenna.
641 */
642 switch ((int)ant->tx) {
643 case 1:
644 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
645 if (rt2x00_intf_is_pci(rt2x00dev))
646 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
647 break;
648 case 2:
649 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
650 break;
651 case 3:
652 /* Do nothing */
653 break;
654 }
655
656 /*
657 * Configure the RX antenna.
658 */
659 switch ((int)ant->rx) {
660 case 1:
661 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
662 break;
663 case 2:
664 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
665 break;
666 case 3:
667 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
668 break;
669 }
670
671 rt2800_bbp_write(rt2x00dev, 3, r3);
672 rt2800_bbp_write(rt2x00dev, 1, r1);
673 }
674 EXPORT_SYMBOL_GPL(rt2800_config_ant);
675
676 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
677 struct rt2x00lib_conf *libconf)
678 {
679 u16 eeprom;
680 short lna_gain;
681
682 if (libconf->rf.channel <= 14) {
683 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
684 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
685 } else if (libconf->rf.channel <= 64) {
686 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
687 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
688 } else if (libconf->rf.channel <= 128) {
689 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
690 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
691 } else {
692 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
693 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
694 }
695
696 rt2x00dev->lna_gain = lna_gain;
697 }
698
699 static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
700 struct ieee80211_conf *conf,
701 struct rf_channel *rf,
702 struct channel_info *info)
703 {
704 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
705
706 if (rt2x00dev->default_ant.tx == 1)
707 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
708
709 if (rt2x00dev->default_ant.rx == 1) {
710 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
711 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
712 } else if (rt2x00dev->default_ant.rx == 2)
713 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
714
715 if (rf->channel > 14) {
716 /*
717 * When TX power is below 0, we should increase it by 7 to
718 * make it a positive value (Minumum value is -7).
719 * However this means that values between 0 and 7 have
720 * double meaning, and we should set a 7DBm boost flag.
721 */
722 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
723 (info->tx_power1 >= 0));
724
725 if (info->tx_power1 < 0)
726 info->tx_power1 += 7;
727
728 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
729 TXPOWER_A_TO_DEV(info->tx_power1));
730
731 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
732 (info->tx_power2 >= 0));
733
734 if (info->tx_power2 < 0)
735 info->tx_power2 += 7;
736
737 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
738 TXPOWER_A_TO_DEV(info->tx_power2));
739 } else {
740 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
741 TXPOWER_G_TO_DEV(info->tx_power1));
742 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
743 TXPOWER_G_TO_DEV(info->tx_power2));
744 }
745
746 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
747
748 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
749 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
750 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
751 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
752
753 udelay(200);
754
755 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
756 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
757 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
758 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
759
760 udelay(200);
761
762 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
763 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
764 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
765 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
766 }
767
768 static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
769 struct ieee80211_conf *conf,
770 struct rf_channel *rf,
771 struct channel_info *info)
772 {
773 u8 rfcsr;
774
775 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
776 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
777
778 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
779 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
780 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
781
782 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
783 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
784 TXPOWER_G_TO_DEV(info->tx_power1));
785 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
786
787 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
788 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
789 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
790
791 rt2800_rfcsr_write(rt2x00dev, 24,
792 rt2x00dev->calibration[conf_is_ht40(conf)]);
793
794 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
795 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
796 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
797 }
798
799 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
800 struct ieee80211_conf *conf,
801 struct rf_channel *rf,
802 struct channel_info *info)
803 {
804 u32 reg;
805 unsigned int tx_pin;
806 u8 bbp;
807
808 if ((rt2x00_rt(rt2x00dev, RT3070) ||
809 rt2x00_rt(rt2x00dev, RT3090)) &&
810 (rt2x00_rf(rt2x00dev, RF2020) ||
811 rt2x00_rf(rt2x00dev, RF3020) ||
812 rt2x00_rf(rt2x00dev, RF3021) ||
813 rt2x00_rf(rt2x00dev, RF3022)))
814 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
815 else
816 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
817
818 /*
819 * Change BBP settings
820 */
821 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
822 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
823 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
824 rt2800_bbp_write(rt2x00dev, 86, 0);
825
826 if (rf->channel <= 14) {
827 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
828 rt2800_bbp_write(rt2x00dev, 82, 0x62);
829 rt2800_bbp_write(rt2x00dev, 75, 0x46);
830 } else {
831 rt2800_bbp_write(rt2x00dev, 82, 0x84);
832 rt2800_bbp_write(rt2x00dev, 75, 0x50);
833 }
834 } else {
835 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
836
837 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
838 rt2800_bbp_write(rt2x00dev, 75, 0x46);
839 else
840 rt2800_bbp_write(rt2x00dev, 75, 0x50);
841 }
842
843 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
844 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
845 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
846 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
847 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
848
849 tx_pin = 0;
850
851 /* Turn on unused PA or LNA when not using 1T or 1R */
852 if (rt2x00dev->default_ant.tx != 1) {
853 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
854 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
855 }
856
857 /* Turn on unused PA or LNA when not using 1T or 1R */
858 if (rt2x00dev->default_ant.rx != 1) {
859 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
860 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
861 }
862
863 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
864 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
865 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
866 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
867 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
868 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
869
870 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
871
872 rt2800_bbp_read(rt2x00dev, 4, &bbp);
873 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
874 rt2800_bbp_write(rt2x00dev, 4, bbp);
875
876 rt2800_bbp_read(rt2x00dev, 3, &bbp);
877 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
878 rt2800_bbp_write(rt2x00dev, 3, bbp);
879
880 if (rt2x00_rev(rt2x00dev) == RT2860C_VERSION) {
881 if (conf_is_ht40(conf)) {
882 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
883 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
884 rt2800_bbp_write(rt2x00dev, 73, 0x16);
885 } else {
886 rt2800_bbp_write(rt2x00dev, 69, 0x16);
887 rt2800_bbp_write(rt2x00dev, 70, 0x08);
888 rt2800_bbp_write(rt2x00dev, 73, 0x11);
889 }
890 }
891
892 msleep(1);
893 }
894
895 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
896 const int txpower)
897 {
898 u32 reg;
899 u32 value = TXPOWER_G_TO_DEV(txpower);
900 u8 r1;
901
902 rt2800_bbp_read(rt2x00dev, 1, &r1);
903 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
904 rt2800_bbp_write(rt2x00dev, 1, r1);
905
906 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
907 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
908 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
909 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
910 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
911 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
912 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
913 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
914 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
915 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
916
917 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
918 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
919 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
920 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
921 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
922 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
923 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
924 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
925 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
926 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
927
928 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
929 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
930 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
931 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
932 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
933 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
937 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
938
939 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
940 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
941 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
942 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
943 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
944 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
945 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
946 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
947 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
948 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
949
950 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
951 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
952 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
953 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
954 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
955 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
956 }
957
958 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
959 struct rt2x00lib_conf *libconf)
960 {
961 u32 reg;
962
963 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
964 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
965 libconf->conf->short_frame_max_tx_count);
966 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
967 libconf->conf->long_frame_max_tx_count);
968 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
969 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
970 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
971 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
972 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
973 }
974
975 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
976 struct rt2x00lib_conf *libconf)
977 {
978 enum dev_state state =
979 (libconf->conf->flags & IEEE80211_CONF_PS) ?
980 STATE_SLEEP : STATE_AWAKE;
981 u32 reg;
982
983 if (state == STATE_SLEEP) {
984 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
985
986 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
987 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
988 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
989 libconf->conf->listen_interval - 1);
990 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
991 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
992
993 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
994 } else {
995 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
996
997 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
998 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
999 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1000 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1001 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1002 }
1003 }
1004
1005 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1006 struct rt2x00lib_conf *libconf,
1007 const unsigned int flags)
1008 {
1009 /* Always recalculate LNA gain before changing configuration */
1010 rt2800_config_lna_gain(rt2x00dev, libconf);
1011
1012 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1013 rt2800_config_channel(rt2x00dev, libconf->conf,
1014 &libconf->rf, &libconf->channel);
1015 if (flags & IEEE80211_CONF_CHANGE_POWER)
1016 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1017 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1018 rt2800_config_retry_limit(rt2x00dev, libconf);
1019 if (flags & IEEE80211_CONF_CHANGE_PS)
1020 rt2800_config_ps(rt2x00dev, libconf);
1021 }
1022 EXPORT_SYMBOL_GPL(rt2800_config);
1023
1024 /*
1025 * Link tuning
1026 */
1027 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1028 {
1029 u32 reg;
1030
1031 /*
1032 * Update FCS error count from register.
1033 */
1034 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1035 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1036 }
1037 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1038
1039 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1040 {
1041 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1042 if (rt2x00_intf_is_usb(rt2x00dev) &&
1043 rt2x00_rev(rt2x00dev) == RT3070_VERSION)
1044 return 0x1c + (2 * rt2x00dev->lna_gain);
1045 else
1046 return 0x2e + rt2x00dev->lna_gain;
1047 }
1048
1049 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1050 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1051 else
1052 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1053 }
1054
1055 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1056 struct link_qual *qual, u8 vgc_level)
1057 {
1058 if (qual->vgc_level != vgc_level) {
1059 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1060 qual->vgc_level = vgc_level;
1061 qual->vgc_level_reg = vgc_level;
1062 }
1063 }
1064
1065 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1066 {
1067 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1068 }
1069 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1070
1071 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1072 const u32 count)
1073 {
1074 if (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)
1075 return;
1076
1077 /*
1078 * When RSSI is better then -80 increase VGC level with 0x10
1079 */
1080 rt2800_set_vgc(rt2x00dev, qual,
1081 rt2800_get_default_vgc(rt2x00dev) +
1082 ((qual->rssi > -80) * 0x10));
1083 }
1084 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1085
1086 /*
1087 * Initialization functions.
1088 */
1089 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1090 {
1091 u32 reg;
1092 unsigned int i;
1093
1094 if (rt2x00_intf_is_usb(rt2x00dev)) {
1095 /*
1096 * Wait until BBP and RF are ready.
1097 */
1098 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1099 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1100 if (reg && reg != ~0)
1101 break;
1102 msleep(1);
1103 }
1104
1105 if (i == REGISTER_BUSY_COUNT) {
1106 ERROR(rt2x00dev, "Unstable hardware.\n");
1107 return -EBUSY;
1108 }
1109
1110 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1111 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1112 reg & ~0x00002000);
1113 } else if (rt2x00_intf_is_pci(rt2x00dev))
1114 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1115
1116 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1117 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1118 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1119 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1120
1121 if (rt2x00_intf_is_usb(rt2x00dev)) {
1122 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1123 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1124 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1125 USB_MODE_RESET, REGISTER_TIMEOUT);
1126 #endif
1127 }
1128
1129 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1130
1131 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1132 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1133 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1134 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1135 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1136 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1137
1138 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1139 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1140 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1141 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1142 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1143 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1144
1145 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1146 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1147
1148 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1149
1150 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1151 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1152 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1153 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1154 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1155 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1156 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1157 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1158
1159 if (rt2x00_intf_is_usb(rt2x00dev) &&
1160 rt2x00_rev(rt2x00dev) == RT3070_VERSION) {
1161 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1162 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1163 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1164 } else {
1165 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1166 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1167 }
1168
1169 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1170 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1171 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1172 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1173 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1174 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1175 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1176 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1177 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1178 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1179
1180 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1181 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1182 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1183 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1184
1185 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1186 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1187 if (rt2x00_rev(rt2x00dev) >= RT2880E_VERSION &&
1188 rt2x00_rev(rt2x00dev) < RT3070_VERSION)
1189 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1190 else
1191 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1192 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1193 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1194 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1195
1196 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1197
1198 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1199 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1200 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1201 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1202 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1203 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1204 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1205
1206 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1207 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1208 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1209 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1210 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1211 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1212 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1213 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1214 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1215 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1216 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1217
1218 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1219 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1220 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1221 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1222 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1223 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1224 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1225 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1226 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1227 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1228 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1229
1230 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1231 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1232 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1233 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1234 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1235 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1236 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1237 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1238 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1239 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1240 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1241
1242 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1243 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1244 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1245 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1246 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1247 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1248 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1249 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1250 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1251 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1252 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1253
1254 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1255 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1256 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1257 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1258 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1259 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1260 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1261 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1262 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1263 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1264 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1265
1266 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1267 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1268 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1269 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1270 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1271 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1272 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1273 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1274 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1275 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1276 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1277
1278 if (rt2x00_intf_is_usb(rt2x00dev)) {
1279 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1280
1281 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1282 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1284 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1285 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1286 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1287 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1288 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1289 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1290 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1291 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1292 }
1293
1294 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1295 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1296
1297 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1298 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1299 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1300 IEEE80211_MAX_RTS_THRESHOLD);
1301 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1302 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1303
1304 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1305 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1306
1307 /*
1308 * ASIC will keep garbage value after boot, clear encryption keys.
1309 */
1310 for (i = 0; i < 4; i++)
1311 rt2800_register_write(rt2x00dev,
1312 SHARED_KEY_MODE_ENTRY(i), 0);
1313
1314 for (i = 0; i < 256; i++) {
1315 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1316 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1317 wcid, sizeof(wcid));
1318
1319 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1320 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1321 }
1322
1323 /*
1324 * Clear all beacons
1325 * For the Beacon base registers we only need to clear
1326 * the first byte since that byte contains the VALID and OWNER
1327 * bits which (when set to 0) will invalidate the entire beacon.
1328 */
1329 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1330 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1331 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1332 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1333 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1334 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1335 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1336 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1337
1338 if (rt2x00_intf_is_usb(rt2x00dev)) {
1339 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1340 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1341 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1342 }
1343
1344 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1345 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1346 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1347 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1348 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1349 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1350 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1351 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1352 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1353 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1354
1355 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1356 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1357 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1358 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1359 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1360 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1361 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1362 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1363 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1364 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1365
1366 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1367 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1368 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1369 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1370 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1371 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1372 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1373 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1374 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1375 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1376
1377 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1378 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1379 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1380 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1381 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1382 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1383
1384 /*
1385 * We must clear the error counters.
1386 * These registers are cleared on read,
1387 * so we may pass a useless variable to store the value.
1388 */
1389 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1390 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1391 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1392 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1393 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1394 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1395
1396 return 0;
1397 }
1398 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1399
1400 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1401 {
1402 unsigned int i;
1403 u32 reg;
1404
1405 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1406 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1407 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1408 return 0;
1409
1410 udelay(REGISTER_BUSY_DELAY);
1411 }
1412
1413 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1414 return -EACCES;
1415 }
1416
1417 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1418 {
1419 unsigned int i;
1420 u8 value;
1421
1422 /*
1423 * BBP was enabled after firmware was loaded,
1424 * but we need to reactivate it now.
1425 */
1426 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1427 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1428 msleep(1);
1429
1430 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1431 rt2800_bbp_read(rt2x00dev, 0, &value);
1432 if ((value != 0xff) && (value != 0x00))
1433 return 0;
1434 udelay(REGISTER_BUSY_DELAY);
1435 }
1436
1437 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1438 return -EACCES;
1439 }
1440
1441 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1442 {
1443 unsigned int i;
1444 u16 eeprom;
1445 u8 reg_id;
1446 u8 value;
1447
1448 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1449 rt2800_wait_bbp_ready(rt2x00dev)))
1450 return -EACCES;
1451
1452 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1453 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1454 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1455 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1456 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1457 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1458 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1459 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1460 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1461 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1462 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1463 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1464 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1465 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1466
1467 if (rt2x00_rev(rt2x00dev) == RT2860C_VERSION) {
1468 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1469 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1470 }
1471
1472 if (rt2x00_rev(rt2x00dev) > RT2860D_VERSION)
1473 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1474
1475 if (rt2x00_intf_is_usb(rt2x00dev) &&
1476 rt2x00_rev(rt2x00dev) == RT3070_VERSION) {
1477 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1478 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1479 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1480 }
1481
1482 if (rt2x00_rt(rt2x00dev, RT3052)) {
1483 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1484 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1485 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1486 }
1487
1488 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1489 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1490
1491 if (eeprom != 0xffff && eeprom != 0x0000) {
1492 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1493 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1494 rt2800_bbp_write(rt2x00dev, reg_id, value);
1495 }
1496 }
1497
1498 return 0;
1499 }
1500 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1501
1502 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1503 bool bw40, u8 rfcsr24, u8 filter_target)
1504 {
1505 unsigned int i;
1506 u8 bbp;
1507 u8 rfcsr;
1508 u8 passband;
1509 u8 stopband;
1510 u8 overtuned = 0;
1511
1512 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1513
1514 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1515 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1516 rt2800_bbp_write(rt2x00dev, 4, bbp);
1517
1518 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1519 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1520 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1521
1522 /*
1523 * Set power & frequency of passband test tone
1524 */
1525 rt2800_bbp_write(rt2x00dev, 24, 0);
1526
1527 for (i = 0; i < 100; i++) {
1528 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1529 msleep(1);
1530
1531 rt2800_bbp_read(rt2x00dev, 55, &passband);
1532 if (passband)
1533 break;
1534 }
1535
1536 /*
1537 * Set power & frequency of stopband test tone
1538 */
1539 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1540
1541 for (i = 0; i < 100; i++) {
1542 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1543 msleep(1);
1544
1545 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1546
1547 if ((passband - stopband) <= filter_target) {
1548 rfcsr24++;
1549 overtuned += ((passband - stopband) == filter_target);
1550 } else
1551 break;
1552
1553 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1554 }
1555
1556 rfcsr24 -= !!overtuned;
1557
1558 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1559 return rfcsr24;
1560 }
1561
1562 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1563 {
1564 u8 rfcsr;
1565 u8 bbp;
1566
1567 if (rt2x00_intf_is_usb(rt2x00dev) &&
1568 rt2x00_rev(rt2x00dev) != RT3070_VERSION)
1569 return 0;
1570
1571 if (rt2x00_intf_is_pci(rt2x00dev)) {
1572 if (!rt2x00_rf(rt2x00dev, RF3020) &&
1573 !rt2x00_rf(rt2x00dev, RF3021) &&
1574 !rt2x00_rf(rt2x00dev, RF3022))
1575 return 0;
1576 }
1577
1578 /*
1579 * Init RF calibration.
1580 */
1581 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1582 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1583 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1584 msleep(1);
1585 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1586 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1587
1588 if (rt2x00_intf_is_usb(rt2x00dev)) {
1589 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1590 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1591 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1592 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1593 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1594 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1595 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1596 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1597 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1598 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1599 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1600 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1601 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1602 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1603 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1604 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1605 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1606 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1607 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1608 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1609 } else if (rt2x00_intf_is_pci(rt2x00dev)) {
1610 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1611 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1612 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1613 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1614 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1615 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1616 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1617 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1618 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1619 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1620 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1621 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1622 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1623 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1624 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1625 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1626 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1627 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1628 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1629 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1630 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1631 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1632 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1633 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1634 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1635 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1636 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1637 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1638 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1639 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1640 }
1641
1642 /*
1643 * Set RX Filter calibration for 20MHz and 40MHz
1644 */
1645 rt2x00dev->calibration[0] =
1646 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1647 rt2x00dev->calibration[1] =
1648 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1649
1650 /*
1651 * Set back to initial state
1652 */
1653 rt2800_bbp_write(rt2x00dev, 24, 0);
1654
1655 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1656 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1657 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1658
1659 /*
1660 * set BBP back to BW20
1661 */
1662 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1663 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1664 rt2800_bbp_write(rt2x00dev, 4, bbp);
1665
1666 return 0;
1667 }
1668 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1669
1670 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1671 {
1672 u32 reg;
1673
1674 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1675
1676 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1677 }
1678 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1679
1680 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1681 {
1682 u32 reg;
1683
1684 mutex_lock(&rt2x00dev->csr_mutex);
1685
1686 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
1687 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1688 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1689 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1690 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
1691
1692 /* Wait until the EEPROM has been loaded */
1693 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1694
1695 /* Apparently the data is read from end to start */
1696 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
1697 (u32 *)&rt2x00dev->eeprom[i]);
1698 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
1699 (u32 *)&rt2x00dev->eeprom[i + 2]);
1700 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
1701 (u32 *)&rt2x00dev->eeprom[i + 4]);
1702 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
1703 (u32 *)&rt2x00dev->eeprom[i + 6]);
1704
1705 mutex_unlock(&rt2x00dev->csr_mutex);
1706 }
1707
1708 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1709 {
1710 unsigned int i;
1711
1712 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1713 rt2800_efuse_read(rt2x00dev, i);
1714 }
1715 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1716
1717 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1718 {
1719 u16 word;
1720 u8 *mac;
1721 u8 default_lna_gain;
1722
1723 /*
1724 * Start validation of the data that has been read.
1725 */
1726 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1727 if (!is_valid_ether_addr(mac)) {
1728 random_ether_addr(mac);
1729 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1730 }
1731
1732 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1733 if (word == 0xffff) {
1734 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1735 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1736 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1737 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1738 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1739 } else if (rt2x00_rev(rt2x00dev) < RT2883_VERSION) {
1740 /*
1741 * There is a max of 2 RX streams for RT28x0 series
1742 */
1743 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1744 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1745 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1746 }
1747
1748 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1749 if (word == 0xffff) {
1750 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1751 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1752 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1753 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1754 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1755 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1756 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1757 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1758 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1759 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1760 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1761 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1762 }
1763
1764 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1765 if ((word & 0x00ff) == 0x00ff) {
1766 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1767 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1768 LED_MODE_TXRX_ACTIVITY);
1769 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1770 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1771 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1772 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1773 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1774 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1775 }
1776
1777 /*
1778 * During the LNA validation we are going to use
1779 * lna0 as correct value. Note that EEPROM_LNA
1780 * is never validated.
1781 */
1782 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1783 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1784
1785 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1786 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1787 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1788 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1789 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1790 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1791
1792 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1793 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1794 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1795 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1796 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1797 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1798 default_lna_gain);
1799 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1800
1801 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1802 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1803 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1804 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1805 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1806 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1807
1808 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1809 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1810 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1811 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1812 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1813 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1814 default_lna_gain);
1815 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1816
1817 return 0;
1818 }
1819 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
1820
1821 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1822 {
1823 u32 reg;
1824 u16 value;
1825 u16 eeprom;
1826
1827 /*
1828 * Read EEPROM word for configuration.
1829 */
1830 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1831
1832 /*
1833 * Identify RF chipset.
1834 */
1835 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1836 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1837
1838 rt2x00_set_chip_rf(rt2x00dev, value, reg);
1839
1840 if (rt2x00_intf_is_usb(rt2x00dev)) {
1841 /*
1842 * The check for rt2860 is not a typo, some rt2870 hardware
1843 * identifies itself as rt2860 in the CSR register.
1844 */
1845 if (rt2x00_check_rev(rt2x00dev, 0xfff00000, 0x28600000) ||
1846 rt2x00_check_rev(rt2x00dev, 0xfff00000, 0x28700000) ||
1847 rt2x00_check_rev(rt2x00dev, 0xfff00000, 0x28800000)) {
1848 rt2x00_set_chip_rt(rt2x00dev, RT2870);
1849 } else if (rt2x00_check_rev(rt2x00dev, 0xffff0000, 0x30700000)) {
1850 rt2x00_set_chip_rt(rt2x00dev, RT3070);
1851 } else {
1852 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1853 return -ENODEV;
1854 }
1855 }
1856 rt2x00_print_chip(rt2x00dev);
1857
1858 if (!rt2x00_rf(rt2x00dev, RF2820) &&
1859 !rt2x00_rf(rt2x00dev, RF2850) &&
1860 !rt2x00_rf(rt2x00dev, RF2720) &&
1861 !rt2x00_rf(rt2x00dev, RF2750) &&
1862 !rt2x00_rf(rt2x00dev, RF3020) &&
1863 !rt2x00_rf(rt2x00dev, RF2020) &&
1864 !rt2x00_rf(rt2x00dev, RF3021) &&
1865 !rt2x00_rf(rt2x00dev, RF3022) &&
1866 !rt2x00_rf(rt2x00dev, RF3052)) {
1867 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1868 return -ENODEV;
1869 }
1870
1871 /*
1872 * Identify default antenna configuration.
1873 */
1874 rt2x00dev->default_ant.tx =
1875 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1876 rt2x00dev->default_ant.rx =
1877 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1878
1879 /*
1880 * Read frequency offset and RF programming sequence.
1881 */
1882 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1883 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1884
1885 /*
1886 * Read external LNA informations.
1887 */
1888 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1889
1890 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1891 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1892 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1893 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1894
1895 /*
1896 * Detect if this device has an hardware controlled radio.
1897 */
1898 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1899 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1900
1901 /*
1902 * Store led settings, for correct led behaviour.
1903 */
1904 #ifdef CONFIG_RT2X00_LIB_LEDS
1905 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1906 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1907 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
1908
1909 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1910 #endif /* CONFIG_RT2X00_LIB_LEDS */
1911
1912 return 0;
1913 }
1914 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
1915
1916 /*
1917 * RF value list for rt28x0
1918 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1919 */
1920 static const struct rf_channel rf_vals[] = {
1921 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1922 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1923 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1924 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1925 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1926 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1927 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1928 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1929 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1930 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1931 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1932 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1933 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1934 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1935
1936 /* 802.11 UNI / HyperLan 2 */
1937 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1938 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1939 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1940 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1941 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1942 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1943 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1944 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1945 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1946 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1947 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1948 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1949
1950 /* 802.11 HyperLan 2 */
1951 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1952 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1953 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1954 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1955 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1956 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1957 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1958 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1959 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1960 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1961 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1962 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1963 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1964 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1965 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1966 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1967
1968 /* 802.11 UNII */
1969 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1970 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
1971 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
1972 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
1973 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
1974 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
1975 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
1976 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
1977 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
1978 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
1979 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
1980
1981 /* 802.11 Japan */
1982 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
1983 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
1984 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
1985 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
1986 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
1987 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
1988 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
1989 };
1990
1991 /*
1992 * RF value list for rt3070
1993 * Supports: 2.4 GHz
1994 */
1995 static const struct rf_channel rf_vals_302x[] = {
1996 {1, 241, 2, 2 },
1997 {2, 241, 2, 7 },
1998 {3, 242, 2, 2 },
1999 {4, 242, 2, 7 },
2000 {5, 243, 2, 2 },
2001 {6, 243, 2, 7 },
2002 {7, 244, 2, 2 },
2003 {8, 244, 2, 7 },
2004 {9, 245, 2, 2 },
2005 {10, 245, 2, 7 },
2006 {11, 246, 2, 2 },
2007 {12, 246, 2, 7 },
2008 {13, 247, 2, 2 },
2009 {14, 248, 2, 4 },
2010 };
2011
2012 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2013 {
2014 struct hw_mode_spec *spec = &rt2x00dev->spec;
2015 struct channel_info *info;
2016 char *tx_power1;
2017 char *tx_power2;
2018 unsigned int i;
2019 u16 eeprom;
2020
2021 /*
2022 * Disable powersaving as default on PCI devices.
2023 */
2024 if (rt2x00_intf_is_pci(rt2x00dev))
2025 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2026
2027 /*
2028 * Initialize all hw fields.
2029 */
2030 rt2x00dev->hw->flags =
2031 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2032 IEEE80211_HW_SIGNAL_DBM |
2033 IEEE80211_HW_SUPPORTS_PS |
2034 IEEE80211_HW_PS_NULLFUNC_STACK;
2035
2036 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2037 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2038 rt2x00_eeprom_addr(rt2x00dev,
2039 EEPROM_MAC_ADDR_0));
2040
2041 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2042
2043 /*
2044 * Initialize hw_mode information.
2045 */
2046 spec->supported_bands = SUPPORT_BAND_2GHZ;
2047 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2048
2049 if (rt2x00_rf(rt2x00dev, RF2820) ||
2050 rt2x00_rf(rt2x00dev, RF2720) ||
2051 rt2x00_rf(rt2x00dev, RF3052)) {
2052 spec->num_channels = 14;
2053 spec->channels = rf_vals;
2054 } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
2055 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2056 spec->num_channels = ARRAY_SIZE(rf_vals);
2057 spec->channels = rf_vals;
2058 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2059 rt2x00_rf(rt2x00dev, RF2020) ||
2060 rt2x00_rf(rt2x00dev, RF3021) ||
2061 rt2x00_rf(rt2x00dev, RF3022)) {
2062 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2063 spec->channels = rf_vals_302x;
2064 }
2065
2066 /*
2067 * Initialize HT information.
2068 */
2069 if (!rt2x00_rf(rt2x00dev, RF2020))
2070 spec->ht.ht_supported = true;
2071 else
2072 spec->ht.ht_supported = false;
2073
2074 spec->ht.cap =
2075 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2076 IEEE80211_HT_CAP_GRN_FLD |
2077 IEEE80211_HT_CAP_SGI_20 |
2078 IEEE80211_HT_CAP_SGI_40 |
2079 IEEE80211_HT_CAP_TX_STBC |
2080 IEEE80211_HT_CAP_RX_STBC;
2081 spec->ht.ampdu_factor = 3;
2082 spec->ht.ampdu_density = 4;
2083 spec->ht.mcs.tx_params =
2084 IEEE80211_HT_MCS_TX_DEFINED |
2085 IEEE80211_HT_MCS_TX_RX_DIFF |
2086 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2087 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2088
2089 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2090 case 3:
2091 spec->ht.mcs.rx_mask[2] = 0xff;
2092 case 2:
2093 spec->ht.mcs.rx_mask[1] = 0xff;
2094 case 1:
2095 spec->ht.mcs.rx_mask[0] = 0xff;
2096 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2097 break;
2098 }
2099
2100 /*
2101 * Create channel information array
2102 */
2103 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2104 if (!info)
2105 return -ENOMEM;
2106
2107 spec->channels_info = info;
2108
2109 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2110 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2111
2112 for (i = 0; i < 14; i++) {
2113 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2114 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2115 }
2116
2117 if (spec->num_channels > 14) {
2118 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2119 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2120
2121 for (i = 14; i < spec->num_channels; i++) {
2122 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2123 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2124 }
2125 }
2126
2127 return 0;
2128 }
2129 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2130
2131 /*
2132 * IEEE80211 stack callback functions.
2133 */
2134 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2135 u32 *iv32, u16 *iv16)
2136 {
2137 struct rt2x00_dev *rt2x00dev = hw->priv;
2138 struct mac_iveiv_entry iveiv_entry;
2139 u32 offset;
2140
2141 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2142 rt2800_register_multiread(rt2x00dev, offset,
2143 &iveiv_entry, sizeof(iveiv_entry));
2144
2145 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2146 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2147 }
2148
2149 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2150 {
2151 struct rt2x00_dev *rt2x00dev = hw->priv;
2152 u32 reg;
2153 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2154
2155 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2156 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2157 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2158
2159 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2160 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2161 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2162
2163 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2164 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2165 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2166
2167 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2168 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2169 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2170
2171 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2172 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2173 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2174
2175 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2176 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2177 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2178
2179 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2180 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2181 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2182
2183 return 0;
2184 }
2185
2186 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2187 const struct ieee80211_tx_queue_params *params)
2188 {
2189 struct rt2x00_dev *rt2x00dev = hw->priv;
2190 struct data_queue *queue;
2191 struct rt2x00_field32 field;
2192 int retval;
2193 u32 reg;
2194 u32 offset;
2195
2196 /*
2197 * First pass the configuration through rt2x00lib, that will
2198 * update the queue settings and validate the input. After that
2199 * we are free to update the registers based on the value
2200 * in the queue parameter.
2201 */
2202 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2203 if (retval)
2204 return retval;
2205
2206 /*
2207 * We only need to perform additional register initialization
2208 * for WMM queues/
2209 */
2210 if (queue_idx >= 4)
2211 return 0;
2212
2213 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2214
2215 /* Update WMM TXOP register */
2216 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2217 field.bit_offset = (queue_idx & 1) * 16;
2218 field.bit_mask = 0xffff << field.bit_offset;
2219
2220 rt2800_register_read(rt2x00dev, offset, &reg);
2221 rt2x00_set_field32(&reg, field, queue->txop);
2222 rt2800_register_write(rt2x00dev, offset, reg);
2223
2224 /* Update WMM registers */
2225 field.bit_offset = queue_idx * 4;
2226 field.bit_mask = 0xf << field.bit_offset;
2227
2228 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2229 rt2x00_set_field32(&reg, field, queue->aifs);
2230 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2231
2232 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2233 rt2x00_set_field32(&reg, field, queue->cw_min);
2234 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2235
2236 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2237 rt2x00_set_field32(&reg, field, queue->cw_max);
2238 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2239
2240 /* Update EDCA registers */
2241 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2242
2243 rt2800_register_read(rt2x00dev, offset, &reg);
2244 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2245 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2246 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2247 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2248 rt2800_register_write(rt2x00dev, offset, reg);
2249
2250 return 0;
2251 }
2252
2253 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2254 {
2255 struct rt2x00_dev *rt2x00dev = hw->priv;
2256 u64 tsf;
2257 u32 reg;
2258
2259 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2260 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2261 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2262 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2263
2264 return tsf;
2265 }
2266
2267 const struct ieee80211_ops rt2800_mac80211_ops = {
2268 .tx = rt2x00mac_tx,
2269 .start = rt2x00mac_start,
2270 .stop = rt2x00mac_stop,
2271 .add_interface = rt2x00mac_add_interface,
2272 .remove_interface = rt2x00mac_remove_interface,
2273 .config = rt2x00mac_config,
2274 .configure_filter = rt2x00mac_configure_filter,
2275 .set_tim = rt2x00mac_set_tim,
2276 .set_key = rt2x00mac_set_key,
2277 .get_stats = rt2x00mac_get_stats,
2278 .get_tkip_seq = rt2800_get_tkip_seq,
2279 .set_rts_threshold = rt2800_set_rts_threshold,
2280 .bss_info_changed = rt2x00mac_bss_info_changed,
2281 .conf_tx = rt2800_conf_tx,
2282 .get_tx_stats = rt2x00mac_get_tx_stats,
2283 .get_tsf = rt2800_get_tsf,
2284 .rfkill_poll = rt2x00mac_rfkill_poll,
2285 };
2286 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
Linux 2.6 libata-dev (mirror)