drivers/net/qla3xxx.h

   1 /*
   2  * QLogic QLA3xxx NIC HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla3xxx for copyright and licensing details.
   6  */
   7 #ifndef _QLA3XXX_H_
   8 #define _QLA3XXX_H_
   9
  10 /*
  11  * IOCB Definitions...
  12  */
  13 #pragma pack(1)
  14
  15 #define OPCODE_OB_MAC_IOCB_FN0          0x01
  16 #define OPCODE_OB_MAC_IOCB_FN2          0x21
  17
  18 #define OPCODE_IB_MAC_IOCB          0xF9
  19 #define OPCODE_IB_3032_MAC_IOCB     0x09
  20 #define OPCODE_IB_IP_IOCB           0xFA
  21 #define OPCODE_IB_3032_IP_IOCB      0x0A
  22
  23 #define OPCODE_FUNC_ID_MASK                 0x30
  24 #define OUTBOUND_MAC_IOCB                   0x01        /* plus function bits */
  25 #define OUTBOUND_TCP_IOCB                   0x03        /* plus function bits */
  26 #define UPDATE_NCB_IOCB                     0x00        /* plus function bits */
  27
  28 #define FN0_MA_BITS_MASK    0x00
  29 #define FN1_MA_BITS_MASK    0x80
  30
  31 struct ob_mac_iocb_req {
  32         u8 opcode;
  33         u8 flags;
  34 #define OB_MAC_IOCB_REQ_MA  0xe0
  35 #define OB_MAC_IOCB_REQ_F   0x10
  36 #define OB_MAC_IOCB_REQ_X   0x08
  37 #define OB_MAC_IOCB_REQ_D   0x02
  38 #define OB_MAC_IOCB_REQ_I   0x01
  39         u8 flags1;
  40 #define OB_3032MAC_IOCB_REQ_IC  0x04
  41 #define OB_3032MAC_IOCB_REQ_TC  0x02
  42 #define OB_3032MAC_IOCB_REQ_UC  0x01
  43         u8 reserved0;
  44
  45         u32 transaction_id;     /* opaque for hardware */
  46         __le16 data_len;
  47         u8 ip_hdr_off;
  48         u8 ip_hdr_len;
  49         __le32 reserved1;
  50         __le32 reserved2;
  51         __le32 buf_addr0_low;
  52         __le32 buf_addr0_high;
  53         __le32 buf_0_len;
  54         __le32 buf_addr1_low;
  55         __le32 buf_addr1_high;
  56         __le32 buf_1_len;
  57         __le32 buf_addr2_low;
  58         __le32 buf_addr2_high;
  59         __le32 buf_2_len;
  60         __le32 reserved3;
  61         __le32 reserved4;
  62 };
  63 /*
  64  * The following constants define control bits for buffer
  65  * length fields for all IOCB's.
  66  */
  67 #define OB_MAC_IOCB_REQ_E   0x80000000  /* Last valid buffer in list. */
  68 #define OB_MAC_IOCB_REQ_C   0x40000000  /* points to an OAL. (continuation) */
  69 #define OB_MAC_IOCB_REQ_L   0x20000000  /* Auburn local address pointer. */
  70 #define OB_MAC_IOCB_REQ_R   0x10000000  /* 32-bit address pointer. */
  71
  72 struct ob_mac_iocb_rsp {
  73         u8 opcode;
  74         u8 flags;
  75 #define OB_MAC_IOCB_RSP_P   0x08
  76 #define OB_MAC_IOCB_RSP_L   0x04
  77 #define OB_MAC_IOCB_RSP_S   0x02
  78 #define OB_MAC_IOCB_RSP_I   0x01
  79
  80         __le16 reserved0;
  81         u32 transaction_id;     /* opaque for hardware */
  82         __le32 reserved1;
  83         __le32 reserved2;
  84 };
  85
  86 struct ib_mac_iocb_rsp {
  87         u8 opcode;
  88 #define IB_MAC_IOCB_RSP_V   0x80
  89         u8 flags;
  90 #define IB_MAC_IOCB_RSP_S   0x80
  91 #define IB_MAC_IOCB_RSP_H1  0x40
  92 #define IB_MAC_IOCB_RSP_H0  0x20
  93 #define IB_MAC_IOCB_RSP_B   0x10
  94 #define IB_MAC_IOCB_RSP_M   0x08
  95 #define IB_MAC_IOCB_RSP_MA  0x07
  96
  97         __le16 length;
  98         __le32 reserved;
  99         __le32 ial_low;
 100         __le32 ial_high;
 101
 102 };
 103
 104 struct ob_ip_iocb_req {
 105         u8 opcode;
 106         __le16 flags;
 107 #define OB_IP_IOCB_REQ_O        0x100
 108 #define OB_IP_IOCB_REQ_H        0x008
 109 #define OB_IP_IOCB_REQ_U        0x004
 110 #define OB_IP_IOCB_REQ_D        0x002
 111 #define OB_IP_IOCB_REQ_I        0x001
 112
 113         u8 reserved0;
 114
 115         __le32 transaction_id;
 116         __le16 data_len;
 117         __le16 reserved1;
 118         __le32 hncb_ptr_low;
 119         __le32 hncb_ptr_high;
 120         __le32 buf_addr0_low;
 121         __le32 buf_addr0_high;
 122         __le32 buf_0_len;
 123         __le32 buf_addr1_low;
 124         __le32 buf_addr1_high;
 125         __le32 buf_1_len;
 126         __le32 buf_addr2_low;
 127         __le32 buf_addr2_high;
 128         __le32 buf_2_len;
 129         __le32 reserved2;
 130         __le32 reserved3;
 131 };
 132
 133 /* defines for BufferLength fields above */
 134 #define OB_IP_IOCB_REQ_E    0x80000000
 135 #define OB_IP_IOCB_REQ_C    0x40000000
 136 #define OB_IP_IOCB_REQ_L    0x20000000
 137 #define OB_IP_IOCB_REQ_R    0x10000000
 138
 139 struct ob_ip_iocb_rsp {
 140         u8 opcode;
 141         u8 flags;
 142 #define OB_MAC_IOCB_RSP_H       0x10
 143 #define OB_MAC_IOCB_RSP_E       0x08
 144 #define OB_MAC_IOCB_RSP_L       0x04
 145 #define OB_MAC_IOCB_RSP_S       0x02
 146 #define OB_MAC_IOCB_RSP_I       0x01
 147
 148         __le16 reserved0;
 149         __le32 transaction_id;
 150         __le32 reserved1;
 151         __le32 reserved2;
 152 };
 153
 154 struct ob_tcp_iocb_req {
 155         u8 opcode;
 156
 157         u8 flags0;
 158 #define OB_TCP_IOCB_REQ_P       0x80
 159 #define OB_TCP_IOCB_REQ_CI      0x20
 160 #define OB_TCP_IOCB_REQ_H       0x10
 161 #define OB_TCP_IOCB_REQ_LN      0x08
 162 #define OB_TCP_IOCB_REQ_K       0x04
 163 #define OB_TCP_IOCB_REQ_D       0x02
 164 #define OB_TCP_IOCB_REQ_I       0x01
 165
 166         u8 flags1;
 167 #define OB_TCP_IOCB_REQ_OSM     0x40
 168 #define OB_TCP_IOCB_REQ_URG     0x20
 169 #define OB_TCP_IOCB_REQ_ACK     0x10
 170 #define OB_TCP_IOCB_REQ_PSH     0x08
 171 #define OB_TCP_IOCB_REQ_RST     0x04
 172 #define OB_TCP_IOCB_REQ_SYN     0x02
 173 #define OB_TCP_IOCB_REQ_FIN     0x01
 174
 175         u8 options_len;
 176 #define OB_TCP_IOCB_REQ_OMASK   0xF0
 177 #define OB_TCP_IOCB_REQ_SHIFT   4
 178
 179         __le32 transaction_id;
 180         __le32 data_len;
 181         __le32 hncb_ptr_low;
 182         __le32 hncb_ptr_high;
 183         __le32 buf_addr0_low;
 184         __le32 buf_addr0_high;
 185         __le32 buf_0_len;
 186         __le32 buf_addr1_low;
 187         __le32 buf_addr1_high;
 188         __le32 buf_1_len;
 189         __le32 buf_addr2_low;
 190         __le32 buf_addr2_high;
 191         __le32 buf_2_len;
 192         __le32 time_stamp;
 193         __le32 reserved1;
 194 };
 195
 196 struct ob_tcp_iocb_rsp {
 197         u8 opcode;
 198
 199         u8 flags0;
 200 #define OB_TCP_IOCB_RSP_C       0x20
 201 #define OB_TCP_IOCB_RSP_H       0x10
 202 #define OB_TCP_IOCB_RSP_LN      0x08
 203 #define OB_TCP_IOCB_RSP_K       0x04
 204 #define OB_TCP_IOCB_RSP_D       0x02
 205 #define OB_TCP_IOCB_RSP_I       0x01
 206
 207         u8 flags1;
 208 #define OB_TCP_IOCB_RSP_E       0x10
 209 #define OB_TCP_IOCB_RSP_W       0x08
 210 #define OB_TCP_IOCB_RSP_P       0x04
 211 #define OB_TCP_IOCB_RSP_T       0x02
 212 #define OB_TCP_IOCB_RSP_F       0x01
 213
 214         u8 state;
 215 #define OB_TCP_IOCB_RSP_SMASK   0xF0
 216 #define OB_TCP_IOCB_RSP_SHIFT   4
 217
 218         __le32 transaction_id;
 219         __le32 local_ncb_ptr;
 220         __le32 reserved0;
 221 };
 222
 223 struct ib_ip_iocb_rsp {
 224         u8 opcode;
 225 #define IB_IP_IOCB_RSP_3032_V   0x80
 226 #define IB_IP_IOCB_RSP_3032_O   0x40
 227 #define IB_IP_IOCB_RSP_3032_I   0x20
 228 #define IB_IP_IOCB_RSP_3032_R   0x10
 229         u8 flags;
 230 #define IB_IP_IOCB_RSP_S        0x80
 231 #define IB_IP_IOCB_RSP_H1       0x40
 232 #define IB_IP_IOCB_RSP_H0       0x20
 233 #define IB_IP_IOCB_RSP_B        0x10
 234 #define IB_IP_IOCB_RSP_M        0x08
 235 #define IB_IP_IOCB_RSP_MA       0x07
 236
 237         __le16 length;
 238         __le16 checksum;
 239 #define IB_IP_IOCB_RSP_3032_ICE         0x01
 240 #define IB_IP_IOCB_RSP_3032_CE          0x02
 241 #define IB_IP_IOCB_RSP_3032_NUC         0x04
 242 #define IB_IP_IOCB_RSP_3032_UDP         0x08
 243 #define IB_IP_IOCB_RSP_3032_TCP         0x10
 244 #define IB_IP_IOCB_RSP_3032_IPE         0x20
 245         __le16 reserved;
 246 #define IB_IP_IOCB_RSP_R        0x01
 247         __le32 ial_low;
 248         __le32 ial_high;
 249 };
 250
 251 struct ib_tcp_iocb_rsp {
 252         u8 opcode;
 253         u8 flags;
 254 #define IB_TCP_IOCB_RSP_P       0x80
 255 #define IB_TCP_IOCB_RSP_T       0x40
 256 #define IB_TCP_IOCB_RSP_D       0x20
 257 #define IB_TCP_IOCB_RSP_N       0x10
 258 #define IB_TCP_IOCB_RSP_IP      0x03
 259 #define IB_TCP_FLAG_MASK        0xf0
 260 #define IB_TCP_FLAG_IOCB_SYN    0x00
 261
 262 #define TCP_IB_RSP_FLAGS(x) (x->flags & ~IB_TCP_FLAG_MASK)
 263
 264         __le16 length;
 265         __le32 hncb_ref_num;
 266         __le32 ial_low;
 267         __le32 ial_high;
 268 };
 269
 270 struct net_rsp_iocb {
 271         u8 opcode;
 272         u8 flags;
 273         __le16 reserved0;
 274         __le32 reserved[3];
 275 };
 276 #pragma pack()
 277
 278 /*
 279  * Register Definitions...
 280  */
 281 #define PORT0_PHY_ADDRESS   0x1e00
 282 #define PORT1_PHY_ADDRESS   0x1f00
 283
 284 #define ETHERNET_CRC_SIZE   4
 285
 286 #define MII_SCAN_REGISTER 0x00000001
 287
 288 #define PHY_ID_0_REG    2
 289 #define PHY_ID_1_REG    3
 290
 291 #define PHY_OUI_1_MASK       0xfc00
 292 #define PHY_MODEL_MASK       0x03f0
 293
 294 /*  Address for the Agere Phy */
 295 #define MII_AGERE_ADDR_1  0x00001000
 296 #define MII_AGERE_ADDR_2  0x00001100
 297
 298 /* 32-bit ispControlStatus */
 299 enum {
 300         ISP_CONTROL_NP_MASK = 0x0003,
 301         ISP_CONTROL_NP_PCSR = 0x0000,
 302         ISP_CONTROL_NP_HMCR = 0x0001,
 303         ISP_CONTROL_NP_LRAMCR = 0x0002,
 304         ISP_CONTROL_NP_PSR = 0x0003,
 305         ISP_CONTROL_RI = 0x0008,
 306         ISP_CONTROL_CI = 0x0010,
 307         ISP_CONTROL_PI = 0x0020,
 308         ISP_CONTROL_IN = 0x0040,
 309         ISP_CONTROL_BE = 0x0080,
 310         ISP_CONTROL_FN_MASK = 0x0700,
 311         ISP_CONTROL_FN0_NET = 0x0400,
 312         ISP_CONTROL_FN0_SCSI = 0x0500,
 313         ISP_CONTROL_FN1_NET = 0x0600,
 314         ISP_CONTROL_FN1_SCSI = 0x0700,
 315         ISP_CONTROL_LINK_DN_0 = 0x0800,
 316         ISP_CONTROL_LINK_DN_1 = 0x1000,
 317         ISP_CONTROL_FSR = 0x2000,
 318         ISP_CONTROL_FE = 0x4000,
 319         ISP_CONTROL_SR = 0x8000,
 320 };
 321
 322 /* 32-bit ispInterruptMaskReg */
 323 enum {
 324         ISP_IMR_ENABLE_INT = 0x0004,
 325         ISP_IMR_DISABLE_RESET_INT = 0x0008,
 326         ISP_IMR_DISABLE_CMPL_INT = 0x0010,
 327         ISP_IMR_DISABLE_PROC_INT = 0x0020,
 328 };
 329
 330 /* 32-bit serialPortInterfaceReg */
 331 enum {
 332         ISP_SERIAL_PORT_IF_CLK = 0x0001,
 333         ISP_SERIAL_PORT_IF_CS = 0x0002,
 334         ISP_SERIAL_PORT_IF_D0 = 0x0004,
 335         ISP_SERIAL_PORT_IF_DI = 0x0008,
 336         ISP_NVRAM_MASK = (0x000F << 16),
 337         ISP_SERIAL_PORT_IF_WE = 0x0010,
 338         ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,
 339         ISP_SERIAL_PORT_IF_SCI = 0x0400,
 340         ISP_SERIAL_PORT_IF_SC0 = 0x0800,
 341         ISP_SERIAL_PORT_IF_SCE = 0x1000,
 342         ISP_SERIAL_PORT_IF_SDI = 0x2000,
 343         ISP_SERIAL_PORT_IF_SDO = 0x4000,
 344         ISP_SERIAL_PORT_IF_SDE = 0x8000,
 345         ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00,
 346 };
 347
 348 /* semaphoreReg */
 349 enum {
 350         QL_RESOURCE_MASK_BASE_CODE = 0x7,
 351         QL_RESOURCE_BITS_BASE_CODE = 0x4,
 352         QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1),
 353         QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),
 354         QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7),
 355         QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10),
 356         QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13),
 357         QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),
 358         QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)),
 359         QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)),
 360         QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)),
 361         QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16)),
 362 };
 363
 364  /*
 365   * QL3XXX memory-mapped registers
 366   * QL3XXX has 4 "pages" of registers, each page occupying
 367   * 256 bytes.  Each page has a "common" area at the start and then
 368   * page-specific registers after that.
 369   */
 370 struct ql3xxx_common_registers {
 371         u32 MB0;                /* Offset 0x00 */
 372         u32 MB1;                /* Offset 0x04 */
 373         u32 MB2;                /* Offset 0x08 */
 374         u32 MB3;                /* Offset 0x0c */
 375         u32 MB4;                /* Offset 0x10 */
 376         u32 MB5;                /* Offset 0x14 */
 377         u32 MB6;                /* Offset 0x18 */
 378         u32 MB7;                /* Offset 0x1c */
 379         u32 flashBiosAddr;
 380         u32 flashBiosData;
 381         u32 ispControlStatus;
 382         u32 ispInterruptMaskReg;
 383         u32 serialPortInterfaceReg;
 384         u32 semaphoreReg;
 385         u32 reqQProducerIndex;
 386         u32 rspQConsumerIndex;
 387
 388         u32 rxLargeQProducerIndex;
 389         u32 rxSmallQProducerIndex;
 390         u32 arcMadiCommand;
 391         u32 arcMadiData;
 392 };
 393
 394 enum {
 395         EXT_HW_CONFIG_SP_MASK = 0x0006,
 396         EXT_HW_CONFIG_SP_NONE = 0x0000,
 397         EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,
 398         EXT_HW_CONFIG_SP_ECC = 0x0004,
 399         EXT_HW_CONFIG_SP_ECCx = 0x0006,
 400         EXT_HW_CONFIG_SIZE_MASK = 0x0060,
 401         EXT_HW_CONFIG_SIZE_128M = 0x0000,
 402         EXT_HW_CONFIG_SIZE_256M = 0x0020,
 403         EXT_HW_CONFIG_SIZE_512M = 0x0040,
 404         EXT_HW_CONFIG_SIZE_INVALID = 0x0060,
 405         EXT_HW_CONFIG_PD = 0x0080,
 406         EXT_HW_CONFIG_FW = 0x0200,
 407         EXT_HW_CONFIG_US = 0x0400,
 408         EXT_HW_CONFIG_DCS_MASK = 0x1800,
 409         EXT_HW_CONFIG_DCS_9MA = 0x0000,
 410         EXT_HW_CONFIG_DCS_15MA = 0x0800,
 411         EXT_HW_CONFIG_DCS_18MA = 0x1000,
 412         EXT_HW_CONFIG_DCS_24MA = 0x1800,
 413         EXT_HW_CONFIG_DDS_MASK = 0x6000,
 414         EXT_HW_CONFIG_DDS_9MA = 0x0000,
 415         EXT_HW_CONFIG_DDS_15MA = 0x2000,
 416         EXT_HW_CONFIG_DDS_18MA = 0x4000,
 417         EXT_HW_CONFIG_DDS_24MA = 0x6000,
 418 };
 419
 420 /* InternalChipConfig */
 421 enum {
 422         INTERNAL_CHIP_DM = 0x0001,
 423         INTERNAL_CHIP_SD = 0x0002,
 424         INTERNAL_CHIP_RAP_MASK = 0x000C,
 425         INTERNAL_CHIP_RAP_RR = 0x0000,
 426         INTERNAL_CHIP_RAP_NRM = 0x0004,
 427         INTERNAL_CHIP_RAP_ERM = 0x0008,
 428         INTERNAL_CHIP_RAP_ERMx = 0x000C,
 429         INTERNAL_CHIP_WE = 0x0010,
 430         INTERNAL_CHIP_EF = 0x0020,
 431         INTERNAL_CHIP_FR = 0x0040,
 432         INTERNAL_CHIP_FW = 0x0080,
 433         INTERNAL_CHIP_FI = 0x0100,
 434         INTERNAL_CHIP_FT = 0x0200,
 435 };
 436
 437 /* portControl */
 438 enum {
 439         PORT_CONTROL_DS = 0x0001,
 440         PORT_CONTROL_HH = 0x0002,
 441         PORT_CONTROL_EI = 0x0004,
 442         PORT_CONTROL_ET = 0x0008,
 443         PORT_CONTROL_EF = 0x0010,
 444         PORT_CONTROL_DRM = 0x0020,
 445         PORT_CONTROL_RLB = 0x0040,
 446         PORT_CONTROL_RCB = 0x0080,
 447         PORT_CONTROL_MAC = 0x0100,
 448         PORT_CONTROL_IPV = 0x0200,
 449         PORT_CONTROL_IFP = 0x0400,
 450         PORT_CONTROL_ITP = 0x0800,
 451         PORT_CONTROL_FI = 0x1000,
 452         PORT_CONTROL_DFP = 0x2000,
 453         PORT_CONTROL_OI = 0x4000,
 454         PORT_CONTROL_CC = 0x8000,
 455 };
 456
 457 /* portStatus */
 458 enum {
 459         PORT_STATUS_SM0 = 0x0001,
 460         PORT_STATUS_SM1 = 0x0002,
 461         PORT_STATUS_X = 0x0008,
 462         PORT_STATUS_DL = 0x0080,
 463         PORT_STATUS_IC = 0x0200,
 464         PORT_STATUS_MRC = 0x0400,
 465         PORT_STATUS_NL = 0x0800,
 466         PORT_STATUS_REV_ID_MASK = 0x7000,
 467         PORT_STATUS_REV_ID_1 = 0x1000,
 468         PORT_STATUS_REV_ID_2 = 0x2000,
 469         PORT_STATUS_REV_ID_3 = 0x3000,
 470         PORT_STATUS_64 = 0x8000,
 471         PORT_STATUS_UP0 = 0x10000,
 472         PORT_STATUS_AC0 = 0x20000,
 473         PORT_STATUS_AE0 = 0x40000,
 474         PORT_STATUS_UP1 = 0x100000,
 475         PORT_STATUS_AC1 = 0x200000,
 476         PORT_STATUS_AE1 = 0x400000,
 477         PORT_STATUS_F0_ENABLED = 0x1000000,
 478         PORT_STATUS_F1_ENABLED = 0x2000000,
 479         PORT_STATUS_F2_ENABLED = 0x4000000,
 480         PORT_STATUS_F3_ENABLED = 0x8000000,
 481 };
 482
 483 /* macMIIMgmtControlReg */
 484 enum {
 485         MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,
 486         MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,
 487         MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,
 488         MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
 489         MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,
 490         MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,
 491         MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,
 492         MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
 493         MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,
 494         MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080,
 495 };
 496
 497 /* macMIIMgmtControlReg */
 498 enum {
 499         MAC_MII_CONTROL_RC = 0x0001,
 500         MAC_MII_CONTROL_SC = 0x0002,
 501         MAC_MII_CONTROL_AS = 0x0004,
 502         MAC_MII_CONTROL_NP = 0x0008,
 503         MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,
 504         MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,
 505         MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,
 506         MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
 507         MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,
 508         MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,
 509         MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,
 510         MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
 511         MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,
 512         MAC_MII_CONTROL_RM = 0x8000,
 513 };
 514
 515 /* macMIIStatusReg */
 516 enum {
 517         MAC_MII_STATUS_BSY = 0x0001,
 518         MAC_MII_STATUS_SC = 0x0002,
 519         MAC_MII_STATUS_NV = 0x0004,
 520 };
 521
 522 enum {
 523         MAC_CONFIG_REG_PE = 0x0001,
 524         MAC_CONFIG_REG_TF = 0x0002,
 525         MAC_CONFIG_REG_RF = 0x0004,
 526         MAC_CONFIG_REG_FD = 0x0008,
 527         MAC_CONFIG_REG_GM = 0x0010,
 528         MAC_CONFIG_REG_LB = 0x0020,
 529         MAC_CONFIG_REG_SR = 0x8000,
 530 };
 531
 532 enum {
 533         MAC_HALF_DUPLEX_REG_ED = 0x10000,
 534         MAC_HALF_DUPLEX_REG_NB = 0x20000,
 535         MAC_HALF_DUPLEX_REG_BNB = 0x40000,
 536         MAC_HALF_DUPLEX_REG_ALT = 0x80000,
 537 };
 538
 539 enum {
 540         IP_ADDR_INDEX_REG_MASK = 0x000f,
 541         IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,
 542         IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,
 543         IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
 544         IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,
 545         IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,
 546         IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
 547         IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
 548         IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
 549         IP_ADDR_INDEX_REG_6 = 0x0008,
 550         IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
 551         IP_ADDR_INDEX_REG_E = 0x0040,
 552 };
 553 enum {
 554         QL3032_PORT_CONTROL_DS = 0x0001,
 555         QL3032_PORT_CONTROL_HH = 0x0002,
 556         QL3032_PORT_CONTROL_EIv6 = 0x0004,
 557         QL3032_PORT_CONTROL_EIv4 = 0x0008,
 558         QL3032_PORT_CONTROL_ET = 0x0010,
 559         QL3032_PORT_CONTROL_EF = 0x0020,
 560         QL3032_PORT_CONTROL_DRM = 0x0040,
 561         QL3032_PORT_CONTROL_RLB = 0x0080,
 562         QL3032_PORT_CONTROL_RCB = 0x0100,
 563         QL3032_PORT_CONTROL_KIE = 0x0200,
 564 };
 565
 566 enum {
 567         PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,
 568         PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,
 569         PROBE_MUX_ADDR_REG_PCICLK = 0x0040,
 570         PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
 571         PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,
 572         PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,
 573         PROBE_MUX_ADDR_REG_UP = 0x4000,
 574         PROBE_MUX_ADDR_REG_RE = 0x8000,
 575 };
 576
 577 enum {
 578         STATISTICS_INDEX_REG_MASK = 0x01ff,
 579         STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,
 580         STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,
 581         STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
 582         STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,
 583         STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,
 584         STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,
 585         STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
 586         STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,
 587         STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,
 588         STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,
 589         STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
 590         STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,
 591         STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,
 592         STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,
 593         STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
 594         STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,
 595         STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,
 596         STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,
 597         STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
 598         STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,
 599         STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,
 600         STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,
 601         STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
 602         STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,
 603         STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,
 604         STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,
 605         STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
 606         STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,
 607         STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,
 608         STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,
 609         STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
 610         STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,
 611         STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,
 612         STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,
 613         STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
 614         STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,
 615         STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,
 616         STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,
 617         STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
 618         STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,
 619         STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,
 620         STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,
 621         STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
 622         STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,
 623         STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,
 624         STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,
 625         STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
 626         STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,
 627         STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,
 628         STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,
 629         STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
 630         STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f,
 631 };
 632
 633 enum {
 634         PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,
 635         PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,
 636         PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,
 637         PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
 638         PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,
 639         PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,
 640         PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,
 641         PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
 642         PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,
 643         PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,
 644         PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,
 645         PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
 646         PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,
 647         PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,
 648         PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,
 649         PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
 650         PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,
 651         PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,
 652         PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,
 653         PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
 654         PORT_FATAL_ERROR_STATUS_MA = 0x00100000,
 655         PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,
 656         PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,
 657         PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
 658         PORT_FATAL_ERROR_STATUS_OCE = 0x01000000,
 659 };
 660
 661 /*
 662  *  port control and status page - page 0
 663  */
 664
 665 struct ql3xxx_port_registers {
 666         struct ql3xxx_common_registers CommonRegs;
 667
 668         u32 ExternalHWConfig;
 669         u32 InternalChipConfig;
 670         u32 portControl;
 671         u32 portStatus;
 672         u32 macAddrIndirectPtrReg;
 673         u32 macAddrDataReg;
 674         u32 macMIIMgmtControlReg;
 675         u32 macMIIMgmtAddrReg;
 676         u32 macMIIMgmtDataReg;
 677         u32 macMIIStatusReg;
 678         u32 mac0ConfigReg;
 679         u32 mac0IpgIfgReg;
 680         u32 mac0HalfDuplexReg;
 681         u32 mac0MaxFrameLengthReg;
 682         u32 mac0PauseThresholdReg;
 683         u32 mac1ConfigReg;
 684         u32 mac1IpgIfgReg;
 685         u32 mac1HalfDuplexReg;
 686         u32 mac1MaxFrameLengthReg;
 687         u32 mac1PauseThresholdReg;
 688         u32 ipAddrIndexReg;
 689         u32 ipAddrDataReg;
 690         u32 ipReassemblyTimeout;
 691         u32 tcpMaxWindow;
 692         u32 currentTcpTimestamp[2];
 693         u32 internalRamRWAddrReg;
 694         u32 internalRamWDataReg;
 695         u32 reclaimedBufferAddrRegLow;
 696         u32 reclaimedBufferAddrRegHigh;
 697         u32 tcpConfiguration;
 698         u32 functionControl;
 699         u32 fpgaRevID;
 700         u32 localRamAddr;
 701         u32 localRamDataAutoIncr;
 702         u32 localRamDataNonIncr;
 703         u32 gpOutput;
 704         u32 gpInput;
 705         u32 probeMuxAddr;
 706         u32 probeMuxData;
 707         u32 statisticsIndexReg;
 708         u32 statisticsReadDataRegAutoIncr;
 709         u32 statisticsReadDataRegNoIncr;
 710         u32 PortFatalErrStatus;
 711 };
 712
 713 /*
 714  * port host memory config page - page 1
 715  */
 716 struct ql3xxx_host_memory_registers {
 717         struct ql3xxx_common_registers CommonRegs;
 718
 719         u32 reserved[12];
 720
 721         /* Network Request Queue */
 722         u32 reqConsumerIndex;
 723         u32 reqConsumerIndexAddrLow;
 724         u32 reqConsumerIndexAddrHigh;
 725         u32 reqBaseAddrLow;
 726         u32 reqBaseAddrHigh;
 727         u32 reqLength;
 728
 729         /* Network Completion Queue */
 730         u32 rspProducerIndex;
 731         u32 rspProducerIndexAddrLow;
 732         u32 rspProducerIndexAddrHigh;
 733         u32 rspBaseAddrLow;
 734         u32 rspBaseAddrHigh;
 735         u32 rspLength;
 736
 737         /* RX Large Buffer Queue */
 738         u32 rxLargeQConsumerIndex;
 739         u32 rxLargeQBaseAddrLow;
 740         u32 rxLargeQBaseAddrHigh;
 741         u32 rxLargeQLength;
 742         u32 rxLargeBufferLength;
 743
 744         /* RX Small Buffer Queue */
 745         u32 rxSmallQConsumerIndex;
 746         u32 rxSmallQBaseAddrLow;
 747         u32 rxSmallQBaseAddrHigh;
 748         u32 rxSmallQLength;
 749         u32 rxSmallBufferLength;
 750
 751 };
 752
 753 /*
 754  *  port local RAM page - page 2
 755  */
 756 struct ql3xxx_local_ram_registers {
 757         struct ql3xxx_common_registers CommonRegs;
 758         u32 bufletSize;
 759         u32 maxBufletCount;
 760         u32 currentBufletCount;
 761         u32 reserved;
 762         u32 freeBufletThresholdLow;
 763         u32 freeBufletThresholdHigh;
 764         u32 ipHashTableBase;
 765         u32 ipHashTableCount;
 766         u32 tcpHashTableBase;
 767         u32 tcpHashTableCount;
 768         u32 ncbBase;
 769         u32 maxNcbCount;
 770         u32 currentNcbCount;
 771         u32 drbBase;
 772         u32 maxDrbCount;
 773         u32 currentDrbCount;
 774 };
 775
 776 /*
 777  * definitions for Semaphore bits in Semaphore/Serial NVRAM interface register
 778  */
 779
 780 #define LS_64BITS(x)    (u32)(0xffffffff & ((u64)x))
 781 #define MS_64BITS(x)    (u32)(0xffffffff & (((u64)x)>>16>>16) )
 782
 783 /*
 784  * I/O register
 785  */
 786
 787 enum {
 788         CONTROL_REG = 0,
 789         STATUS_REG = 1,
 790         PHY_STAT_LINK_UP = 0x0004,
 791         PHY_CTRL_LOOPBACK = 0x4000,
 792
 793         PETBI_CONTROL_REG = 0x00,
 794         PETBI_CTRL_ALL_PARAMS = 0x7140,
 795         PETBI_CTRL_SOFT_RESET = 0x8000,
 796         PETBI_CTRL_AUTO_NEG = 0x1000,
 797         PETBI_CTRL_RESTART_NEG = 0x0200,
 798         PETBI_CTRL_FULL_DUPLEX = 0x0100,
 799         PETBI_CTRL_SPEED_1000 = 0x0040,
 800
 801         PETBI_STATUS_REG = 0x01,
 802         PETBI_STAT_NEG_DONE = 0x0020,
 803         PETBI_STAT_LINK_UP = 0x0004,
 804
 805         PETBI_NEG_ADVER = 0x04,
 806         PETBI_NEG_PAUSE = 0x0080,
 807         PETBI_NEG_PAUSE_MASK = 0x0180,
 808         PETBI_NEG_DUPLEX = 0x0020,
 809         PETBI_NEG_DUPLEX_MASK = 0x0060,
 810
 811         PETBI_NEG_PARTNER = 0x05,
 812         PETBI_NEG_ERROR_MASK = 0x3000,
 813
 814         PETBI_EXPANSION_REG = 0x06,
 815         PETBI_EXP_PAGE_RX = 0x0002,
 816
 817         PHY_GIG_CONTROL = 9,
 818         PHY_GIG_ENABLE_MAN = 0x1000,  /* Enable Master/Slave Manual Config*/
 819         PHY_GIG_SET_MASTER = 0x0800,  /* Set Master (slave if clear)*/
 820         PHY_GIG_ALL_PARAMS = 0x0300,
 821         PHY_GIG_ADV_1000F = 0x0200,
 822         PHY_GIG_ADV_1000H = 0x0100,
 823
 824         PHY_NEG_ADVER = 4,
 825         PHY_NEG_ALL_PARAMS = 0x0fe0,
 826         PHY_NEG_ASY_PAUSE =  0x0800,
 827         PHY_NEG_SYM_PAUSE =  0x0400,
 828         PHY_NEG_ADV_SPEED =  0x01e0,
 829         PHY_NEG_ADV_100F =   0x0100,
 830         PHY_NEG_ADV_100H =   0x0080,
 831         PHY_NEG_ADV_10F =    0x0040,
 832         PHY_NEG_ADV_10H =    0x0020,
 833
 834         PETBI_TBI_CTRL = 0x11,
 835         PETBI_TBI_RESET = 0x8000,
 836         PETBI_TBI_AUTO_SENSE = 0x0100,
 837         PETBI_TBI_SERDES_MODE = 0x0010,
 838         PETBI_TBI_SERDES_WRAP = 0x0002,
 839
 840         AUX_CONTROL_STATUS = 0x1c,
 841         PHY_AUX_NEG_DONE = 0x8000,
 842         PHY_NEG_PARTNER = 5,
 843         PHY_AUX_DUPLEX_STAT = 0x0020,
 844         PHY_AUX_SPEED_STAT = 0x0018,
 845         PHY_AUX_NO_HW_STRAP = 0x0004,
 846         PHY_AUX_RESET_STICK = 0x0002,
 847         PHY_NEG_PAUSE = 0x0400,
 848         PHY_CTRL_SOFT_RESET = 0x8000,
 849         PHY_CTRL_AUTO_NEG = 0x1000,
 850         PHY_CTRL_RESTART_NEG = 0x0200,
 851 };
 852 enum {
 853 /* AM29LV Flash definitions     */
 854         FM93C56A_START = 0x1,
 855 /* Commands */
 856         FM93C56A_READ = 0x2,
 857         FM93C56A_WEN = 0x0,
 858         FM93C56A_WRITE = 0x1,
 859         FM93C56A_WRITE_ALL = 0x0,
 860         FM93C56A_WDS = 0x0,
 861         FM93C56A_ERASE = 0x3,
 862         FM93C56A_ERASE_ALL = 0x0,
 863 /* Command Extentions */
 864         FM93C56A_WEN_EXT = 0x3,
 865         FM93C56A_WRITE_ALL_EXT = 0x1,
 866         FM93C56A_WDS_EXT = 0x0,
 867         FM93C56A_ERASE_ALL_EXT = 0x2,
 868 /* Special Bits */
 869         FM93C56A_READ_DUMMY_BITS = 1,
 870         FM93C56A_READY = 0,
 871         FM93C56A_BUSY = 1,
 872         FM93C56A_CMD_BITS = 2,
 873 /* AM29LV Flash definitions     */
 874         FM93C56A_SIZE_8 = 0x100,
 875         FM93C56A_SIZE_16 = 0x80,
 876         FM93C66A_SIZE_8 = 0x200,
 877         FM93C66A_SIZE_16 = 0x100,
 878         FM93C86A_SIZE_16 = 0x400,
 879 /* Address Bits */
 880         FM93C56A_NO_ADDR_BITS_16 = 8,
 881         FM93C56A_NO_ADDR_BITS_8 = 9,
 882         FM93C86A_NO_ADDR_BITS_16 = 10,
 883 /* Data Bits */
 884         FM93C56A_DATA_BITS_16 = 16,
 885         FM93C56A_DATA_BITS_8 = 8,
 886 };
 887 enum {
 888 /* Auburn Bits */
 889             AUBURN_EEPROM_DI = 0x8,
 890         AUBURN_EEPROM_DI_0 = 0x0,
 891         AUBURN_EEPROM_DI_1 = 0x8,
 892         AUBURN_EEPROM_DO = 0x4,
 893         AUBURN_EEPROM_DO_0 = 0x0,
 894         AUBURN_EEPROM_DO_1 = 0x4,
 895         AUBURN_EEPROM_CS = 0x2,
 896         AUBURN_EEPROM_CS_0 = 0x0,
 897         AUBURN_EEPROM_CS_1 = 0x2,
 898         AUBURN_EEPROM_CLK_RISE = 0x1,
 899         AUBURN_EEPROM_CLK_FALL = 0x0,
 900 };
 901 enum {EEPROM_SIZE = FM93C86A_SIZE_16,
 902         EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16,
 903         EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16,
 904 };
 905
 906 /*
 907  *  MAC Config data structure
 908  */
 909     struct eeprom_port_cfg {
 910         u16 etherMtu_mac;
 911         u16 pauseThreshold_mac;
 912         u16 resumeThreshold_mac;
 913         u16 portConfiguration;
 914 #define PORT_CONFIG_DEFAULT                 0xf700
 915 #define PORT_CONFIG_AUTO_NEG_ENABLED        0x8000
 916 #define PORT_CONFIG_SYM_PAUSE_ENABLED       0x4000
 917 #define PORT_CONFIG_FULL_DUPLEX_ENABLED     0x2000
 918 #define PORT_CONFIG_HALF_DUPLEX_ENABLED     0x1000
 919 #define PORT_CONFIG_1000MB_SPEED            0x0400
 920 #define PORT_CONFIG_100MB_SPEED             0x0200
 921 #define PORT_CONFIG_10MB_SPEED              0x0100
 922 #define PORT_CONFIG_LINK_SPEED_MASK         0x0F00
 923         u16 reserved[12];
 924
 925 };
 926
 927 /*
 928  * BIOS data structure
 929  */
 930 struct eeprom_bios_cfg {
 931         u16 SpinDlyEn:1, disBios:1, EnMemMap:1, EnSelectBoot:1, Reserved:12;
 932
 933         u8 bootID0:7, boodID0Valid:1;
 934         u8 bootLun0[8];
 935
 936         u8 bootID1:7, boodID1Valid:1;
 937         u8 bootLun1[8];
 938
 939         u16 MaxLunsTrgt;
 940         u8 reserved[10];
 941 };
 942
 943 /*
 944  *  Function Specific Data structure
 945  */
 946 struct eeprom_function_cfg {
 947         u8 reserved[30];
 948         u16 macAddress[3];
 949         u16 macAddressSecondary[3];
 950
 951         u16 subsysVendorId;
 952         u16 subsysDeviceId;
 953 };
 954
 955 /*
 956  *  EEPROM format
 957  */
 958 struct eeprom_data {
 959         u8 asicId[4];
 960         u16 version_and_numPorts; /* together to avoid endianness crap */
 961         u16 boardId;
 962
 963 #define EEPROM_BOARDID_STR_SIZE   16
 964 #define EEPROM_SERIAL_NUM_SIZE    16
 965
 966         u8 boardIdStr[16];
 967         u8 serialNumber[16];
 968         u16 extHwConfig;
 969         struct eeprom_port_cfg macCfg_port0;
 970         struct eeprom_port_cfg macCfg_port1;
 971         u16 bufletSize;
 972         u16 bufletCount;
 973         u16 tcpWindowThreshold50;
 974         u16 tcpWindowThreshold25;
 975         u16 tcpWindowThreshold0;
 976         u16 ipHashTableBaseHi;
 977         u16 ipHashTableBaseLo;
 978         u16 ipHashTableSize;
 979         u16 tcpHashTableBaseHi;
 980         u16 tcpHashTableBaseLo;
 981         u16 tcpHashTableSize;
 982         u16 ncbTableBaseHi;
 983         u16 ncbTableBaseLo;
 984         u16 ncbTableSize;
 985         u16 drbTableBaseHi;
 986         u16 drbTableBaseLo;
 987         u16 drbTableSize;
 988         u16 reserved_142[4];
 989         u16 ipReassemblyTimeout;
 990         u16 tcpMaxWindowSize;
 991         u16 ipSecurity;
 992 #define IPSEC_CONFIG_PRESENT 0x0001
 993         u8 reserved_156[294];
 994         u16 qDebug[8];
 995         struct eeprom_function_cfg funcCfg_fn0;
 996         u16 reserved_510;
 997         u8 oemSpace[432];
 998         struct eeprom_bios_cfg biosCfg_fn1;
 999         struct eeprom_function_cfg funcCfg_fn1;
1000         u16 reserved_1022;
1001         u8 reserved_1024[464];
1002         struct eeprom_function_cfg funcCfg_fn2;
1003         u16 reserved_1534;
1004         u8 reserved_1536[432];
1005         struct eeprom_bios_cfg biosCfg_fn3;
1006         struct eeprom_function_cfg funcCfg_fn3;
1007         u16 checksum;
1008 };
1009
1010 /*
1011  * General definitions...
1012  */
1013
1014 /*
1015  * Below are a number compiler switches for controlling driver behavior.
1016  * Some are not supported under certain conditions and are notated as such.
1017  */
1018
1019 #define QL3XXX_VENDOR_ID    0x1077
1020 #define QL3022_DEVICE_ID    0x3022
1021 #define QL3032_DEVICE_ID    0x3032
1022
1023 /* MTU & Frame Size stuff */
1024 #define NORMAL_MTU_SIZE                 ETH_DATA_LEN
1025 #define JUMBO_MTU_SIZE                  9000
1026 #define VLAN_ID_LEN                         2
1027
1028 /* Request Queue Related Definitions */
1029 #define NUM_REQ_Q_ENTRIES   256 /* so that 64 * 64  = 4096 (1 page) */
1030
1031 /* Response Queue Related Definitions */
1032 #define NUM_RSP_Q_ENTRIES   256 /* so that 256 * 16  = 4096 (1 page) */
1033
1034 /* Transmit and Receive Buffers */
1035 #define NUM_LBUFQ_ENTRIES       128
1036 #define JUMBO_NUM_LBUFQ_ENTRIES 32
1037 #define NUM_SBUFQ_ENTRIES       64
1038 #define QL_SMALL_BUFFER_SIZE    32
1039 #define QL_ADDR_ELE_PER_BUFQ_ENTRY \
1040 (sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
1041     /* Each send has at least control block.  This is how many we keep. */
1042 #define NUM_SMALL_BUFFERS       NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
1043
1044 #define QL_HEADER_SPACE 32      /* make header space at top of skb. */
1045 /*
1046  * Large & Small Buffers for Receives
1047  */
1048 struct lrg_buf_q_entry {
1049
1050         __le32 addr0_lower;
1051 #define IAL_LAST_ENTRY 0x00000001
1052 #define IAL_CONT_ENTRY 0x00000002
1053 #define IAL_FLAG_MASK  0x00000003
1054         __le32 addr0_upper;
1055         __le32 addr1_lower;
1056         __le32 addr1_upper;
1057         __le32 addr2_lower;
1058         __le32 addr2_upper;
1059         __le32 addr3_lower;
1060         __le32 addr3_upper;
1061         __le32 addr4_lower;
1062         __le32 addr4_upper;
1063         __le32 addr5_lower;
1064         __le32 addr5_upper;
1065         __le32 addr6_lower;
1066         __le32 addr6_upper;
1067         __le32 addr7_lower;
1068         __le32 addr7_upper;
1069
1070 };
1071
1072 struct bufq_addr_element {
1073         __le32 addr_low;
1074         __le32 addr_high;
1075 };
1076
1077 #define QL_NO_RESET                     0
1078 #define QL_DO_RESET                     1
1079
1080 enum link_state_t {
1081         LS_UNKNOWN = 0,
1082         LS_DOWN,
1083         LS_DEGRADE,
1084         LS_RECOVER,
1085         LS_UP,
1086 };
1087
1088 struct ql_rcv_buf_cb {
1089         struct ql_rcv_buf_cb *next;
1090         struct sk_buff *skb;
1091          DECLARE_PCI_UNMAP_ADDR(mapaddr);
1092          DECLARE_PCI_UNMAP_LEN(maplen);
1093         __le32 buf_phy_addr_low;
1094         __le32 buf_phy_addr_high;
1095         int index;
1096 };
1097
1098 /*
1099  * Original IOCB has 3 sg entries:
1100  * first points to skb-data area
1101  * second points to first frag
1102  * third points to next oal.
1103  * OAL has 5 entries:
1104  * 1 thru 4 point to frags
1105  * fifth points to next oal.
1106  */
1107 #define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1)
1108
1109 struct oal_entry {
1110         __le32 dma_lo;
1111         __le32 dma_hi;
1112         __le32 len;
1113 #define OAL_LAST_ENTRY   0x80000000     /* Last valid buffer in list. */
1114 #define OAL_CONT_ENTRY   0x40000000     /* points to an OAL. (continuation) */
1115 };
1116
1117 struct oal {
1118         struct oal_entry oal_entry[5];
1119 };
1120
1121 struct map_list {
1122          DECLARE_PCI_UNMAP_ADDR(mapaddr);
1123          DECLARE_PCI_UNMAP_LEN(maplen);
1124 };
1125
1126 struct ql_tx_buf_cb {
1127         struct sk_buff *skb;
1128         struct ob_mac_iocb_req *queue_entry ;
1129         int seg_count;
1130         struct oal *oal;
1131         struct map_list map[MAX_SKB_FRAGS+1];
1132 };
1133
1134 /* definitions for type field */
1135 #define QL_BUF_TYPE_MACIOCB 0x01
1136 #define QL_BUF_TYPE_IPIOCB  0x02
1137 #define QL_BUF_TYPE_TCPIOCB 0x03
1138
1139 /* qdev->flags definitions. */
1140 enum { QL_RESET_DONE = 1,       /* Reset finished. */
1141         QL_RESET_ACTIVE = 2,    /* Waiting for reset to finish. */
1142         QL_RESET_START = 3,     /* Please reset the chip. */
1143         QL_RESET_PER_SCSI = 4,  /* SCSI driver requests reset. */
1144         QL_TX_TIMEOUT = 5,      /* Timeout in progress. */
1145         QL_LINK_MASTER = 6,     /* This driver controls the link. */
1146         QL_ADAPTER_UP = 7,      /* Adapter has been brought up. */
1147         QL_THREAD_UP = 8,       /* This flag is available. */
1148         QL_LINK_UP = 9, /* Link Status. */
1149         QL_ALLOC_REQ_RSP_Q_DONE = 10,
1150         QL_ALLOC_BUFQS_DONE = 11,
1151         QL_ALLOC_SMALL_BUF_DONE = 12,
1152         QL_LINK_OPTICAL = 13,
1153         QL_MSI_ENABLED = 14,
1154 };
1155
1156 /*
1157  * ql3_adapter - The main Adapter structure definition.
1158  * This structure has all fields relevant to the hardware.
1159  */
1160
1161 struct ql3_adapter {
1162         u32 reserved_00;
1163         unsigned long flags;
1164
1165         /* PCI Configuration information for this device */
1166         struct pci_dev *pdev;
1167         struct net_device *ndev;        /* Parent NET device */
1168
1169         struct napi_struct napi;
1170
1171         /* Hardware information */
1172         u8 chip_rev_id;
1173         u8 pci_slot;
1174         u8 pci_width;
1175         u8 pci_x;
1176         u32 msi;
1177         int index;
1178         struct timer_list adapter_timer;        /* timer used for various functions */
1179
1180         spinlock_t adapter_lock;
1181         spinlock_t hw_lock;
1182
1183         /* PCI Bus Relative Register Addresses */
1184         u8 __iomem *mmap_virt_base;     /* stores return value from ioremap() */
1185         struct ql3xxx_port_registers __iomem *mem_map_registers;
1186         u32 current_page;       /* tracks current register page */
1187
1188         u32 msg_enable;
1189         u8 reserved_01[2];
1190         u8 reserved_02[2];
1191
1192         /* Page for Shadow Registers */
1193         void *shadow_reg_virt_addr;
1194         dma_addr_t shadow_reg_phy_addr;
1195
1196         /* Net Request Queue */
1197         u32 req_q_size;
1198         u32 reserved_03;
1199         struct ob_mac_iocb_req *req_q_virt_addr;
1200         dma_addr_t req_q_phy_addr;
1201         u16 req_producer_index;
1202         u16 reserved_04;
1203         u16 *preq_consumer_index;
1204         u32 req_consumer_index_phy_addr_high;
1205         u32 req_consumer_index_phy_addr_low;
1206         atomic_t tx_count;
1207         struct ql_tx_buf_cb tx_buf[NUM_REQ_Q_ENTRIES];
1208
1209         /* Net Response Queue */
1210         u32 rsp_q_size;
1211         u32 eeprom_cmd_data;
1212         struct net_rsp_iocb *rsp_q_virt_addr;
1213         dma_addr_t rsp_q_phy_addr;
1214         struct net_rsp_iocb *rsp_current;
1215         u16 rsp_consumer_index;
1216         u16 reserved_06;
1217         volatile __le32 *prsp_producer_index;
1218         u32 rsp_producer_index_phy_addr_high;
1219         u32 rsp_producer_index_phy_addr_low;
1220
1221         /* Large Buffer Queue */
1222         u32 lrg_buf_q_alloc_size;
1223         u32 lrg_buf_q_size;
1224         void *lrg_buf_q_alloc_virt_addr;
1225         void *lrg_buf_q_virt_addr;
1226         dma_addr_t lrg_buf_q_alloc_phy_addr;
1227         dma_addr_t lrg_buf_q_phy_addr;
1228         u32 lrg_buf_q_producer_index;
1229         u32 lrg_buf_release_cnt;
1230         struct bufq_addr_element *lrg_buf_next_free;
1231         u32 num_large_buffers;
1232         u32 num_lbufq_entries;
1233
1234         /* Large (Receive) Buffers */
1235         struct ql_rcv_buf_cb *lrg_buf;
1236         struct ql_rcv_buf_cb *lrg_buf_free_head;
1237         struct ql_rcv_buf_cb *lrg_buf_free_tail;
1238         u32 lrg_buf_free_count;
1239         u32 lrg_buffer_len;
1240         u32 lrg_buf_index;
1241         u32 lrg_buf_skb_check;
1242
1243         /* Small Buffer Queue */
1244         u32 small_buf_q_alloc_size;
1245         u32 small_buf_q_size;
1246         u32 small_buf_q_producer_index;
1247         void *small_buf_q_alloc_virt_addr;
1248         void *small_buf_q_virt_addr;
1249         dma_addr_t small_buf_q_alloc_phy_addr;
1250         dma_addr_t small_buf_q_phy_addr;
1251         u32 small_buf_index;
1252
1253         /* Small (Receive) Buffers */
1254         void *small_buf_virt_addr;
1255         dma_addr_t small_buf_phy_addr;
1256         u32 small_buf_phy_addr_low;
1257         u32 small_buf_phy_addr_high;
1258         u32 small_buf_release_cnt;
1259         u32 small_buf_total_size;
1260
1261         /* ISR related, saves status for DPC. */
1262         u32 control_status;
1263
1264         struct eeprom_data nvram_data;
1265         struct timer_list ioctl_timer;
1266         u32 port_link_state;
1267         u32 last_rsp_offset;
1268
1269         /* 4022 specific */
1270         u32 mac_index;          /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */
1271         u32 PHYAddr;            /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */
1272         u32 mac_ob_opcode;      /* Opcode to use on mac transmission */
1273         u32 tcp_ob_opcode;      /* Opcode to use on tcp transmission */
1274         u32 update_ob_opcode;   /* Opcode to use for updating NCB */
1275         u32 mb_bit_mask;        /* MA Bits mask to use on transmission */
1276         u32 numPorts;
1277         struct workqueue_struct *workqueue;
1278         struct delayed_work reset_work;
1279         struct delayed_work tx_timeout_work;
1280         struct delayed_work link_state_work;
1281         u32 max_frame_size;
1282         u32 device_id;
1283         u16 phyType;
1284 };
1285
1286 #endif                          /* _QLA3XXX_H_ */