1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
35 #define IXGBE_82599_MAX_TX_QUEUES 128
36 #define IXGBE_82599_MAX_RX_QUEUES 128
37 #define IXGBE_82599_RAR_ENTRIES 128
38 #define IXGBE_82599_MC_TBL_SIZE 128
39 #define IXGBE_82599_VFT_TBL_SIZE 128
41 s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
42 ixgbe_link_speed speed
,
44 bool autoneg_wait_to_complete
);
45 s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
46 bool autoneg_wait_to_complete
);
47 s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
48 ixgbe_link_speed speed
,
50 bool autoneg_wait_to_complete
);
51 static s32
ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw
*hw
,
52 ixgbe_link_speed
*speed
,
54 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
55 ixgbe_link_speed speed
,
57 bool autoneg_wait_to_complete
);
58 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
);
60 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw
*hw
)
62 struct ixgbe_mac_info
*mac
= &hw
->mac
;
63 if (hw
->phy
.multispeed_fiber
) {
64 /* Set up dual speed SFP+ support */
65 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_multispeed_fiber
;
67 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_82599
;
71 static s32
ixgbe_setup_sfp_modules_82599(struct ixgbe_hw
*hw
)
74 u16 list_offset
, data_offset
, data_value
;
76 if (hw
->phy
.sfp_type
!= ixgbe_sfp_type_unknown
) {
77 ixgbe_init_mac_link_ops_82599(hw
);
79 hw
->phy
.ops
.reset
= NULL
;
81 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
, &list_offset
,
87 /* PHY config will finish before releasing the semaphore */
88 ret_val
= ixgbe_acquire_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
90 ret_val
= IXGBE_ERR_SWFW_SYNC
;
94 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
95 while (data_value
!= 0xffff) {
96 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, data_value
);
97 IXGBE_WRITE_FLUSH(hw
);
98 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
100 /* Now restart DSP by setting Restart_AN */
101 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
,
102 (IXGBE_READ_REG(hw
, IXGBE_AUTOC
) | IXGBE_AUTOC_AN_RESTART
));
104 /* Release the semaphore */
105 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
106 /* Delay obtaining semaphore again to allow FW access */
107 msleep(hw
->eeprom
.semaphore_delay
);
115 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
116 * @hw: pointer to hardware structure
118 * Read PCIe configuration space, and get the MSI-X vector count from
119 * the capabilities table.
121 static u32
ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw
*hw
)
123 struct ixgbe_adapter
*adapter
= hw
->back
;
125 pci_read_config_word(adapter
->pdev
, IXGBE_PCIE_MSIX_82599_CAPS
,
127 msix_count
&= IXGBE_PCIE_MSIX_TBL_SZ_MASK
;
129 /* MSI-X count is zero-based in HW, so increment to give proper value */
135 static s32
ixgbe_get_invariants_82599(struct ixgbe_hw
*hw
)
137 struct ixgbe_mac_info
*mac
= &hw
->mac
;
139 ixgbe_init_mac_link_ops_82599(hw
);
141 mac
->mcft_size
= IXGBE_82599_MC_TBL_SIZE
;
142 mac
->vft_size
= IXGBE_82599_VFT_TBL_SIZE
;
143 mac
->num_rar_entries
= IXGBE_82599_RAR_ENTRIES
;
144 mac
->max_rx_queues
= IXGBE_82599_MAX_RX_QUEUES
;
145 mac
->max_tx_queues
= IXGBE_82599_MAX_TX_QUEUES
;
146 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_82599(hw
);
152 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
153 * @hw: pointer to hardware structure
155 * Initialize any function pointers that were not able to be
156 * set during get_invariants because the PHY/SFP type was
157 * not known. Perform the SFP init if necessary.
160 static s32
ixgbe_init_phy_ops_82599(struct ixgbe_hw
*hw
)
162 struct ixgbe_mac_info
*mac
= &hw
->mac
;
163 struct ixgbe_phy_info
*phy
= &hw
->phy
;
166 /* Identify the PHY or SFP module */
167 ret_val
= phy
->ops
.identify(hw
);
169 /* Setup function pointers based on detected SFP module and speeds */
170 ixgbe_init_mac_link_ops_82599(hw
);
172 /* If copper media, overwrite with copper function pointers */
173 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_copper
) {
174 mac
->ops
.setup_link
= &ixgbe_setup_copper_link_82599
;
175 mac
->ops
.get_link_capabilities
=
176 &ixgbe_get_copper_link_capabilities_82599
;
179 /* Set necessary function pointers based on phy type */
180 switch (hw
->phy
.type
) {
182 phy
->ops
.check_link
= &ixgbe_check_phy_link_tnx
;
183 phy
->ops
.get_firmware_version
=
184 &ixgbe_get_phy_firmware_version_tnx
;
194 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
195 * @hw: pointer to hardware structure
196 * @speed: pointer to link speed
197 * @negotiation: true when autoneg or autotry is enabled
199 * Determines the link capabilities by reading the AUTOC register.
201 static s32
ixgbe_get_link_capabilities_82599(struct ixgbe_hw
*hw
,
202 ixgbe_link_speed
*speed
,
209 * Determine link capabilities based on the stored value of AUTOC,
210 * which represents EEPROM defaults. If AUTOC value has not been
211 * stored, use the current register value.
213 if (hw
->mac
.orig_link_settings_stored
)
214 autoc
= hw
->mac
.orig_autoc
;
216 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
218 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
219 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
220 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
221 *negotiation
= false;
224 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
225 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
226 *negotiation
= false;
229 case IXGBE_AUTOC_LMS_1G_AN
:
230 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
234 case IXGBE_AUTOC_LMS_10G_SERIAL
:
235 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
236 *negotiation
= false;
239 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
240 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
241 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
242 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
243 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
244 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
245 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
246 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
247 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
251 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
:
252 *speed
= IXGBE_LINK_SPEED_100_FULL
;
253 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
254 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
255 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
256 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
257 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
258 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
262 case IXGBE_AUTOC_LMS_SGMII_1G_100M
:
263 *speed
= IXGBE_LINK_SPEED_1GB_FULL
| IXGBE_LINK_SPEED_100_FULL
;
264 *negotiation
= false;
268 status
= IXGBE_ERR_LINK_SETUP
;
273 if (hw
->phy
.multispeed_fiber
) {
274 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
|
275 IXGBE_LINK_SPEED_1GB_FULL
;
284 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
285 * @hw: pointer to hardware structure
286 * @speed: pointer to link speed
287 * @autoneg: boolean auto-negotiation value
289 * Determines the link capabilities by reading the AUTOC register.
291 static s32
ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw
*hw
,
292 ixgbe_link_speed
*speed
,
295 s32 status
= IXGBE_ERR_LINK_SETUP
;
301 status
= hw
->phy
.ops
.read_reg(hw
, MDIO_SPEED
, MDIO_MMD_PMAPMD
,
305 if (speed_ability
& MDIO_SPEED_10G
)
306 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
307 if (speed_ability
& MDIO_PMA_SPEED_1000
)
308 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
315 * ixgbe_get_media_type_82599 - Get media type
316 * @hw: pointer to hardware structure
318 * Returns the media type (fiber, copper, backplane)
320 static enum ixgbe_media_type
ixgbe_get_media_type_82599(struct ixgbe_hw
*hw
)
322 enum ixgbe_media_type media_type
;
324 /* Detect if there is a copper PHY attached. */
325 if (hw
->phy
.type
== ixgbe_phy_cu_unknown
||
326 hw
->phy
.type
== ixgbe_phy_tn
) {
327 media_type
= ixgbe_media_type_copper
;
331 switch (hw
->device_id
) {
332 case IXGBE_DEV_ID_82599_KX4
:
333 case IXGBE_DEV_ID_82599_XAUI_LOM
:
334 /* Default device ID is mezzanine card KX/KX4 */
335 media_type
= ixgbe_media_type_backplane
;
337 case IXGBE_DEV_ID_82599_SFP
:
338 media_type
= ixgbe_media_type_fiber
;
340 case IXGBE_DEV_ID_82599_CX4
:
341 media_type
= ixgbe_media_type_cx4
;
344 media_type
= ixgbe_media_type_unknown
;
352 * ixgbe_start_mac_link_82599 - Setup MAC link settings
353 * @hw: pointer to hardware structure
354 * @autoneg_wait_to_complete: true when waiting for completion is needed
356 * Configures link settings based on values in the ixgbe_hw struct.
357 * Restarts the link. Performs autonegotiation if needed.
359 s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
360 bool autoneg_wait_to_complete
)
368 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
369 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
370 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
372 /* Only poll for autoneg to complete if specified to do so */
373 if (autoneg_wait_to_complete
) {
374 if ((autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
375 IXGBE_AUTOC_LMS_KX4_KX_KR
||
376 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
377 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
378 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
379 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
380 links_reg
= 0; /* Just in case Autoneg time = 0 */
381 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
382 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
383 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
387 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
388 status
= IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
389 hw_dbg(hw
, "Autoneg did not complete.\n");
394 /* Add delay to filter out noises during initial link setup */
401 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
402 * @hw: pointer to hardware structure
403 * @speed: new link speed
404 * @autoneg: true if autonegotiation enabled
405 * @autoneg_wait_to_complete: true when waiting for completion is needed
407 * Set the link speed in the AUTOC register and restarts link.
409 s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
410 ixgbe_link_speed speed
,
412 bool autoneg_wait_to_complete
)
415 ixgbe_link_speed phy_link_speed
;
416 ixgbe_link_speed highest_link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
418 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
419 bool link_up
= false;
423 /* Mask off requested but non-supported speeds */
424 hw
->mac
.ops
.get_link_capabilities(hw
, &phy_link_speed
, &negotiation
);
425 speed
&= phy_link_speed
;
428 * When the driver changes the link speeds that it can support,
429 * it sets autotry_restart to true to indicate that we need to
430 * initiate a new autotry session with the link partner. To do
431 * so, we set the speed then disable and re-enable the tx laser, to
432 * alert the link partner that it also needs to restart autotry on its
433 * end. This is consistent with true clause 37 autoneg, which also
434 * involves a loss of signal.
438 * Try each speed one by one, highest priority first. We do this in
439 * software because 10gb fiber doesn't support speed autonegotiation.
441 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
) {
443 highest_link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
445 /* If we already have link at this speed, just jump out */
446 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
448 if ((phy_link_speed
== IXGBE_LINK_SPEED_10GB_FULL
) && link_up
)
451 /* Set the module link speed */
452 esdp_reg
|= (IXGBE_ESDP_SDP5_DIR
| IXGBE_ESDP_SDP5
);
453 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
455 /* Allow module to change analog characteristics (1G->10G) */
458 status
= ixgbe_setup_mac_link_82599(hw
,
459 IXGBE_LINK_SPEED_10GB_FULL
,
461 autoneg_wait_to_complete
);
465 /* Flap the tx laser if it has not already been done */
466 if (hw
->mac
.autotry_restart
) {
467 /* Disable tx laser; allow 100us to go dark per spec */
468 esdp_reg
|= IXGBE_ESDP_SDP3
;
469 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
472 /* Enable tx laser; allow 2ms to light up per spec */
473 esdp_reg
&= ~IXGBE_ESDP_SDP3
;
474 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
477 hw
->mac
.autotry_restart
= false;
480 /* The controller may take up to 500ms at 10g to acquire link */
481 for (i
= 0; i
< 5; i
++) {
482 /* Wait for the link partner to also set speed */
485 /* If we have link, just jump out */
486 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
,
493 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
) {
495 if (highest_link_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
496 highest_link_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
498 /* If we already have link at this speed, just jump out */
499 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
501 if ((phy_link_speed
== IXGBE_LINK_SPEED_1GB_FULL
) && link_up
)
504 /* Set the module link speed */
505 esdp_reg
&= ~IXGBE_ESDP_SDP5
;
506 esdp_reg
|= IXGBE_ESDP_SDP5_DIR
;
507 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
509 /* Allow module to change analog characteristics (10G->1G) */
512 status
= ixgbe_setup_mac_link_82599(hw
,
513 IXGBE_LINK_SPEED_1GB_FULL
,
515 autoneg_wait_to_complete
);
519 /* Flap the tx laser if it has not already been done */
520 if (hw
->mac
.autotry_restart
) {
521 /* Disable tx laser; allow 100us to go dark per spec */
522 esdp_reg
|= IXGBE_ESDP_SDP3
;
523 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
526 /* Enable tx laser; allow 2ms to light up per spec */
527 esdp_reg
&= ~IXGBE_ESDP_SDP3
;
528 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
531 hw
->mac
.autotry_restart
= false;
534 /* Wait for the link partner to also set speed */
537 /* If we have link, just jump out */
538 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
544 * We didn't get link. Configure back to the highest speed we tried,
545 * (if there was more than one). We call ourselves back with just the
546 * single highest speed that the user requested.
549 status
= ixgbe_setup_mac_link_multispeed_fiber(hw
,
552 autoneg_wait_to_complete
);
555 /* Set autoneg_advertised value based on input link speed */
556 hw
->phy
.autoneg_advertised
= 0;
558 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
559 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
561 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
562 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
568 * ixgbe_check_mac_link_82599 - Determine link and speed status
569 * @hw: pointer to hardware structure
570 * @speed: pointer to link speed
571 * @link_up: true when link is up
572 * @link_up_wait_to_complete: bool used to wait for link up or not
574 * Reads the links register to determine if link is up and the current speed
576 static s32
ixgbe_check_mac_link_82599(struct ixgbe_hw
*hw
,
577 ixgbe_link_speed
*speed
,
579 bool link_up_wait_to_complete
)
584 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
585 if (link_up_wait_to_complete
) {
586 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
587 if (links_reg
& IXGBE_LINKS_UP
) {
594 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
597 if (links_reg
& IXGBE_LINKS_UP
)
603 if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
604 IXGBE_LINKS_SPEED_10G_82599
)
605 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
606 else if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
607 IXGBE_LINKS_SPEED_1G_82599
)
608 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
610 *speed
= IXGBE_LINK_SPEED_100_FULL
;
612 /* if link is down, zero out the current_mode */
613 if (*link_up
== false) {
614 hw
->fc
.current_mode
= ixgbe_fc_none
;
615 hw
->fc
.fc_was_autonegged
= false;
622 * ixgbe_setup_mac_link_82599 - Set MAC link speed
623 * @hw: pointer to hardware structure
624 * @speed: new link speed
625 * @autoneg: true if autonegotiation enabled
626 * @autoneg_wait_to_complete: true when waiting for completion is needed
628 * Set the link speed in the AUTOC register and restarts link.
630 s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
631 ixgbe_link_speed speed
, bool autoneg
,
632 bool autoneg_wait_to_complete
)
635 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
636 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
637 u32 start_autoc
= autoc
;
639 u32 link_mode
= autoc
& IXGBE_AUTOC_LMS_MASK
;
640 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
641 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
644 ixgbe_link_speed link_capabilities
= IXGBE_LINK_SPEED_UNKNOWN
;
646 /* Check to see if speed passed in is supported. */
647 hw
->mac
.ops
.get_link_capabilities(hw
, &link_capabilities
, &autoneg
);
648 speed
&= link_capabilities
;
650 if (speed
== IXGBE_LINK_SPEED_UNKNOWN
) {
651 status
= IXGBE_ERR_LINK_SETUP
;
655 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
656 if (hw
->mac
.orig_link_settings_stored
)
657 orig_autoc
= hw
->mac
.orig_autoc
;
662 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
663 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
664 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
665 /* Set KX4/KX/KR support according to speed requested */
666 autoc
&= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK
| IXGBE_AUTOC_KR_SUPP
);
667 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
668 if (orig_autoc
& IXGBE_AUTOC_KX4_SUPP
)
669 autoc
|= IXGBE_AUTOC_KX4_SUPP
;
670 if (orig_autoc
& IXGBE_AUTOC_KR_SUPP
)
671 autoc
|= IXGBE_AUTOC_KR_SUPP
;
672 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
673 autoc
|= IXGBE_AUTOC_KX_SUPP
;
674 } else if ((pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
) &&
675 (link_mode
== IXGBE_AUTOC_LMS_1G_LINK_NO_AN
||
676 link_mode
== IXGBE_AUTOC_LMS_1G_AN
)) {
677 /* Switch from 1G SFI to 10G SFI if requested */
678 if ((speed
== IXGBE_LINK_SPEED_10GB_FULL
) &&
679 (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)) {
680 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
681 autoc
|= IXGBE_AUTOC_LMS_10G_SERIAL
;
683 } else if ((pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
) &&
684 (link_mode
== IXGBE_AUTOC_LMS_10G_SERIAL
)) {
685 /* Switch from 10G SFI to 1G SFI if requested */
686 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
687 (pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
)) {
688 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
690 autoc
|= IXGBE_AUTOC_LMS_1G_AN
;
692 autoc
|= IXGBE_AUTOC_LMS_1G_LINK_NO_AN
;
696 if (autoc
!= start_autoc
) {
698 autoc
|= IXGBE_AUTOC_AN_RESTART
;
699 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc
);
701 /* Only poll for autoneg to complete if specified to do so */
702 if (autoneg_wait_to_complete
) {
703 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
704 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
705 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
706 links_reg
= 0; /*Just in case Autoneg time=0*/
707 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
709 IXGBE_READ_REG(hw
, IXGBE_LINKS
);
710 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
714 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
716 IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
717 hw_dbg(hw
, "Autoneg did not "
723 /* Add delay to filter out noises during initial link setup */
732 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
733 * @hw: pointer to hardware structure
734 * @speed: new link speed
735 * @autoneg: true if autonegotiation enabled
736 * @autoneg_wait_to_complete: true if waiting is needed to complete
738 * Restarts link on PHY and MAC based on settings passed in.
740 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
741 ixgbe_link_speed speed
,
743 bool autoneg_wait_to_complete
)
747 /* Setup the PHY according to input speed */
748 status
= hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
749 autoneg_wait_to_complete
);
751 ixgbe_start_mac_link_82599(hw
, autoneg_wait_to_complete
);
757 * ixgbe_reset_hw_82599 - Perform hardware reset
758 * @hw: pointer to hardware structure
760 * Resets the hardware by resetting the transmit and receive units, masks
761 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
764 static s32
ixgbe_reset_hw_82599(struct ixgbe_hw
*hw
)
772 /* Call adapter stop to disable tx/rx and clear interrupts */
773 hw
->mac
.ops
.stop_adapter(hw
);
775 /* PHY ops must be identified and initialized prior to reset */
777 /* Init PHY and function pointers, perform SFP setup */
778 status
= hw
->phy
.ops
.init(hw
);
780 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
783 /* Setup SFP module if there is one present. */
784 if (hw
->phy
.sfp_setup_needed
) {
785 status
= hw
->mac
.ops
.setup_sfp(hw
);
786 hw
->phy
.sfp_setup_needed
= false;
790 if (hw
->phy
.reset_disable
== false && hw
->phy
.ops
.reset
!= NULL
)
791 hw
->phy
.ops
.reset(hw
);
794 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
795 * access and verify no pending requests before reset
797 status
= ixgbe_disable_pcie_master(hw
);
799 status
= IXGBE_ERR_MASTER_REQUESTS_PENDING
;
800 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
804 * Issue global reset to the MAC. This needs to be a SW reset.
805 * If link reset is used, it might reset the MAC when mng is using it
807 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
808 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, (ctrl
| IXGBE_CTRL_RST
));
809 IXGBE_WRITE_FLUSH(hw
);
811 /* Poll for reset bit to self-clear indicating reset is complete */
812 for (i
= 0; i
< 10; i
++) {
814 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
815 if (!(ctrl
& IXGBE_CTRL_RST
))
818 if (ctrl
& IXGBE_CTRL_RST
) {
819 status
= IXGBE_ERR_RESET_FAILED
;
820 hw_dbg(hw
, "Reset polling failed to complete.\n");
822 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
823 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
824 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
825 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
832 * Store the original AUTOC/AUTOC2 values if they have not been
833 * stored off yet. Otherwise restore the stored original
834 * values since the reset operation sets back to defaults.
836 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
837 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
838 if (hw
->mac
.orig_link_settings_stored
== false) {
839 hw
->mac
.orig_autoc
= autoc
;
840 hw
->mac
.orig_autoc2
= autoc2
;
841 hw
->mac
.orig_link_settings_stored
= true;
843 if (autoc
!= hw
->mac
.orig_autoc
)
844 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (hw
->mac
.orig_autoc
|
845 IXGBE_AUTOC_AN_RESTART
));
847 if ((autoc2
& IXGBE_AUTOC2_UPPER_MASK
) !=
848 (hw
->mac
.orig_autoc2
& IXGBE_AUTOC2_UPPER_MASK
)) {
849 autoc2
&= ~IXGBE_AUTOC2_UPPER_MASK
;
850 autoc2
|= (hw
->mac
.orig_autoc2
&
851 IXGBE_AUTOC2_UPPER_MASK
);
852 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC2
, autoc2
);
857 * Store MAC address from RAR0, clear receive address registers, and
858 * clear the multicast table. Also reset num_rar_entries to 128,
859 * since we modify this value when programming the SAN MAC address.
861 hw
->mac
.num_rar_entries
= 128;
862 hw
->mac
.ops
.init_rx_addrs(hw
);
864 /* Store the permanent mac address */
865 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
867 /* Store the permanent SAN mac address */
868 hw
->mac
.ops
.get_san_mac_addr(hw
, hw
->mac
.san_addr
);
870 /* Add the SAN MAC address to the RAR only if it's a valid address */
871 if (ixgbe_validate_mac_addr(hw
->mac
.san_addr
) == 0) {
872 hw
->mac
.ops
.set_rar(hw
, hw
->mac
.num_rar_entries
- 1,
873 hw
->mac
.san_addr
, 0, IXGBE_RAH_AV
);
875 /* Reserve the last RAR for the SAN MAC address */
876 hw
->mac
.num_rar_entries
--;
884 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
885 * @hw: pointer to hardware struct
886 * @rar: receive address register index to disassociate
887 * @vmdq: VMDq pool index to remove from the rar
889 static s32
ixgbe_clear_vmdq_82599(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
891 u32 mpsar_lo
, mpsar_hi
;
892 u32 rar_entries
= hw
->mac
.num_rar_entries
;
894 if (rar
< rar_entries
) {
895 mpsar_lo
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
896 mpsar_hi
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
898 if (!mpsar_lo
&& !mpsar_hi
)
901 if (vmdq
== IXGBE_CLEAR_VMDQ_ALL
) {
903 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 0);
907 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 0);
910 } else if (vmdq
< 32) {
911 mpsar_lo
&= ~(1 << vmdq
);
912 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar_lo
);
914 mpsar_hi
&= ~(1 << (vmdq
- 32));
915 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar_hi
);
918 /* was that the last pool using this rar? */
919 if (mpsar_lo
== 0 && mpsar_hi
== 0 && rar
!= 0)
920 hw
->mac
.ops
.clear_rar(hw
, rar
);
922 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
930 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
931 * @hw: pointer to hardware struct
932 * @rar: receive address register index to associate with a VMDq index
933 * @vmdq: VMDq pool index
935 static s32
ixgbe_set_vmdq_82599(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
938 u32 rar_entries
= hw
->mac
.num_rar_entries
;
940 if (rar
< rar_entries
) {
942 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
944 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar
);
946 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
947 mpsar
|= 1 << (vmdq
- 32);
948 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar
);
951 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
957 * ixgbe_set_vfta_82599 - Set VLAN filter table
958 * @hw: pointer to hardware structure
959 * @vlan: VLAN id to write to VLAN filter
960 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
961 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
963 * Turn on/off specified VLAN in the VLAN filter table.
965 static s32
ixgbe_set_vfta_82599(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
971 u32 first_empty_slot
;
974 return IXGBE_ERR_PARAM
;
977 * this is a 2 part operation - first the VFTA, then the
978 * VLVF and VLVFB if vind is set
982 * The VFTA is a bitstring made up of 128 32-bit registers
983 * that enable the particular VLAN id, much like the MTA:
984 * bits[11-5]: which register
985 * bits[4-0]: which bit in the register
987 regindex
= (vlan
>> 5) & 0x7F;
988 bitindex
= vlan
& 0x1F;
989 bits
= IXGBE_READ_REG(hw
, IXGBE_VFTA(regindex
));
991 bits
|= (1 << bitindex
);
993 bits
&= ~(1 << bitindex
);
994 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regindex
), bits
);
1000 * make sure the vlan is in VLVF
1001 * set the vind bit in the matching VLVFB
1003 * clear the pool bit and possibly the vind
1006 /* find the vlanid or the first empty slot */
1007 first_empty_slot
= 0;
1009 for (regindex
= 1; regindex
< IXGBE_VLVF_ENTRIES
; regindex
++) {
1010 bits
= IXGBE_READ_REG(hw
, IXGBE_VLVF(regindex
));
1011 if (!bits
&& !first_empty_slot
)
1012 first_empty_slot
= regindex
;
1013 else if ((bits
& 0x0FFF) == vlan
)
1017 if (regindex
>= IXGBE_VLVF_ENTRIES
) {
1018 if (first_empty_slot
)
1019 regindex
= first_empty_slot
;
1021 hw_dbg(hw
, "No space in VLVF.\n");
1027 /* set the pool bit */
1029 bits
= IXGBE_READ_REG(hw
,
1030 IXGBE_VLVFB(regindex
* 2));
1031 bits
|= (1 << vind
);
1033 IXGBE_VLVFB(regindex
* 2), bits
);
1035 bits
= IXGBE_READ_REG(hw
,
1036 IXGBE_VLVFB((regindex
* 2) + 1));
1037 bits
|= (1 << vind
);
1039 IXGBE_VLVFB((regindex
* 2) + 1), bits
);
1042 /* clear the pool bit */
1044 bits
= IXGBE_READ_REG(hw
,
1045 IXGBE_VLVFB(regindex
* 2));
1046 bits
&= ~(1 << vind
);
1048 IXGBE_VLVFB(regindex
* 2), bits
);
1049 bits
|= IXGBE_READ_REG(hw
,
1050 IXGBE_VLVFB((regindex
* 2) + 1));
1052 bits
= IXGBE_READ_REG(hw
,
1053 IXGBE_VLVFB((regindex
* 2) + 1));
1054 bits
&= ~(1 << vind
);
1056 IXGBE_VLVFB((regindex
* 2) + 1), bits
);
1057 bits
|= IXGBE_READ_REG(hw
,
1058 IXGBE_VLVFB(regindex
* 2));
1063 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(regindex
),
1064 (IXGBE_VLVF_VIEN
| vlan
));
1066 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(regindex
), 0);
1074 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1075 * @hw: pointer to hardware structure
1077 * Clears the VLAN filer table, and the VMDq index associated with the filter
1079 static s32
ixgbe_clear_vfta_82599(struct ixgbe_hw
*hw
)
1083 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
1084 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(offset
), 0);
1086 for (offset
= 0; offset
< IXGBE_VLVF_ENTRIES
; offset
++) {
1087 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(offset
), 0);
1088 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(offset
* 2), 0);
1089 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB((offset
* 2) + 1), 0);
1096 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1097 * @hw: pointer to hardware structure
1099 static s32
ixgbe_init_uta_tables_82599(struct ixgbe_hw
*hw
)
1102 hw_dbg(hw
, " Clearing UTA\n");
1104 for (i
= 0; i
< 128; i
++)
1105 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), 0);
1111 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1112 * @hw: pointer to hardware structure
1114 s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
)
1117 u32 fdirctrl
= IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
);
1118 fdirctrl
&= ~IXGBE_FDIRCTRL_INIT_DONE
;
1121 * Before starting reinitialization process,
1122 * FDIRCMD.CMD must be zero.
1124 for (i
= 0; i
< IXGBE_FDIRCMD_CMD_POLL
; i
++) {
1125 if (!(IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1126 IXGBE_FDIRCMD_CMD_MASK
))
1130 if (i
>= IXGBE_FDIRCMD_CMD_POLL
) {
1131 hw_dbg(hw
,"Flow Director previous command isn't complete, "
1132 "aborting table re-initialization. \n");
1133 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1136 IXGBE_WRITE_REG(hw
, IXGBE_FDIRFREE
, 0);
1137 IXGBE_WRITE_FLUSH(hw
);
1139 * 82599 adapters flow director init flow cannot be restarted,
1140 * Workaround 82599 silicon errata by performing the following steps
1141 * before re-writing the FDIRCTRL control register with the same value.
1142 * - write 1 to bit 8 of FDIRCMD register &
1143 * - write 0 to bit 8 of FDIRCMD register
1145 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1146 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) |
1147 IXGBE_FDIRCMD_CLEARHT
));
1148 IXGBE_WRITE_FLUSH(hw
);
1149 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1150 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1151 ~IXGBE_FDIRCMD_CLEARHT
));
1152 IXGBE_WRITE_FLUSH(hw
);
1154 * Clear FDIR Hash register to clear any leftover hashes
1155 * waiting to be programmed.
1157 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, 0x00);
1158 IXGBE_WRITE_FLUSH(hw
);
1160 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1161 IXGBE_WRITE_FLUSH(hw
);
1163 /* Poll init-done after we write FDIRCTRL register */
1164 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1165 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1166 IXGBE_FDIRCTRL_INIT_DONE
)
1170 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
) {
1171 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1172 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1175 /* Clear FDIR statistics registers (read to clear) */
1176 IXGBE_READ_REG(hw
, IXGBE_FDIRUSTAT
);
1177 IXGBE_READ_REG(hw
, IXGBE_FDIRFSTAT
);
1178 IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
1179 IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
1180 IXGBE_READ_REG(hw
, IXGBE_FDIRLEN
);
1186 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1187 * @hw: pointer to hardware structure
1188 * @pballoc: which mode to allocate filters with
1190 s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1197 * Before enabling Flow Director, the Rx Packet Buffer size
1198 * must be reduced. The new value is the current size minus
1199 * flow director memory usage size.
1201 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1202 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1203 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1206 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1207 * intialized to zero for non DCB mode otherwise actual total RX PB
1208 * would be bigger than programmed and filter space would run into
1211 for (i
= 1; i
< 8; i
++)
1212 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1214 /* Send interrupt when 64 filters are left */
1215 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1217 /* Set the maximum length per hash bucket to 0xA filters */
1218 fdirctrl
|= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
;
1221 case IXGBE_FDIR_PBALLOC_64K
:
1222 /* 8k - 1 signature filters */
1223 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1225 case IXGBE_FDIR_PBALLOC_128K
:
1226 /* 16k - 1 signature filters */
1227 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1229 case IXGBE_FDIR_PBALLOC_256K
:
1230 /* 32k - 1 signature filters */
1231 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1235 return IXGBE_ERR_CONFIG
;
1238 /* Move the flexible bytes to use the ethertype - shift 6 words */
1239 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1241 fdirctrl
|= IXGBE_FDIRCTRL_REPORT_STATUS
;
1243 /* Prime the keys for hashing */
1244 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
,
1245 htonl(IXGBE_ATR_BUCKET_HASH_KEY
));
1246 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
,
1247 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY
));
1250 * Poll init-done after we write the register. Estimated times:
1251 * 10G: PBALLOC = 11b, timing is 60us
1252 * 1G: PBALLOC = 11b, timing is 600us
1253 * 100M: PBALLOC = 11b, timing is 6ms
1255 * Multiple these timings by 4 if under full Rx load
1257 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1258 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1259 * this might not finish in our poll time, but we can live with that
1262 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1263 IXGBE_WRITE_FLUSH(hw
);
1264 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1265 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1266 IXGBE_FDIRCTRL_INIT_DONE
)
1270 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1271 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1277 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1278 * @hw: pointer to hardware structure
1279 * @pballoc: which mode to allocate filters with
1281 s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1288 * Before enabling Flow Director, the Rx Packet Buffer size
1289 * must be reduced. The new value is the current size minus
1290 * flow director memory usage size.
1292 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1293 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1294 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1297 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1298 * intialized to zero for non DCB mode otherwise actual total RX PB
1299 * would be bigger than programmed and filter space would run into
1302 for (i
= 1; i
< 8; i
++)
1303 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1305 /* Send interrupt when 64 filters are left */
1306 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1309 case IXGBE_FDIR_PBALLOC_64K
:
1310 /* 2k - 1 perfect filters */
1311 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1313 case IXGBE_FDIR_PBALLOC_128K
:
1314 /* 4k - 1 perfect filters */
1315 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1317 case IXGBE_FDIR_PBALLOC_256K
:
1318 /* 8k - 1 perfect filters */
1319 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1323 return IXGBE_ERR_CONFIG
;
1326 /* Turn perfect match filtering on */
1327 fdirctrl
|= IXGBE_FDIRCTRL_PERFECT_MATCH
;
1328 fdirctrl
|= IXGBE_FDIRCTRL_REPORT_STATUS
;
1330 /* Move the flexible bytes to use the ethertype - shift 6 words */
1331 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1333 /* Prime the keys for hashing */
1334 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
,
1335 htonl(IXGBE_ATR_BUCKET_HASH_KEY
));
1336 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
,
1337 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY
));
1340 * Poll init-done after we write the register. Estimated times:
1341 * 10G: PBALLOC = 11b, timing is 60us
1342 * 1G: PBALLOC = 11b, timing is 600us
1343 * 100M: PBALLOC = 11b, timing is 6ms
1345 * Multiple these timings by 4 if under full Rx load
1347 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1348 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1349 * this might not finish in our poll time, but we can live with that
1353 /* Set the maximum length per hash bucket to 0xA filters */
1354 fdirctrl
|= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
);
1356 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1357 IXGBE_WRITE_FLUSH(hw
);
1358 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1359 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1360 IXGBE_FDIRCTRL_INIT_DONE
)
1364 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1365 hw_dbg(hw
, "Flow Director Perfect poll time exceeded!\n");
1372 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1373 * @stream: input bitstream to compute the hash on
1374 * @key: 32-bit hash key
1376 static u16
ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input
*atr_input
,
1380 * The algorithm is as follows:
1381 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1382 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1383 * and A[n] x B[n] is bitwise AND between same length strings
1385 * K[n] is 16 bits, defined as:
1386 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1387 * for n modulo 32 < 15, K[n] =
1388 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1390 * S[n] is 16 bits, defined as:
1391 * for n >= 15, S[n] = S[n:n - 15]
1392 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1394 * To simplify for programming, the algorithm is implemented
1395 * in software this way:
1397 * Key[31:0], Stream[335:0]
1399 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1400 * int_key[350:0] = tmp_key[351:1]
1401 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1404 * for (i = 0; i < 351; i++) {
1406 * hash ^= int_stream[(i + 15):i];
1416 u8
*stream
= (u8
*)atr_input
;
1417 u8 int_key
[44]; /* upper-most bit unused */
1418 u8 hash_str
[46]; /* upper-most 2 bits unused */
1419 u16 hash_result
= 0;
1423 * Initialize the fill member to prevent warnings
1426 tmp_key
.fill
[0] = 0;
1428 /* First load the temporary key stream */
1429 for (i
= 0; i
< 6; i
++) {
1430 u64 fillkey
= ((u64
)key
<< 32) | key
;
1431 tmp_key
.fill
[i
] = fillkey
;
1435 * Set the interim key for the hashing. Bit 352 is unused, so we must
1436 * shift and compensate when building the key.
1439 int_key
[0] = tmp_key
.key_stream
[0] >> 1;
1440 for (i
= 1, j
= 0; i
< 44; i
++) {
1441 unsigned int this_key
= tmp_key
.key_stream
[j
] << 7;
1443 int_key
[i
] = (u8
)(this_key
| (tmp_key
.key_stream
[j
] >> 1));
1447 * Set the interim bit string for the hashing. Bits 368 and 367 are
1448 * unused, so shift and compensate when building the string.
1450 hash_str
[0] = (stream
[40] & 0x7f) >> 1;
1451 for (i
= 1, j
= 40; i
< 46; i
++) {
1452 unsigned int this_str
= stream
[j
] << 7;
1456 hash_str
[i
] = (u8
)(this_str
| (stream
[j
] >> 1));
1460 * Now compute the hash. i is the index into hash_str, j is into our
1461 * key stream, k is counting the number of bits, and h interates within
1464 for (i
= 45, j
= 43, k
= 0; k
< 351 && i
>= 2 && j
>= 0; i
--, j
--) {
1465 for (h
= 0; h
< 8 && k
< 351; h
++, k
++) {
1466 if (int_key
[j
] & (1 << h
)) {
1468 * Key bit is set, XOR in the current 16-bit
1469 * string. Example of processing:
1471 * tmp = (hash_str[i - 2] & 0 << 16) |
1472 * (hash_str[i - 1] & 0xff << 8) |
1473 * (hash_str[i] & 0xff >> 0)
1474 * So tmp = hash_str[15 + k:k], since the
1475 * i + 2 clause rolls off the 16-bit value
1477 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1478 * (hash_str[i - 1] & 0xff << 1) |
1479 * (hash_str[i] & 0x80 >> 7)
1481 int tmp
= (hash_str
[i
] >> h
);
1482 tmp
|= (hash_str
[i
- 1] << (8 - h
));
1483 tmp
|= (int)(hash_str
[i
- 2] & ((1 << h
) - 1))
1485 hash_result
^= (u16
)tmp
;
1494 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1495 * @input: input stream to modify
1496 * @vlan: the VLAN id to load
1498 s32
ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input
*input
, u16 vlan
)
1500 input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
+ 1] = vlan
>> 8;
1501 input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
] = vlan
& 0xff;
1507 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1508 * @input: input stream to modify
1509 * @src_addr: the IP address to load
1511 s32
ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input
*input
, u32 src_addr
)
1513 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 3] = src_addr
>> 24;
1514 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 2] =
1515 (src_addr
>> 16) & 0xff;
1516 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 1] =
1517 (src_addr
>> 8) & 0xff;
1518 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
] = src_addr
& 0xff;
1524 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1525 * @input: input stream to modify
1526 * @dst_addr: the IP address to load
1528 s32
ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input
*input
, u32 dst_addr
)
1530 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 3] = dst_addr
>> 24;
1531 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 2] =
1532 (dst_addr
>> 16) & 0xff;
1533 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 1] =
1534 (dst_addr
>> 8) & 0xff;
1535 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
] = dst_addr
& 0xff;
1541 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1542 * @input: input stream to modify
1543 * @src_addr_1: the first 4 bytes of the IP address to load
1544 * @src_addr_2: the second 4 bytes of the IP address to load
1545 * @src_addr_3: the third 4 bytes of the IP address to load
1546 * @src_addr_4: the fourth 4 bytes of the IP address to load
1548 s32
ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input
*input
,
1549 u32 src_addr_1
, u32 src_addr_2
,
1550 u32 src_addr_3
, u32 src_addr_4
)
1552 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
] = src_addr_4
& 0xff;
1553 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 1] =
1554 (src_addr_4
>> 8) & 0xff;
1555 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 2] =
1556 (src_addr_4
>> 16) & 0xff;
1557 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 3] = src_addr_4
>> 24;
1559 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 4] = src_addr_3
& 0xff;
1560 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 5] =
1561 (src_addr_3
>> 8) & 0xff;
1562 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 6] =
1563 (src_addr_3
>> 16) & 0xff;
1564 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 7] = src_addr_3
>> 24;
1566 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 8] = src_addr_2
& 0xff;
1567 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 9] =
1568 (src_addr_2
>> 8) & 0xff;
1569 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 10] =
1570 (src_addr_2
>> 16) & 0xff;
1571 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 11] = src_addr_2
>> 24;
1573 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 12] = src_addr_1
& 0xff;
1574 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 13] =
1575 (src_addr_1
>> 8) & 0xff;
1576 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 14] =
1577 (src_addr_1
>> 16) & 0xff;
1578 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 15] = src_addr_1
>> 24;
1584 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1585 * @input: input stream to modify
1586 * @dst_addr_1: the first 4 bytes of the IP address to load
1587 * @dst_addr_2: the second 4 bytes of the IP address to load
1588 * @dst_addr_3: the third 4 bytes of the IP address to load
1589 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1591 s32
ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input
*input
,
1592 u32 dst_addr_1
, u32 dst_addr_2
,
1593 u32 dst_addr_3
, u32 dst_addr_4
)
1595 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
] = dst_addr_4
& 0xff;
1596 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 1] =
1597 (dst_addr_4
>> 8) & 0xff;
1598 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 2] =
1599 (dst_addr_4
>> 16) & 0xff;
1600 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 3] = dst_addr_4
>> 24;
1602 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 4] = dst_addr_3
& 0xff;
1603 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 5] =
1604 (dst_addr_3
>> 8) & 0xff;
1605 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 6] =
1606 (dst_addr_3
>> 16) & 0xff;
1607 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 7] = dst_addr_3
>> 24;
1609 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 8] = dst_addr_2
& 0xff;
1610 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 9] =
1611 (dst_addr_2
>> 8) & 0xff;
1612 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 10] =
1613 (dst_addr_2
>> 16) & 0xff;
1614 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 11] = dst_addr_2
>> 24;
1616 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 12] = dst_addr_1
& 0xff;
1617 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 13] =
1618 (dst_addr_1
>> 8) & 0xff;
1619 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 14] =
1620 (dst_addr_1
>> 16) & 0xff;
1621 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 15] = dst_addr_1
>> 24;
1627 * ixgbe_atr_set_src_port_82599 - Sets the source port
1628 * @input: input stream to modify
1629 * @src_port: the source port to load
1631 s32
ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input
*input
, u16 src_port
)
1633 input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
+ 1] = src_port
>> 8;
1634 input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
] = src_port
& 0xff;
1640 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1641 * @input: input stream to modify
1642 * @dst_port: the destination port to load
1644 s32
ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input
*input
, u16 dst_port
)
1646 input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
+ 1] = dst_port
>> 8;
1647 input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
] = dst_port
& 0xff;
1653 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1654 * @input: input stream to modify
1655 * @flex_bytes: the flexible bytes to load
1657 s32
ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input
*input
, u16 flex_byte
)
1659 input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
+ 1] = flex_byte
>> 8;
1660 input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
] = flex_byte
& 0xff;
1666 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1667 * @input: input stream to modify
1668 * @vm_pool: the Virtual Machine pool to load
1670 s32
ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input
*input
,
1673 input
->byte_stream
[IXGBE_ATR_VM_POOL_OFFSET
] = vm_pool
;
1679 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1680 * @input: input stream to modify
1681 * @l4type: the layer 4 type value to load
1683 s32
ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input
*input
, u8 l4type
)
1685 input
->byte_stream
[IXGBE_ATR_L4TYPE_OFFSET
] = l4type
;
1691 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1692 * @input: input stream to search
1693 * @vlan: the VLAN id to load
1695 static s32
ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input
*input
,
1698 *vlan
= input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
];
1699 *vlan
|= input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
+ 1] << 8;
1705 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1706 * @input: input stream to search
1707 * @src_addr: the IP address to load
1709 static s32
ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input
*input
,
1712 *src_addr
= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
];
1713 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 1] << 8;
1714 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 2] << 16;
1715 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 3] << 24;
1721 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1722 * @input: input stream to search
1723 * @dst_addr: the IP address to load
1725 static s32
ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input
*input
,
1728 *dst_addr
= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
];
1729 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 1] << 8;
1730 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 2] << 16;
1731 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 3] << 24;
1737 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1738 * @input: input stream to search
1739 * @src_addr_1: the first 4 bytes of the IP address to load
1740 * @src_addr_2: the second 4 bytes of the IP address to load
1741 * @src_addr_3: the third 4 bytes of the IP address to load
1742 * @src_addr_4: the fourth 4 bytes of the IP address to load
1744 static s32
ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input
*input
,
1745 u32
*src_addr_1
, u32
*src_addr_2
,
1746 u32
*src_addr_3
, u32
*src_addr_4
)
1748 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 12];
1749 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 13] << 8;
1750 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 14] << 16;
1751 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 15] << 24;
1753 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 8];
1754 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 9] << 8;
1755 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 10] << 16;
1756 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 11] << 24;
1758 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 4];
1759 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 5] << 8;
1760 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 6] << 16;
1761 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 7] << 24;
1763 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
];
1764 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 1] << 8;
1765 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 2] << 16;
1766 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 3] << 24;
1772 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1773 * @input: input stream to search
1774 * @dst_addr_1: the first 4 bytes of the IP address to load
1775 * @dst_addr_2: the second 4 bytes of the IP address to load
1776 * @dst_addr_3: the third 4 bytes of the IP address to load
1777 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1779 s32
ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input
*input
,
1780 u32
*dst_addr_1
, u32
*dst_addr_2
,
1781 u32
*dst_addr_3
, u32
*dst_addr_4
)
1783 *dst_addr_1
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 12];
1784 *dst_addr_1
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 13] << 8;
1785 *dst_addr_1
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 14] << 16;
1786 *dst_addr_1
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 15] << 24;
1788 *dst_addr_2
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 8];
1789 *dst_addr_2
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 9] << 8;
1790 *dst_addr_2
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 10] << 16;
1791 *dst_addr_2
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 11] << 24;
1793 *dst_addr_3
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 4];
1794 *dst_addr_3
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 5] << 8;
1795 *dst_addr_3
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 6] << 16;
1796 *dst_addr_3
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 7] << 24;
1798 *dst_addr_4
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
];
1799 *dst_addr_4
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 1] << 8;
1800 *dst_addr_4
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 2] << 16;
1801 *dst_addr_4
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 3] << 24;
1807 * ixgbe_atr_get_src_port_82599 - Gets the source port
1808 * @input: input stream to modify
1809 * @src_port: the source port to load
1811 * Even though the input is given in big-endian, the FDIRPORT registers
1812 * expect the ports to be programmed in little-endian. Hence the need to swap
1813 * endianness when retrieving the data. This can be confusing since the
1814 * internal hash engine expects it to be big-endian.
1816 static s32
ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input
*input
,
1819 *src_port
= input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
] << 8;
1820 *src_port
|= input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
+ 1];
1826 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1827 * @input: input stream to modify
1828 * @dst_port: the destination port to load
1830 * Even though the input is given in big-endian, the FDIRPORT registers
1831 * expect the ports to be programmed in little-endian. Hence the need to swap
1832 * endianness when retrieving the data. This can be confusing since the
1833 * internal hash engine expects it to be big-endian.
1835 static s32
ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input
*input
,
1838 *dst_port
= input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
] << 8;
1839 *dst_port
|= input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
+ 1];
1845 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1846 * @input: input stream to modify
1847 * @flex_bytes: the flexible bytes to load
1849 static s32
ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input
*input
,
1852 *flex_byte
= input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
];
1853 *flex_byte
|= input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
+ 1] << 8;
1859 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1860 * @input: input stream to modify
1861 * @vm_pool: the Virtual Machine pool to load
1863 s32
ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input
*input
,
1866 *vm_pool
= input
->byte_stream
[IXGBE_ATR_VM_POOL_OFFSET
];
1872 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1873 * @input: input stream to modify
1874 * @l4type: the layer 4 type value to load
1876 static s32
ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input
*input
,
1879 *l4type
= input
->byte_stream
[IXGBE_ATR_L4TYPE_OFFSET
];
1885 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1886 * @hw: pointer to hardware structure
1887 * @stream: input bitstream
1888 * @queue: queue index to direct traffic to
1890 s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
1891 struct ixgbe_atr_input
*input
,
1897 u16 bucket_hash
, sig_hash
;
1900 bucket_hash
= ixgbe_atr_compute_hash_82599(input
,
1901 IXGBE_ATR_BUCKET_HASH_KEY
);
1903 /* bucket_hash is only 15 bits */
1904 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
1906 sig_hash
= ixgbe_atr_compute_hash_82599(input
,
1907 IXGBE_ATR_SIGNATURE_HASH_KEY
);
1909 /* Get the l4type in order to program FDIRCMD properly */
1910 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1911 ixgbe_atr_get_l4type_82599(input
, &l4type
);
1914 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1915 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1917 fdirhash
= sig_hash
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
| bucket_hash
;
1919 fdircmd
= (IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1920 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
);
1922 switch (l4type
& IXGBE_ATR_L4TYPE_MASK
) {
1923 case IXGBE_ATR_L4TYPE_TCP
:
1924 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_TCP
;
1926 case IXGBE_ATR_L4TYPE_UDP
:
1927 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_UDP
;
1929 case IXGBE_ATR_L4TYPE_SCTP
:
1930 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_SCTP
;
1933 hw_dbg(hw
, "Error on l4type input\n");
1934 return IXGBE_ERR_CONFIG
;
1937 if (l4type
& IXGBE_ATR_L4TYPE_IPV6_MASK
)
1938 fdircmd
|= IXGBE_FDIRCMD_IPV6
;
1940 fdircmd
|= ((u64
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
);
1941 fdirhashcmd
= ((fdircmd
<< 32) | fdirhash
);
1943 IXGBE_WRITE_REG64(hw
, IXGBE_FDIRHASH
, fdirhashcmd
);
1949 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1950 * @hw: pointer to hardware structure
1951 * @input: input bitstream
1952 * @queue: queue index to direct traffic to
1954 * Note that the caller to this function must lock before calling, since the
1955 * hardware writes must be protected from one another.
1957 s32
ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw
*hw
,
1958 struct ixgbe_atr_input
*input
,
1964 u32 src_ipv4
, dst_ipv4
;
1965 u32 src_ipv6_1
, src_ipv6_2
, src_ipv6_3
, src_ipv6_4
;
1966 u16 src_port
, dst_port
, vlan_id
, flex_bytes
;
1970 /* Get our input values */
1971 ixgbe_atr_get_l4type_82599(input
, &l4type
);
1974 * Check l4type formatting, and bail out before we touch the hardware
1975 * if there's a configuration issue
1977 switch (l4type
& IXGBE_ATR_L4TYPE_MASK
) {
1978 case IXGBE_ATR_L4TYPE_TCP
:
1979 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_TCP
;
1981 case IXGBE_ATR_L4TYPE_UDP
:
1982 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_UDP
;
1984 case IXGBE_ATR_L4TYPE_SCTP
:
1985 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_SCTP
;
1988 hw_dbg(hw
, "Error on l4type input\n");
1989 return IXGBE_ERR_CONFIG
;
1992 bucket_hash
= ixgbe_atr_compute_hash_82599(input
,
1993 IXGBE_ATR_BUCKET_HASH_KEY
);
1995 /* bucket_hash is only 15 bits */
1996 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
1998 ixgbe_atr_get_vlan_id_82599(input
, &vlan_id
);
1999 ixgbe_atr_get_src_port_82599(input
, &src_port
);
2000 ixgbe_atr_get_dst_port_82599(input
, &dst_port
);
2001 ixgbe_atr_get_flex_byte_82599(input
, &flex_bytes
);
2003 fdirhash
= soft_id
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
| bucket_hash
;
2005 /* Now figure out if we're IPv4 or IPv6 */
2006 if (l4type
& IXGBE_ATR_L4TYPE_IPV6_MASK
) {
2008 ixgbe_atr_get_src_ipv6_82599(input
, &src_ipv6_1
, &src_ipv6_2
,
2009 &src_ipv6_3
, &src_ipv6_4
);
2011 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(0), src_ipv6_1
);
2012 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(1), src_ipv6_2
);
2013 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(2), src_ipv6_3
);
2014 /* The last 4 bytes is the same register as IPv4 */
2015 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPSA
, src_ipv6_4
);
2017 fdircmd
|= IXGBE_FDIRCMD_IPV6
;
2018 fdircmd
|= IXGBE_FDIRCMD_IPv6DMATCH
;
2021 ixgbe_atr_get_src_ipv4_82599(input
, &src_ipv4
);
2022 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPSA
, src_ipv4
);
2026 ixgbe_atr_get_dst_ipv4_82599(input
, &dst_ipv4
);
2027 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPDA
, dst_ipv4
);
2029 IXGBE_WRITE_REG(hw
, IXGBE_FDIRVLAN
, (vlan_id
|
2030 (flex_bytes
<< IXGBE_FDIRVLAN_FLEX_SHIFT
)));
2031 IXGBE_WRITE_REG(hw
, IXGBE_FDIRPORT
, (src_port
|
2032 (dst_port
<< IXGBE_FDIRPORT_DESTINATION_SHIFT
)));
2034 fdircmd
|= IXGBE_FDIRCMD_CMD_ADD_FLOW
;
2035 fdircmd
|= IXGBE_FDIRCMD_FILTER_UPDATE
;
2036 fdircmd
|= IXGBE_FDIRCMD_LAST
;
2037 fdircmd
|= IXGBE_FDIRCMD_QUEUE_EN
;
2038 fdircmd
|= queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
2040 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
2041 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
, fdircmd
);
2046 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2047 * @hw: pointer to hardware structure
2048 * @reg: analog register to read
2051 * Performs read operation to Omer analog register specified.
2053 static s32
ixgbe_read_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
)
2057 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, IXGBE_CORECTL_WRITE_CMD
|
2059 IXGBE_WRITE_FLUSH(hw
);
2061 core_ctl
= IXGBE_READ_REG(hw
, IXGBE_CORECTL
);
2062 *val
= (u8
)core_ctl
;
2068 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2069 * @hw: pointer to hardware structure
2070 * @reg: atlas register to write
2071 * @val: value to write
2073 * Performs write operation to Omer analog register specified.
2075 static s32
ixgbe_write_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8 val
)
2079 core_ctl
= (reg
<< 8) | val
;
2080 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, core_ctl
);
2081 IXGBE_WRITE_FLUSH(hw
);
2088 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2089 * @hw: pointer to hardware structure
2091 * Starts the hardware using the generic start_hw function.
2092 * Then performs device-specific:
2093 * Clears the rate limiter registers.
2095 static s32
ixgbe_start_hw_82599(struct ixgbe_hw
*hw
)
2100 ret_val
= ixgbe_start_hw_generic(hw
);
2102 /* Clear the rate limiters */
2103 for (q_num
= 0; q_num
< hw
->mac
.max_tx_queues
; q_num
++) {
2104 IXGBE_WRITE_REG(hw
, IXGBE_RTTDQSEL
, q_num
);
2105 IXGBE_WRITE_REG(hw
, IXGBE_RTTBCNRC
, 0);
2107 IXGBE_WRITE_FLUSH(hw
);
2109 /* We need to run link autotry after the driver loads */
2110 hw
->mac
.autotry_restart
= true;
2113 ret_val
= ixgbe_verify_fw_version_82599(hw
);
2119 * ixgbe_identify_phy_82599 - Get physical layer module
2120 * @hw: pointer to hardware structure
2122 * Determines the physical layer module found on the current adapter.
2124 static s32
ixgbe_identify_phy_82599(struct ixgbe_hw
*hw
)
2126 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
2127 status
= ixgbe_identify_phy_generic(hw
);
2129 status
= ixgbe_identify_sfp_module_generic(hw
);
2134 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2135 * @hw: pointer to hardware structure
2137 * Determines physical layer capabilities of the current configuration.
2139 static u32
ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw
*hw
)
2141 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
2142 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2143 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
2144 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
2145 u32 pma_pmd_10g_parallel
= autoc
& IXGBE_AUTOC_10G_PMA_PMD_MASK
;
2146 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
2147 u16 ext_ability
= 0;
2148 u8 comp_codes_10g
= 0;
2150 hw
->phy
.ops
.identify(hw
);
2152 if (hw
->phy
.type
== ixgbe_phy_tn
||
2153 hw
->phy
.type
== ixgbe_phy_cu_unknown
) {
2154 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
2156 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
2157 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
2158 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
2159 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
2160 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
2161 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
2165 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
2166 case IXGBE_AUTOC_LMS_1G_AN
:
2167 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
2168 if (pma_pmd_1g
== IXGBE_AUTOC_1G_KX_BX
) {
2169 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_KX
|
2170 IXGBE_PHYSICAL_LAYER_1000BASE_BX
;
2173 /* SFI mode so read SFP module */
2176 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
2177 if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_CX4
)
2178 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_CX4
;
2179 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_KX4
)
2180 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
2181 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_XAUI
)
2182 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_XAUI
;
2185 case IXGBE_AUTOC_LMS_10G_SERIAL
:
2186 if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_KR
) {
2187 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
2189 } else if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)
2192 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
2193 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
2194 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
2195 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
2196 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
2197 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
2198 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
2199 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
2208 /* SFP check must be done last since DA modules are sometimes used to
2209 * test KR mode - we need to id KR mode correctly before SFP module.
2210 * Call identify_sfp because the pluggable module may have changed */
2211 hw
->phy
.ops
.identify_sfp(hw
);
2212 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)
2215 switch (hw
->phy
.type
) {
2216 case ixgbe_phy_tw_tyco
:
2217 case ixgbe_phy_tw_unknown
:
2218 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
2220 case ixgbe_phy_sfp_avago
:
2221 case ixgbe_phy_sfp_ftl
:
2222 case ixgbe_phy_sfp_intel
:
2223 case ixgbe_phy_sfp_unknown
:
2224 hw
->phy
.ops
.read_i2c_eeprom(hw
,
2225 IXGBE_SFF_10GBE_COMP_CODES
, &comp_codes_10g
);
2226 if (comp_codes_10g
& IXGBE_SFF_10GBASESR_CAPABLE
)
2227 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
2228 else if (comp_codes_10g
& IXGBE_SFF_10GBASELR_CAPABLE
)
2229 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
2236 return physical_layer
;
2240 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2241 * @hw: pointer to hardware structure
2242 * @regval: register value to write to RXCTRL
2244 * Enables the Rx DMA unit for 82599
2246 static s32
ixgbe_enable_rx_dma_82599(struct ixgbe_hw
*hw
, u32 regval
)
2248 #define IXGBE_MAX_SECRX_POLL 30
2253 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2254 * If traffic is incoming before we enable the Rx unit, it could hang
2255 * the Rx DMA unit. Therefore, make sure the security engine is
2256 * completely disabled prior to enabling the Rx unit.
2258 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2259 secrxreg
|= IXGBE_SECRXCTRL_RX_DIS
;
2260 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2261 for (i
= 0; i
< IXGBE_MAX_SECRX_POLL
; i
++) {
2262 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXSTAT
);
2263 if (secrxreg
& IXGBE_SECRXSTAT_SECRX_RDY
)
2269 /* For informational purposes only */
2270 if (i
>= IXGBE_MAX_SECRX_POLL
)
2271 hw_dbg(hw
, "Rx unit being enabled before security "
2272 "path fully disabled. Continuing with init.\n");
2274 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
2275 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2276 secrxreg
&= ~IXGBE_SECRXCTRL_RX_DIS
;
2277 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2278 IXGBE_WRITE_FLUSH(hw
);
2284 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2285 * @hw: pointer to hardware structure
2286 * @device_caps: the EEPROM word with the extra device capabilities
2288 * This function will read the EEPROM location for the device capabilities,
2289 * and return the word through device_caps.
2291 static s32
ixgbe_get_device_caps_82599(struct ixgbe_hw
*hw
, u16
*device_caps
)
2293 hw
->eeprom
.ops
.read(hw
, IXGBE_DEVICE_CAPS
, device_caps
);
2299 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2300 * @hw: pointer to hardware structure
2301 * @san_mac_offset: SAN MAC address offset
2303 * This function will read the EEPROM location for the SAN MAC address
2304 * pointer, and returns the value at that location. This is used in both
2305 * get and set mac_addr routines.
2307 static s32
ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw
*hw
,
2308 u16
*san_mac_offset
)
2311 * First read the EEPROM pointer to see if the MAC addresses are
2314 hw
->eeprom
.ops
.read(hw
, IXGBE_SAN_MAC_ADDR_PTR
, san_mac_offset
);
2320 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2321 * @hw: pointer to hardware structure
2322 * @san_mac_addr: SAN MAC address
2324 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2325 * per-port, so set_lan_id() must be called before reading the addresses.
2326 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2327 * upon for non-SFP connections, so we must call it here.
2329 static s32
ixgbe_get_san_mac_addr_82599(struct ixgbe_hw
*hw
, u8
*san_mac_addr
)
2331 u16 san_mac_data
, san_mac_offset
;
2335 * First read the EEPROM pointer to see if the MAC addresses are
2336 * available. If they're not, no point in calling set_lan_id() here.
2338 ixgbe_get_san_mac_addr_offset_82599(hw
, &san_mac_offset
);
2340 if ((san_mac_offset
== 0) || (san_mac_offset
== 0xFFFF)) {
2342 * No addresses available in this EEPROM. It's not an
2343 * error though, so just wipe the local address and return.
2345 for (i
= 0; i
< 6; i
++)
2346 san_mac_addr
[i
] = 0xFF;
2348 goto san_mac_addr_out
;
2351 /* make sure we know which port we need to program */
2352 hw
->mac
.ops
.set_lan_id(hw
);
2353 /* apply the port offset to the address offset */
2354 (hw
->bus
.func
) ? (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
) :
2355 (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
);
2356 for (i
= 0; i
< 3; i
++) {
2357 hw
->eeprom
.ops
.read(hw
, san_mac_offset
, &san_mac_data
);
2358 san_mac_addr
[i
* 2] = (u8
)(san_mac_data
);
2359 san_mac_addr
[i
* 2 + 1] = (u8
)(san_mac_data
>> 8);
2368 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2369 * @hw: pointer to hardware structure
2371 * Verifies that installed the firmware version is 0.6 or higher
2372 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2374 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2375 * if the FW version is not supported.
2377 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
)
2379 s32 status
= IXGBE_ERR_EEPROM_VERSION
;
2380 u16 fw_offset
, fw_ptp_cfg_offset
;
2383 /* firmware check is only necessary for SFI devices */
2384 if (hw
->phy
.media_type
!= ixgbe_media_type_fiber
) {
2386 goto fw_version_out
;
2389 /* get the offset to the Firmware Module block */
2390 hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
2392 if ((fw_offset
== 0) || (fw_offset
== 0xFFFF))
2393 goto fw_version_out
;
2395 /* get the offset to the Pass Through Patch Configuration block */
2396 hw
->eeprom
.ops
.read(hw
, (fw_offset
+
2397 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR
),
2398 &fw_ptp_cfg_offset
);
2400 if ((fw_ptp_cfg_offset
== 0) || (fw_ptp_cfg_offset
== 0xFFFF))
2401 goto fw_version_out
;
2403 /* get the firmware version */
2404 hw
->eeprom
.ops
.read(hw
, (fw_ptp_cfg_offset
+
2405 IXGBE_FW_PATCH_VERSION_4
),
2408 if (fw_version
> 0x5)
2415 static struct ixgbe_mac_operations mac_ops_82599
= {
2416 .init_hw
= &ixgbe_init_hw_generic
,
2417 .reset_hw
= &ixgbe_reset_hw_82599
,
2418 .start_hw
= &ixgbe_start_hw_82599
,
2419 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
2420 .get_media_type
= &ixgbe_get_media_type_82599
,
2421 .get_supported_physical_layer
= &ixgbe_get_supported_physical_layer_82599
,
2422 .enable_rx_dma
= &ixgbe_enable_rx_dma_82599
,
2423 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
2424 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_82599
,
2425 .get_device_caps
= &ixgbe_get_device_caps_82599
,
2426 .stop_adapter
= &ixgbe_stop_adapter_generic
,
2427 .get_bus_info
= &ixgbe_get_bus_info_generic
,
2428 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
2429 .read_analog_reg8
= &ixgbe_read_analog_reg8_82599
,
2430 .write_analog_reg8
= &ixgbe_write_analog_reg8_82599
,
2431 .setup_link
= &ixgbe_setup_mac_link_82599
,
2432 .check_link
= &ixgbe_check_mac_link_82599
,
2433 .get_link_capabilities
= &ixgbe_get_link_capabilities_82599
,
2434 .led_on
= &ixgbe_led_on_generic
,
2435 .led_off
= &ixgbe_led_off_generic
,
2436 .blink_led_start
= &ixgbe_blink_led_start_generic
,
2437 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
2438 .set_rar
= &ixgbe_set_rar_generic
,
2439 .clear_rar
= &ixgbe_clear_rar_generic
,
2440 .set_vmdq
= &ixgbe_set_vmdq_82599
,
2441 .clear_vmdq
= &ixgbe_clear_vmdq_82599
,
2442 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
2443 .update_uc_addr_list
= &ixgbe_update_uc_addr_list_generic
,
2444 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
2445 .enable_mc
= &ixgbe_enable_mc_generic
,
2446 .disable_mc
= &ixgbe_disable_mc_generic
,
2447 .clear_vfta
= &ixgbe_clear_vfta_82599
,
2448 .set_vfta
= &ixgbe_set_vfta_82599
,
2449 .fc_enable
= &ixgbe_fc_enable_generic
,
2450 .init_uta_tables
= &ixgbe_init_uta_tables_82599
,
2451 .setup_sfp
= &ixgbe_setup_sfp_modules_82599
,
2454 static struct ixgbe_eeprom_operations eeprom_ops_82599
= {
2455 .init_params
= &ixgbe_init_eeprom_params_generic
,
2456 .read
= &ixgbe_read_eeprom_generic
,
2457 .write
= &ixgbe_write_eeprom_generic
,
2458 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
2459 .update_checksum
= &ixgbe_update_eeprom_checksum_generic
,
2462 static struct ixgbe_phy_operations phy_ops_82599
= {
2463 .identify
= &ixgbe_identify_phy_82599
,
2464 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
2465 .init
= &ixgbe_init_phy_ops_82599
,
2466 .reset
= &ixgbe_reset_phy_generic
,
2467 .read_reg
= &ixgbe_read_phy_reg_generic
,
2468 .write_reg
= &ixgbe_write_phy_reg_generic
,
2469 .setup_link
= &ixgbe_setup_phy_link_generic
,
2470 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
2471 .read_i2c_byte
= &ixgbe_read_i2c_byte_generic
,
2472 .write_i2c_byte
= &ixgbe_write_i2c_byte_generic
,
2473 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_generic
,
2474 .write_i2c_eeprom
= &ixgbe_write_i2c_eeprom_generic
,
2477 struct ixgbe_info ixgbe_82599_info
= {
2478 .mac
= ixgbe_mac_82599EB
,
2479 .get_invariants
= &ixgbe_get_invariants_82599
,
2480 .mac_ops
= &mac_ops_82599
,
2481 .eeprom_ops
= &eeprom_ops_82599
,
2482 .phy_ops
= &phy_ops_82599
,