1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
31 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
34 #include <linux/netdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/delay.h>
37 #include <linux/pci.h>
41 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
42 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
43 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
45 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
46 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
47 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
49 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
50 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
60 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
61 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
66 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
67 /* 1=Reverse Auto-Negotiation */
69 /* MAC Specific Control Register (Page 2, Register 21) */
70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
71 #define GG82563_MSCR_TX_CLK_MASK 0x0007
72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
73 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
74 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
76 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
78 /* DSP Distance Register (Page 5, Register 26) */
79 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
85 /* Kumeran Mode Control Register (Page 193, Register 16) */
86 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
88 /* Power Management Control Register (Page 193, Register 20) */
89 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
90 /* 1=Enable SERDES Electrical Idle */
92 /* In-Band Control Register (Page 194, Register 18) */
93 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
96 * A table for the GG82563 cable length where the range is defined
97 * with a lower bound at "index" and the upper bound at
100 static const u16 e1000_gg82563_cable_length_table
[] =
101 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
103 static s32
e1000_setup_copper_link_80003es2lan(struct e1000_hw
*hw
);
104 static s32
e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw
*hw
, u16 mask
);
105 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw
*hw
, u16 mask
);
106 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw
*hw
);
107 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw
*hw
);
108 static s32
e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw
*hw
);
109 static s32
e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw
*hw
, u16 duplex
);
112 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
113 * @hw: pointer to the HW structure
115 * This is a function pointer entry point called by the api module.
117 static s32
e1000_init_phy_params_80003es2lan(struct e1000_hw
*hw
)
119 struct e1000_phy_info
*phy
= &hw
->phy
;
122 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
123 phy
->type
= e1000_phy_none
;
128 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
129 phy
->reset_delay_us
= 100;
130 phy
->type
= e1000_phy_gg82563
;
132 /* This can only be done after all function pointers are setup. */
133 ret_val
= e1000e_get_phy_id(hw
);
136 if (phy
->id
!= GG82563_E_PHY_ID
)
137 return -E1000_ERR_PHY
;
143 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
144 * @hw: pointer to the HW structure
146 * This is a function pointer entry point called by the api module.
148 static s32
e1000_init_nvm_params_80003es2lan(struct e1000_hw
*hw
)
150 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
151 u32 eecd
= er32(EECD
);
154 nvm
->opcode_bits
= 8;
156 switch (nvm
->override
) {
157 case e1000_nvm_override_spi_large
:
159 nvm
->address_bits
= 16;
161 case e1000_nvm_override_spi_small
:
163 nvm
->address_bits
= 8;
166 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
167 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
171 nvm
->type
= e1000_nvm_eeprom_spi
;
173 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
174 E1000_EECD_SIZE_EX_SHIFT
);
177 * Added to a constant, "size" becomes the left-shift value
178 * for setting word_size.
180 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
182 /* EEPROM access above 16k is unsupported */
185 nvm
->word_size
= 1 << size
;
191 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
192 * @hw: pointer to the HW structure
194 * This is a function pointer entry point called by the api module.
196 static s32
e1000_init_mac_params_80003es2lan(struct e1000_adapter
*adapter
)
198 struct e1000_hw
*hw
= &adapter
->hw
;
199 struct e1000_mac_info
*mac
= &hw
->mac
;
200 struct e1000_mac_operations
*func
= &mac
->ops
;
203 switch (adapter
->pdev
->device
) {
204 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT
:
205 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
208 hw
->phy
.media_type
= e1000_media_type_copper
;
212 /* Set mta register count */
213 mac
->mta_reg_count
= 128;
214 /* Set rar entry count */
215 mac
->rar_entry_count
= E1000_RAR_ENTRIES
;
216 /* Set if manageability features are enabled. */
217 mac
->arc_subsystem_valid
= (er32(FWSM
) & E1000_FWSM_MODE_MASK
) ? 1 : 0;
220 switch (hw
->phy
.media_type
) {
221 case e1000_media_type_copper
:
222 func
->setup_physical_interface
= e1000_setup_copper_link_80003es2lan
;
223 func
->check_for_link
= e1000e_check_for_copper_link
;
225 case e1000_media_type_fiber
:
226 func
->setup_physical_interface
= e1000e_setup_fiber_serdes_link
;
227 func
->check_for_link
= e1000e_check_for_fiber_link
;
229 case e1000_media_type_internal_serdes
:
230 func
->setup_physical_interface
= e1000e_setup_fiber_serdes_link
;
231 func
->check_for_link
= e1000e_check_for_serdes_link
;
234 return -E1000_ERR_CONFIG
;
241 static s32
e1000_get_variants_80003es2lan(struct e1000_adapter
*adapter
)
243 struct e1000_hw
*hw
= &adapter
->hw
;
246 rc
= e1000_init_mac_params_80003es2lan(adapter
);
250 rc
= e1000_init_nvm_params_80003es2lan(hw
);
254 rc
= e1000_init_phy_params_80003es2lan(hw
);
262 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
263 * @hw: pointer to the HW structure
265 * A wrapper to acquire access rights to the correct PHY. This is a
266 * function pointer entry point called by the api module.
268 static s32
e1000_acquire_phy_80003es2lan(struct e1000_hw
*hw
)
272 mask
= hw
->bus
.func
? E1000_SWFW_PHY1_SM
: E1000_SWFW_PHY0_SM
;
274 return e1000_acquire_swfw_sync_80003es2lan(hw
, mask
);
278 * e1000_release_phy_80003es2lan - Release rights to access PHY
279 * @hw: pointer to the HW structure
281 * A wrapper to release access rights to the correct PHY. This is a
282 * function pointer entry point called by the api module.
284 static void e1000_release_phy_80003es2lan(struct e1000_hw
*hw
)
288 mask
= hw
->bus
.func
? E1000_SWFW_PHY1_SM
: E1000_SWFW_PHY0_SM
;
289 e1000_release_swfw_sync_80003es2lan(hw
, mask
);
293 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
294 * @hw: pointer to the HW structure
296 * Acquire the semaphore to access the EEPROM. This is a function
297 * pointer entry point called by the api module.
299 static s32
e1000_acquire_nvm_80003es2lan(struct e1000_hw
*hw
)
303 ret_val
= e1000_acquire_swfw_sync_80003es2lan(hw
, E1000_SWFW_EEP_SM
);
307 ret_val
= e1000e_acquire_nvm(hw
);
310 e1000_release_swfw_sync_80003es2lan(hw
, E1000_SWFW_EEP_SM
);
316 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
317 * @hw: pointer to the HW structure
319 * Release the semaphore used to access the EEPROM. This is a
320 * function pointer entry point called by the api module.
322 static void e1000_release_nvm_80003es2lan(struct e1000_hw
*hw
)
324 e1000e_release_nvm(hw
);
325 e1000_release_swfw_sync_80003es2lan(hw
, E1000_SWFW_EEP_SM
);
329 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
330 * @hw: pointer to the HW structure
331 * @mask: specifies which semaphore to acquire
333 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
334 * will also specify which port we're acquiring the lock for.
336 static s32
e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw
*hw
, u16 mask
)
340 u32 fwmask
= mask
<< 16;
344 while (i
< timeout
) {
345 if (e1000e_get_hw_semaphore(hw
))
346 return -E1000_ERR_SWFW_SYNC
;
348 swfw_sync
= er32(SW_FW_SYNC
);
349 if (!(swfw_sync
& (fwmask
| swmask
)))
353 * Firmware currently using resource (fwmask)
354 * or other software thread using resource (swmask)
356 e1000e_put_hw_semaphore(hw
);
363 "Driver can't access resource, SW_FW_SYNC timeout.\n");
364 return -E1000_ERR_SWFW_SYNC
;
368 ew32(SW_FW_SYNC
, swfw_sync
);
370 e1000e_put_hw_semaphore(hw
);
376 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
377 * @hw: pointer to the HW structure
378 * @mask: specifies which semaphore to acquire
380 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
381 * will also specify which port we're releasing the lock for.
383 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw
*hw
, u16 mask
)
387 while (e1000e_get_hw_semaphore(hw
) != 0);
390 swfw_sync
= er32(SW_FW_SYNC
);
392 ew32(SW_FW_SYNC
, swfw_sync
);
394 e1000e_put_hw_semaphore(hw
);
398 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
399 * @hw: pointer to the HW structure
400 * @offset: offset of the register to read
401 * @data: pointer to the data returned from the operation
403 * Read the GG82563 PHY register. This is a function pointer entry
404 * point called by the api module.
406 static s32
e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw
*hw
,
407 u32 offset
, u16
*data
)
413 /* Select Configuration Page */
414 if ((offset
& MAX_PHY_REG_ADDRESS
) < GG82563_MIN_ALT_REG
)
415 page_select
= GG82563_PHY_PAGE_SELECT
;
418 * Use Alternative Page Select register to access
419 * registers 30 and 31
421 page_select
= GG82563_PHY_PAGE_SELECT_ALT
;
423 temp
= (u16
)((u16
)offset
>> GG82563_PAGE_SHIFT
);
424 ret_val
= e1000e_write_phy_reg_m88(hw
, page_select
, temp
);
429 * The "ready" bit in the MDIC register may be incorrectly set
430 * before the device has completed the "Page Select" MDI
431 * transaction. So we wait 200us after each MDI command...
435 /* ...and verify the command was successful. */
436 ret_val
= e1000e_read_phy_reg_m88(hw
, page_select
, &temp
);
438 if (((u16
)offset
>> GG82563_PAGE_SHIFT
) != temp
) {
439 ret_val
= -E1000_ERR_PHY
;
445 ret_val
= e1000e_read_phy_reg_m88(hw
,
446 MAX_PHY_REG_ADDRESS
& offset
,
455 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
456 * @hw: pointer to the HW structure
457 * @offset: offset of the register to read
458 * @data: value to write to the register
460 * Write to the GG82563 PHY register. This is a function pointer entry
461 * point called by the api module.
463 static s32
e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw
*hw
,
464 u32 offset
, u16 data
)
470 /* Select Configuration Page */
471 if ((offset
& MAX_PHY_REG_ADDRESS
) < GG82563_MIN_ALT_REG
)
472 page_select
= GG82563_PHY_PAGE_SELECT
;
475 * Use Alternative Page Select register to access
476 * registers 30 and 31
478 page_select
= GG82563_PHY_PAGE_SELECT_ALT
;
480 temp
= (u16
)((u16
)offset
>> GG82563_PAGE_SHIFT
);
481 ret_val
= e1000e_write_phy_reg_m88(hw
, page_select
, temp
);
487 * The "ready" bit in the MDIC register may be incorrectly set
488 * before the device has completed the "Page Select" MDI
489 * transaction. So we wait 200us after each MDI command...
493 /* ...and verify the command was successful. */
494 ret_val
= e1000e_read_phy_reg_m88(hw
, page_select
, &temp
);
496 if (((u16
)offset
>> GG82563_PAGE_SHIFT
) != temp
)
497 return -E1000_ERR_PHY
;
501 ret_val
= e1000e_write_phy_reg_m88(hw
,
502 MAX_PHY_REG_ADDRESS
& offset
,
511 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
512 * @hw: pointer to the HW structure
513 * @offset: offset of the register to read
514 * @words: number of words to write
515 * @data: buffer of data to write to the NVM
517 * Write "words" of data to the ESB2 NVM. This is a function
518 * pointer entry point called by the api module.
520 static s32
e1000_write_nvm_80003es2lan(struct e1000_hw
*hw
, u16 offset
,
521 u16 words
, u16
*data
)
523 return e1000e_write_nvm_spi(hw
, offset
, words
, data
);
527 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
528 * @hw: pointer to the HW structure
530 * Wait a specific amount of time for manageability processes to complete.
531 * This is a function pointer entry point called by the phy module.
533 static s32
e1000_get_cfg_done_80003es2lan(struct e1000_hw
*hw
)
535 s32 timeout
= PHY_CFG_TIMEOUT
;
536 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
538 if (hw
->bus
.func
== 1)
539 mask
= E1000_NVM_CFG_DONE_PORT_1
;
542 if (er32(EEMNGCTL
) & mask
)
548 hw_dbg(hw
, "MNG configuration cycle has not completed.\n");
549 return -E1000_ERR_RESET
;
556 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
557 * @hw: pointer to the HW structure
559 * Force the speed and duplex settings onto the PHY. This is a
560 * function pointer entry point called by the phy module.
562 static s32
e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw
*hw
)
569 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
570 * forced whenever speed and duplex are forced.
572 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
576 phy_data
&= ~GG82563_PSCR_CROSSOVER_MODE_AUTO
;
577 ret_val
= e1e_wphy(hw
, GG82563_PHY_SPEC_CTRL
, phy_data
);
581 hw_dbg(hw
, "GG82563 PSCR: %X\n", phy_data
);
583 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
587 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
589 /* Reset the phy to commit changes. */
590 phy_data
|= MII_CR_RESET
;
592 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
598 if (hw
->phy
.autoneg_wait_to_complete
) {
599 hw_dbg(hw
, "Waiting for forced speed/duplex link "
600 "on GG82563 phy.\n");
602 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
609 * We didn't get link.
610 * Reset the DSP and cross our fingers.
612 ret_val
= e1000e_phy_reset_dsp(hw
);
618 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
624 ret_val
= e1e_rphy(hw
, GG82563_PHY_MAC_SPEC_CTRL
, &phy_data
);
629 * Resetting the phy means we need to verify the TX_CLK corresponds
630 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
632 phy_data
&= ~GG82563_MSCR_TX_CLK_MASK
;
633 if (hw
->mac
.forced_speed_duplex
& E1000_ALL_10_SPEED
)
634 phy_data
|= GG82563_MSCR_TX_CLK_10MBPS_2_5
;
636 phy_data
|= GG82563_MSCR_TX_CLK_100MBPS_25
;
639 * In addition, we must re-enable CRS on Tx for both half and full
642 phy_data
|= GG82563_MSCR_ASSERT_CRS_ON_TX
;
643 ret_val
= e1e_wphy(hw
, GG82563_PHY_MAC_SPEC_CTRL
, phy_data
);
649 * e1000_get_cable_length_80003es2lan - Set approximate cable length
650 * @hw: pointer to the HW structure
652 * Find the approximate cable length as measured by the GG82563 PHY.
653 * This is a function pointer entry point called by the phy module.
655 static s32
e1000_get_cable_length_80003es2lan(struct e1000_hw
*hw
)
657 struct e1000_phy_info
*phy
= &hw
->phy
;
662 ret_val
= e1e_rphy(hw
, GG82563_PHY_DSP_DISTANCE
, &phy_data
);
666 index
= phy_data
& GG82563_DSPD_CABLE_LENGTH
;
667 phy
->min_cable_length
= e1000_gg82563_cable_length_table
[index
];
668 phy
->max_cable_length
= e1000_gg82563_cable_length_table
[index
+5];
670 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
676 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
677 * @hw: pointer to the HW structure
678 * @speed: pointer to speed buffer
679 * @duplex: pointer to duplex buffer
681 * Retrieve the current speed and duplex configuration.
682 * This is a function pointer entry point called by the api module.
684 static s32
e1000_get_link_up_info_80003es2lan(struct e1000_hw
*hw
, u16
*speed
,
689 if (hw
->phy
.media_type
== e1000_media_type_copper
) {
690 ret_val
= e1000e_get_speed_and_duplex_copper(hw
,
695 if (*speed
== SPEED_1000
)
696 ret_val
= e1000_cfg_kmrn_1000_80003es2lan(hw
);
698 ret_val
= e1000_cfg_kmrn_10_100_80003es2lan(hw
,
701 ret_val
= e1000e_get_speed_and_duplex_fiber_serdes(hw
,
710 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
711 * @hw: pointer to the HW structure
713 * Perform a global reset to the ESB2 controller.
714 * This is a function pointer entry point called by the api module.
716 static s32
e1000_reset_hw_80003es2lan(struct e1000_hw
*hw
)
723 * Prevent the PCI-E bus from sticking if there is no TLP connection
724 * on the last TLP read/write transaction when MAC is reset.
726 ret_val
= e1000e_disable_pcie_master(hw
);
728 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
730 hw_dbg(hw
, "Masking off all interrupts\n");
731 ew32(IMC
, 0xffffffff);
734 ew32(TCTL
, E1000_TCTL_PSP
);
741 hw_dbg(hw
, "Issuing a global reset to MAC\n");
742 ew32(CTRL
, ctrl
| E1000_CTRL_RST
);
744 ret_val
= e1000e_get_auto_rd_done(hw
);
746 /* We don't want to continue accessing MAC registers. */
749 /* Clear any pending interrupt events. */
750 ew32(IMC
, 0xffffffff);
757 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
758 * @hw: pointer to the HW structure
760 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
761 * This is a function pointer entry point called by the api module.
763 static s32
e1000_init_hw_80003es2lan(struct e1000_hw
*hw
)
765 struct e1000_mac_info
*mac
= &hw
->mac
;
770 e1000_initialize_hw_bits_80003es2lan(hw
);
772 /* Initialize identification LED */
773 ret_val
= e1000e_id_led_init(hw
);
775 hw_dbg(hw
, "Error initializing identification LED\n");
779 /* Disabling VLAN filtering */
780 hw_dbg(hw
, "Initializing the IEEE VLAN\n");
781 e1000e_clear_vfta(hw
);
783 /* Setup the receive address. */
784 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
786 /* Zero out the Multicast HASH table */
787 hw_dbg(hw
, "Zeroing the MTA\n");
788 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
789 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
791 /* Setup link and flow control */
792 ret_val
= e1000e_setup_link(hw
);
794 /* Set the transmit descriptor write-back policy */
795 reg_data
= er32(TXDCTL(0));
796 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
797 E1000_TXDCTL_FULL_TX_DESC_WB
| E1000_TXDCTL_COUNT_DESC
;
798 ew32(TXDCTL(0), reg_data
);
800 /* ...for both queues. */
801 reg_data
= er32(TXDCTL(1));
802 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
803 E1000_TXDCTL_FULL_TX_DESC_WB
| E1000_TXDCTL_COUNT_DESC
;
804 ew32(TXDCTL(1), reg_data
);
806 /* Enable retransmit on late collisions */
807 reg_data
= er32(TCTL
);
808 reg_data
|= E1000_TCTL_RTLC
;
809 ew32(TCTL
, reg_data
);
811 /* Configure Gigabit Carry Extend Padding */
812 reg_data
= er32(TCTL_EXT
);
813 reg_data
&= ~E1000_TCTL_EXT_GCEX_MASK
;
814 reg_data
|= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN
;
815 ew32(TCTL_EXT
, reg_data
);
817 /* Configure Transmit Inter-Packet Gap */
818 reg_data
= er32(TIPG
);
819 reg_data
&= ~E1000_TIPG_IPGT_MASK
;
820 reg_data
|= DEFAULT_TIPG_IPGT_1000_80003ES2LAN
;
821 ew32(TIPG
, reg_data
);
823 reg_data
= E1000_READ_REG_ARRAY(hw
, E1000_FFLT
, 0x0001);
824 reg_data
&= ~0x00100000;
825 E1000_WRITE_REG_ARRAY(hw
, E1000_FFLT
, 0x0001, reg_data
);
828 * Clear all of the statistics registers (clear on read). It is
829 * important that we do this after we have tried to establish link
830 * because the symbol error count will increment wildly if there
833 e1000_clear_hw_cntrs_80003es2lan(hw
);
839 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
840 * @hw: pointer to the HW structure
842 * Initializes required hardware-dependent bits needed for normal operation.
844 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw
*hw
)
848 /* Transmit Descriptor Control 0 */
849 reg
= er32(TXDCTL(0));
851 ew32(TXDCTL(0), reg
);
853 /* Transmit Descriptor Control 1 */
854 reg
= er32(TXDCTL(1));
856 ew32(TXDCTL(1), reg
);
858 /* Transmit Arbitration Control 0 */
860 reg
&= ~(0xF << 27); /* 30:27 */
861 if (hw
->phy
.media_type
!= e1000_media_type_copper
)
865 /* Transmit Arbitration Control 1 */
867 if (er32(TCTL
) & E1000_TCTL_MULR
)
875 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
876 * @hw: pointer to the HW structure
878 * Setup some GG82563 PHY registers for obtaining link
880 static s32
e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw
*hw
)
882 struct e1000_phy_info
*phy
= &hw
->phy
;
887 ret_val
= e1e_rphy(hw
, GG82563_PHY_MAC_SPEC_CTRL
,
892 data
|= GG82563_MSCR_ASSERT_CRS_ON_TX
;
893 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
894 data
|= GG82563_MSCR_TX_CLK_1000MBPS_25
;
896 ret_val
= e1e_wphy(hw
, GG82563_PHY_MAC_SPEC_CTRL
,
903 * MDI/MDI-X = 0 (default)
904 * 0 - Auto for all speeds
907 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
909 ret_val
= e1e_rphy(hw
, GG82563_PHY_SPEC_CTRL
, &data
);
913 data
&= ~GG82563_PSCR_CROSSOVER_MODE_MASK
;
917 data
|= GG82563_PSCR_CROSSOVER_MODE_MDI
;
920 data
|= GG82563_PSCR_CROSSOVER_MODE_MDIX
;
924 data
|= GG82563_PSCR_CROSSOVER_MODE_AUTO
;
930 * disable_polarity_correction = 0 (default)
931 * Automatic Correction for Reversed Cable Polarity
935 data
&= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE
;
936 if (phy
->disable_polarity_correction
)
937 data
|= GG82563_PSCR_POLARITY_REVERSAL_DISABLE
;
939 ret_val
= e1e_wphy(hw
, GG82563_PHY_SPEC_CTRL
, data
);
943 /* SW Reset the PHY so all changes take effect */
944 ret_val
= e1000e_commit_phy(hw
);
946 hw_dbg(hw
, "Error Resetting the PHY\n");
950 /* Bypass Rx and Tx FIFO's */
951 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL
,
952 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS
|
953 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS
);
957 ret_val
= e1e_rphy(hw
, GG82563_PHY_SPEC_CTRL_2
, &data
);
961 data
&= ~GG82563_PSCR2_REVERSE_AUTO_NEG
;
962 ret_val
= e1e_wphy(hw
, GG82563_PHY_SPEC_CTRL_2
, data
);
966 ctrl_ext
= er32(CTRL_EXT
);
967 ctrl_ext
&= ~(E1000_CTRL_EXT_LINK_MODE_MASK
);
968 ew32(CTRL_EXT
, ctrl_ext
);
970 ret_val
= e1e_rphy(hw
, GG82563_PHY_PWR_MGMT_CTRL
, &data
);
975 * Do not init these registers when the HW is in IAMT mode, since the
976 * firmware will have already initialized them. We only initialize
977 * them if the HW is not in IAMT mode.
979 if (!e1000e_check_mng_mode(hw
)) {
980 /* Enable Electrical Idle on the PHY */
981 data
|= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE
;
982 ret_val
= e1e_wphy(hw
, GG82563_PHY_PWR_MGMT_CTRL
, data
);
986 ret_val
= e1e_rphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, &data
);
990 data
&= ~GG82563_KMCR_PASS_FALSE_CARRIER
;
991 ret_val
= e1e_wphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, data
);
997 * Workaround: Disable padding in Kumeran interface in the MAC
998 * and in the PHY to avoid CRC errors.
1000 ret_val
= e1e_rphy(hw
, GG82563_PHY_INBAND_CTRL
, &data
);
1004 data
|= GG82563_ICR_DIS_PADDING
;
1005 ret_val
= e1e_wphy(hw
, GG82563_PHY_INBAND_CTRL
, data
);
1013 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1014 * @hw: pointer to the HW structure
1016 * Essentially a wrapper for setting up all things "copper" related.
1017 * This is a function pointer entry point called by the mac module.
1019 static s32
e1000_setup_copper_link_80003es2lan(struct e1000_hw
*hw
)
1026 ctrl
|= E1000_CTRL_SLU
;
1027 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1031 * Set the mac to wait the maximum time between each
1032 * iteration and increase the max iterations when
1033 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1035 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 4), 0xFFFF);
1038 ret_val
= e1000e_read_kmrn_reg(hw
, GG82563_REG(0x34, 9), ®_data
);
1042 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 9), reg_data
);
1045 ret_val
= e1000e_read_kmrn_reg(hw
,
1046 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL
,
1050 reg_data
|= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING
;
1051 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL
,
1056 ret_val
= e1000_copper_link_setup_gg82563_80003es2lan(hw
);
1060 ret_val
= e1000e_setup_copper_link(hw
);
1066 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1067 * @hw: pointer to the HW structure
1068 * @duplex: current duplex setting
1070 * Configure the KMRN interface by applying last minute quirks for
1073 static s32
e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw
*hw
, u16 duplex
)
1079 reg_data
= E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT
;
1080 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL
,
1085 /* Configure Transmit Inter-Packet Gap */
1087 tipg
&= ~E1000_TIPG_IPGT_MASK
;
1088 tipg
|= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN
;
1091 ret_val
= e1e_rphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, ®_data
);
1095 if (duplex
== HALF_DUPLEX
)
1096 reg_data
|= GG82563_KMCR_PASS_FALSE_CARRIER
;
1098 reg_data
&= ~GG82563_KMCR_PASS_FALSE_CARRIER
;
1100 ret_val
= e1e_wphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, reg_data
);
1106 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1107 * @hw: pointer to the HW structure
1109 * Configure the KMRN interface by applying last minute quirks for
1110 * gigabit operation.
1112 static s32
e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw
*hw
)
1118 reg_data
= E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT
;
1119 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL
,
1124 /* Configure Transmit Inter-Packet Gap */
1126 tipg
&= ~E1000_TIPG_IPGT_MASK
;
1127 tipg
|= DEFAULT_TIPG_IPGT_1000_80003ES2LAN
;
1130 ret_val
= e1e_rphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, ®_data
);
1134 reg_data
&= ~GG82563_KMCR_PASS_FALSE_CARRIER
;
1135 ret_val
= e1e_wphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, reg_data
);
1141 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1142 * @hw: pointer to the HW structure
1144 * Clears the hardware counters by reading the counter registers.
1146 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw
*hw
)
1150 e1000e_clear_hw_cntrs_base(hw
);
1153 temp
= er32(PRC127
);
1154 temp
= er32(PRC255
);
1155 temp
= er32(PRC511
);
1156 temp
= er32(PRC1023
);
1157 temp
= er32(PRC1522
);
1159 temp
= er32(PTC127
);
1160 temp
= er32(PTC255
);
1161 temp
= er32(PTC511
);
1162 temp
= er32(PTC1023
);
1163 temp
= er32(PTC1522
);
1165 temp
= er32(ALGNERRC
);
1166 temp
= er32(RXERRC
);
1168 temp
= er32(CEXTERR
);
1170 temp
= er32(TSCTFC
);
1172 temp
= er32(MGTPRC
);
1173 temp
= er32(MGTPDC
);
1174 temp
= er32(MGTPTC
);
1177 temp
= er32(ICRXOC
);
1179 temp
= er32(ICRXPTC
);
1180 temp
= er32(ICRXATC
);
1181 temp
= er32(ICTXPTC
);
1182 temp
= er32(ICTXATC
);
1183 temp
= er32(ICTXQEC
);
1184 temp
= er32(ICTXQMTC
);
1185 temp
= er32(ICRXDMTC
);
1188 static struct e1000_mac_operations es2_mac_ops
= {
1189 .mng_mode_enab
= E1000_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
,
1190 /* check_for_link dependent on media type */
1191 .cleanup_led
= e1000e_cleanup_led_generic
,
1192 .clear_hw_cntrs
= e1000_clear_hw_cntrs_80003es2lan
,
1193 .get_bus_info
= e1000e_get_bus_info_pcie
,
1194 .get_link_up_info
= e1000_get_link_up_info_80003es2lan
,
1195 .led_on
= e1000e_led_on_generic
,
1196 .led_off
= e1000e_led_off_generic
,
1197 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
1198 .reset_hw
= e1000_reset_hw_80003es2lan
,
1199 .init_hw
= e1000_init_hw_80003es2lan
,
1200 .setup_link
= e1000e_setup_link
,
1201 /* setup_physical_interface dependent on media type */
1204 static struct e1000_phy_operations es2_phy_ops
= {
1205 .acquire_phy
= e1000_acquire_phy_80003es2lan
,
1206 .check_reset_block
= e1000e_check_reset_block_generic
,
1207 .commit_phy
= e1000e_phy_sw_reset
,
1208 .force_speed_duplex
= e1000_phy_force_speed_duplex_80003es2lan
,
1209 .get_cfg_done
= e1000_get_cfg_done_80003es2lan
,
1210 .get_cable_length
= e1000_get_cable_length_80003es2lan
,
1211 .get_phy_info
= e1000e_get_phy_info_m88
,
1212 .read_phy_reg
= e1000_read_phy_reg_gg82563_80003es2lan
,
1213 .release_phy
= e1000_release_phy_80003es2lan
,
1214 .reset_phy
= e1000e_phy_hw_reset_generic
,
1215 .set_d0_lplu_state
= NULL
,
1216 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1217 .write_phy_reg
= e1000_write_phy_reg_gg82563_80003es2lan
,
1220 static struct e1000_nvm_operations es2_nvm_ops
= {
1221 .acquire_nvm
= e1000_acquire_nvm_80003es2lan
,
1222 .read_nvm
= e1000e_read_nvm_eerd
,
1223 .release_nvm
= e1000_release_nvm_80003es2lan
,
1224 .update_nvm
= e1000e_update_nvm_checksum_generic
,
1225 .valid_led_default
= e1000e_valid_led_default
,
1226 .validate_nvm
= e1000e_validate_nvm_checksum_generic
,
1227 .write_nvm
= e1000_write_nvm_80003es2lan
,
1230 struct e1000_info e1000_es2_info
= {
1231 .mac
= e1000_80003es2lan
,
1232 .flags
= FLAG_HAS_HW_VLAN_FILTER
1233 | FLAG_HAS_JUMBO_FRAMES
1234 | FLAG_HAS_STATS_PTC_PRC
1236 | FLAG_APME_IN_CTRL3
1237 | FLAG_RX_CSUM_ENABLED
1238 | FLAG_HAS_CTRLEXT_ON_LOAD
1239 | FLAG_HAS_STATS_ICR_ICT
1240 | FLAG_RX_NEEDS_RESTART
/* errata */
1241 | FLAG_TARC_SET_BIT_ZERO
/* errata */
1242 | FLAG_APME_CHECK_PORT_B
1243 | FLAG_DISABLE_FC_PAUSE_TIME
/* errata */
1244 | FLAG_TIPG_MEDIUM_FOR_80003ESLAN
,
1246 .get_variants
= e1000_get_variants_80003es2lan
,
1247 .mac_ops
= &es2_mac_ops
,
1248 .phy_ops
= &es2_phy_ops
,
1249 .nvm_ops
= &es2_nvm_ops
,