drivers/pci/hotplug/shpchp.h

   1 /*
   2  * Standard Hot Plug Controller Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29 #ifndef _SHPCHP_H
  30 #define _SHPCHP_H
  31
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/delay.h>
  35 #include <linux/sched.h>        /* signal_pending(), struct timer_list */
  36 #include <linux/mutex.h>
  37
  38 #include "pci_hotplug.h"
  39
  40 #if !defined(MODULE)
  41         #define MY_NAME "shpchp"
  42 #else
  43         #define MY_NAME THIS_MODULE->name
  44 #endif
  45
  46 extern int shpchp_poll_mode;
  47 extern int shpchp_poll_time;
  48 extern int shpchp_debug;
  49
  50 /*#define dbg(format, arg...) do { if (shpchp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/
  51 #define dbg(format, arg...) do { if (shpchp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
  52 #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
  53 #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
  54 #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
  55
  56 #define SLOT_NAME_SIZE 10
  57 struct slot {
  58         u8 bus;
  59         u8 device;
  60         u16 status;
  61         u32 number;
  62         u8 is_a_board;
  63         u8 state;
  64         u8 presence_save;
  65         u8 pwr_save;
  66         struct timer_list task_event;
  67         u8 hp_slot;
  68         struct controller *ctrl;
  69         struct hpc_ops *hpc_ops;
  70         struct hotplug_slot *hotplug_slot;
  71         struct list_head        slot_list;
  72         char name[SLOT_NAME_SIZE];
  73 };
  74
  75 struct event_info {
  76         u32 event_type;
  77         u8 hp_slot;
  78 };
  79
  80 struct controller {
  81         struct list_head ctrl_list;
  82         struct mutex crit_sect;         /* critical section mutex */
  83         struct mutex cmd_lock;          /* command lock */
  84         struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */
  85         int num_slots;                  /* Number of slots on ctlr */
  86         int slot_num_inc;               /* 1 or -1 */
  87         struct pci_dev *pci_dev;
  88         struct event_info event_queue[10];
  89         struct list_head slot_list;
  90         struct hpc_ops *hpc_ops;
  91         wait_queue_head_t queue;        /* sleep & wake process */
  92         u8 next_event;
  93         u8 bus;
  94         u8 device;
  95         u8 function;
  96         u8 slot_device_offset;
  97         u8 add_support;
  98         u32 pcix_misc2_reg;     /* for amd pogo errata */
  99         enum pci_bus_speed speed;
 100         u32 first_slot;         /* First physical slot number */
 101         u8 slot_bus;            /* Bus where the slots handled by this controller sit */
 102         u32 cap_offset;
 103         unsigned long mmio_base;
 104         unsigned long mmio_size;
 105         volatile int cmd_busy;
 106 };
 107
 108 struct hotplug_params {
 109         u8      cache_line_size;
 110         u8      latency_timer;
 111         u8      enable_serr;
 112         u8      enable_perr;
 113 };
 114
 115 /* Define AMD SHPC ID  */
 116 #define PCI_DEVICE_ID_AMD_GOLAM_7450    0x7450
 117 #define PCI_DEVICE_ID_AMD_POGO_7458     0x7458
 118
 119 /* AMD PCIX bridge registers */
 120
 121 #define PCIX_MEM_BASE_LIMIT_OFFSET      0x1C
 122 #define PCIX_MISCII_OFFSET              0x48
 123 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET  0x80
 124
 125 /* AMD PCIX_MISCII masks and offsets */
 126 #define PERRNONFATALENABLE_MASK         0x00040000
 127 #define PERRFATALENABLE_MASK            0x00080000
 128 #define PERRFLOODENABLE_MASK            0x00100000
 129 #define SERRNONFATALENABLE_MASK         0x00200000
 130 #define SERRFATALENABLE_MASK            0x00400000
 131
 132 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
 133 #define PERR_OBSERVED_MASK              0x00000001
 134
 135 /* AMD PCIX_MEM_BASE_LIMIT masks */
 136 #define RSE_MASK                        0x40000000
 137
 138 #define INT_BUTTON_IGNORE               0
 139 #define INT_PRESENCE_ON                 1
 140 #define INT_PRESENCE_OFF                2
 141 #define INT_SWITCH_CLOSE                3
 142 #define INT_SWITCH_OPEN                 4
 143 #define INT_POWER_FAULT                 5
 144 #define INT_POWER_FAULT_CLEAR           6
 145 #define INT_BUTTON_PRESS                7
 146 #define INT_BUTTON_RELEASE              8
 147 #define INT_BUTTON_CANCEL               9
 148
 149 #define STATIC_STATE                    0
 150 #define BLINKINGON_STATE                1
 151 #define BLINKINGOFF_STATE               2
 152 #define POWERON_STATE                   3
 153 #define POWEROFF_STATE                  4
 154
 155 #define PCI_TO_PCI_BRIDGE_CLASS         0x00060400
 156
 157 /* Error messages */
 158 #define INTERLOCK_OPEN                  0x00000002
 159 #define ADD_NOT_SUPPORTED               0x00000003
 160 #define CARD_FUNCTIONING                0x00000005
 161 #define ADAPTER_NOT_SAME                0x00000006
 162 #define NO_ADAPTER_PRESENT              0x00000009
 163 #define NOT_ENOUGH_RESOURCES            0x0000000B
 164 #define DEVICE_TYPE_NOT_SUPPORTED       0x0000000C
 165 #define WRONG_BUS_FREQUENCY             0x0000000D
 166 #define POWER_FAILURE                   0x0000000E
 167
 168 #define REMOVE_NOT_SUPPORTED            0x00000003
 169
 170 #define DISABLE_CARD                    1
 171
 172 /*
 173  * error Messages
 174  */
 175 #define msg_initialization_err  "Initialization failure, error=%d\n"
 176 #define msg_button_on           "PCI slot #%d - powering on due to button press.\n"
 177 #define msg_button_off          "PCI slot #%d - powering off due to button press.\n"
 178 #define msg_button_cancel       "PCI slot #%d - action canceled due to button press.\n"
 179
 180 /* sysfs functions for the hotplug controller info */
 181 extern void shpchp_create_ctrl_files    (struct controller *ctrl);
 182
 183 /* controller functions */
 184 extern int      shpchp_event_start_thread(void);
 185 extern void     shpchp_event_stop_thread(void);
 186 extern int      shpchp_enable_slot(struct slot *slot);
 187 extern int      shpchp_disable_slot(struct slot *slot);
 188
 189 extern u8       shpchp_handle_attention_button(u8 hp_slot, void *inst_id);
 190 extern u8       shpchp_handle_switch_change(u8 hp_slot, void *inst_id);
 191 extern u8       shpchp_handle_presence_change(u8 hp_slot, void *inst_id);
 192 extern u8       shpchp_handle_power_fault(u8 hp_slot, void *inst_id);
 193
 194 /* pci functions */
 195 extern int      shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num);
 196 extern int      shpchp_configure_device(struct slot *p_slot);
 197 extern int      shpchp_unconfigure_device(struct slot *p_slot);
 198 extern void     get_hp_hw_control_from_firmware(struct pci_dev *dev);
 199 extern void     get_hp_params_from_firmware(struct pci_dev *dev,
 200                 struct hotplug_params *hpp);
 201 extern int      shpchprm_get_physical_slot_number(struct controller *ctrl,
 202                 u32 *sun, u8 busnum, u8 devnum);
 203 extern void     shpchp_remove_ctrl_files(struct controller *ctrl);
 204
 205
 206 /* Global variables */
 207 extern struct list_head shpchp_ctrl_list;
 208
 209 struct ctrl_reg {
 210         volatile u32 base_offset;
 211         volatile u32 slot_avail1;
 212         volatile u32 slot_avail2;
 213         volatile u32 slot_config;
 214         volatile u16 sec_bus_config;
 215         volatile u8  msi_ctrl;
 216         volatile u8  prog_interface;
 217         volatile u16 cmd;
 218         volatile u16 cmd_status;
 219         volatile u32 intr_loc;
 220         volatile u32 serr_loc;
 221         volatile u32 serr_intr_enable;
 222         volatile u32 slot1;
 223         volatile u32 slot2;
 224         volatile u32 slot3;
 225         volatile u32 slot4;
 226         volatile u32 slot5;
 227         volatile u32 slot6;
 228         volatile u32 slot7;
 229         volatile u32 slot8;
 230         volatile u32 slot9;
 231         volatile u32 slot10;
 232         volatile u32 slot11;
 233         volatile u32 slot12;
 234 } __attribute__ ((packed));
 235
 236 /* offsets to the controller registers based on the above structure layout */
 237 enum ctrl_offsets {
 238         BASE_OFFSET =   offsetof(struct ctrl_reg, base_offset),
 239         SLOT_AVAIL1 =   offsetof(struct ctrl_reg, slot_avail1),
 240         SLOT_AVAIL2     =       offsetof(struct ctrl_reg, slot_avail2),
 241         SLOT_CONFIG =   offsetof(struct ctrl_reg, slot_config),
 242         SEC_BUS_CONFIG =        offsetof(struct ctrl_reg, sec_bus_config),
 243         MSI_CTRL        =       offsetof(struct ctrl_reg, msi_ctrl),
 244         PROG_INTERFACE =        offsetof(struct ctrl_reg, prog_interface),
 245         CMD             =       offsetof(struct ctrl_reg, cmd),
 246         CMD_STATUS      =       offsetof(struct ctrl_reg, cmd_status),
 247         INTR_LOC        =       offsetof(struct ctrl_reg, intr_loc),
 248         SERR_LOC        =       offsetof(struct ctrl_reg, serr_loc),
 249         SERR_INTR_ENABLE =      offsetof(struct ctrl_reg, serr_intr_enable),
 250         SLOT1 =         offsetof(struct ctrl_reg, slot1),
 251         SLOT2 =         offsetof(struct ctrl_reg, slot2),
 252         SLOT3 =         offsetof(struct ctrl_reg, slot3),
 253         SLOT4 =         offsetof(struct ctrl_reg, slot4),
 254         SLOT5 =         offsetof(struct ctrl_reg, slot5),
 255         SLOT6 =         offsetof(struct ctrl_reg, slot6),
 256         SLOT7 =         offsetof(struct ctrl_reg, slot7),
 257         SLOT8 =         offsetof(struct ctrl_reg, slot8),
 258         SLOT9 =         offsetof(struct ctrl_reg, slot9),
 259         SLOT10 =        offsetof(struct ctrl_reg, slot10),
 260         SLOT11 =        offsetof(struct ctrl_reg, slot11),
 261         SLOT12 =        offsetof(struct ctrl_reg, slot12),
 262 };
 263 typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id);
 264 struct php_ctlr_state_s {
 265         struct php_ctlr_state_s *pnext;
 266         struct pci_dev *pci_dev;
 267         unsigned int irq;
 268         unsigned long flags;    /* spinlock's */
 269         u32 slot_device_offset;
 270         u32 num_slots;
 271         struct timer_list       int_poll_timer; /* Added for poll event */
 272         php_intr_callback_t attention_button_callback;
 273         php_intr_callback_t switch_change_callback;
 274         php_intr_callback_t presence_change_callback;
 275         php_intr_callback_t power_fault_callback;
 276         void *callback_instance_id;
 277         void __iomem *creg;                     /* Ptr to controller register space */
 278 };
 279 /* Inline functions */
 280
 281
 282 /* Inline functions to check the sanity of a pointer that is passed to us */
 283 static inline int slot_paranoia_check (struct slot *slot, const char *function)
 284 {
 285         if (!slot) {
 286                 dbg("%s - slot == NULL", function);
 287                 return -1;
 288         }
 289         if (!slot->hotplug_slot) {
 290                 dbg("%s - slot->hotplug_slot == NULL!", function);
 291                 return -1;
 292         }
 293         return 0;
 294 }
 295
 296 static inline struct slot *get_slot (struct hotplug_slot *hotplug_slot, const char *function)
 297 {
 298         struct slot *slot;
 299
 300         if (!hotplug_slot) {
 301                 dbg("%s - hotplug_slot == NULL\n", function);
 302                 return NULL;
 303         }
 304
 305         slot = (struct slot *)hotplug_slot->private;
 306         if (slot_paranoia_check (slot, function))
 307                 return NULL;
 308         return slot;
 309 }
 310
 311 static inline struct slot *shpchp_find_slot (struct controller *ctrl, u8 device)
 312 {
 313         struct slot *slot;
 314
 315         if (!ctrl)
 316                 return NULL;
 317
 318         list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
 319                 if (slot->device == device)
 320                         return slot;
 321         }
 322
 323         err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device);
 324
 325         return NULL;
 326 }
 327
 328 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
 329 {
 330         u32 pcix_misc2_temp;
 331
 332         /* save MiscII register */
 333         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
 334
 335         p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
 336
 337         /* clear SERR/PERR enable bits */
 338         pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
 339         pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
 340         pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
 341         pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
 342         pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
 343         pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
 344 }
 345
 346 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
 347 {
 348         u32 pcix_misc2_temp;
 349         u32 pcix_bridge_errors_reg;
 350         u32 pcix_mem_base_reg;
 351         u8  perr_set;
 352         u8  rse_set;
 353
 354         /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
 355         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
 356         perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
 357         if (perr_set) {
 358                 dbg ("%s  W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set);
 359
 360                 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
 361         }
 362
 363         /* write-one-to-clear Memory_Base_Limit[ RSE ] */
 364         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
 365         rse_set = pcix_mem_base_reg & RSE_MASK;
 366         if (rse_set) {
 367                 dbg ("%s  W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ );
 368
 369                 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
 370         }
 371         /* restore MiscII register */
 372         pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
 373
 374         if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
 375                 pcix_misc2_temp |= SERRFATALENABLE_MASK;
 376         else
 377                 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
 378
 379         if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
 380                 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
 381         else
 382                 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
 383
 384         if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
 385                 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
 386         else
 387                 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
 388
 389         if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
 390                 pcix_misc2_temp |= PERRFATALENABLE_MASK;
 391         else
 392                 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
 393
 394         if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
 395                 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
 396         else
 397                 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
 398         pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
 399 }
 400
 401 enum php_ctlr_type {
 402         PCI,
 403         ISA,
 404         ACPI
 405 };
 406
 407 int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
 408
 409 int shpc_get_ctlr_slot_config( struct controller *ctrl,
 410                 int *num_ctlr_slots,
 411                 int *first_device_num,
 412                 int *physical_slot_num,
 413                 int *updown,
 414                 int *flags);
 415
 416 struct hpc_ops {
 417         int     (*power_on_slot )               (struct slot *slot);
 418         int     (*slot_enable )                 (struct slot *slot);
 419         int     (*slot_disable )                (struct slot *slot);
 420         int     (*set_bus_speed_mode)   (struct slot *slot, enum pci_bus_speed speed);
 421         int     (*get_power_status)             (struct slot *slot, u8 *status);
 422         int     (*get_attention_status) (struct slot *slot, u8 *status);
 423         int     (*set_attention_status) (struct slot *slot, u8 status);
 424         int     (*get_latch_status)             (struct slot *slot, u8 *status);
 425         int     (*get_adapter_status)   (struct slot *slot, u8 *status);
 426
 427         int     (*get_max_bus_speed)    (struct slot *slot, enum pci_bus_speed *speed);
 428         int     (*get_cur_bus_speed)    (struct slot *slot, enum pci_bus_speed *speed);
 429         int     (*get_adapter_speed)    (struct slot *slot, enum pci_bus_speed *speed);
 430         int     (*get_mode1_ECC_cap)    (struct slot *slot, u8 *mode);
 431         int     (*get_prog_int)                 (struct slot *slot, u8 *prog_int);
 432
 433         int     (*query_power_fault)    (struct slot *slot);
 434         void    (*green_led_on)         (struct slot *slot);
 435         void    (*green_led_off)        (struct slot *slot);
 436         void    (*green_led_blink)      (struct slot *slot);
 437         void    (*release_ctlr)         (struct controller *ctrl);
 438         int (*check_cmd_status)         (struct controller *ctrl);
 439 };
 440
 441 #endif                          /* _SHPCHP_H */