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mv643xx_eth: allow multiple RX queues
[linux-2.6/libata-dev.git] / drivers / net / mv643xx_eth.c
blob3c8591853999ae87232f85cb5624f7c3d74bddde
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/in.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
53 #include <asm/io.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
56
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.0";
59
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
63
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66 #else
67 #define MAX_DESCS_PER_SKB 1
68 #endif
69
70 /*
71 * Registers shared between all ports.
72 */
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
80
81 /*
82 * Per-port registers.
83 */
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
94 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
96 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
97 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
98 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
99 #define INT_RX 0x0007fbfc
100 #define INT_EXT 0x00000002
101 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
102 #define INT_EXT_LINK 0x00100000
103 #define INT_EXT_PHY 0x00010000
104 #define INT_EXT_TX_ERROR_0 0x00000100
105 #define INT_EXT_TX_0 0x00000001
106 #define INT_EXT_TX 0x00000101
107 #define INT_MASK(p) (0x0468 + ((p) << 10))
108 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
109 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
110 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
111 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
112 #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
113 #define TXQ_BW_TOKENS(p) (0x0700 + ((p) << 10))
114 #define TXQ_BW_CONF(p) (0x0704 + ((p) << 10))
115 #define TXQ_BW_WRR_CONF(p) (0x0708 + ((p) << 10))
116 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
117 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
118 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
119 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
120
121
122 /*
123 * SDMA configuration register.
124 */
125 #define RX_BURST_SIZE_4_64BIT (2 << 1)
126 #define BLM_RX_NO_SWAP (1 << 4)
127 #define BLM_TX_NO_SWAP (1 << 5)
128 #define TX_BURST_SIZE_4_64BIT (2 << 22)
129
130 #if defined(__BIG_ENDIAN)
131 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
132 RX_BURST_SIZE_4_64BIT | \
133 TX_BURST_SIZE_4_64BIT
134 #elif defined(__LITTLE_ENDIAN)
135 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
136 RX_BURST_SIZE_4_64BIT | \
137 BLM_RX_NO_SWAP | \
138 BLM_TX_NO_SWAP | \
139 TX_BURST_SIZE_4_64BIT
140 #else
141 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
142 #endif
143
144
145 /*
146 * Port serial control register.
147 */
148 #define SET_MII_SPEED_TO_100 (1 << 24)
149 #define SET_GMII_SPEED_TO_1000 (1 << 23)
150 #define SET_FULL_DUPLEX_MODE (1 << 21)
151 #define MAX_RX_PACKET_1522BYTE (1 << 17)
152 #define MAX_RX_PACKET_9700BYTE (5 << 17)
153 #define MAX_RX_PACKET_MASK (7 << 17)
154 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
155 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
156 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
157 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
158 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
159 #define FORCE_LINK_PASS (1 << 1)
160 #define SERIAL_PORT_ENABLE (1 << 0)
161
162 #define DEFAULT_RX_QUEUE_SIZE 400
163 #define DEFAULT_TX_QUEUE_SIZE 800
164
165
166 /*
167 * RX/TX descriptors.
168 */
169 #if defined(__BIG_ENDIAN)
170 struct rx_desc {
171 u16 byte_cnt; /* Descriptor buffer byte count */
172 u16 buf_size; /* Buffer size */
173 u32 cmd_sts; /* Descriptor command status */
174 u32 next_desc_ptr; /* Next descriptor pointer */
175 u32 buf_ptr; /* Descriptor buffer pointer */
176 };
177
178 struct tx_desc {
179 u16 byte_cnt; /* buffer byte count */
180 u16 l4i_chk; /* CPU provided TCP checksum */
181 u32 cmd_sts; /* Command/status field */
182 u32 next_desc_ptr; /* Pointer to next descriptor */
183 u32 buf_ptr; /* pointer to buffer for this descriptor*/
184 };
185 #elif defined(__LITTLE_ENDIAN)
186 struct rx_desc {
187 u32 cmd_sts; /* Descriptor command status */
188 u16 buf_size; /* Buffer size */
189 u16 byte_cnt; /* Descriptor buffer byte count */
190 u32 buf_ptr; /* Descriptor buffer pointer */
191 u32 next_desc_ptr; /* Next descriptor pointer */
192 };
193
194 struct tx_desc {
195 u32 cmd_sts; /* Command/status field */
196 u16 l4i_chk; /* CPU provided TCP checksum */
197 u16 byte_cnt; /* buffer byte count */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199 u32 next_desc_ptr; /* Pointer to next descriptor */
200 };
201 #else
202 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
203 #endif
204
205 /* RX & TX descriptor command */
206 #define BUFFER_OWNED_BY_DMA 0x80000000
207
208 /* RX & TX descriptor status */
209 #define ERROR_SUMMARY 0x00000001
210
211 /* RX descriptor status */
212 #define LAYER_4_CHECKSUM_OK 0x40000000
213 #define RX_ENABLE_INTERRUPT 0x20000000
214 #define RX_FIRST_DESC 0x08000000
215 #define RX_LAST_DESC 0x04000000
216
217 /* TX descriptor command */
218 #define TX_ENABLE_INTERRUPT 0x00800000
219 #define GEN_CRC 0x00400000
220 #define TX_FIRST_DESC 0x00200000
221 #define TX_LAST_DESC 0x00100000
222 #define ZERO_PADDING 0x00080000
223 #define GEN_IP_V4_CHECKSUM 0x00040000
224 #define GEN_TCP_UDP_CHECKSUM 0x00020000
225 #define UDP_FRAME 0x00010000
226
227 #define TX_IHL_SHIFT 11
228
229
230 /* global *******************************************************************/
231 struct mv643xx_eth_shared_private {
232 /*
233 * Ethernet controller base address.
234 */
235 void __iomem *base;
236
237 /*
238 * Protects access to SMI_REG, which is shared between ports.
239 */
240 spinlock_t phy_lock;
241
242 /*
243 * Per-port MBUS window access register value.
244 */
245 u32 win_protect;
246
247 /*
248 * Hardware-specific parameters.
249 */
250 unsigned int t_clk;
251 };
252
253
254 /* per-port *****************************************************************/
255 struct mib_counters {
256 u64 good_octets_received;
257 u32 bad_octets_received;
258 u32 internal_mac_transmit_err;
259 u32 good_frames_received;
260 u32 bad_frames_received;
261 u32 broadcast_frames_received;
262 u32 multicast_frames_received;
263 u32 frames_64_octets;
264 u32 frames_65_to_127_octets;
265 u32 frames_128_to_255_octets;
266 u32 frames_256_to_511_octets;
267 u32 frames_512_to_1023_octets;
268 u32 frames_1024_to_max_octets;
269 u64 good_octets_sent;
270 u32 good_frames_sent;
271 u32 excessive_collision;
272 u32 multicast_frames_sent;
273 u32 broadcast_frames_sent;
274 u32 unrec_mac_control_received;
275 u32 fc_sent;
276 u32 good_fc_received;
277 u32 bad_fc_received;
278 u32 undersize_received;
279 u32 fragments_received;
280 u32 oversize_received;
281 u32 jabber_received;
282 u32 mac_receive_error;
283 u32 bad_crc_event;
284 u32 collision;
285 u32 late_collision;
286 };
287
288 struct rx_queue {
289 int index;
290
291 int rx_ring_size;
292
293 int rx_desc_count;
294 int rx_curr_desc;
295 int rx_used_desc;
296
297 struct rx_desc *rx_desc_area;
298 dma_addr_t rx_desc_dma;
299 int rx_desc_area_size;
300 struct sk_buff **rx_skb;
301
302 struct timer_list rx_oom;
303 };
304
305 struct tx_queue {
306 int tx_ring_size;
307
308 int tx_desc_count;
309 int tx_curr_desc;
310 int tx_used_desc;
311
312 struct tx_desc *tx_desc_area;
313 dma_addr_t tx_desc_dma;
314 int tx_desc_area_size;
315 struct sk_buff **tx_skb;
316 };
317
318 struct mv643xx_eth_private {
319 struct mv643xx_eth_shared_private *shared;
320 int port_num;
321
322 struct net_device *dev;
323
324 struct mv643xx_eth_shared_private *shared_smi;
325 int phy_addr;
326
327 spinlock_t lock;
328
329 struct mib_counters mib_counters;
330 struct work_struct tx_timeout_task;
331 struct mii_if_info mii;
332
333 /*
334 * RX state.
335 */
336 int default_rx_ring_size;
337 unsigned long rx_desc_sram_addr;
338 int rx_desc_sram_size;
339 u8 rxq_mask;
340 int rxq_primary;
341 struct napi_struct napi;
342 struct rx_queue rxq[8];
343
344 /*
345 * TX state.
346 */
347 int default_tx_ring_size;
348 unsigned long tx_desc_sram_addr;
349 int tx_desc_sram_size;
350 struct tx_queue txq[1];
351 #ifdef MV643XX_ETH_TX_FAST_REFILL
352 int tx_clean_threshold;
353 #endif
354 };
355
356
357 /* port register accessors **************************************************/
358 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
359 {
360 return readl(mp->shared->base + offset);
361 }
362
363 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
364 {
365 writel(data, mp->shared->base + offset);
366 }
367
368
369 /* rxq/txq helper functions *************************************************/
370 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
371 {
372 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
373 }
374
375 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
376 {
377 return container_of(txq, struct mv643xx_eth_private, txq[0]);
378 }
379
380 static void rxq_enable(struct rx_queue *rxq)
381 {
382 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
383 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
384 }
385
386 static void rxq_disable(struct rx_queue *rxq)
387 {
388 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
389 u8 mask = 1 << rxq->index;
390
391 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
392 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
393 udelay(10);
394 }
395
396 static void txq_enable(struct tx_queue *txq)
397 {
398 struct mv643xx_eth_private *mp = txq_to_mp(txq);
399 wrl(mp, TXQ_COMMAND(mp->port_num), 1);
400 }
401
402 static void txq_disable(struct tx_queue *txq)
403 {
404 struct mv643xx_eth_private *mp = txq_to_mp(txq);
405 u8 mask = 1;
406
407 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
408 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
409 udelay(10);
410 }
411
412 static void __txq_maybe_wake(struct tx_queue *txq)
413 {
414 struct mv643xx_eth_private *mp = txq_to_mp(txq);
415
416 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
417 netif_wake_queue(mp->dev);
418 }
419
420
421 /* rx ***********************************************************************/
422 static void txq_reclaim(struct tx_queue *txq, int force);
423
424 static void rxq_refill(struct rx_queue *rxq)
425 {
426 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
427 unsigned long flags;
428
429 spin_lock_irqsave(&mp->lock, flags);
430
431 while (rxq->rx_desc_count < rxq->rx_ring_size) {
432 int skb_size;
433 struct sk_buff *skb;
434 int unaligned;
435 int rx;
436
437 /*
438 * Reserve 2+14 bytes for an ethernet header (the
439 * hardware automatically prepends 2 bytes of dummy
440 * data to each received packet), 4 bytes for a VLAN
441 * header, and 4 bytes for the trailing FCS -- 24
442 * bytes total.
443 */
444 skb_size = mp->dev->mtu + 24;
445
446 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
447 if (skb == NULL)
448 break;
449
450 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
451 if (unaligned)
452 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
453
454 rxq->rx_desc_count++;
455 rx = rxq->rx_used_desc;
456 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
457
458 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
459 skb_size, DMA_FROM_DEVICE);
460 rxq->rx_desc_area[rx].buf_size = skb_size;
461 rxq->rx_skb[rx] = skb;
462 wmb();
463 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
464 RX_ENABLE_INTERRUPT;
465 wmb();
466
467 /*
468 * The hardware automatically prepends 2 bytes of
469 * dummy data to each received packet, so that the
470 * IP header ends up 16-byte aligned.
471 */
472 skb_reserve(skb, 2);
473 }
474
475 if (rxq->rx_desc_count == 0) {
476 rxq->rx_oom.expires = jiffies + (HZ / 10);
477 add_timer(&rxq->rx_oom);
478 }
479
480 spin_unlock_irqrestore(&mp->lock, flags);
481 }
482
483 static inline void rxq_refill_timer_wrapper(unsigned long data)
484 {
485 rxq_refill((struct rx_queue *)data);
486 }
487
488 static int rxq_process(struct rx_queue *rxq, int budget)
489 {
490 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
491 struct net_device_stats *stats = &mp->dev->stats;
492 int rx;
493
494 rx = 0;
495 while (rx < budget) {
496 struct rx_desc *rx_desc;
497 unsigned int cmd_sts;
498 struct sk_buff *skb;
499 unsigned long flags;
500
501 spin_lock_irqsave(&mp->lock, flags);
502
503 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
504
505 cmd_sts = rx_desc->cmd_sts;
506 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
507 spin_unlock_irqrestore(&mp->lock, flags);
508 break;
509 }
510 rmb();
511
512 skb = rxq->rx_skb[rxq->rx_curr_desc];
513 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
514
515 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
516
517 spin_unlock_irqrestore(&mp->lock, flags);
518
519 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
520 mp->dev->mtu + 24, DMA_FROM_DEVICE);
521 rxq->rx_desc_count--;
522 rx++;
523
524 /*
525 * Update statistics.
526 *
527 * Note that the descriptor byte count includes 2 dummy
528 * bytes automatically inserted by the hardware at the
529 * start of the packet (which we don't count), and a 4
530 * byte CRC at the end of the packet (which we do count).
531 */
532 stats->rx_packets++;
533 stats->rx_bytes += rx_desc->byte_cnt - 2;
534
535 /*
536 * In case we received a packet without first / last bits
537 * on, or the error summary bit is set, the packet needs
538 * to be dropped.
539 */
540 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
541 (RX_FIRST_DESC | RX_LAST_DESC))
542 || (cmd_sts & ERROR_SUMMARY)) {
543 stats->rx_dropped++;
544
545 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
546 (RX_FIRST_DESC | RX_LAST_DESC)) {
547 if (net_ratelimit())
548 dev_printk(KERN_ERR, &mp->dev->dev,
549 "received packet spanning "
550 "multiple descriptors\n");
551 }
552
553 if (cmd_sts & ERROR_SUMMARY)
554 stats->rx_errors++;
555
556 dev_kfree_skb_irq(skb);
557 } else {
558 /*
559 * The -4 is for the CRC in the trailer of the
560 * received packet
561 */
562 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
563
564 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
565 skb->ip_summed = CHECKSUM_UNNECESSARY;
566 skb->csum = htons(
567 (cmd_sts & 0x0007fff8) >> 3);
568 }
569 skb->protocol = eth_type_trans(skb, mp->dev);
570 #ifdef MV643XX_ETH_NAPI
571 netif_receive_skb(skb);
572 #else
573 netif_rx(skb);
574 #endif
575 }
576
577 mp->dev->last_rx = jiffies;
578 }
579
580 rxq_refill(rxq);
581
582 return rx;
583 }
584
585 #ifdef MV643XX_ETH_NAPI
586 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
587 {
588 struct mv643xx_eth_private *mp;
589 int rx;
590 int i;
591
592 mp = container_of(napi, struct mv643xx_eth_private, napi);
593
594 #ifdef MV643XX_ETH_TX_FAST_REFILL
595 if (++mp->tx_clean_threshold > 5) {
596 txq_reclaim(mp->txq, 0);
597 mp->tx_clean_threshold = 0;
598 }
599 #endif
600
601 rx = 0;
602 for (i = 7; rx < budget && i >= 0; i--)
603 if (mp->rxq_mask & (1 << i))
604 rx += rxq_process(mp->rxq + i, budget - rx);
605
606 if (rx < budget) {
607 netif_rx_complete(mp->dev, napi);
608 wrl(mp, INT_CAUSE(mp->port_num), 0);
609 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
610 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
611 }
612
613 return rx;
614 }
615 #endif
616
617
618 /* tx ***********************************************************************/
619 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
620 {
621 int frag;
622
623 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
624 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
625 if (fragp->size <= 8 && fragp->page_offset & 7)
626 return 1;
627 }
628
629 return 0;
630 }
631
632 static int txq_alloc_desc_index(struct tx_queue *txq)
633 {
634 int tx_desc_curr;
635
636 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
637
638 tx_desc_curr = txq->tx_curr_desc;
639 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
640
641 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
642
643 return tx_desc_curr;
644 }
645
646 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
647 {
648 int nr_frags = skb_shinfo(skb)->nr_frags;
649 int frag;
650
651 for (frag = 0; frag < nr_frags; frag++) {
652 skb_frag_t *this_frag;
653 int tx_index;
654 struct tx_desc *desc;
655
656 this_frag = &skb_shinfo(skb)->frags[frag];
657 tx_index = txq_alloc_desc_index(txq);
658 desc = &txq->tx_desc_area[tx_index];
659
660 /*
661 * The last fragment will generate an interrupt
662 * which will free the skb on TX completion.
663 */
664 if (frag == nr_frags - 1) {
665 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
666 ZERO_PADDING | TX_LAST_DESC |
667 TX_ENABLE_INTERRUPT;
668 txq->tx_skb[tx_index] = skb;
669 } else {
670 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
671 txq->tx_skb[tx_index] = NULL;
672 }
673
674 desc->l4i_chk = 0;
675 desc->byte_cnt = this_frag->size;
676 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
677 this_frag->page_offset,
678 this_frag->size,
679 DMA_TO_DEVICE);
680 }
681 }
682
683 static inline __be16 sum16_as_be(__sum16 sum)
684 {
685 return (__force __be16)sum;
686 }
687
688 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
689 {
690 int nr_frags = skb_shinfo(skb)->nr_frags;
691 int tx_index;
692 struct tx_desc *desc;
693 u32 cmd_sts;
694 int length;
695
696 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
697
698 tx_index = txq_alloc_desc_index(txq);
699 desc = &txq->tx_desc_area[tx_index];
700
701 if (nr_frags) {
702 txq_submit_frag_skb(txq, skb);
703
704 length = skb_headlen(skb);
705 txq->tx_skb[tx_index] = NULL;
706 } else {
707 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
708 length = skb->len;
709 txq->tx_skb[tx_index] = skb;
710 }
711
712 desc->byte_cnt = length;
713 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
714
715 if (skb->ip_summed == CHECKSUM_PARTIAL) {
716 BUG_ON(skb->protocol != htons(ETH_P_IP));
717
718 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
719 GEN_IP_V4_CHECKSUM |
720 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
721
722 switch (ip_hdr(skb)->protocol) {
723 case IPPROTO_UDP:
724 cmd_sts |= UDP_FRAME;
725 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
726 break;
727 case IPPROTO_TCP:
728 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
729 break;
730 default:
731 BUG();
732 }
733 } else {
734 /* Errata BTS #50, IHL must be 5 if no HW checksum */
735 cmd_sts |= 5 << TX_IHL_SHIFT;
736 desc->l4i_chk = 0;
737 }
738
739 /* ensure all other descriptors are written before first cmd_sts */
740 wmb();
741 desc->cmd_sts = cmd_sts;
742
743 /* ensure all descriptors are written before poking hardware */
744 wmb();
745 txq_enable(txq);
746
747 txq->tx_desc_count += nr_frags + 1;
748 }
749
750 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
751 {
752 struct mv643xx_eth_private *mp = netdev_priv(dev);
753 struct net_device_stats *stats = &dev->stats;
754 struct tx_queue *txq;
755 unsigned long flags;
756
757 BUG_ON(netif_queue_stopped(dev));
758
759 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
760 stats->tx_dropped++;
761 dev_printk(KERN_DEBUG, &dev->dev,
762 "failed to linearize skb with tiny "
763 "unaligned fragment\n");
764 return NETDEV_TX_BUSY;
765 }
766
767 spin_lock_irqsave(&mp->lock, flags);
768
769 txq = mp->txq;
770
771 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
772 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
773 netif_stop_queue(dev);
774 spin_unlock_irqrestore(&mp->lock, flags);
775 return NETDEV_TX_BUSY;
776 }
777
778 txq_submit_skb(txq, skb);
779 stats->tx_bytes += skb->len;
780 stats->tx_packets++;
781 dev->trans_start = jiffies;
782
783 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB)
784 netif_stop_queue(dev);
785
786 spin_unlock_irqrestore(&mp->lock, flags);
787
788 return NETDEV_TX_OK;
789 }
790
791
792 /* tx rate control **********************************************************/
793 /*
794 * Set total maximum TX rate (shared by all TX queues for this port)
795 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
796 */
797 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
798 {
799 int token_rate;
800 int mtu;
801 int bucket_size;
802
803 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
804 if (token_rate > 1023)
805 token_rate = 1023;
806
807 mtu = (mp->dev->mtu + 255) >> 8;
808 if (mtu > 63)
809 mtu = 63;
810
811 bucket_size = (burst + 255) >> 8;
812 if (bucket_size > 65535)
813 bucket_size = 65535;
814
815 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
816 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
817 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
818 }
819
820 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
821 {
822 struct mv643xx_eth_private *mp = txq_to_mp(txq);
823 int token_rate;
824 int bucket_size;
825
826 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
827 if (token_rate > 1023)
828 token_rate = 1023;
829
830 bucket_size = (burst + 255) >> 8;
831 if (bucket_size > 65535)
832 bucket_size = 65535;
833
834 wrl(mp, TXQ_BW_TOKENS(mp->port_num), token_rate << 14);
835 wrl(mp, TXQ_BW_CONF(mp->port_num),
836 (bucket_size << 10) | token_rate);
837 }
838
839 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
840 {
841 struct mv643xx_eth_private *mp = txq_to_mp(txq);
842 int off;
843 u32 val;
844
845 /*
846 * Turn on fixed priority mode.
847 */
848 off = TXQ_FIX_PRIO_CONF(mp->port_num);
849
850 val = rdl(mp, off);
851 val |= 1;
852 wrl(mp, off, val);
853 }
854
855 static void txq_set_wrr(struct tx_queue *txq, int weight)
856 {
857 struct mv643xx_eth_private *mp = txq_to_mp(txq);
858 int off;
859 u32 val;
860
861 /*
862 * Turn off fixed priority mode.
863 */
864 off = TXQ_FIX_PRIO_CONF(mp->port_num);
865
866 val = rdl(mp, off);
867 val &= ~1;
868 wrl(mp, off, val);
869
870 /*
871 * Configure WRR weight for this queue.
872 */
873 off = TXQ_BW_WRR_CONF(mp->port_num);
874
875 val = rdl(mp, off);
876 val = (val & ~0xff) | (weight & 0xff);
877 wrl(mp, off, val);
878 }
879
880
881 /* mii management interface *************************************************/
882 #define SMI_BUSY 0x10000000
883 #define SMI_READ_VALID 0x08000000
884 #define SMI_OPCODE_READ 0x04000000
885 #define SMI_OPCODE_WRITE 0x00000000
886
887 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
888 unsigned int reg, unsigned int *value)
889 {
890 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
891 unsigned long flags;
892 int i;
893
894 /* the SMI register is a shared resource */
895 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
896
897 /* wait for the SMI register to become available */
898 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
899 if (i == 1000) {
900 printk("%s: PHY busy timeout\n", mp->dev->name);
901 goto out;
902 }
903 udelay(10);
904 }
905
906 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
907
908 /* now wait for the data to be valid */
909 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
910 if (i == 1000) {
911 printk("%s: PHY read timeout\n", mp->dev->name);
912 goto out;
913 }
914 udelay(10);
915 }
916
917 *value = readl(smi_reg) & 0xffff;
918 out:
919 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
920 }
921
922 static void smi_reg_write(struct mv643xx_eth_private *mp,
923 unsigned int addr,
924 unsigned int reg, unsigned int value)
925 {
926 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
927 unsigned long flags;
928 int i;
929
930 /* the SMI register is a shared resource */
931 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
932
933 /* wait for the SMI register to become available */
934 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
935 if (i == 1000) {
936 printk("%s: PHY busy timeout\n", mp->dev->name);
937 goto out;
938 }
939 udelay(10);
940 }
941
942 writel(SMI_OPCODE_WRITE | (reg << 21) |
943 (addr << 16) | (value & 0xffff), smi_reg);
944 out:
945 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
946 }
947
948
949 /* mib counters *************************************************************/
950 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
951 {
952 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
953 }
954
955 static void mib_counters_clear(struct mv643xx_eth_private *mp)
956 {
957 int i;
958
959 for (i = 0; i < 0x80; i += 4)
960 mib_read(mp, i);
961 }
962
963 static void mib_counters_update(struct mv643xx_eth_private *mp)
964 {
965 struct mib_counters *p = &mp->mib_counters;
966
967 p->good_octets_received += mib_read(mp, 0x00);
968 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
969 p->bad_octets_received += mib_read(mp, 0x08);
970 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
971 p->good_frames_received += mib_read(mp, 0x10);
972 p->bad_frames_received += mib_read(mp, 0x14);
973 p->broadcast_frames_received += mib_read(mp, 0x18);
974 p->multicast_frames_received += mib_read(mp, 0x1c);
975 p->frames_64_octets += mib_read(mp, 0x20);
976 p->frames_65_to_127_octets += mib_read(mp, 0x24);
977 p->frames_128_to_255_octets += mib_read(mp, 0x28);
978 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
979 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
980 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
981 p->good_octets_sent += mib_read(mp, 0x38);
982 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
983 p->good_frames_sent += mib_read(mp, 0x40);
984 p->excessive_collision += mib_read(mp, 0x44);
985 p->multicast_frames_sent += mib_read(mp, 0x48);
986 p->broadcast_frames_sent += mib_read(mp, 0x4c);
987 p->unrec_mac_control_received += mib_read(mp, 0x50);
988 p->fc_sent += mib_read(mp, 0x54);
989 p->good_fc_received += mib_read(mp, 0x58);
990 p->bad_fc_received += mib_read(mp, 0x5c);
991 p->undersize_received += mib_read(mp, 0x60);
992 p->fragments_received += mib_read(mp, 0x64);
993 p->oversize_received += mib_read(mp, 0x68);
994 p->jabber_received += mib_read(mp, 0x6c);
995 p->mac_receive_error += mib_read(mp, 0x70);
996 p->bad_crc_event += mib_read(mp, 0x74);
997 p->collision += mib_read(mp, 0x78);
998 p->late_collision += mib_read(mp, 0x7c);
999 }
1000
1001
1002 /* ethtool ******************************************************************/
1003 struct mv643xx_eth_stats {
1004 char stat_string[ETH_GSTRING_LEN];
1005 int sizeof_stat;
1006 int netdev_off;
1007 int mp_off;
1008 };
1009
1010 #define SSTAT(m) \
1011 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1012 offsetof(struct net_device, stats.m), -1 }
1013
1014 #define MIBSTAT(m) \
1015 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1016 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1017
1018 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1019 SSTAT(rx_packets),
1020 SSTAT(tx_packets),
1021 SSTAT(rx_bytes),
1022 SSTAT(tx_bytes),
1023 SSTAT(rx_errors),
1024 SSTAT(tx_errors),
1025 SSTAT(rx_dropped),
1026 SSTAT(tx_dropped),
1027 MIBSTAT(good_octets_received),
1028 MIBSTAT(bad_octets_received),
1029 MIBSTAT(internal_mac_transmit_err),
1030 MIBSTAT(good_frames_received),
1031 MIBSTAT(bad_frames_received),
1032 MIBSTAT(broadcast_frames_received),
1033 MIBSTAT(multicast_frames_received),
1034 MIBSTAT(frames_64_octets),
1035 MIBSTAT(frames_65_to_127_octets),
1036 MIBSTAT(frames_128_to_255_octets),
1037 MIBSTAT(frames_256_to_511_octets),
1038 MIBSTAT(frames_512_to_1023_octets),
1039 MIBSTAT(frames_1024_to_max_octets),
1040 MIBSTAT(good_octets_sent),
1041 MIBSTAT(good_frames_sent),
1042 MIBSTAT(excessive_collision),
1043 MIBSTAT(multicast_frames_sent),
1044 MIBSTAT(broadcast_frames_sent),
1045 MIBSTAT(unrec_mac_control_received),
1046 MIBSTAT(fc_sent),
1047 MIBSTAT(good_fc_received),
1048 MIBSTAT(bad_fc_received),
1049 MIBSTAT(undersize_received),
1050 MIBSTAT(fragments_received),
1051 MIBSTAT(oversize_received),
1052 MIBSTAT(jabber_received),
1053 MIBSTAT(mac_receive_error),
1054 MIBSTAT(bad_crc_event),
1055 MIBSTAT(collision),
1056 MIBSTAT(late_collision),
1057 };
1058
1059 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1060 {
1061 struct mv643xx_eth_private *mp = netdev_priv(dev);
1062 int err;
1063
1064 spin_lock_irq(&mp->lock);
1065 err = mii_ethtool_gset(&mp->mii, cmd);
1066 spin_unlock_irq(&mp->lock);
1067
1068 /*
1069 * The MAC does not support 1000baseT_Half.
1070 */
1071 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1072 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1073
1074 return err;
1075 }
1076
1077 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1078 {
1079 struct mv643xx_eth_private *mp = netdev_priv(dev);
1080 int err;
1081
1082 /*
1083 * The MAC does not support 1000baseT_Half.
1084 */
1085 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1086
1087 spin_lock_irq(&mp->lock);
1088 err = mii_ethtool_sset(&mp->mii, cmd);
1089 spin_unlock_irq(&mp->lock);
1090
1091 return err;
1092 }
1093
1094 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1095 struct ethtool_drvinfo *drvinfo)
1096 {
1097 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1098 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1099 strncpy(drvinfo->fw_version, "N/A", 32);
1100 strncpy(drvinfo->bus_info, "platform", 32);
1101 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1102 }
1103
1104 static int mv643xx_eth_nway_reset(struct net_device *dev)
1105 {
1106 struct mv643xx_eth_private *mp = netdev_priv(dev);
1107
1108 return mii_nway_restart(&mp->mii);
1109 }
1110
1111 static u32 mv643xx_eth_get_link(struct net_device *dev)
1112 {
1113 struct mv643xx_eth_private *mp = netdev_priv(dev);
1114
1115 return mii_link_ok(&mp->mii);
1116 }
1117
1118 static void mv643xx_eth_get_strings(struct net_device *dev,
1119 uint32_t stringset, uint8_t *data)
1120 {
1121 int i;
1122
1123 if (stringset == ETH_SS_STATS) {
1124 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1125 memcpy(data + i * ETH_GSTRING_LEN,
1126 mv643xx_eth_stats[i].stat_string,
1127 ETH_GSTRING_LEN);
1128 }
1129 }
1130 }
1131
1132 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1133 struct ethtool_stats *stats,
1134 uint64_t *data)
1135 {
1136 struct mv643xx_eth_private *mp = dev->priv;
1137 int i;
1138
1139 mib_counters_update(mp);
1140
1141 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1142 const struct mv643xx_eth_stats *stat;
1143 void *p;
1144
1145 stat = mv643xx_eth_stats + i;
1146
1147 if (stat->netdev_off >= 0)
1148 p = ((void *)mp->dev) + stat->netdev_off;
1149 else
1150 p = ((void *)mp) + stat->mp_off;
1151
1152 data[i] = (stat->sizeof_stat == 8) ?
1153 *(uint64_t *)p : *(uint32_t *)p;
1154 }
1155 }
1156
1157 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1158 {
1159 if (sset == ETH_SS_STATS)
1160 return ARRAY_SIZE(mv643xx_eth_stats);
1161
1162 return -EOPNOTSUPP;
1163 }
1164
1165 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1166 .get_settings = mv643xx_eth_get_settings,
1167 .set_settings = mv643xx_eth_set_settings,
1168 .get_drvinfo = mv643xx_eth_get_drvinfo,
1169 .nway_reset = mv643xx_eth_nway_reset,
1170 .get_link = mv643xx_eth_get_link,
1171 .set_sg = ethtool_op_set_sg,
1172 .get_strings = mv643xx_eth_get_strings,
1173 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1174 .get_sset_count = mv643xx_eth_get_sset_count,
1175 };
1176
1177
1178 /* address handling *********************************************************/
1179 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1180 {
1181 unsigned int mac_h;
1182 unsigned int mac_l;
1183
1184 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1185 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1186
1187 addr[0] = (mac_h >> 24) & 0xff;
1188 addr[1] = (mac_h >> 16) & 0xff;
1189 addr[2] = (mac_h >> 8) & 0xff;
1190 addr[3] = mac_h & 0xff;
1191 addr[4] = (mac_l >> 8) & 0xff;
1192 addr[5] = mac_l & 0xff;
1193 }
1194
1195 static void init_mac_tables(struct mv643xx_eth_private *mp)
1196 {
1197 int i;
1198
1199 for (i = 0; i < 0x100; i += 4) {
1200 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1201 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1202 }
1203
1204 for (i = 0; i < 0x10; i += 4)
1205 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1206 }
1207
1208 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1209 int table, unsigned char entry)
1210 {
1211 unsigned int table_reg;
1212
1213 /* Set "accepts frame bit" at specified table entry */
1214 table_reg = rdl(mp, table + (entry & 0xfc));
1215 table_reg |= 0x01 << (8 * (entry & 3));
1216 wrl(mp, table + (entry & 0xfc), table_reg);
1217 }
1218
1219 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1220 {
1221 unsigned int mac_h;
1222 unsigned int mac_l;
1223 int table;
1224
1225 mac_l = (addr[4] << 8) | addr[5];
1226 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1227
1228 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1229 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1230
1231 table = UNICAST_TABLE(mp->port_num);
1232 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1233 }
1234
1235 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1236 {
1237 struct mv643xx_eth_private *mp = netdev_priv(dev);
1238
1239 /* +2 is for the offset of the HW addr type */
1240 memcpy(dev->dev_addr, addr + 2, 6);
1241
1242 init_mac_tables(mp);
1243 uc_addr_set(mp, dev->dev_addr);
1244
1245 return 0;
1246 }
1247
1248 static int addr_crc(unsigned char *addr)
1249 {
1250 int crc = 0;
1251 int i;
1252
1253 for (i = 0; i < 6; i++) {
1254 int j;
1255
1256 crc = (crc ^ addr[i]) << 8;
1257 for (j = 7; j >= 0; j--) {
1258 if (crc & (0x100 << j))
1259 crc ^= 0x107 << j;
1260 }
1261 }
1262
1263 return crc;
1264 }
1265
1266 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1267 {
1268 struct mv643xx_eth_private *mp = netdev_priv(dev);
1269 u32 port_config;
1270 struct dev_addr_list *addr;
1271 int i;
1272
1273 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1274 if (dev->flags & IFF_PROMISC)
1275 port_config |= UNICAST_PROMISCUOUS_MODE;
1276 else
1277 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1278 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1279
1280 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1281 int port_num = mp->port_num;
1282 u32 accept = 0x01010101;
1283
1284 for (i = 0; i < 0x100; i += 4) {
1285 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1286 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1287 }
1288 return;
1289 }
1290
1291 for (i = 0; i < 0x100; i += 4) {
1292 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1293 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1294 }
1295
1296 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1297 u8 *a = addr->da_addr;
1298 int table;
1299
1300 if (addr->da_addrlen != 6)
1301 continue;
1302
1303 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1304 table = SPECIAL_MCAST_TABLE(mp->port_num);
1305 set_filter_table_entry(mp, table, a[5]);
1306 } else {
1307 int crc = addr_crc(a);
1308
1309 table = OTHER_MCAST_TABLE(mp->port_num);
1310 set_filter_table_entry(mp, table, crc);
1311 }
1312 }
1313 }
1314
1315
1316 /* rx/tx queue initialisation ***********************************************/
1317 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1318 {
1319 struct rx_queue *rxq = mp->rxq + index;
1320 struct rx_desc *rx_desc;
1321 int size;
1322 int i;
1323
1324 rxq->index = index;
1325
1326 rxq->rx_ring_size = mp->default_rx_ring_size;
1327
1328 rxq->rx_desc_count = 0;
1329 rxq->rx_curr_desc = 0;
1330 rxq->rx_used_desc = 0;
1331
1332 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1333
1334 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1335 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1336 mp->rx_desc_sram_size);
1337 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1338 } else {
1339 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1340 &rxq->rx_desc_dma,
1341 GFP_KERNEL);
1342 }
1343
1344 if (rxq->rx_desc_area == NULL) {
1345 dev_printk(KERN_ERR, &mp->dev->dev,
1346 "can't allocate rx ring (%d bytes)\n", size);
1347 goto out;
1348 }
1349 memset(rxq->rx_desc_area, 0, size);
1350
1351 rxq->rx_desc_area_size = size;
1352 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1353 GFP_KERNEL);
1354 if (rxq->rx_skb == NULL) {
1355 dev_printk(KERN_ERR, &mp->dev->dev,
1356 "can't allocate rx skb ring\n");
1357 goto out_free;
1358 }
1359
1360 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1361 for (i = 0; i < rxq->rx_ring_size; i++) {
1362 int nexti = (i + 1) % rxq->rx_ring_size;
1363 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1364 nexti * sizeof(struct rx_desc);
1365 }
1366
1367 init_timer(&rxq->rx_oom);
1368 rxq->rx_oom.data = (unsigned long)rxq;
1369 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1370
1371 return 0;
1372
1373
1374 out_free:
1375 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1376 iounmap(rxq->rx_desc_area);
1377 else
1378 dma_free_coherent(NULL, size,
1379 rxq->rx_desc_area,
1380 rxq->rx_desc_dma);
1381
1382 out:
1383 return -ENOMEM;
1384 }
1385
1386 static void rxq_deinit(struct rx_queue *rxq)
1387 {
1388 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1389 int i;
1390
1391 rxq_disable(rxq);
1392
1393 del_timer_sync(&rxq->rx_oom);
1394
1395 for (i = 0; i < rxq->rx_ring_size; i++) {
1396 if (rxq->rx_skb[i]) {
1397 dev_kfree_skb(rxq->rx_skb[i]);
1398 rxq->rx_desc_count--;
1399 }
1400 }
1401
1402 if (rxq->rx_desc_count) {
1403 dev_printk(KERN_ERR, &mp->dev->dev,
1404 "error freeing rx ring -- %d skbs stuck\n",
1405 rxq->rx_desc_count);
1406 }
1407
1408 if (rxq->index == mp->rxq_primary &&
1409 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1410 iounmap(rxq->rx_desc_area);
1411 else
1412 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1413 rxq->rx_desc_area, rxq->rx_desc_dma);
1414
1415 kfree(rxq->rx_skb);
1416 }
1417
1418 static int txq_init(struct mv643xx_eth_private *mp)
1419 {
1420 struct tx_queue *txq = mp->txq;
1421 struct tx_desc *tx_desc;
1422 int size;
1423 int i;
1424
1425 txq->tx_ring_size = mp->default_tx_ring_size;
1426
1427 txq->tx_desc_count = 0;
1428 txq->tx_curr_desc = 0;
1429 txq->tx_used_desc = 0;
1430
1431 size = txq->tx_ring_size * sizeof(struct tx_desc);
1432
1433 if (size <= mp->tx_desc_sram_size) {
1434 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1435 mp->tx_desc_sram_size);
1436 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1437 } else {
1438 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1439 &txq->tx_desc_dma,
1440 GFP_KERNEL);
1441 }
1442
1443 if (txq->tx_desc_area == NULL) {
1444 dev_printk(KERN_ERR, &mp->dev->dev,
1445 "can't allocate tx ring (%d bytes)\n", size);
1446 goto out;
1447 }
1448 memset(txq->tx_desc_area, 0, size);
1449
1450 txq->tx_desc_area_size = size;
1451 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1452 GFP_KERNEL);
1453 if (txq->tx_skb == NULL) {
1454 dev_printk(KERN_ERR, &mp->dev->dev,
1455 "can't allocate tx skb ring\n");
1456 goto out_free;
1457 }
1458
1459 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1460 for (i = 0; i < txq->tx_ring_size; i++) {
1461 int nexti = (i + 1) % txq->tx_ring_size;
1462 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1463 nexti * sizeof(struct tx_desc);
1464 }
1465
1466 return 0;
1467
1468
1469 out_free:
1470 if (size <= mp->tx_desc_sram_size)
1471 iounmap(txq->tx_desc_area);
1472 else
1473 dma_free_coherent(NULL, size,
1474 txq->tx_desc_area,
1475 txq->tx_desc_dma);
1476
1477 out:
1478 return -ENOMEM;
1479 }
1480
1481 static void txq_reclaim(struct tx_queue *txq, int force)
1482 {
1483 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1484 unsigned long flags;
1485
1486 spin_lock_irqsave(&mp->lock, flags);
1487 while (txq->tx_desc_count > 0) {
1488 int tx_index;
1489 struct tx_desc *desc;
1490 u32 cmd_sts;
1491 struct sk_buff *skb;
1492 dma_addr_t addr;
1493 int count;
1494
1495 tx_index = txq->tx_used_desc;
1496 desc = &txq->tx_desc_area[tx_index];
1497 cmd_sts = desc->cmd_sts;
1498
1499 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1500 break;
1501
1502 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1503 txq->tx_desc_count--;
1504
1505 addr = desc->buf_ptr;
1506 count = desc->byte_cnt;
1507 skb = txq->tx_skb[tx_index];
1508 txq->tx_skb[tx_index] = NULL;
1509
1510 if (cmd_sts & ERROR_SUMMARY) {
1511 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1512 mp->dev->stats.tx_errors++;
1513 }
1514
1515 /*
1516 * Drop mp->lock while we free the skb.
1517 */
1518 spin_unlock_irqrestore(&mp->lock, flags);
1519
1520 if (cmd_sts & TX_FIRST_DESC)
1521 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1522 else
1523 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1524
1525 if (skb)
1526 dev_kfree_skb_irq(skb);
1527
1528 spin_lock_irqsave(&mp->lock, flags);
1529 }
1530 spin_unlock_irqrestore(&mp->lock, flags);
1531 }
1532
1533 static void txq_deinit(struct tx_queue *txq)
1534 {
1535 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1536
1537 txq_disable(txq);
1538 txq_reclaim(txq, 1);
1539
1540 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1541
1542 if (txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1543 iounmap(txq->tx_desc_area);
1544 else
1545 dma_free_coherent(NULL, txq->tx_desc_area_size,
1546 txq->tx_desc_area, txq->tx_desc_dma);
1547
1548 kfree(txq->tx_skb);
1549 }
1550
1551
1552 /* netdev ops and related ***************************************************/
1553 static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1554 {
1555 u32 pscr_o;
1556 u32 pscr_n;
1557
1558 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1559
1560 /* clear speed, duplex and rx buffer size fields */
1561 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1562 SET_GMII_SPEED_TO_1000 |
1563 SET_FULL_DUPLEX_MODE |
1564 MAX_RX_PACKET_MASK);
1565
1566 if (speed == SPEED_1000) {
1567 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1568 } else {
1569 if (speed == SPEED_100)
1570 pscr_n |= SET_MII_SPEED_TO_100;
1571 pscr_n |= MAX_RX_PACKET_1522BYTE;
1572 }
1573
1574 if (duplex == DUPLEX_FULL)
1575 pscr_n |= SET_FULL_DUPLEX_MODE;
1576
1577 if (pscr_n != pscr_o) {
1578 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1579 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1580 else {
1581 txq_disable(mp->txq);
1582 pscr_o &= ~SERIAL_PORT_ENABLE;
1583 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1584 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1585 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1586 txq_enable(mp->txq);
1587 }
1588 }
1589 }
1590
1591 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1592 {
1593 struct net_device *dev = (struct net_device *)dev_id;
1594 struct mv643xx_eth_private *mp = netdev_priv(dev);
1595 u32 int_cause;
1596 u32 int_cause_ext;
1597
1598 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & (INT_RX | INT_EXT);
1599 if (int_cause == 0)
1600 return IRQ_NONE;
1601
1602 int_cause_ext = 0;
1603 if (int_cause & INT_EXT) {
1604 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1605 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1606 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1607 }
1608
1609 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
1610 if (mii_link_ok(&mp->mii)) {
1611 struct ethtool_cmd cmd;
1612
1613 mii_ethtool_gset(&mp->mii, &cmd);
1614 update_pscr(mp, cmd.speed, cmd.duplex);
1615 txq_enable(mp->txq);
1616 if (!netif_carrier_ok(dev)) {
1617 netif_carrier_on(dev);
1618 __txq_maybe_wake(mp->txq);
1619 }
1620 } else if (netif_carrier_ok(dev)) {
1621 netif_stop_queue(dev);
1622 netif_carrier_off(dev);
1623 }
1624 }
1625
1626 /*
1627 * RxBuffer or RxError set for any of the 8 queues?
1628 */
1629 #ifdef MV643XX_ETH_NAPI
1630 if (int_cause & INT_RX) {
1631 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1632 rdl(mp, INT_MASK(mp->port_num));
1633
1634 netif_rx_schedule(dev, &mp->napi);
1635 }
1636 #else
1637 if (int_cause & INT_RX) {
1638 int i;
1639
1640 for (i = 7; i >= 0; i--)
1641 if (mp->rxq_mask & (1 << i))
1642 rxq_process(mp->rxq + i, INT_MAX);
1643 }
1644 #endif
1645
1646 if (int_cause_ext & INT_EXT_TX) {
1647 txq_reclaim(mp->txq, 0);
1648 __txq_maybe_wake(mp->txq);
1649 }
1650
1651 return IRQ_HANDLED;
1652 }
1653
1654 static void phy_reset(struct mv643xx_eth_private *mp)
1655 {
1656 unsigned int data;
1657
1658 smi_reg_read(mp, mp->phy_addr, 0, &data);
1659 data |= 0x8000;
1660 smi_reg_write(mp, mp->phy_addr, 0, data);
1661
1662 do {
1663 udelay(1);
1664 smi_reg_read(mp, mp->phy_addr, 0, &data);
1665 } while (data & 0x8000);
1666 }
1667
1668 static void port_start(struct mv643xx_eth_private *mp)
1669 {
1670 u32 pscr;
1671 struct ethtool_cmd ethtool_cmd;
1672 int i;
1673
1674 /*
1675 * Configure basic link parameters.
1676 */
1677 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1678 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1679 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1680 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1681 DISABLE_AUTO_NEG_SPEED_GMII |
1682 DISABLE_AUTO_NEG_FOR_DUPLEX |
1683 DO_NOT_FORCE_LINK_FAIL |
1684 SERIAL_PORT_CONTROL_RESERVED;
1685 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1686 pscr |= SERIAL_PORT_ENABLE;
1687 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1688
1689 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1690
1691 mv643xx_eth_get_settings(mp->dev, &ethtool_cmd);
1692 phy_reset(mp);
1693 mv643xx_eth_set_settings(mp->dev, &ethtool_cmd);
1694
1695 /*
1696 * Configure TX path and queues.
1697 */
1698 tx_set_rate(mp, 1000000000, 16777216);
1699 for (i = 0; i < 1; i++) {
1700 struct tx_queue *txq = mp->txq;
1701 int off = TXQ_CURRENT_DESC_PTR(mp->port_num);
1702 u32 addr;
1703
1704 addr = (u32)txq->tx_desc_dma;
1705 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1706 wrl(mp, off, addr);
1707
1708 txq_set_rate(txq, 1000000000, 16777216);
1709 txq_set_fixed_prio_mode(txq);
1710 }
1711
1712 /*
1713 * Add configured unicast address to address filter table.
1714 */
1715 uc_addr_set(mp, mp->dev->dev_addr);
1716
1717 /*
1718 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1719 * frames to RX queue #0.
1720 */
1721 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1722
1723 /*
1724 * Treat BPDUs as normal multicasts, and disable partition mode.
1725 */
1726 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1727
1728 /*
1729 * Enable the receive queues.
1730 */
1731 for (i = 0; i < 8; i++) {
1732 struct rx_queue *rxq = mp->rxq + i;
1733 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1734 u32 addr;
1735
1736 if ((mp->rxq_mask & (1 << i)) == 0)
1737 continue;
1738
1739 addr = (u32)rxq->rx_desc_dma;
1740 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1741 wrl(mp, off, addr);
1742
1743 rxq_enable(rxq);
1744 }
1745 }
1746
1747 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1748 {
1749 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1750
1751 if (coal > 0x3fff)
1752 coal = 0x3fff;
1753
1754 wrl(mp, SDMA_CONFIG(mp->port_num),
1755 ((coal & 0x3fff) << 8) |
1756 (rdl(mp, SDMA_CONFIG(mp->port_num))
1757 & 0xffc000ff));
1758 }
1759
1760 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1761 {
1762 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1763
1764 if (coal > 0x3fff)
1765 coal = 0x3fff;
1766 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
1767 }
1768
1769 static int mv643xx_eth_open(struct net_device *dev)
1770 {
1771 struct mv643xx_eth_private *mp = netdev_priv(dev);
1772 int err;
1773 int i;
1774
1775 wrl(mp, INT_CAUSE(mp->port_num), 0);
1776 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1777 rdl(mp, INT_CAUSE_EXT(mp->port_num));
1778
1779 err = request_irq(dev->irq, mv643xx_eth_irq,
1780 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1781 dev->name, dev);
1782 if (err) {
1783 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1784 return -EAGAIN;
1785 }
1786
1787 init_mac_tables(mp);
1788
1789 for (i = 0; i < 8; i++) {
1790 if ((mp->rxq_mask & (1 << i)) == 0)
1791 continue;
1792
1793 err = rxq_init(mp, i);
1794 if (err) {
1795 while (--i >= 0)
1796 if (mp->rxq_mask & (1 << i))
1797 rxq_deinit(mp->rxq + i);
1798 goto out;
1799 }
1800
1801 rxq_refill(mp->rxq + i);
1802 }
1803
1804 err = txq_init(mp);
1805 if (err)
1806 goto out_free;
1807
1808 #ifdef MV643XX_ETH_NAPI
1809 napi_enable(&mp->napi);
1810 #endif
1811
1812 port_start(mp);
1813
1814 set_rx_coal(mp, 0);
1815 set_tx_coal(mp, 0);
1816
1817 wrl(mp, INT_MASK_EXT(mp->port_num),
1818 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1819
1820 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
1821
1822 return 0;
1823
1824
1825 out_free:
1826 for (i = 0; i < 8; i++)
1827 if (mp->rxq_mask & (1 << i))
1828 rxq_deinit(mp->rxq + i);
1829 out:
1830 free_irq(dev->irq, dev);
1831
1832 return err;
1833 }
1834
1835 static void port_reset(struct mv643xx_eth_private *mp)
1836 {
1837 unsigned int data;
1838 int i;
1839
1840 for (i = 0; i < 8; i++) {
1841 if (mp->rxq_mask & (1 << i))
1842 rxq_disable(mp->rxq + i);
1843 }
1844 txq_disable(mp->txq);
1845 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
1846 udelay(10);
1847
1848 /* Reset the Enable bit in the Configuration Register */
1849 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1850 data &= ~(SERIAL_PORT_ENABLE |
1851 DO_NOT_FORCE_LINK_FAIL |
1852 FORCE_LINK_PASS);
1853 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1854 }
1855
1856 static int mv643xx_eth_stop(struct net_device *dev)
1857 {
1858 struct mv643xx_eth_private *mp = netdev_priv(dev);
1859 int i;
1860
1861 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1862 rdl(mp, INT_MASK(mp->port_num));
1863
1864 #ifdef MV643XX_ETH_NAPI
1865 napi_disable(&mp->napi);
1866 #endif
1867 netif_carrier_off(dev);
1868 netif_stop_queue(dev);
1869
1870 free_irq(dev->irq, dev);
1871
1872 port_reset(mp);
1873 mib_counters_update(mp);
1874
1875 for (i = 0; i < 8; i++) {
1876 if (mp->rxq_mask & (1 << i))
1877 rxq_deinit(mp->rxq + i);
1878 }
1879 txq_deinit(mp->txq);
1880
1881 return 0;
1882 }
1883
1884 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1885 {
1886 struct mv643xx_eth_private *mp = netdev_priv(dev);
1887
1888 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1889 }
1890
1891 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1892 {
1893 struct mv643xx_eth_private *mp = netdev_priv(dev);
1894
1895 if (new_mtu < 64 || new_mtu > 9500)
1896 return -EINVAL;
1897
1898 dev->mtu = new_mtu;
1899 tx_set_rate(mp, 1000000000, 16777216);
1900
1901 if (!netif_running(dev))
1902 return 0;
1903
1904 /*
1905 * Stop and then re-open the interface. This will allocate RX
1906 * skbs of the new MTU.
1907 * There is a possible danger that the open will not succeed,
1908 * due to memory being full.
1909 */
1910 mv643xx_eth_stop(dev);
1911 if (mv643xx_eth_open(dev)) {
1912 dev_printk(KERN_ERR, &dev->dev,
1913 "fatal error on re-opening device after "
1914 "MTU change\n");
1915 }
1916
1917 return 0;
1918 }
1919
1920 static void tx_timeout_task(struct work_struct *ugly)
1921 {
1922 struct mv643xx_eth_private *mp;
1923
1924 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
1925 if (netif_running(mp->dev)) {
1926 netif_stop_queue(mp->dev);
1927
1928 port_reset(mp);
1929 port_start(mp);
1930
1931 __txq_maybe_wake(mp->txq);
1932 }
1933 }
1934
1935 static void mv643xx_eth_tx_timeout(struct net_device *dev)
1936 {
1937 struct mv643xx_eth_private *mp = netdev_priv(dev);
1938
1939 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
1940
1941 schedule_work(&mp->tx_timeout_task);
1942 }
1943
1944 #ifdef CONFIG_NET_POLL_CONTROLLER
1945 static void mv643xx_eth_netpoll(struct net_device *dev)
1946 {
1947 struct mv643xx_eth_private *mp = netdev_priv(dev);
1948
1949 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1950 rdl(mp, INT_MASK(mp->port_num));
1951
1952 mv643xx_eth_irq(dev->irq, dev);
1953
1954 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_CAUSE_EXT);
1955 }
1956 #endif
1957
1958 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
1959 {
1960 struct mv643xx_eth_private *mp = netdev_priv(dev);
1961 int val;
1962
1963 smi_reg_read(mp, addr, reg, &val);
1964
1965 return val;
1966 }
1967
1968 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
1969 {
1970 struct mv643xx_eth_private *mp = netdev_priv(dev);
1971 smi_reg_write(mp, addr, reg, val);
1972 }
1973
1974
1975 /* platform glue ************************************************************/
1976 static void
1977 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
1978 struct mbus_dram_target_info *dram)
1979 {
1980 void __iomem *base = msp->base;
1981 u32 win_enable;
1982 u32 win_protect;
1983 int i;
1984
1985 for (i = 0; i < 6; i++) {
1986 writel(0, base + WINDOW_BASE(i));
1987 writel(0, base + WINDOW_SIZE(i));
1988 if (i < 4)
1989 writel(0, base + WINDOW_REMAP_HIGH(i));
1990 }
1991
1992 win_enable = 0x3f;
1993 win_protect = 0;
1994
1995 for (i = 0; i < dram->num_cs; i++) {
1996 struct mbus_dram_window *cs = dram->cs + i;
1997
1998 writel((cs->base & 0xffff0000) |
1999 (cs->mbus_attr << 8) |
2000 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2001 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2002
2003 win_enable &= ~(1 << i);
2004 win_protect |= 3 << (2 * i);
2005 }
2006
2007 writel(win_enable, base + WINDOW_BAR_ENABLE);
2008 msp->win_protect = win_protect;
2009 }
2010
2011 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2012 {
2013 static int mv643xx_eth_version_printed = 0;
2014 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2015 struct mv643xx_eth_shared_private *msp;
2016 struct resource *res;
2017 int ret;
2018
2019 if (!mv643xx_eth_version_printed++)
2020 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2021
2022 ret = -EINVAL;
2023 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2024 if (res == NULL)
2025 goto out;
2026
2027 ret = -ENOMEM;
2028 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2029 if (msp == NULL)
2030 goto out;
2031 memset(msp, 0, sizeof(*msp));
2032
2033 msp->base = ioremap(res->start, res->end - res->start + 1);
2034 if (msp->base == NULL)
2035 goto out_free;
2036
2037 spin_lock_init(&msp->phy_lock);
2038
2039 /*
2040 * (Re-)program MBUS remapping windows if we are asked to.
2041 */
2042 if (pd != NULL && pd->dram != NULL)
2043 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2044
2045 /*
2046 * Detect hardware parameters.
2047 */
2048 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2049
2050 platform_set_drvdata(pdev, msp);
2051
2052 return 0;
2053
2054 out_free:
2055 kfree(msp);
2056 out:
2057 return ret;
2058 }
2059
2060 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2061 {
2062 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2063
2064 iounmap(msp->base);
2065 kfree(msp);
2066
2067 return 0;
2068 }
2069
2070 static struct platform_driver mv643xx_eth_shared_driver = {
2071 .probe = mv643xx_eth_shared_probe,
2072 .remove = mv643xx_eth_shared_remove,
2073 .driver = {
2074 .name = MV643XX_ETH_SHARED_NAME,
2075 .owner = THIS_MODULE,
2076 },
2077 };
2078
2079 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2080 {
2081 int addr_shift = 5 * mp->port_num;
2082 u32 data;
2083
2084 data = rdl(mp, PHY_ADDR);
2085 data &= ~(0x1f << addr_shift);
2086 data |= (phy_addr & 0x1f) << addr_shift;
2087 wrl(mp, PHY_ADDR, data);
2088 }
2089
2090 static int phy_addr_get(struct mv643xx_eth_private *mp)
2091 {
2092 unsigned int data;
2093
2094 data = rdl(mp, PHY_ADDR);
2095
2096 return (data >> (5 * mp->port_num)) & 0x1f;
2097 }
2098
2099 static void set_params(struct mv643xx_eth_private *mp,
2100 struct mv643xx_eth_platform_data *pd)
2101 {
2102 struct net_device *dev = mp->dev;
2103
2104 if (is_valid_ether_addr(pd->mac_addr))
2105 memcpy(dev->dev_addr, pd->mac_addr, 6);
2106 else
2107 uc_addr_get(mp, dev->dev_addr);
2108
2109 if (pd->phy_addr == -1) {
2110 mp->shared_smi = NULL;
2111 mp->phy_addr = -1;
2112 } else {
2113 mp->shared_smi = mp->shared;
2114 if (pd->shared_smi != NULL)
2115 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2116
2117 if (pd->force_phy_addr || pd->phy_addr) {
2118 mp->phy_addr = pd->phy_addr & 0x3f;
2119 phy_addr_set(mp, mp->phy_addr);
2120 } else {
2121 mp->phy_addr = phy_addr_get(mp);
2122 }
2123 }
2124
2125 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2126 if (pd->rx_queue_size)
2127 mp->default_rx_ring_size = pd->rx_queue_size;
2128 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2129 mp->rx_desc_sram_size = pd->rx_sram_size;
2130
2131 if (pd->rx_queue_mask)
2132 mp->rxq_mask = pd->rx_queue_mask;
2133 else
2134 mp->rxq_mask = 0x01;
2135 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2136
2137 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2138 if (pd->tx_queue_size)
2139 mp->default_tx_ring_size = pd->tx_queue_size;
2140 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2141 mp->tx_desc_sram_size = pd->tx_sram_size;
2142 }
2143
2144 static int phy_detect(struct mv643xx_eth_private *mp)
2145 {
2146 unsigned int data;
2147 unsigned int data2;
2148
2149 smi_reg_read(mp, mp->phy_addr, 0, &data);
2150 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
2151
2152 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2153 if (((data ^ data2) & 0x1000) == 0)
2154 return -ENODEV;
2155
2156 smi_reg_write(mp, mp->phy_addr, 0, data);
2157
2158 return 0;
2159 }
2160
2161 static int phy_init(struct mv643xx_eth_private *mp,
2162 struct mv643xx_eth_platform_data *pd)
2163 {
2164 struct ethtool_cmd cmd;
2165 int err;
2166
2167 err = phy_detect(mp);
2168 if (err) {
2169 dev_printk(KERN_INFO, &mp->dev->dev,
2170 "no PHY detected at addr %d\n", mp->phy_addr);
2171 return err;
2172 }
2173 phy_reset(mp);
2174
2175 mp->mii.phy_id = mp->phy_addr;
2176 mp->mii.phy_id_mask = 0x3f;
2177 mp->mii.reg_num_mask = 0x1f;
2178 mp->mii.dev = mp->dev;
2179 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2180 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2181
2182 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2183
2184 memset(&cmd, 0, sizeof(cmd));
2185
2186 cmd.port = PORT_MII;
2187 cmd.transceiver = XCVR_INTERNAL;
2188 cmd.phy_address = mp->phy_addr;
2189 if (pd->speed == 0) {
2190 cmd.autoneg = AUTONEG_ENABLE;
2191 cmd.speed = SPEED_100;
2192 cmd.advertising = ADVERTISED_10baseT_Half |
2193 ADVERTISED_10baseT_Full |
2194 ADVERTISED_100baseT_Half |
2195 ADVERTISED_100baseT_Full;
2196 if (mp->mii.supports_gmii)
2197 cmd.advertising |= ADVERTISED_1000baseT_Full;
2198 } else {
2199 cmd.autoneg = AUTONEG_DISABLE;
2200 cmd.speed = pd->speed;
2201 cmd.duplex = pd->duplex;
2202 }
2203
2204 update_pscr(mp, cmd.speed, cmd.duplex);
2205 mv643xx_eth_set_settings(mp->dev, &cmd);
2206
2207 return 0;
2208 }
2209
2210 static int mv643xx_eth_probe(struct platform_device *pdev)
2211 {
2212 struct mv643xx_eth_platform_data *pd;
2213 struct mv643xx_eth_private *mp;
2214 struct net_device *dev;
2215 struct resource *res;
2216 DECLARE_MAC_BUF(mac);
2217 int err;
2218
2219 pd = pdev->dev.platform_data;
2220 if (pd == NULL) {
2221 dev_printk(KERN_ERR, &pdev->dev,
2222 "no mv643xx_eth_platform_data\n");
2223 return -ENODEV;
2224 }
2225
2226 if (pd->shared == NULL) {
2227 dev_printk(KERN_ERR, &pdev->dev,
2228 "no mv643xx_eth_platform_data->shared\n");
2229 return -ENODEV;
2230 }
2231
2232 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2233 if (!dev)
2234 return -ENOMEM;
2235
2236 mp = netdev_priv(dev);
2237 platform_set_drvdata(pdev, mp);
2238
2239 mp->shared = platform_get_drvdata(pd->shared);
2240 mp->port_num = pd->port_number;
2241
2242 mp->dev = dev;
2243 #ifdef MV643XX_ETH_NAPI
2244 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2245 #endif
2246
2247 set_params(mp, pd);
2248
2249 spin_lock_init(&mp->lock);
2250
2251 mib_counters_clear(mp);
2252 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2253
2254 err = phy_init(mp, pd);
2255 if (err)
2256 goto out;
2257 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2258
2259
2260 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2261 BUG_ON(!res);
2262 dev->irq = res->start;
2263
2264 dev->hard_start_xmit = mv643xx_eth_xmit;
2265 dev->open = mv643xx_eth_open;
2266 dev->stop = mv643xx_eth_stop;
2267 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2268 dev->set_mac_address = mv643xx_eth_set_mac_address;
2269 dev->do_ioctl = mv643xx_eth_ioctl;
2270 dev->change_mtu = mv643xx_eth_change_mtu;
2271 dev->tx_timeout = mv643xx_eth_tx_timeout;
2272 #ifdef CONFIG_NET_POLL_CONTROLLER
2273 dev->poll_controller = mv643xx_eth_netpoll;
2274 #endif
2275 dev->watchdog_timeo = 2 * HZ;
2276 dev->base_addr = 0;
2277
2278 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2279 /*
2280 * Zero copy can only work if we use Discovery II memory. Else, we will
2281 * have to map the buffers to ISA memory which is only 16 MB
2282 */
2283 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2284 #endif
2285
2286 SET_NETDEV_DEV(dev, &pdev->dev);
2287
2288 if (mp->shared->win_protect)
2289 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2290
2291 err = register_netdev(dev);
2292 if (err)
2293 goto out;
2294
2295 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2296 mp->port_num, print_mac(mac, dev->dev_addr));
2297
2298 if (dev->features & NETIF_F_SG)
2299 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2300
2301 if (dev->features & NETIF_F_IP_CSUM)
2302 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2303
2304 #ifdef MV643XX_ETH_NAPI
2305 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2306 #endif
2307
2308 if (mp->tx_desc_sram_size > 0)
2309 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2310
2311 return 0;
2312
2313 out:
2314 free_netdev(dev);
2315
2316 return err;
2317 }
2318
2319 static int mv643xx_eth_remove(struct platform_device *pdev)
2320 {
2321 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2322
2323 unregister_netdev(mp->dev);
2324 flush_scheduled_work();
2325 free_netdev(mp->dev);
2326
2327 platform_set_drvdata(pdev, NULL);
2328
2329 return 0;
2330 }
2331
2332 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2333 {
2334 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2335
2336 /* Mask all interrupts on ethernet port */
2337 wrl(mp, INT_MASK(mp->port_num), 0);
2338 rdl(mp, INT_MASK(mp->port_num));
2339
2340 if (netif_running(mp->dev))
2341 port_reset(mp);
2342 }
2343
2344 static struct platform_driver mv643xx_eth_driver = {
2345 .probe = mv643xx_eth_probe,
2346 .remove = mv643xx_eth_remove,
2347 .shutdown = mv643xx_eth_shutdown,
2348 .driver = {
2349 .name = MV643XX_ETH_NAME,
2350 .owner = THIS_MODULE,
2351 },
2352 };
2353
2354 static int __init mv643xx_eth_init_module(void)
2355 {
2356 int rc;
2357
2358 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2359 if (!rc) {
2360 rc = platform_driver_register(&mv643xx_eth_driver);
2361 if (rc)
2362 platform_driver_unregister(&mv643xx_eth_shared_driver);
2363 }
2364
2365 return rc;
2366 }
2367 module_init(mv643xx_eth_init_module);
2368
2369 static void __exit mv643xx_eth_cleanup_module(void)
2370 {
2371 platform_driver_unregister(&mv643xx_eth_driver);
2372 platform_driver_unregister(&mv643xx_eth_shared_driver);
2373 }
2374 module_exit(mv643xx_eth_cleanup_module);
2375
2376 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani "
2377 "and Dale Farnsworth");
2378 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2379 MODULE_LICENSE("GPL");
2380 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2381 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 2.6 libata-dev (mirror)