arch/ppc/platforms/85xx/mpc85xx_cds_common.c

   1 /*
   2  * arch/ppc/platform/85xx/mpc85xx_cds_common.c
   3  *
   4  * MPC85xx CDS board specific routines
   5  *
   6  * Maintainer: Kumar Gala <kumar.gala@freescale.com>
   7  *
   8  * Copyright 2004 Freescale Semiconductor, Inc
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/stddef.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/reboot.h>
  22 #include <linux/pci.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/major.h>
  25 #include <linux/console.h>
  26 #include <linux/delay.h>
  27 #include <linux/irq.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/serial.h>
  30 #include <linux/module.h>
  31 #include <linux/root_dev.h>
  32 #include <linux/initrd.h>
  33 #include <linux/tty.h>
  34 #include <linux/serial_core.h>
  35 #include <linux/fsl_devices.h>
  36
  37 #include <asm/system.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/page.h>
  40 #include <asm/atomic.h>
  41 #include <asm/time.h>
  42 #include <asm/todc.h>
  43 #include <asm/io.h>
  44 #include <asm/machdep.h>
  45 #include <asm/prom.h>
  46 #include <asm/open_pic.h>
  47 #include <asm/i8259.h>
  48 #include <asm/bootinfo.h>
  49 #include <asm/pci-bridge.h>
  50 #include <asm/mpc85xx.h>
  51 #include <asm/irq.h>
  52 #include <asm/immap_85xx.h>
  53 #include <asm/immap_cpm2.h>
  54 #include <asm/ppc_sys.h>
  55 #include <asm/kgdb.h>
  56
  57 #include <mm/mmu_decl.h>
  58 #include <syslib/cpm2_pic.h>
  59 #include <syslib/ppc85xx_common.h>
  60 #include <syslib/ppc85xx_setup.h>
  61
  62
  63 #ifndef CONFIG_PCI
  64 unsigned long isa_io_base = 0;
  65 unsigned long isa_mem_base = 0;
  66 #endif
  67
  68 extern unsigned long total_memory;      /* in mm/init */
  69
  70 unsigned char __res[sizeof (bd_t)];
  71
  72 static int cds_pci_slot = 2;
  73 static volatile u8 * cadmus;
  74
  75 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  76 static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
  77         MPC85XX_INTERNAL_IRQ_SENSES,
  78 #if defined(CONFIG_PCI)
  79         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 0: PCI1 slot */
  80         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI1 slot */
  81         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 2: PCI1 slot */
  82         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 3: PCI1 slot */
  83 #else
  84         0x0,                                            /* External  0: */
  85         0x0,                                            /* External  1: */
  86         0x0,                                            /* External  2: */
  87         0x0,                                            /* External  3: */
  88 #endif
  89         0x0,                                            /* External  4: */
  90         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External  5: PHY */
  91         0x0,                                            /* External  6: */
  92         0x0,                                            /* External  7: */
  93         0x0,                                            /* External  8: */
  94         0x0,                                            /* External  9: */
  95         0x0,                                            /* External 10: */
  96 #if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
  97         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 11: PCI2 slot 0 */
  98 #else
  99         0x0,                                            /* External 11: */
 100 #endif
 101 };
 102
 103 /* ************************************************************************ */
 104 int
 105 mpc85xx_cds_show_cpuinfo(struct seq_file *m)
 106 {
 107         uint pvid, svid, phid1;
 108         uint memsize = total_memory;
 109         bd_t *binfo = (bd_t *) __res;
 110         unsigned int freq;
 111
 112         /* get the core frequency */
 113         freq = binfo->bi_intfreq;
 114
 115         pvid = mfspr(SPRN_PVR);
 116         svid = mfspr(SPRN_SVR);
 117
 118         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 119         seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
 120         seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
 121         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 122         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 123
 124         /* Display cpu Pll setting */
 125         phid1 = mfspr(SPRN_HID1);
 126         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 127
 128         /* Display the amount of memory */
 129         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 130
 131         return 0;
 132 }
 133
 134 #ifdef CONFIG_CPM2
 135 static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
 136 {
 137         while((irq = cpm2_get_irq(regs)) >= 0)
 138                 __do_IRQ(irq, regs);
 139 }
 140
 141 static struct irqaction cpm2_irqaction = {
 142         .handler = cpm2_cascade,
 143         .flags = SA_INTERRUPT,
 144         .mask = CPU_MASK_NONE,
 145         .name = "cpm2_cascade",
 146 };
 147 #endif /* CONFIG_CPM2 */
 148
 149 void __init
 150 mpc85xx_cds_init_IRQ(void)
 151 {
 152         bd_t *binfo = (bd_t *) __res;
 153
 154         /* Determine the Physical Address of the OpenPIC regs */
 155         phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
 156         OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
 157         OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
 158         OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
 159
 160         /* Skip reserved space and internal sources */
 161 #ifdef CONFIG_MPC8548
 162         openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200);
 163 #else
 164         openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
 165 #endif
 166         /* Map PIC IRQs 0-11 */
 167         openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
 168
 169         /* we let openpic interrupts starting from an offset, to
 170          * leave space for cascading interrupts underneath.
 171          */
 172         openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 173
 174 #ifdef CONFIG_PCI
 175         openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
 176
 177         for (i = 0; i < NUM_8259_INTERRUPTS; i++)
 178                 irq_desc[i].handler = &i8259_pic;
 179
 180         i8259_init(0);
 181 #endif
 182
 183 #ifdef CONFIG_CPM2
 184         /* Setup CPM2 PIC */
 185         cpm2_init_IRQ();
 186
 187         setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
 188 #endif
 189
 190         return;
 191 }
 192
 193 #ifdef CONFIG_PCI
 194 /*
 195  * interrupt routing
 196  */
 197 int
 198 mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 199 {
 200         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
 201
 202         if (!hose->index)
 203         {
 204                 /* Handle PCI1 interrupts */
 205                 char pci_irq_table[][4] =
 206                         /*
 207                          *      PCI IDSEL/INTPIN->INTLINE
 208                          *        A      B      C      D
 209                          */
 210
 211                         /* Note IRQ assignment for slots is based on which slot the elysium is
 212                          * in -- in this setup elysium is in slot #2 (this PIRQA as first
 213                          * interrupt on slot */
 214                 {
 215                         { 0, 1, 2, 3 }, /* 16 - PMC */
 216                         { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
 217                         { 0, 1, 2, 3 }, /* 18 - Slot 1 */
 218                         { 1, 2, 3, 0 }, /* 19 - Slot 2 */
 219                         { 2, 3, 0, 1 }, /* 20 - Slot 3 */
 220                         { 3, 0, 1, 2 }, /* 21 - Slot 4 */
 221                 };
 222
 223                 const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
 224                 int i, j;
 225
 226                 for (i = 0; i < 6; i++)
 227                         for (j = 0; j < 4; j++)
 228                                 pci_irq_table[i][j] =
 229                                         ((pci_irq_table[i][j] + 5 -
 230                                           cds_pci_slot) & 0x3) + PIRQ0A;
 231
 232                 return PCI_IRQ_TABLE_LOOKUP;
 233         } else {
 234                 /* Handle PCI2 interrupts (if we have one) */
 235                 char pci_irq_table[][4] =
 236                 {
 237                         /*
 238                          * We only have one slot and one interrupt
 239                          * going to PIRQA - PIRQD */
 240                         { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
 241                 };
 242
 243                 const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
 244
 245                 return PCI_IRQ_TABLE_LOOKUP;
 246         }
 247 }
 248
 249 #define ARCADIA_HOST_BRIDGE_IDSEL       17
 250 #define ARCADIA_2ND_BRIDGE_IDSEL        3
 251
 252 extern int mpc85xx_pci1_last_busno;
 253
 254 int
 255 mpc85xx_exclude_device(u_char bus, u_char devfn)
 256 {
 257         if (bus == 0 && PCI_SLOT(devfn) == 0)
 258                 return PCIBIOS_DEVICE_NOT_FOUND;
 259 #ifdef CONFIG_85xx_PCI2
 260         if (mpc85xx_pci1_last_busno)
 261                 if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
 262                         return PCIBIOS_DEVICE_NOT_FOUND;
 263 #endif
 264         /* We explicitly do not go past the Tundra 320 Bridge */
 265         if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
 266                 return PCIBIOS_DEVICE_NOT_FOUND;
 267         if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
 268                 return PCIBIOS_DEVICE_NOT_FOUND;
 269         else
 270                 return PCIBIOS_SUCCESSFUL;
 271 }
 272
 273 void __init
 274 mpc85xx_cds_enable_via(struct pci_controller *hose)
 275 {
 276         u32 pci_class;
 277         u16 vid, did;
 278
 279         early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
 280         if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
 281                 return;
 282
 283         /* Configure P2P so that we can reach bus 1 */
 284         early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
 285         early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
 286         early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
 287
 288         early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
 289         early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
 290
 291         if ((vid != PCI_VENDOR_ID_VIA) ||
 292                         (did != PCI_DEVICE_ID_VIA_82C686))
 293                 return;
 294
 295         /* Enable USB and IDE functions */
 296         early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
 297 }
 298
 299 void __init
 300 mpc85xx_cds_fixup_via(struct pci_controller *hose)
 301 {
 302         u32 pci_class;
 303         u16 vid, did;
 304
 305         early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
 306         if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
 307                 return;
 308
 309         /*
 310          * Force the backplane P2P bridge to have a window
 311          * open from 0x00000000-0x00001fff in PCI I/O space.
 312          * This allows legacy I/O (i8259, etc) on the VIA
 313          * southbridge to be accessed.
 314          */
 315         early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
 316         early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
 317         early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
 318         early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
 319
 320         early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
 321         early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
 322         if ((vid != PCI_VENDOR_ID_VIA) ||
 323                         (did != PCI_DEVICE_ID_VIA_82C686))
 324                 return;
 325
 326         /*
 327          * Since the P2P window was forced to cover the fixed
 328          * legacy I/O addresses, it is necessary to manually
 329          * place the base addresses for the IDE and USB functions
 330          * within this window.
 331          */
 332         /* Function 1, IDE */
 333         early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
 334         early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
 335         early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
 336         early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
 337         early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
 338
 339         /* Function 2, USB ports 0-1 */
 340         early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
 341
 342         /* Function 3, USB ports 2-3 */
 343         early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
 344
 345         /* Function 5, Power Management */
 346         early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
 347         early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
 348         early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
 349
 350         /* Function 6, AC97 Interface */
 351         early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
 352 }
 353
 354 void __init
 355 mpc85xx_cds_pcibios_fixup(void)
 356 {
 357         struct pci_dev *dev = NULL;
 358         u_char          c;
 359
 360         if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
 361                                         PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
 362                 /*
 363                  * U-Boot does not set the enable bits
 364                  * for the IDE device. Force them on here.
 365                  */
 366                 pci_read_config_byte(dev, 0x40, &c);
 367                 c |= 0x03; /* IDE: Chip Enable Bits */
 368                 pci_write_config_byte(dev, 0x40, c);
 369
 370                 /*
 371                  * Since only primary interface works, force the
 372                  * IDE function to standard primary IDE interrupt
 373                  * w/ 8259 offset
 374                  */
 375                 dev->irq = 14;
 376                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 377         }
 378
 379         /*
 380          * Force legacy USB interrupt routing
 381          */
 382         if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
 383                                         PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
 384                 dev->irq = 10;
 385                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
 386         }
 387
 388         if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
 389                                         PCI_DEVICE_ID_VIA_82C586_2, dev))) {
 390                 dev->irq = 11;
 391                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
 392         }
 393 }
 394 #endif /* CONFIG_PCI */
 395
 396 TODC_ALLOC();
 397
 398 /* ************************************************************************
 399  *
 400  * Setup the architecture
 401  *
 402  */
 403 static void __init
 404 mpc85xx_cds_setup_arch(void)
 405 {
 406         bd_t *binfo = (bd_t *) __res;
 407         unsigned int freq;
 408         struct gianfar_platform_data *pdata;
 409
 410         /* get the core frequency */
 411         freq = binfo->bi_intfreq;
 412
 413         printk("mpc85xx_cds_setup_arch\n");
 414
 415 #ifdef CONFIG_CPM2
 416         cpm2_reset();
 417 #endif
 418
 419         cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
 420         cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
 421         printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
 422
 423         /* Setup TODC access */
 424         TODC_INIT(TODC_TYPE_DS1743,
 425                         0,
 426                         0,
 427                         ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
 428                         8);
 429
 430         /* Set loops_per_jiffy to a half-way reasonable value,
 431            for use until calibrate_delay gets called. */
 432         loops_per_jiffy = freq / HZ;
 433
 434 #ifdef CONFIG_PCI
 435         /* VIA IDE configuration */
 436         ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
 437
 438         /* setup PCI host bridges */
 439         mpc85xx_setup_hose();
 440 #endif
 441
 442 #ifdef CONFIG_SERIAL_8250
 443         mpc85xx_early_serial_map();
 444 #endif
 445
 446 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 447         /* Invalidate the entry we stole earlier the serial ports
 448          * should be properly mapped */
 449         invalidate_tlbcam_entry(num_tlbcam_entries - 1);
 450 #endif
 451
 452         /* setup the board related information for the enet controllers */
 453         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
 454         if (pdata) {
 455                 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 456                 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
 457                 pdata->phyid = 0;
 458                 /* fixup phy address */
 459                 pdata->phy_reg_addr += binfo->bi_immr_base;
 460                 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
 461         }
 462
 463         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
 464         if (pdata) {
 465                 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 466                 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
 467                 pdata->phyid = 1;
 468                 /* fixup phy address */
 469                 pdata->phy_reg_addr += binfo->bi_immr_base;
 470                 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
 471         }
 472
 473         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1);
 474         if (pdata) {
 475                 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 476                 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
 477                 pdata->phyid = 0;
 478                 /* fixup phy address */
 479                 pdata->phy_reg_addr += binfo->bi_immr_base;
 480                 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
 481         }
 482
 483         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2);
 484         if (pdata) {
 485                 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 486                 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
 487                 pdata->phyid = 1;
 488                 /* fixup phy address */
 489                 pdata->phy_reg_addr += binfo->bi_immr_base;
 490                 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
 491         }
 492
 493         ppc_sys_device_remove(MPC85xx_eTSEC3);
 494         ppc_sys_device_remove(MPC85xx_eTSEC4);
 495
 496 #ifdef CONFIG_BLK_DEV_INITRD
 497         if (initrd_start)
 498                 ROOT_DEV = Root_RAM0;
 499         else
 500 #endif
 501 #ifdef  CONFIG_ROOT_NFS
 502                 ROOT_DEV = Root_NFS;
 503 #else
 504         ROOT_DEV = Root_HDA1;
 505 #endif
 506 }
 507
 508 /* ************************************************************************ */
 509 void __init
 510 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 511               unsigned long r6, unsigned long r7)
 512 {
 513         /* parse_bootinfo must always be called first */
 514         parse_bootinfo(find_bootinfo());
 515
 516         /*
 517          * If we were passed in a board information, copy it into the
 518          * residual data area.
 519          */
 520         if (r3) {
 521                 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
 522                                 sizeof (bd_t));
 523
 524         }
 525 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 526         {
 527                 bd_t *binfo = (bd_t *) __res;
 528                 struct uart_port p;
 529
 530                 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
 531                 settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
 532                                 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
 533
 534                 memset(&p, 0, sizeof (p));
 535                 p.iotype = SERIAL_IO_MEM;
 536                 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
 537                 p.uartclk = binfo->bi_busfreq;
 538
 539                 gen550_init(0, &p);
 540
 541                 memset(&p, 0, sizeof (p));
 542                 p.iotype = SERIAL_IO_MEM;
 543                 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
 544                 p.uartclk = binfo->bi_busfreq;
 545
 546                 gen550_init(1, &p);
 547         }
 548 #endif
 549
 550 #if defined(CONFIG_BLK_DEV_INITRD)
 551         /*
 552          * If the init RAM disk has been configured in, and there's a valid
 553          * starting address for it, set it up.
 554          */
 555         if (r4) {
 556                 initrd_start = r4 + KERNELBASE;
 557                 initrd_end = r5 + KERNELBASE;
 558         }
 559 #endif /* CONFIG_BLK_DEV_INITRD */
 560
 561         /* Copy the kernel command line arguments to a safe place. */
 562
 563         if (r6) {
 564                 *(char *) (r7 + KERNELBASE) = 0;
 565                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 566         }
 567
 568         identify_ppc_sys_by_id(mfspr(SPRN_SVR));
 569
 570         /* setup the PowerPC module struct */
 571         ppc_md.setup_arch = mpc85xx_cds_setup_arch;
 572         ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
 573
 574         ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
 575         ppc_md.get_irq = openpic_get_irq;
 576
 577         ppc_md.restart = mpc85xx_restart;
 578         ppc_md.power_off = mpc85xx_power_off;
 579         ppc_md.halt = mpc85xx_halt;
 580
 581         ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
 582
 583         ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
 584
 585         ppc_md.time_init = todc_time_init;
 586         ppc_md.set_rtc_time = todc_set_rtc_time;
 587         ppc_md.get_rtc_time = todc_get_rtc_time;
 588
 589         ppc_md.nvram_read_val = todc_direct_read_val;
 590         ppc_md.nvram_write_val = todc_direct_write_val;
 591
 592 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
 593         ppc_md.progress = gen550_progress;
 594 #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
 595 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
 596         ppc_md.early_serial_map = mpc85xx_early_serial_map;
 597 #endif  /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
 598
 599         if (ppc_md.progress)
 600                 ppc_md.progress("mpc85xx_cds_init(): exit", 0);
 601
 602         return;
 603 }