1 comment "Processor Type"
3 # Select CPU types depending on the architecture selected. This selects
4 # which CPUs we support in the kernel image, and the compiler instruction
9 bool "Support ARM610 processor" if ARCH_RPC
14 select CPU_COPY_V3 if MMU
15 select CPU_TLB_V3 if MMU
16 select CPU_PABRT_LEGACY
18 The ARM610 is the successor to the ARM3 processor
19 and was produced by VLSI Technology Inc.
21 Say Y if you want support for the ARM610 processor.
26 bool "Support ARM7TDMI processor"
30 select CPU_PABRT_LEGACY
33 A 32-bit RISC microprocessor based on the ARM7 processor core
34 which has no memory control unit and cache.
36 Say Y if you want support for the ARM7TDMI processor.
41 bool "Support ARM710 processor" if ARCH_RPC
46 select CPU_COPY_V3 if MMU
47 select CPU_TLB_V3 if MMU
48 select CPU_PABRT_LEGACY
50 A 32-bit RISC microprocessor based on the ARM7 processor core
51 designed by Advanced RISC Machines Ltd. The ARM710 is the
52 successor to the ARM610 processor. It was released in
53 July 1994 by VLSI Technology Inc.
55 Say Y if you want support for the ARM710 processor.
60 bool "Support ARM720T processor" if ARCH_INTEGRATOR
63 select CPU_PABRT_LEGACY
67 select CPU_COPY_V4WT if MMU
68 select CPU_TLB_V4WT if MMU
70 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
71 MMU built around an ARM7TDMI core.
73 Say Y if you want support for the ARM720T processor.
78 bool "Support ARM740T processor" if ARCH_INTEGRATOR
82 select CPU_PABRT_LEGACY
83 select CPU_CACHE_V3 # although the core is v4t
86 A 32-bit RISC processor with 8KB cache or 4KB variants,
87 write buffer and MPU(Protection Unit) built around
90 Say Y if you want support for the ARM740T processor.
95 bool "Support ARM9TDMI processor"
99 select CPU_PABRT_LEGACY
102 A 32-bit RISC microprocessor based on the ARM9 processor core
103 which has no memory control unit and cache.
105 Say Y if you want support for the ARM9TDMI processor.
110 bool "Support ARM920T processor" if ARCH_INTEGRATOR
113 select CPU_PABRT_LEGACY
114 select CPU_CACHE_V4WT
115 select CPU_CACHE_VIVT
117 select CPU_COPY_V4WB if MMU
118 select CPU_TLB_V4WBI if MMU
120 The ARM920T is licensed to be produced by numerous vendors,
121 and is used in the Cirrus EP93xx and the Samsung S3C2410.
123 Say Y if you want support for the ARM920T processor.
128 bool "Support ARM922T processor" if ARCH_INTEGRATOR
131 select CPU_PABRT_LEGACY
132 select CPU_CACHE_V4WT
133 select CPU_CACHE_VIVT
135 select CPU_COPY_V4WB if MMU
136 select CPU_TLB_V4WBI if MMU
138 The ARM922T is a version of the ARM920T, but with smaller
139 instruction and data caches. It is used in Altera's
140 Excalibur XA device family and Micrel's KS8695 Centaur.
142 Say Y if you want support for the ARM922T processor.
147 bool "Support ARM925T processor" if ARCH_OMAP1
150 select CPU_PABRT_LEGACY
151 select CPU_CACHE_V4WT
152 select CPU_CACHE_VIVT
154 select CPU_COPY_V4WB if MMU
155 select CPU_TLB_V4WBI if MMU
157 The ARM925T is a mix between the ARM920T and ARM926T, but with
158 different instruction and data caches. It is used in TI's OMAP
161 Say Y if you want support for the ARM925T processor.
166 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
168 select CPU_ABRT_EV5TJ
169 select CPU_PABRT_LEGACY
170 select CPU_CACHE_VIVT
172 select CPU_COPY_V4WB if MMU
173 select CPU_TLB_V4WBI if MMU
175 This is a variant of the ARM920. It has slightly different
176 instruction sequences for cache and TLB operations. Curiously,
177 there is no documentation on it at the ARM corporate website.
179 Say Y if you want support for the ARM926T processor.
187 select CPU_PABRT_LEGACY
188 select CPU_CACHE_VIVT
191 select CPU_COPY_FA if MMU
192 select CPU_TLB_FA if MMU
194 The FA526 is a version of the ARMv4 compatible processor with
195 Branch Target Buffer, Unified TLB and cache line size 16.
197 Say Y if you want support for the FA526 processor.
202 bool "Support ARM940T processor" if ARCH_INTEGRATOR
205 select CPU_ABRT_NOMMU
206 select CPU_PABRT_LEGACY
207 select CPU_CACHE_VIVT
210 ARM940T is a member of the ARM9TDMI family of general-
211 purpose microprocessors with MPU and separate 4KB
212 instruction and 4KB data cases, each with a 4-word line
215 Say Y if you want support for the ARM940T processor.
220 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
223 select CPU_ABRT_NOMMU
224 select CPU_PABRT_LEGACY
225 select CPU_CACHE_VIVT
228 ARM946E-S is a member of the ARM9E-S family of high-
229 performance, 32-bit system-on-chip processor solutions.
230 The TCM and ARMv5TE 32-bit instruction set is supported.
232 Say Y if you want support for the ARM946E-S processor.
235 # ARM1020 - needs validating
237 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
240 select CPU_PABRT_LEGACY
241 select CPU_CACHE_V4WT
242 select CPU_CACHE_VIVT
244 select CPU_COPY_V4WB if MMU
245 select CPU_TLB_V4WBI if MMU
247 The ARM1020 is the 32K cached version of the ARM10 processor,
248 with an addition of a floating-point unit.
250 Say Y if you want support for the ARM1020 processor.
253 # ARM1020E - needs validating
255 bool "Support ARM1020E processor" if ARCH_INTEGRATOR
258 select CPU_PABRT_LEGACY
259 select CPU_CACHE_V4WT
260 select CPU_CACHE_VIVT
262 select CPU_COPY_V4WB if MMU
263 select CPU_TLB_V4WBI if MMU
268 bool "Support ARM1022E processor" if ARCH_INTEGRATOR
271 select CPU_PABRT_LEGACY
272 select CPU_CACHE_VIVT
274 select CPU_COPY_V4WB if MMU # can probably do better
275 select CPU_TLB_V4WBI if MMU
277 The ARM1022E is an implementation of the ARMv5TE architecture
278 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
279 embedded trace macrocell, and a floating-point unit.
281 Say Y if you want support for the ARM1022E processor.
286 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
288 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
289 select CPU_PABRT_LEGACY
290 select CPU_CACHE_VIVT
292 select CPU_COPY_V4WB if MMU # can probably do better
293 select CPU_TLB_V4WBI if MMU
295 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
296 based upon the ARM10 integer core.
298 Say Y if you want support for the ARM1026EJ-S processor.
303 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
304 select CPU_32v3 if ARCH_RPC
305 select CPU_32v4 if !ARCH_RPC
307 select CPU_PABRT_LEGACY
308 select CPU_CACHE_V4WB
309 select CPU_CACHE_VIVT
311 select CPU_COPY_V4WB if MMU
312 select CPU_TLB_V4WB if MMU
314 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
315 is available at five speeds ranging from 100 MHz to 233 MHz.
316 More information is available at
317 <http://developer.intel.com/design/strong/sa110.htm>.
319 Say Y if you want support for the SA-110 processor.
327 select CPU_PABRT_LEGACY
328 select CPU_CACHE_V4WB
329 select CPU_CACHE_VIVT
331 select CPU_TLB_V4WB if MMU
338 select CPU_PABRT_LEGACY
339 select CPU_CACHE_VIVT
341 select CPU_TLB_V4WBI if MMU
343 # XScale Core Version 3
348 select CPU_PABRT_LEGACY
349 select CPU_CACHE_VIVT
351 select CPU_TLB_V4WBI if MMU
354 # Marvell PJ1 (Mohawk)
359 select CPU_PABRT_LEGACY
360 select CPU_CACHE_VIVT
362 select CPU_TLB_V4WBI if MMU
363 select CPU_COPY_V4WB if MMU
370 select CPU_PABRT_LEGACY
371 select CPU_CACHE_VIVT
373 select CPU_COPY_FEROCEON if MMU
374 select CPU_TLB_FEROCEON if MMU
376 config CPU_FEROCEON_OLD_ID
377 bool "Accept early Feroceon cores with an ARM926 ID"
378 depends on CPU_FEROCEON && !CPU_ARM926T
381 This enables the usage of some old Feroceon cores
382 for which the CPU ID is equal to the ARM926 ID.
383 Relevant for Feroceon-1850 and early Feroceon-2850.
393 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
398 select CPU_CACHE_VIPT
400 select CPU_HAS_ASID if MMU
401 select CPU_COPY_V6 if MMU
402 select CPU_TLB_V6 if MMU
406 bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
412 select CPU_CACHE_VIPT
414 select CPU_HAS_ASID if MMU
415 select CPU_COPY_V6 if MMU
416 select CPU_TLB_V6 if MMU
420 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
426 select CPU_CACHE_VIPT
428 select CPU_HAS_ASID if MMU
429 select CPU_COPY_V6 if MMU
430 select CPU_TLB_V7 if MMU
432 # Figure out what processor architecture version we should be using.
433 # This defines the compiler instruction set which depends on the machine type.
436 select TLS_REG_EMUL if SMP || !MMU
437 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
438 select CPU_USE_DOMAINS if MMU
442 select TLS_REG_EMUL if SMP || !MMU
443 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444 select CPU_USE_DOMAINS if MMU
448 select TLS_REG_EMUL if SMP || !MMU
449 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
450 select CPU_USE_DOMAINS if MMU
454 select TLS_REG_EMUL if SMP || !MMU
455 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
456 select CPU_USE_DOMAINS if MMU
460 select TLS_REG_EMUL if !CPU_32v6K && !MMU
461 select CPU_USE_DOMAINS if CPU_V6 && MMU
470 config CPU_ABRT_NOMMU
485 config CPU_ABRT_EV5TJ
494 config CPU_PABRT_LEGACY
510 config CPU_CACHE_V4WT
513 config CPU_CACHE_V4WB
522 config CPU_CACHE_VIVT
525 config CPU_CACHE_VIPT
532 # The copy-page model
542 config CPU_COPY_FEROCEON
551 # This selects the TLB model
555 ARM Architecture Version 3 TLB.
560 ARM Architecture Version 4 TLB with writethrough cache.
565 ARM Architecture Version 4 TLB with writeback cache.
570 ARM Architecture Version 4 TLB with writeback cache and invalidate
571 instruction cache entry.
573 config CPU_TLB_FEROCEON
576 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
581 Faraday ARM FA526 architecture, unified TLB with writeback cache
582 and invalidate instruction cache entry. Branch target buffer is
591 config VERIFY_PERMISSION_FAULT
598 This indicates whether the CPU has the ASID register; used to
599 tag TLB and possibly cache entries.
604 Processor has the CP15 register.
610 Processor has the CP15 register, which has MMU related registers.
616 Processor has the CP15 register, which has MPU related registers.
618 config CPU_USE_DOMAINS
621 This option enables or disables the use of domain switching
622 via the set_fs() function.
625 # CPU supports 36-bit I/O
630 comment "Processor Features"
633 bool "Support Thumb user binaries"
634 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
637 Say Y if you want to include kernel support for running user space
640 The Thumb instruction set is a compressed form of the standard ARM
641 instruction set resulting in smaller binaries at the expense of
642 slightly less efficient code.
644 If you don't know what this all is, saying Y is a safe choice.
647 bool "Enable ThumbEE CPU extension"
650 Say Y here if you have a CPU with the ThumbEE extension and code to
651 make use of it. Say N for code that can run on CPUs without ThumbEE.
654 bool "Emulate SWP/SWPB instructions"
655 depends on !CPU_USE_DOMAINS && CPU_V7
656 select HAVE_PROC_CPU if PROC_FS
659 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
660 ARMv7 multiprocessing extensions introduce the ability to disable
661 these instructions, triggering an undefined instruction exception
662 when executed. Say Y here to enable software emulation of these
663 instructions for userspace (not kernel) using LDREX/STREX.
664 Also creates /proc/cpu/swp_emulation for statistics.
666 In some older versions of glibc [<=2.8] SWP is used during futex
667 trylock() operations with the assumption that the code will not
668 be preempted. This invalid assumption may be more likely to fail
669 with SWP emulation enabled, leading to deadlock of the user
672 NOTE: when accessing uncached shared regions, LDREX/STREX rely
673 on an external transaction monitoring block called a global
674 monitor to maintain update atomicity. If your system does not
675 implement a global monitor, this option can cause programs that
676 perform SWP operations to uncached memory to deadlock.
680 config CPU_BIG_ENDIAN
681 bool "Build big-endian kernel"
682 depends on ARCH_SUPPORTS_BIG_ENDIAN
684 Say Y if you plan on running a kernel in big-endian mode.
685 Note that your board must be properly built and your board
686 port must properly enable any big-endian related features
687 of your chipset/board/processor.
689 config CPU_ENDIAN_BE8
691 depends on CPU_BIG_ENDIAN
692 default CPU_V6 || CPU_V6K || CPU_V7
694 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
696 config CPU_ENDIAN_BE32
698 depends on CPU_BIG_ENDIAN
699 default !CPU_ENDIAN_BE8
701 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
703 config CPU_HIGH_VECTOR
704 depends on !MMU && CPU_CP15 && !CPU_ARM740T
705 bool "Select the High exception vector"
707 Say Y here to select high exception vector(0xFFFF0000~).
708 The exception vector can be vary depending on the platform
709 design in nommu mode. If your platform needs to select
710 high exception vector, say Y.
711 Otherwise or if you are unsure, say N, and the low exception
712 vector (0x00000000~) will be used.
714 config CPU_ICACHE_DISABLE
715 bool "Disable I-Cache (I-bit)"
716 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
718 Say Y here to disable the processor instruction cache. Unless
719 you have a reason not to or are unsure, say N.
721 config CPU_DCACHE_DISABLE
722 bool "Disable D-Cache (C-bit)"
725 Say Y here to disable the processor data cache. Unless
726 you have a reason not to or are unsure, say N.
728 config CPU_DCACHE_SIZE
730 depends on CPU_ARM740T || CPU_ARM946E
731 default 0x00001000 if CPU_ARM740T
732 default 0x00002000 # default size for ARM946E-S
734 Some cores are synthesizable to have various sized cache. For
735 ARM946E-S case, it can vary from 0KB to 1MB.
736 To support such cache operations, it is efficient to know the size
738 If your SoC is configured to have a different size, define the value
739 here with proper conditions.
741 config CPU_DCACHE_WRITETHROUGH
742 bool "Force write through D-cache"
743 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
744 default y if CPU_ARM925T
746 Say Y here to use the data cache in writethrough mode. Unless you
747 specifically require this or are unsure, say N.
749 config CPU_CACHE_ROUND_ROBIN
750 bool "Round robin I and D cache replacement algorithm"
751 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
753 Say Y here to use the predictable round-robin cache replacement
754 policy. Unless you specifically require this or are unsure, say N.
756 config CPU_BPREDICT_DISABLE
757 bool "Disable branch prediction"
758 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
760 Say Y here to disable branch prediction. If unsure, say N.
765 An SMP system using a pre-ARMv6 processor (there are apparently
766 a few prototypes like that in existence) and therefore access to
767 that required register must be emulated.
769 config NEEDS_SYSCALL_FOR_CMPXCHG
772 SMP on a pre-ARMv6 processor? Well OK then.
773 Forget about fast user space cmpxchg support.
774 It is just not possible.
776 config DMA_CACHE_RWFO
777 bool "Enable read/write for ownership DMA cache maintenance"
778 depends on CPU_V6K && SMP
781 The Snoop Control Unit on ARM11MPCore does not detect the
782 cache maintenance operations and the dma_{map,unmap}_area()
783 functions may leave stale cache entries on other CPUs. By
784 enabling this option, Read or Write For Ownership in the ARMv6
785 DMA cache maintenance functions is performed. These LDR/STR
786 instructions change the cache line state to shared or modified
787 so that the cache operation has the desired effect.
789 Note that the workaround is only valid on processors that do
790 not perform speculative loads into the D-cache. For such
791 processors, if cache maintenance operations are not broadcast
792 in hardware, other workarounds are needed (e.g. cache
793 maintenance broadcasting in software via FIQ).
798 config OUTER_CACHE_SYNC
801 The outer cache has a outer_cache_fns.sync function pointer
802 that can be used to drain the write buffer of the outer cache.
804 config CACHE_FEROCEON_L2
805 bool "Enable the Feroceon L2 cache controller"
806 depends on ARCH_KIRKWOOD || ARCH_MV78XX0
810 This option enables the Feroceon L2 cache controller.
812 config CACHE_FEROCEON_L2_WRITETHROUGH
813 bool "Force Feroceon L2 cache write through"
814 depends on CACHE_FEROCEON_L2
816 Say Y here to use the Feroceon L2 cache in writethrough mode.
817 Unless you specifically require this, say N for writeback mode.
820 bool "Enable the L2x0 outer cache controller"
821 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
822 REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
823 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
824 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
825 ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
828 select OUTER_CACHE_SYNC
830 This option enables the L2x0 PrimeCell.
834 depends on CACHE_L2X0
835 default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
837 This option enables optimisations for the PL310 cache
841 bool "Enable the Tauros2 L2 cache controller"
842 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
846 This option enables the Tauros2 L2 cache controller (as
850 bool "Enable the L2 cache on XScale3"
855 This option enables the L2 cache on XScale3.
857 config ARM_L1_CACHE_SHIFT_6
860 Setting ARM L1 cache line size to 64 Bytes.
862 config ARM_L1_CACHE_SHIFT
864 default 6 if ARM_L1_CACHE_SHIFT_6
867 config ARM_DMA_MEM_BUFFERABLE
868 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
869 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
870 MACH_REALVIEW_PB11MP)
871 default y if CPU_V6 || CPU_V6K || CPU_V7
873 Historically, the kernel has used strongly ordered mappings to
874 provide DMA coherent memory. With the advent of ARMv7, mapping
875 memory with differing types results in unpredictable behaviour,
876 so on these CPUs, this option is forced on.
878 Multiple mappings with differing attributes is also unpredictable
879 on ARMv6 CPUs, but since they do not have aggressive speculative
880 prefetch, no harm appears to occur.
882 However, drivers may be missing the necessary barriers for ARMv6,
883 and therefore turning this on may result in unpredictable driver
884 behaviour. Therefore, we offer this as an option.
886 You are recommended say 'Y' here and debug any affected drivers.
888 config ARCH_HAS_BARRIERS
891 This option allows the use of custom mandatory barriers
892 included via the mach/barriers.h file.