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[linux-2.6/libata-dev.git] / arch / arm / mach-ux500 / cache-l2x0.c
blob122ddde00ba78deabf82db84273705598ffda34e
1 /*
2 * Copyright (C) ST-Ericsson SA 2011
4 * License terms: GNU General Public License (GPL) version 2
5 */
7 #include <linux/io.h>
8 #include <asm/cacheflush.h>
9 #include <asm/hardware/cache-l2x0.h>
10 #include <mach/hardware.h>
11 #include <mach/id.h>
13 static void __iomem *l2x0_base;
15 static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
17 /* wait for the operation to complete */
18 while (readl_relaxed(reg) & mask)
19 cpu_relax();
22 static inline void ux500_cache_sync(void)
24 writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC);
25 ux500_cache_wait(l2x0_base + L2X0_CACHE_SYNC, 1);
29 * The L2 cache cannot be turned off in the non-secure world.
30 * Dummy until a secure service is in place.
32 static void ux500_l2x0_disable(void)
37 * This is only called when doing a kexec, just after turning off the L2
38 * and L1 cache, and it is surrounded by a spinlock in the generic version.
39 * However, we're not really turning off the L2 cache right now and the
40 * PL310 does not support exclusive accesses (used to implement the spinlock).
41 * So, the invalidation needs to be done without the spinlock.
43 static void ux500_l2x0_inv_all(void)
45 uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
47 /* invalidate all ways */
48 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
49 ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
50 ux500_cache_sync();
53 static int __init ux500_l2x0_unlock(void)
55 int i;
58 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
59 * apparently locks both caches before jumping to the kernel. The
60 * l2x0 core will not touch the unlock registers if the l2x0 is
61 * already enabled, so we do it right here instead. The PL310 has
62 * 8 sets of registers, one per possible CPU.
64 for (i = 0; i < 8; i++) {
65 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
66 i * L2X0_LOCKDOWN_STRIDE);
67 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
68 i * L2X0_LOCKDOWN_STRIDE);
70 return 0;
73 static int __init ux500_l2x0_init(void)
75 if (cpu_is_u5500())
76 l2x0_base = __io_address(U5500_L2CC_BASE);
77 else if (cpu_is_u8500())
78 l2x0_base = __io_address(U8500_L2CC_BASE);
79 else
80 ux500_unknown_soc();
82 /* Unlock before init */
83 ux500_l2x0_unlock();
85 /* 64KB way size, 8 way associativity, force WA */
86 l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
88 /* Override invalidate function */
89 outer_cache.disable = ux500_l2x0_disable;
90 outer_cache.inv_all = ux500_l2x0_inv_all;
92 return 0;
95 early_initcall(ux500_l2x0_init);