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Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel...
[linux-2.6/libata-dev.git] / drivers / gpu / drm / i915 / intel_display.c
blob5d127e0689501e225316424a242b726c20ca6376
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58 } intel_clock_t;
59
60 typedef struct {
61 int min, max;
62 } intel_range_t;
63
64 typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
76 };
77
78 /* FDI */
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
81 int
82 intel_pch_rawclk(struct drm_device *dev)
83 {
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89 }
90
91 static bool
92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
95 static bool
96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
99
100 static bool
101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
104 static bool
105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
109 static bool
110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
114 static inline u32 /* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device *dev)
116 {
117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
122 }
123
124 static const intel_limit_t intel_limits_i8xx_dvo = {
125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
135 .find_pll = intel_find_best_PLL,
136 };
137
138 static const intel_limit_t intel_limits_i8xx_lvds = {
139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
149 .find_pll = intel_find_best_PLL,
150 };
151
152 static const intel_limit_t intel_limits_i9xx_sdvo = {
153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
163 .find_pll = intel_find_best_PLL,
164 };
165
166 static const intel_limit_t intel_limits_i9xx_lvds = {
167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
177 .find_pll = intel_find_best_PLL,
178 };
179
180
181 static const intel_limit_t intel_limits_g4x_sdvo = {
182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
193 },
194 .find_pll = intel_g4x_find_best_PLL,
195 };
196
197 static const intel_limit_t intel_limits_g4x_hdmi = {
198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
208 .find_pll = intel_g4x_find_best_PLL,
209 };
210
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
222 },
223 .find_pll = intel_g4x_find_best_PLL,
224 };
225
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
237 },
238 .find_pll = intel_g4x_find_best_PLL,
239 };
240
241 static const intel_limit_t intel_limits_g4x_display_port = {
242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 10, .p2_fast = 10 },
252 .find_pll = intel_find_pll_g4x_dp,
253 };
254
255 static const intel_limit_t intel_limits_pineview_sdvo = {
256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
258 /* Pineview's Ncounter is a ring counter */
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 /* Pineview only has one combined m divider, which we treat as m2. */
262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
268 .find_pll = intel_find_best_PLL,
269 };
270
271 static const intel_limit_t intel_limits_pineview_lvds = {
272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
282 .find_pll = intel_find_best_PLL,
283 };
284
285 /* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
290 static const intel_limit_t intel_limits_ironlake_dac = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
301 .find_pll = intel_g4x_find_best_PLL,
302 };
303
304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
315 .find_pll = intel_g4x_find_best_PLL,
316 };
317
318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
329 .find_pll = intel_g4x_find_best_PLL,
330 };
331
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
344 .find_pll = intel_g4x_find_best_PLL,
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 .find_pll = intel_g4x_find_best_PLL,
359 };
360
361 static const intel_limit_t intel_limits_ironlake_display_port = {
362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
371 .p2_slow = 10, .p2_fast = 10 },
372 .find_pll = intel_find_pll_ironlake_dp,
373 };
374
375 static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387 };
388
389 static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
391 .vco = { .min = 4000000, .max = 5994000},
392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401 };
402
403 static const intel_limit_t intel_limits_vlv_dp = {
404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
406 .n = { .min = 1, .max = 7 },
407 .m = { .min = 22, .max = 450 },
408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415 };
416
417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418 {
419 unsigned long flags;
420 u32 val = 0;
421
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
425 goto out_unlock;
426 }
427
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430 DPIO_BYTE);
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
433 goto out_unlock;
434 }
435 val = I915_READ(DPIO_DATA);
436
437 out_unlock:
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439 return val;
440 }
441
442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443 u32 val)
444 {
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
450 goto out_unlock;
451 }
452
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456 DPIO_BYTE);
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
459
460 out_unlock:
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462 }
463
464 static void vlv_init_dpio(struct drm_device *dev)
465 {
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
473 }
474
475 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
476 {
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
478 return 1;
479 }
480
481 static const struct dmi_system_id intel_dual_link_lvds[] = {
482 {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
485 .matches = {
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
488 },
489 },
490 { } /* terminating entry */
491 };
492
493 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
494 unsigned int reg)
495 {
496 unsigned int val;
497
498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
501
502 if (dmi_check_system(intel_dual_link_lvds))
503 return true;
504
505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
507 else {
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
512 */
513 val = I915_READ(reg);
514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
517 }
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
519 }
520
521 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
522 int refclk)
523 {
524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
526 const intel_limit_t *limit;
527
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
530 /* LVDS dual channel */
531 if (refclk == 100000)
532 limit = &intel_limits_ironlake_dual_lvds_100m;
533 else
534 limit = &intel_limits_ironlake_dual_lvds;
535 } else {
536 if (refclk == 100000)
537 limit = &intel_limits_ironlake_single_lvds_100m;
538 else
539 limit = &intel_limits_ironlake_single_lvds;
540 }
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
543 limit = &intel_limits_ironlake_display_port;
544 else
545 limit = &intel_limits_ironlake_dac;
546
547 return limit;
548 }
549
550 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
551 {
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 if (is_dual_link_lvds(dev_priv, LVDS))
558 /* LVDS with dual channel */
559 limit = &intel_limits_g4x_dual_channel_lvds;
560 else
561 /* LVDS with dual channel */
562 limit = &intel_limits_g4x_single_channel_lvds;
563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
565 limit = &intel_limits_g4x_hdmi;
566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
567 limit = &intel_limits_g4x_sdvo;
568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
569 limit = &intel_limits_g4x_display_port;
570 } else /* The option is for other outputs */
571 limit = &intel_limits_i9xx_sdvo;
572
573 return limit;
574 }
575
576 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
577 {
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
580
581 if (HAS_PCH_SPLIT(dev))
582 limit = intel_ironlake_limit(crtc, refclk);
583 else if (IS_G4X(dev)) {
584 limit = intel_g4x_limit(crtc);
585 } else if (IS_PINEVIEW(dev)) {
586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
587 limit = &intel_limits_pineview_lvds;
588 else
589 limit = &intel_limits_pineview_sdvo;
590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
595 else
596 limit = &intel_limits_vlv_dp;
597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
600 else
601 limit = &intel_limits_i9xx_sdvo;
602 } else {
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
604 limit = &intel_limits_i8xx_lvds;
605 else
606 limit = &intel_limits_i8xx_dvo;
607 }
608 return limit;
609 }
610
611 /* m1 is reserved as 0 in Pineview, n is a ring counter */
612 static void pineview_clock(int refclk, intel_clock_t *clock)
613 {
614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
618 }
619
620 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
621 {
622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
624 return;
625 }
626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
630 }
631
632 /**
633 * Returns whether any output on the specified pipe is of the specified type
634 */
635 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
636 {
637 struct drm_device *dev = crtc->dev;
638 struct intel_encoder *encoder;
639
640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
642 return true;
643
644 return false;
645 }
646
647 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
648 /**
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
651 */
652
653 static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
656 {
657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
658 INTELPllInvalid("p1 out of range\n");
659 if (clock->p < limit->p.min || limit->p.max < clock->p)
660 INTELPllInvalid("p out of range\n");
661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
662 INTELPllInvalid("m2 out of range\n");
663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
664 INTELPllInvalid("m1 out of range\n");
665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
666 INTELPllInvalid("m1 <= m2\n");
667 if (clock->m < limit->m.min || limit->m.max < clock->m)
668 INTELPllInvalid("m out of range\n");
669 if (clock->n < limit->n.min || limit->n.max < clock->n)
670 INTELPllInvalid("n out of range\n");
671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
672 INTELPllInvalid("vco out of range\n");
673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
675 */
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
677 INTELPllInvalid("dot out of range\n");
678
679 return true;
680 }
681
682 static bool
683 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
686
687 {
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 intel_clock_t clock;
691 int err = target;
692
693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
694 (I915_READ(LVDS)) != 0) {
695 /*
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
699 * even can.
700 */
701 if (is_dual_link_lvds(dev_priv, LVDS))
702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
712 memset(best_clock, 0, sizeof(*best_clock));
713
714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
718 /* m1 is always 0 in Pineview */
719 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
720 break;
721 for (clock.n = limit->n.min;
722 clock.n <= limit->n.max; clock.n++) {
723 for (clock.p1 = limit->p1.min;
724 clock.p1 <= limit->p1.max; clock.p1++) {
725 int this_err;
726
727 intel_clock(dev, refclk, &clock);
728 if (!intel_PLL_is_valid(dev, limit,
729 &clock))
730 continue;
731 if (match_clock &&
732 clock.p != match_clock->p)
733 continue;
734
735 this_err = abs(clock.dot - target);
736 if (this_err < err) {
737 *best_clock = clock;
738 err = this_err;
739 }
740 }
741 }
742 }
743 }
744
745 return (err != target);
746 }
747
748 static bool
749 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
752 {
753 struct drm_device *dev = crtc->dev;
754 struct drm_i915_private *dev_priv = dev->dev_private;
755 intel_clock_t clock;
756 int max_n;
757 bool found;
758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
760 found = false;
761
762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
763 int lvds_reg;
764
765 if (HAS_PCH_SPLIT(dev))
766 lvds_reg = PCH_LVDS;
767 else
768 lvds_reg = LVDS;
769 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
770 LVDS_CLKB_POWER_UP)
771 clock.p2 = limit->p2.p2_fast;
772 else
773 clock.p2 = limit->p2.p2_slow;
774 } else {
775 if (target < limit->p2.dot_limit)
776 clock.p2 = limit->p2.p2_slow;
777 else
778 clock.p2 = limit->p2.p2_fast;
779 }
780
781 memset(best_clock, 0, sizeof(*best_clock));
782 max_n = limit->n.max;
783 /* based on hardware requirement, prefer smaller n to precision */
784 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
785 /* based on hardware requirement, prefere larger m1,m2 */
786 for (clock.m1 = limit->m1.max;
787 clock.m1 >= limit->m1.min; clock.m1--) {
788 for (clock.m2 = limit->m2.max;
789 clock.m2 >= limit->m2.min; clock.m2--) {
790 for (clock.p1 = limit->p1.max;
791 clock.p1 >= limit->p1.min; clock.p1--) {
792 int this_err;
793
794 intel_clock(dev, refclk, &clock);
795 if (!intel_PLL_is_valid(dev, limit,
796 &clock))
797 continue;
798 if (match_clock &&
799 clock.p != match_clock->p)
800 continue;
801
802 this_err = abs(clock.dot - target);
803 if (this_err < err_most) {
804 *best_clock = clock;
805 err_most = this_err;
806 max_n = clock.n;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813 return found;
814 }
815
816 static bool
817 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
820 {
821 struct drm_device *dev = crtc->dev;
822 intel_clock_t clock;
823
824 if (target < 200000) {
825 clock.n = 1;
826 clock.p1 = 2;
827 clock.p2 = 10;
828 clock.m1 = 12;
829 clock.m2 = 9;
830 } else {
831 clock.n = 2;
832 clock.p1 = 1;
833 clock.p2 = 10;
834 clock.m1 = 14;
835 clock.m2 = 8;
836 }
837 intel_clock(dev, refclk, &clock);
838 memcpy(best_clock, &clock, sizeof(intel_clock_t));
839 return true;
840 }
841
842 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
843 static bool
844 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
845 int target, int refclk, intel_clock_t *match_clock,
846 intel_clock_t *best_clock)
847 {
848 intel_clock_t clock;
849 if (target < 200000) {
850 clock.p1 = 2;
851 clock.p2 = 10;
852 clock.n = 2;
853 clock.m1 = 23;
854 clock.m2 = 8;
855 } else {
856 clock.p1 = 1;
857 clock.p2 = 10;
858 clock.n = 1;
859 clock.m1 = 14;
860 clock.m2 = 2;
861 }
862 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863 clock.p = (clock.p1 * clock.p2);
864 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
865 clock.vco = 0;
866 memcpy(best_clock, &clock, sizeof(intel_clock_t));
867 return true;
868 }
869 static bool
870 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *match_clock,
872 intel_clock_t *best_clock)
873 {
874 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
875 u32 m, n, fastclk;
876 u32 updrate, minupdate, fracbits, p;
877 unsigned long bestppm, ppm, absppm;
878 int dotclk, flag;
879
880 flag = 0;
881 dotclk = target * 1000;
882 bestppm = 1000000;
883 ppm = absppm = 0;
884 fastclk = dotclk / (2*100);
885 updrate = 0;
886 minupdate = 19200;
887 fracbits = 1;
888 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889 bestm1 = bestm2 = bestp1 = bestp2 = 0;
890
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893 updrate = refclk / n;
894 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
896 if (p2 > 10)
897 p2 = p2 - 1;
898 p = p1 * p2;
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901 m2 = (((2*(fastclk * p * n / m1 )) +
902 refclk) / (2*refclk));
903 m = m1 * m2;
904 vco = updrate * m;
905 if (vco >= limit->vco.min && vco < limit->vco.max) {
906 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907 absppm = (ppm > 0) ? ppm : (-ppm);
908 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
909 bestppm = 0;
910 flag = 1;
911 }
912 if (absppm < bestppm - 10) {
913 bestppm = absppm;
914 flag = 1;
915 }
916 if (flag) {
917 bestn = n;
918 bestm1 = m1;
919 bestm2 = m2;
920 bestp1 = p1;
921 bestp2 = p2;
922 flag = 0;
923 }
924 }
925 }
926 }
927 }
928 }
929 best_clock->n = bestn;
930 best_clock->m1 = bestm1;
931 best_clock->m2 = bestm2;
932 best_clock->p1 = bestp1;
933 best_clock->p2 = bestp2;
934
935 return true;
936 }
937
938 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
939 enum pipe pipe)
940 {
941 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
943
944 return intel_crtc->cpu_transcoder;
945 }
946
947 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
948 {
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 frame, frame_reg = PIPEFRAME(pipe);
951
952 frame = I915_READ(frame_reg);
953
954 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
956 }
957
958 /**
959 * intel_wait_for_vblank - wait for vblank on a given pipe
960 * @dev: drm device
961 * @pipe: pipe to wait for
962 *
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
964 * mode setting code.
965 */
966 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
967 {
968 struct drm_i915_private *dev_priv = dev->dev_private;
969 int pipestat_reg = PIPESTAT(pipe);
970
971 if (INTEL_INFO(dev)->gen >= 5) {
972 ironlake_wait_for_vblank(dev, pipe);
973 return;
974 }
975
976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
978 *
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
985 * vblanks...
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
988 */
989 I915_WRITE(pipestat_reg,
990 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
991
992 /* Wait for vblank interrupt bit to set */
993 if (wait_for(I915_READ(pipestat_reg) &
994 PIPE_VBLANK_INTERRUPT_STATUS,
995 50))
996 DRM_DEBUG_KMS("vblank wait timed out\n");
997 }
998
999 /*
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
1001 * @dev: drm device
1002 * @pipe: pipe to wait for
1003 *
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1007 *
1008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1010 *
1011 * Otherwise:
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
1014 *
1015 */
1016 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1017 {
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020 pipe);
1021
1022 if (INTEL_INFO(dev)->gen >= 4) {
1023 int reg = PIPECONF(cpu_transcoder);
1024
1025 /* Wait for the Pipe State to go off */
1026 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027 100))
1028 WARN(1, "pipe_off wait timed out\n");
1029 } else {
1030 u32 last_line, line_mask;
1031 int reg = PIPEDSL(pipe);
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
1034 if (IS_GEN2(dev))
1035 line_mask = DSL_LINEMASK_GEN2;
1036 else
1037 line_mask = DSL_LINEMASK_GEN3;
1038
1039 /* Wait for the display line to settle */
1040 do {
1041 last_line = I915_READ(reg) & line_mask;
1042 mdelay(5);
1043 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044 time_after(timeout, jiffies));
1045 if (time_after(jiffies, timeout))
1046 WARN(1, "pipe_off wait timed out\n");
1047 }
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052 return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058 {
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069 }
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
1073 /* For ILK+ */
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075 struct intel_pch_pll *pll,
1076 struct intel_crtc *crtc,
1077 bool state)
1078 {
1079 u32 val;
1080 bool cur_state;
1081
1082 if (HAS_PCH_LPT(dev_priv->dev)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 return;
1085 }
1086
1087 if (WARN (!pll,
1088 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1089 return;
1090
1091 val = I915_READ(pll->pll_reg);
1092 cur_state = !!(val & DPLL_VCO_ENABLE);
1093 WARN(cur_state != state,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1099 u32 pch_dpll;
1100
1101 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state, crtc->pipe, pch_dpll)) {
1106 cur_state = !!(val >> (4*crtc->pipe + 3));
1107 WARN(cur_state != state,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll->pll_reg == _PCH_DPLL_B,
1110 state_string(state),
1111 crtc->pipe,
1112 val);
1113 }
1114 }
1115 }
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1118
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121 {
1122 int reg;
1123 u32 val;
1124 bool cur_state;
1125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126 pipe);
1127
1128 if (IS_HASWELL(dev_priv->dev)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133 } else {
1134 reg = FDI_TX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
1138 WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147 {
1148 int reg;
1149 u32 val;
1150 bool cur_state;
1151
1152 reg = FDI_RX_CTL(pipe);
1153 val = I915_READ(reg);
1154 cur_state = !!(val & FDI_RX_ENABLE);
1155 WARN(cur_state != state,
1156 "FDI RX state assertion failure (expected %s, current %s)\n",
1157 state_string(state), state_string(cur_state));
1158 }
1159 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161
1162 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164 {
1165 int reg;
1166 u32 val;
1167
1168 /* ILK FDI PLL is always enabled */
1169 if (dev_priv->info->gen == 5)
1170 return;
1171
1172 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173 if (IS_HASWELL(dev_priv->dev))
1174 return;
1175
1176 reg = FDI_TX_CTL(pipe);
1177 val = I915_READ(reg);
1178 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1179 }
1180
1181 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe)
1183 {
1184 int reg;
1185 u32 val;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1190 }
1191
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
1194 {
1195 int pp_reg, lvds_reg;
1196 u32 val;
1197 enum pipe panel_pipe = PIPE_A;
1198 bool locked = true;
1199
1200 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201 pp_reg = PCH_PP_CONTROL;
1202 lvds_reg = PCH_LVDS;
1203 } else {
1204 pp_reg = PP_CONTROL;
1205 lvds_reg = LVDS;
1206 }
1207
1208 val = I915_READ(pp_reg);
1209 if (!(val & PANEL_POWER_ON) ||
1210 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211 locked = false;
1212
1213 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214 panel_pipe = PIPE_B;
1215
1216 WARN(panel_pipe == pipe && locked,
1217 "panel assertion failure, pipe %c regs locked\n",
1218 pipe_name(pipe));
1219 }
1220
1221 void assert_pipe(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1223 {
1224 int reg;
1225 u32 val;
1226 bool cur_state;
1227 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228 pipe);
1229
1230 /* if we need the pipe A quirk it must be always on */
1231 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1232 state = true;
1233
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 WARN(cur_state != state,
1238 "pipe %c assertion failure (expected %s, current %s)\n",
1239 pipe_name(pipe), state_string(state), state_string(cur_state));
1240 }
1241
1242 static void assert_plane(struct drm_i915_private *dev_priv,
1243 enum plane plane, bool state)
1244 {
1245 int reg;
1246 u32 val;
1247 bool cur_state;
1248
1249 reg = DSPCNTR(plane);
1250 val = I915_READ(reg);
1251 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252 WARN(cur_state != state,
1253 "plane %c assertion failure (expected %s, current %s)\n",
1254 plane_name(plane), state_string(state), state_string(cur_state));
1255 }
1256
1257 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1259
1260 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1261 enum pipe pipe)
1262 {
1263 int reg, i;
1264 u32 val;
1265 int cur_pipe;
1266
1267 /* Planes are fixed to pipes on ILK+ */
1268 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269 reg = DSPCNTR(pipe);
1270 val = I915_READ(reg);
1271 WARN((val & DISPLAY_PLANE_ENABLE),
1272 "plane %c assertion failure, should be disabled but not\n",
1273 plane_name(pipe));
1274 return;
1275 }
1276
1277 /* Need to check both planes against the pipe */
1278 for (i = 0; i < 2; i++) {
1279 reg = DSPCNTR(i);
1280 val = I915_READ(reg);
1281 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282 DISPPLANE_SEL_PIPE_SHIFT;
1283 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1284 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285 plane_name(i), pipe_name(pipe));
1286 }
1287 }
1288
1289 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1290 {
1291 u32 val;
1292 bool enabled;
1293
1294 if (HAS_PCH_LPT(dev_priv->dev)) {
1295 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1296 return;
1297 }
1298
1299 val = I915_READ(PCH_DREF_CONTROL);
1300 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301 DREF_SUPERSPREAD_SOURCE_MASK));
1302 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1303 }
1304
1305 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1306 enum pipe pipe)
1307 {
1308 int reg;
1309 u32 val;
1310 bool enabled;
1311
1312 reg = TRANSCONF(pipe);
1313 val = I915_READ(reg);
1314 enabled = !!(val & TRANS_ENABLE);
1315 WARN(enabled,
1316 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1317 pipe_name(pipe));
1318 }
1319
1320 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, u32 port_sel, u32 val)
1322 {
1323 if ((val & DP_PORT_EN) == 0)
1324 return false;
1325
1326 if (HAS_PCH_CPT(dev_priv->dev)) {
1327 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1330 return false;
1331 } else {
1332 if ((val & DP_PIPE_MASK) != (pipe << 30))
1333 return false;
1334 }
1335 return true;
1336 }
1337
1338 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe, u32 val)
1340 {
1341 if ((val & PORT_ENABLE) == 0)
1342 return false;
1343
1344 if (HAS_PCH_CPT(dev_priv->dev)) {
1345 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1346 return false;
1347 } else {
1348 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1349 return false;
1350 }
1351 return true;
1352 }
1353
1354 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe, u32 val)
1356 {
1357 if ((val & LVDS_PORT_EN) == 0)
1358 return false;
1359
1360 if (HAS_PCH_CPT(dev_priv->dev)) {
1361 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1362 return false;
1363 } else {
1364 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1365 return false;
1366 }
1367 return true;
1368 }
1369
1370 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 val)
1372 {
1373 if ((val & ADPA_DAC_ENABLE) == 0)
1374 return false;
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377 return false;
1378 } else {
1379 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1380 return false;
1381 }
1382 return true;
1383 }
1384
1385 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe, int reg, u32 port_sel)
1387 {
1388 u32 val = I915_READ(reg);
1389 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1390 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1391 reg, pipe_name(pipe));
1392
1393 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394 && (val & DP_PIPEB_SELECT),
1395 "IBX PCH dp port still using transcoder B\n");
1396 }
1397
1398 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe, int reg)
1400 {
1401 u32 val = I915_READ(reg);
1402 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1403 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1404 reg, pipe_name(pipe));
1405
1406 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407 && (val & SDVO_PIPE_B_SELECT),
1408 "IBX PCH hdmi port still using transcoder B\n");
1409 }
1410
1411 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413 {
1414 int reg;
1415 u32 val;
1416
1417 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1420
1421 reg = PCH_ADPA;
1422 val = I915_READ(reg);
1423 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1424 "PCH VGA enabled on transcoder %c, should be disabled\n",
1425 pipe_name(pipe));
1426
1427 reg = PCH_LVDS;
1428 val = I915_READ(reg);
1429 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1430 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1431 pipe_name(pipe));
1432
1433 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1436 }
1437
1438 /**
1439 * intel_enable_pll - enable a PLL
1440 * @dev_priv: i915 private structure
1441 * @pipe: pipe PLL to enable
1442 *
1443 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1444 * make sure the PLL reg is writable first though, since the panel write
1445 * protect mechanism may be enabled.
1446 *
1447 * Note! This is for pre-ILK only.
1448 *
1449 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1450 */
1451 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1452 {
1453 int reg;
1454 u32 val;
1455
1456 /* No really, not for ILK+ */
1457 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1458
1459 /* PLL is protected by panel, make sure we can write it */
1460 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461 assert_panel_unlocked(dev_priv, pipe);
1462
1463 reg = DPLL(pipe);
1464 val = I915_READ(reg);
1465 val |= DPLL_VCO_ENABLE;
1466
1467 /* We do this three times for luck */
1468 I915_WRITE(reg, val);
1469 POSTING_READ(reg);
1470 udelay(150); /* wait for warmup */
1471 I915_WRITE(reg, val);
1472 POSTING_READ(reg);
1473 udelay(150); /* wait for warmup */
1474 I915_WRITE(reg, val);
1475 POSTING_READ(reg);
1476 udelay(150); /* wait for warmup */
1477 }
1478
1479 /**
1480 * intel_disable_pll - disable a PLL
1481 * @dev_priv: i915 private structure
1482 * @pipe: pipe PLL to disable
1483 *
1484 * Disable the PLL for @pipe, making sure the pipe is off first.
1485 *
1486 * Note! This is for pre-ILK only.
1487 */
1488 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1489 {
1490 int reg;
1491 u32 val;
1492
1493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495 return;
1496
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv, pipe);
1499
1500 reg = DPLL(pipe);
1501 val = I915_READ(reg);
1502 val &= ~DPLL_VCO_ENABLE;
1503 I915_WRITE(reg, val);
1504 POSTING_READ(reg);
1505 }
1506
1507 /* SBI access */
1508 static void
1509 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1510 enum intel_sbi_destination destination)
1511 {
1512 unsigned long flags;
1513 u32 tmp;
1514
1515 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1516 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1517 DRM_ERROR("timeout waiting for SBI to become ready\n");
1518 goto out_unlock;
1519 }
1520
1521 I915_WRITE(SBI_ADDR, (reg << 16));
1522 I915_WRITE(SBI_DATA, value);
1523
1524 if (destination == SBI_ICLK)
1525 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1526 else
1527 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1528 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1529
1530 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1531 100)) {
1532 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1533 goto out_unlock;
1534 }
1535
1536 out_unlock:
1537 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1538 }
1539
1540 static u32
1541 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
1543 {
1544 unsigned long flags;
1545 u32 value = 0;
1546
1547 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1548 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
1550 goto out_unlock;
1551 }
1552
1553 I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557 else
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1560
1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1562 100)) {
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1564 goto out_unlock;
1565 }
1566
1567 value = I915_READ(SBI_DATA);
1568
1569 out_unlock:
1570 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1571 return value;
1572 }
1573
1574 /**
1575 * ironlake_enable_pch_pll - enable PCH PLL
1576 * @dev_priv: i915 private structure
1577 * @pipe: pipe PLL to enable
1578 *
1579 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1580 * drives the transcoder clock.
1581 */
1582 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1583 {
1584 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1585 struct intel_pch_pll *pll;
1586 int reg;
1587 u32 val;
1588
1589 /* PCH PLLs only available on ILK, SNB and IVB */
1590 BUG_ON(dev_priv->info->gen < 5);
1591 pll = intel_crtc->pch_pll;
1592 if (pll == NULL)
1593 return;
1594
1595 if (WARN_ON(pll->refcount == 0))
1596 return;
1597
1598 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1599 pll->pll_reg, pll->active, pll->on,
1600 intel_crtc->base.base.id);
1601
1602 /* PCH refclock must be enabled first */
1603 assert_pch_refclk_enabled(dev_priv);
1604
1605 if (pll->active++ && pll->on) {
1606 assert_pch_pll_enabled(dev_priv, pll, NULL);
1607 return;
1608 }
1609
1610 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1611
1612 reg = pll->pll_reg;
1613 val = I915_READ(reg);
1614 val |= DPLL_VCO_ENABLE;
1615 I915_WRITE(reg, val);
1616 POSTING_READ(reg);
1617 udelay(200);
1618
1619 pll->on = true;
1620 }
1621
1622 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1623 {
1624 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1625 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1626 int reg;
1627 u32 val;
1628
1629 /* PCH only available on ILK+ */
1630 BUG_ON(dev_priv->info->gen < 5);
1631 if (pll == NULL)
1632 return;
1633
1634 if (WARN_ON(pll->refcount == 0))
1635 return;
1636
1637 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1638 pll->pll_reg, pll->active, pll->on,
1639 intel_crtc->base.base.id);
1640
1641 if (WARN_ON(pll->active == 0)) {
1642 assert_pch_pll_disabled(dev_priv, pll, NULL);
1643 return;
1644 }
1645
1646 if (--pll->active) {
1647 assert_pch_pll_enabled(dev_priv, pll, NULL);
1648 return;
1649 }
1650
1651 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1652
1653 /* Make sure transcoder isn't still depending on us */
1654 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1655
1656 reg = pll->pll_reg;
1657 val = I915_READ(reg);
1658 val &= ~DPLL_VCO_ENABLE;
1659 I915_WRITE(reg, val);
1660 POSTING_READ(reg);
1661 udelay(200);
1662
1663 pll->on = false;
1664 }
1665
1666 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1667 enum pipe pipe)
1668 {
1669 struct drm_device *dev = dev_priv->dev;
1670 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1671 uint32_t reg, val, pipeconf_val;
1672
1673 /* PCH only available on ILK+ */
1674 BUG_ON(dev_priv->info->gen < 5);
1675
1676 /* Make sure PCH DPLL is enabled */
1677 assert_pch_pll_enabled(dev_priv,
1678 to_intel_crtc(crtc)->pch_pll,
1679 to_intel_crtc(crtc));
1680
1681 /* FDI must be feeding us bits for PCH ports */
1682 assert_fdi_tx_enabled(dev_priv, pipe);
1683 assert_fdi_rx_enabled(dev_priv, pipe);
1684
1685 if (HAS_PCH_CPT(dev)) {
1686 /* Workaround: Set the timing override bit before enabling the
1687 * pch transcoder. */
1688 reg = TRANS_CHICKEN2(pipe);
1689 val = I915_READ(reg);
1690 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1691 I915_WRITE(reg, val);
1692 }
1693
1694 reg = TRANSCONF(pipe);
1695 val = I915_READ(reg);
1696 pipeconf_val = I915_READ(PIPECONF(pipe));
1697
1698 if (HAS_PCH_IBX(dev_priv->dev)) {
1699 /*
1700 * make the BPC in transcoder be consistent with
1701 * that in pipeconf reg.
1702 */
1703 val &= ~PIPE_BPC_MASK;
1704 val |= pipeconf_val & PIPE_BPC_MASK;
1705 }
1706
1707 val &= ~TRANS_INTERLACE_MASK;
1708 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1709 if (HAS_PCH_IBX(dev_priv->dev) &&
1710 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1711 val |= TRANS_LEGACY_INTERLACED_ILK;
1712 else
1713 val |= TRANS_INTERLACED;
1714 else
1715 val |= TRANS_PROGRESSIVE;
1716
1717 I915_WRITE(reg, val | TRANS_ENABLE);
1718 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1719 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1720 }
1721
1722 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1723 enum transcoder cpu_transcoder)
1724 {
1725 u32 val, pipeconf_val;
1726
1727 /* PCH only available on ILK+ */
1728 BUG_ON(dev_priv->info->gen < 5);
1729
1730 /* FDI must be feeding us bits for PCH ports */
1731 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1732 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1733
1734 /* Workaround: set timing override bit. */
1735 val = I915_READ(_TRANSA_CHICKEN2);
1736 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1737 I915_WRITE(_TRANSA_CHICKEN2, val);
1738
1739 val = TRANS_ENABLE;
1740 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1741
1742 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1743 PIPECONF_INTERLACED_ILK)
1744 val |= TRANS_INTERLACED;
1745 else
1746 val |= TRANS_PROGRESSIVE;
1747
1748 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1749 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1750 DRM_ERROR("Failed to enable PCH transcoder\n");
1751 }
1752
1753 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1754 enum pipe pipe)
1755 {
1756 struct drm_device *dev = dev_priv->dev;
1757 uint32_t reg, val;
1758
1759 /* FDI relies on the transcoder */
1760 assert_fdi_tx_disabled(dev_priv, pipe);
1761 assert_fdi_rx_disabled(dev_priv, pipe);
1762
1763 /* Ports must be off as well */
1764 assert_pch_ports_disabled(dev_priv, pipe);
1765
1766 reg = TRANSCONF(pipe);
1767 val = I915_READ(reg);
1768 val &= ~TRANS_ENABLE;
1769 I915_WRITE(reg, val);
1770 /* wait for PCH transcoder off, transcoder state */
1771 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1772 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1773
1774 if (!HAS_PCH_IBX(dev)) {
1775 /* Workaround: Clear the timing override chicken bit again. */
1776 reg = TRANS_CHICKEN2(pipe);
1777 val = I915_READ(reg);
1778 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1779 I915_WRITE(reg, val);
1780 }
1781 }
1782
1783 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1784 {
1785 u32 val;
1786
1787 val = I915_READ(_TRANSACONF);
1788 val &= ~TRANS_ENABLE;
1789 I915_WRITE(_TRANSACONF, val);
1790 /* wait for PCH transcoder off, transcoder state */
1791 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1792 DRM_ERROR("Failed to disable PCH transcoder\n");
1793
1794 /* Workaround: clear timing override bit. */
1795 val = I915_READ(_TRANSA_CHICKEN2);
1796 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1797 I915_WRITE(_TRANSA_CHICKEN2, val);
1798 }
1799
1800 /**
1801 * intel_enable_pipe - enable a pipe, asserting requirements
1802 * @dev_priv: i915 private structure
1803 * @pipe: pipe to enable
1804 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1805 *
1806 * Enable @pipe, making sure that various hardware specific requirements
1807 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1808 *
1809 * @pipe should be %PIPE_A or %PIPE_B.
1810 *
1811 * Will wait until the pipe is actually running (i.e. first vblank) before
1812 * returning.
1813 */
1814 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1815 bool pch_port)
1816 {
1817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1818 pipe);
1819 enum transcoder pch_transcoder;
1820 int reg;
1821 u32 val;
1822
1823 if (IS_HASWELL(dev_priv->dev))
1824 pch_transcoder = TRANSCODER_A;
1825 else
1826 pch_transcoder = pipe;
1827
1828 /*
1829 * A pipe without a PLL won't actually be able to drive bits from
1830 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1831 * need the check.
1832 */
1833 if (!HAS_PCH_SPLIT(dev_priv->dev))
1834 assert_pll_enabled(dev_priv, pipe);
1835 else {
1836 if (pch_port) {
1837 /* if driving the PCH, we need FDI enabled */
1838 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1839 assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
1840 }
1841 /* FIXME: assert CPU port conditions for SNB+ */
1842 }
1843
1844 reg = PIPECONF(cpu_transcoder);
1845 val = I915_READ(reg);
1846 if (val & PIPECONF_ENABLE)
1847 return;
1848
1849 I915_WRITE(reg, val | PIPECONF_ENABLE);
1850 intel_wait_for_vblank(dev_priv->dev, pipe);
1851 }
1852
1853 /**
1854 * intel_disable_pipe - disable a pipe, asserting requirements
1855 * @dev_priv: i915 private structure
1856 * @pipe: pipe to disable
1857 *
1858 * Disable @pipe, making sure that various hardware specific requirements
1859 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1860 *
1861 * @pipe should be %PIPE_A or %PIPE_B.
1862 *
1863 * Will wait until the pipe has shut down before returning.
1864 */
1865 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1866 enum pipe pipe)
1867 {
1868 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1869 pipe);
1870 int reg;
1871 u32 val;
1872
1873 /*
1874 * Make sure planes won't keep trying to pump pixels to us,
1875 * or we might hang the display.
1876 */
1877 assert_planes_disabled(dev_priv, pipe);
1878
1879 /* Don't disable pipe A or pipe A PLLs if needed */
1880 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1881 return;
1882
1883 reg = PIPECONF(cpu_transcoder);
1884 val = I915_READ(reg);
1885 if ((val & PIPECONF_ENABLE) == 0)
1886 return;
1887
1888 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1889 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1890 }
1891
1892 /*
1893 * Plane regs are double buffered, going from enabled->disabled needs a
1894 * trigger in order to latch. The display address reg provides this.
1895 */
1896 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1897 enum plane plane)
1898 {
1899 if (dev_priv->info->gen >= 4)
1900 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1901 else
1902 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1903 }
1904
1905 /**
1906 * intel_enable_plane - enable a display plane on a given pipe
1907 * @dev_priv: i915 private structure
1908 * @plane: plane to enable
1909 * @pipe: pipe being fed
1910 *
1911 * Enable @plane on @pipe, making sure that @pipe is running first.
1912 */
1913 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1914 enum plane plane, enum pipe pipe)
1915 {
1916 int reg;
1917 u32 val;
1918
1919 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1920 assert_pipe_enabled(dev_priv, pipe);
1921
1922 reg = DSPCNTR(plane);
1923 val = I915_READ(reg);
1924 if (val & DISPLAY_PLANE_ENABLE)
1925 return;
1926
1927 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1928 intel_flush_display_plane(dev_priv, plane);
1929 intel_wait_for_vblank(dev_priv->dev, pipe);
1930 }
1931
1932 /**
1933 * intel_disable_plane - disable a display plane
1934 * @dev_priv: i915 private structure
1935 * @plane: plane to disable
1936 * @pipe: pipe consuming the data
1937 *
1938 * Disable @plane; should be an independent operation.
1939 */
1940 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1941 enum plane plane, enum pipe pipe)
1942 {
1943 int reg;
1944 u32 val;
1945
1946 reg = DSPCNTR(plane);
1947 val = I915_READ(reg);
1948 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1949 return;
1950
1951 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1952 intel_flush_display_plane(dev_priv, plane);
1953 intel_wait_for_vblank(dev_priv->dev, pipe);
1954 }
1955
1956 int
1957 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1958 struct drm_i915_gem_object *obj,
1959 struct intel_ring_buffer *pipelined)
1960 {
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1962 u32 alignment;
1963 int ret;
1964
1965 switch (obj->tiling_mode) {
1966 case I915_TILING_NONE:
1967 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1968 alignment = 128 * 1024;
1969 else if (INTEL_INFO(dev)->gen >= 4)
1970 alignment = 4 * 1024;
1971 else
1972 alignment = 64 * 1024;
1973 break;
1974 case I915_TILING_X:
1975 /* pin() will align the object as required by fence */
1976 alignment = 0;
1977 break;
1978 case I915_TILING_Y:
1979 /* FIXME: Is this true? */
1980 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1981 return -EINVAL;
1982 default:
1983 BUG();
1984 }
1985
1986 dev_priv->mm.interruptible = false;
1987 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1988 if (ret)
1989 goto err_interruptible;
1990
1991 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1992 * fence, whereas 965+ only requires a fence if using
1993 * framebuffer compression. For simplicity, we always install
1994 * a fence as the cost is not that onerous.
1995 */
1996 ret = i915_gem_object_get_fence(obj);
1997 if (ret)
1998 goto err_unpin;
1999
2000 i915_gem_object_pin_fence(obj);
2001
2002 dev_priv->mm.interruptible = true;
2003 return 0;
2004
2005 err_unpin:
2006 i915_gem_object_unpin(obj);
2007 err_interruptible:
2008 dev_priv->mm.interruptible = true;
2009 return ret;
2010 }
2011
2012 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2013 {
2014 i915_gem_object_unpin_fence(obj);
2015 i915_gem_object_unpin(obj);
2016 }
2017
2018 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2019 * is assumed to be a power-of-two. */
2020 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2021 unsigned int bpp,
2022 unsigned int pitch)
2023 {
2024 int tile_rows, tiles;
2025
2026 tile_rows = *y / 8;
2027 *y %= 8;
2028 tiles = *x / (512/bpp);
2029 *x %= 512/bpp;
2030
2031 return tile_rows * pitch * 8 + tiles * 4096;
2032 }
2033
2034 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2035 int x, int y)
2036 {
2037 struct drm_device *dev = crtc->dev;
2038 struct drm_i915_private *dev_priv = dev->dev_private;
2039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2040 struct intel_framebuffer *intel_fb;
2041 struct drm_i915_gem_object *obj;
2042 int plane = intel_crtc->plane;
2043 unsigned long linear_offset;
2044 u32 dspcntr;
2045 u32 reg;
2046
2047 switch (plane) {
2048 case 0:
2049 case 1:
2050 break;
2051 default:
2052 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2053 return -EINVAL;
2054 }
2055
2056 intel_fb = to_intel_framebuffer(fb);
2057 obj = intel_fb->obj;
2058
2059 reg = DSPCNTR(plane);
2060 dspcntr = I915_READ(reg);
2061 /* Mask out pixel format bits in case we change it */
2062 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2063 switch (fb->pixel_format) {
2064 case DRM_FORMAT_C8:
2065 dspcntr |= DISPPLANE_8BPP;
2066 break;
2067 case DRM_FORMAT_XRGB1555:
2068 case DRM_FORMAT_ARGB1555:
2069 dspcntr |= DISPPLANE_BGRX555;
2070 break;
2071 case DRM_FORMAT_RGB565:
2072 dspcntr |= DISPPLANE_BGRX565;
2073 break;
2074 case DRM_FORMAT_XRGB8888:
2075 case DRM_FORMAT_ARGB8888:
2076 dspcntr |= DISPPLANE_BGRX888;
2077 break;
2078 case DRM_FORMAT_XBGR8888:
2079 case DRM_FORMAT_ABGR8888:
2080 dspcntr |= DISPPLANE_RGBX888;
2081 break;
2082 case DRM_FORMAT_XRGB2101010:
2083 case DRM_FORMAT_ARGB2101010:
2084 dspcntr |= DISPPLANE_BGRX101010;
2085 break;
2086 case DRM_FORMAT_XBGR2101010:
2087 case DRM_FORMAT_ABGR2101010:
2088 dspcntr |= DISPPLANE_RGBX101010;
2089 break;
2090 default:
2091 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2092 return -EINVAL;
2093 }
2094
2095 if (INTEL_INFO(dev)->gen >= 4) {
2096 if (obj->tiling_mode != I915_TILING_NONE)
2097 dspcntr |= DISPPLANE_TILED;
2098 else
2099 dspcntr &= ~DISPPLANE_TILED;
2100 }
2101
2102 I915_WRITE(reg, dspcntr);
2103
2104 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2105
2106 if (INTEL_INFO(dev)->gen >= 4) {
2107 intel_crtc->dspaddr_offset =
2108 intel_gen4_compute_offset_xtiled(&x, &y,
2109 fb->bits_per_pixel / 8,
2110 fb->pitches[0]);
2111 linear_offset -= intel_crtc->dspaddr_offset;
2112 } else {
2113 intel_crtc->dspaddr_offset = linear_offset;
2114 }
2115
2116 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2117 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2118 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2119 if (INTEL_INFO(dev)->gen >= 4) {
2120 I915_MODIFY_DISPBASE(DSPSURF(plane),
2121 obj->gtt_offset + intel_crtc->dspaddr_offset);
2122 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2123 I915_WRITE(DSPLINOFF(plane), linear_offset);
2124 } else
2125 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2126 POSTING_READ(reg);
2127
2128 return 0;
2129 }
2130
2131 static int ironlake_update_plane(struct drm_crtc *crtc,
2132 struct drm_framebuffer *fb, int x, int y)
2133 {
2134 struct drm_device *dev = crtc->dev;
2135 struct drm_i915_private *dev_priv = dev->dev_private;
2136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137 struct intel_framebuffer *intel_fb;
2138 struct drm_i915_gem_object *obj;
2139 int plane = intel_crtc->plane;
2140 unsigned long linear_offset;
2141 u32 dspcntr;
2142 u32 reg;
2143
2144 switch (plane) {
2145 case 0:
2146 case 1:
2147 case 2:
2148 break;
2149 default:
2150 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2151 return -EINVAL;
2152 }
2153
2154 intel_fb = to_intel_framebuffer(fb);
2155 obj = intel_fb->obj;
2156
2157 reg = DSPCNTR(plane);
2158 dspcntr = I915_READ(reg);
2159 /* Mask out pixel format bits in case we change it */
2160 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2161 switch (fb->pixel_format) {
2162 case DRM_FORMAT_C8:
2163 dspcntr |= DISPPLANE_8BPP;
2164 break;
2165 case DRM_FORMAT_RGB565:
2166 dspcntr |= DISPPLANE_BGRX565;
2167 break;
2168 case DRM_FORMAT_XRGB8888:
2169 case DRM_FORMAT_ARGB8888:
2170 dspcntr |= DISPPLANE_BGRX888;
2171 break;
2172 case DRM_FORMAT_XBGR8888:
2173 case DRM_FORMAT_ABGR8888:
2174 dspcntr |= DISPPLANE_RGBX888;
2175 break;
2176 case DRM_FORMAT_XRGB2101010:
2177 case DRM_FORMAT_ARGB2101010:
2178 dspcntr |= DISPPLANE_BGRX101010;
2179 break;
2180 case DRM_FORMAT_XBGR2101010:
2181 case DRM_FORMAT_ABGR2101010:
2182 dspcntr |= DISPPLANE_RGBX101010;
2183 break;
2184 default:
2185 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2186 return -EINVAL;
2187 }
2188
2189 if (obj->tiling_mode != I915_TILING_NONE)
2190 dspcntr |= DISPPLANE_TILED;
2191 else
2192 dspcntr &= ~DISPPLANE_TILED;
2193
2194 /* must disable */
2195 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2196
2197 I915_WRITE(reg, dspcntr);
2198
2199 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2200 intel_crtc->dspaddr_offset =
2201 intel_gen4_compute_offset_xtiled(&x, &y,
2202 fb->bits_per_pixel / 8,
2203 fb->pitches[0]);
2204 linear_offset -= intel_crtc->dspaddr_offset;
2205
2206 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2207 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2208 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2209 I915_MODIFY_DISPBASE(DSPSURF(plane),
2210 obj->gtt_offset + intel_crtc->dspaddr_offset);
2211 if (IS_HASWELL(dev)) {
2212 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2213 } else {
2214 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2215 I915_WRITE(DSPLINOFF(plane), linear_offset);
2216 }
2217 POSTING_READ(reg);
2218
2219 return 0;
2220 }
2221
2222 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2223 static int
2224 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2225 int x, int y, enum mode_set_atomic state)
2226 {
2227 struct drm_device *dev = crtc->dev;
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229
2230 if (dev_priv->display.disable_fbc)
2231 dev_priv->display.disable_fbc(dev);
2232 intel_increase_pllclock(crtc);
2233
2234 return dev_priv->display.update_plane(crtc, fb, x, y);
2235 }
2236
2237 static int
2238 intel_finish_fb(struct drm_framebuffer *old_fb)
2239 {
2240 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2241 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2242 bool was_interruptible = dev_priv->mm.interruptible;
2243 int ret;
2244
2245 wait_event(dev_priv->pending_flip_queue,
2246 atomic_read(&dev_priv->mm.wedged) ||
2247 atomic_read(&obj->pending_flip) == 0);
2248
2249 /* Big Hammer, we also need to ensure that any pending
2250 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251 * current scanout is retired before unpinning the old
2252 * framebuffer.
2253 *
2254 * This should only fail upon a hung GPU, in which case we
2255 * can safely continue.
2256 */
2257 dev_priv->mm.interruptible = false;
2258 ret = i915_gem_object_finish_gpu(obj);
2259 dev_priv->mm.interruptible = was_interruptible;
2260
2261 return ret;
2262 }
2263
2264 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2265 {
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_master_private *master_priv;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269
2270 if (!dev->primary->master)
2271 return;
2272
2273 master_priv = dev->primary->master->driver_priv;
2274 if (!master_priv->sarea_priv)
2275 return;
2276
2277 switch (intel_crtc->pipe) {
2278 case 0:
2279 master_priv->sarea_priv->pipeA_x = x;
2280 master_priv->sarea_priv->pipeA_y = y;
2281 break;
2282 case 1:
2283 master_priv->sarea_priv->pipeB_x = x;
2284 master_priv->sarea_priv->pipeB_y = y;
2285 break;
2286 default:
2287 break;
2288 }
2289 }
2290
2291 static int
2292 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2293 struct drm_framebuffer *fb)
2294 {
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298 struct drm_framebuffer *old_fb;
2299 int ret;
2300
2301 /* no fb bound */
2302 if (!fb) {
2303 DRM_ERROR("No FB bound\n");
2304 return 0;
2305 }
2306
2307 if(intel_crtc->plane > dev_priv->num_pipe) {
2308 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2309 intel_crtc->plane,
2310 dev_priv->num_pipe);
2311 return -EINVAL;
2312 }
2313
2314 mutex_lock(&dev->struct_mutex);
2315 ret = intel_pin_and_fence_fb_obj(dev,
2316 to_intel_framebuffer(fb)->obj,
2317 NULL);
2318 if (ret != 0) {
2319 mutex_unlock(&dev->struct_mutex);
2320 DRM_ERROR("pin & fence failed\n");
2321 return ret;
2322 }
2323
2324 if (crtc->fb)
2325 intel_finish_fb(crtc->fb);
2326
2327 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2328 if (ret) {
2329 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2330 mutex_unlock(&dev->struct_mutex);
2331 DRM_ERROR("failed to update base address\n");
2332 return ret;
2333 }
2334
2335 old_fb = crtc->fb;
2336 crtc->fb = fb;
2337 crtc->x = x;
2338 crtc->y = y;
2339
2340 if (old_fb) {
2341 intel_wait_for_vblank(dev, intel_crtc->pipe);
2342 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2343 }
2344
2345 intel_update_fbc(dev);
2346 mutex_unlock(&dev->struct_mutex);
2347
2348 intel_crtc_update_sarea_pos(crtc, x, y);
2349
2350 return 0;
2351 }
2352
2353 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2354 {
2355 struct drm_device *dev = crtc->dev;
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357 u32 dpa_ctl;
2358
2359 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2360 dpa_ctl = I915_READ(DP_A);
2361 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2362
2363 if (clock < 200000) {
2364 u32 temp;
2365 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2366 /* workaround for 160Mhz:
2367 1) program 0x4600c bits 15:0 = 0x8124
2368 2) program 0x46010 bit 0 = 1
2369 3) program 0x46034 bit 24 = 1
2370 4) program 0x64000 bit 14 = 1
2371 */
2372 temp = I915_READ(0x4600c);
2373 temp &= 0xffff0000;
2374 I915_WRITE(0x4600c, temp | 0x8124);
2375
2376 temp = I915_READ(0x46010);
2377 I915_WRITE(0x46010, temp | 1);
2378
2379 temp = I915_READ(0x46034);
2380 I915_WRITE(0x46034, temp | (1 << 24));
2381 } else {
2382 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2383 }
2384 I915_WRITE(DP_A, dpa_ctl);
2385
2386 POSTING_READ(DP_A);
2387 udelay(500);
2388 }
2389
2390 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2391 {
2392 struct drm_device *dev = crtc->dev;
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2395 int pipe = intel_crtc->pipe;
2396 u32 reg, temp;
2397
2398 /* enable normal train */
2399 reg = FDI_TX_CTL(pipe);
2400 temp = I915_READ(reg);
2401 if (IS_IVYBRIDGE(dev)) {
2402 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2403 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2404 } else {
2405 temp &= ~FDI_LINK_TRAIN_NONE;
2406 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2407 }
2408 I915_WRITE(reg, temp);
2409
2410 reg = FDI_RX_CTL(pipe);
2411 temp = I915_READ(reg);
2412 if (HAS_PCH_CPT(dev)) {
2413 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2414 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2415 } else {
2416 temp &= ~FDI_LINK_TRAIN_NONE;
2417 temp |= FDI_LINK_TRAIN_NONE;
2418 }
2419 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2420
2421 /* wait one idle pattern time */
2422 POSTING_READ(reg);
2423 udelay(1000);
2424
2425 /* IVB wants error correction enabled */
2426 if (IS_IVYBRIDGE(dev))
2427 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2428 FDI_FE_ERRC_ENABLE);
2429 }
2430
2431 static void ivb_modeset_global_resources(struct drm_device *dev)
2432 {
2433 struct drm_i915_private *dev_priv = dev->dev_private;
2434 struct intel_crtc *pipe_B_crtc =
2435 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2436 struct intel_crtc *pipe_C_crtc =
2437 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2438 uint32_t temp;
2439
2440 /* When everything is off disable fdi C so that we could enable fdi B
2441 * with all lanes. XXX: This misses the case where a pipe is not using
2442 * any pch resources and so doesn't need any fdi lanes. */
2443 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2444 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2445 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2446
2447 temp = I915_READ(SOUTH_CHICKEN1);
2448 temp &= ~FDI_BC_BIFURCATION_SELECT;
2449 DRM_DEBUG_KMS("disabling fdi C rx\n");
2450 I915_WRITE(SOUTH_CHICKEN1, temp);
2451 }
2452 }
2453
2454 /* The FDI link training functions for ILK/Ibexpeak. */
2455 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2456 {
2457 struct drm_device *dev = crtc->dev;
2458 struct drm_i915_private *dev_priv = dev->dev_private;
2459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2460 int pipe = intel_crtc->pipe;
2461 int plane = intel_crtc->plane;
2462 u32 reg, temp, tries;
2463
2464 /* FDI needs bits from pipe & plane first */
2465 assert_pipe_enabled(dev_priv, pipe);
2466 assert_plane_enabled(dev_priv, plane);
2467
2468 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2469 for train result */
2470 reg = FDI_RX_IMR(pipe);
2471 temp = I915_READ(reg);
2472 temp &= ~FDI_RX_SYMBOL_LOCK;
2473 temp &= ~FDI_RX_BIT_LOCK;
2474 I915_WRITE(reg, temp);
2475 I915_READ(reg);
2476 udelay(150);
2477
2478 /* enable CPU FDI TX and PCH FDI RX */
2479 reg = FDI_TX_CTL(pipe);
2480 temp = I915_READ(reg);
2481 temp &= ~(7 << 19);
2482 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2483 temp &= ~FDI_LINK_TRAIN_NONE;
2484 temp |= FDI_LINK_TRAIN_PATTERN_1;
2485 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2486
2487 reg = FDI_RX_CTL(pipe);
2488 temp = I915_READ(reg);
2489 temp &= ~FDI_LINK_TRAIN_NONE;
2490 temp |= FDI_LINK_TRAIN_PATTERN_1;
2491 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2492
2493 POSTING_READ(reg);
2494 udelay(150);
2495
2496 /* Ironlake workaround, enable clock pointer after FDI enable*/
2497 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2498 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2499 FDI_RX_PHASE_SYNC_POINTER_EN);
2500
2501 reg = FDI_RX_IIR(pipe);
2502 for (tries = 0; tries < 5; tries++) {
2503 temp = I915_READ(reg);
2504 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2505
2506 if ((temp & FDI_RX_BIT_LOCK)) {
2507 DRM_DEBUG_KMS("FDI train 1 done.\n");
2508 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2509 break;
2510 }
2511 }
2512 if (tries == 5)
2513 DRM_ERROR("FDI train 1 fail!\n");
2514
2515 /* Train 2 */
2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_LINK_TRAIN_NONE;
2519 temp |= FDI_LINK_TRAIN_PATTERN_2;
2520 I915_WRITE(reg, temp);
2521
2522 reg = FDI_RX_CTL(pipe);
2523 temp = I915_READ(reg);
2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_2;
2526 I915_WRITE(reg, temp);
2527
2528 POSTING_READ(reg);
2529 udelay(150);
2530
2531 reg = FDI_RX_IIR(pipe);
2532 for (tries = 0; tries < 5; tries++) {
2533 temp = I915_READ(reg);
2534 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2535
2536 if (temp & FDI_RX_SYMBOL_LOCK) {
2537 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2538 DRM_DEBUG_KMS("FDI train 2 done.\n");
2539 break;
2540 }
2541 }
2542 if (tries == 5)
2543 DRM_ERROR("FDI train 2 fail!\n");
2544
2545 DRM_DEBUG_KMS("FDI train done\n");
2546
2547 }
2548
2549 static const int snb_b_fdi_train_param[] = {
2550 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2551 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2552 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2553 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2554 };
2555
2556 /* The FDI link training functions for SNB/Cougarpoint. */
2557 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2558 {
2559 struct drm_device *dev = crtc->dev;
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2562 int pipe = intel_crtc->pipe;
2563 u32 reg, temp, i, retry;
2564
2565 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2566 for train result */
2567 reg = FDI_RX_IMR(pipe);
2568 temp = I915_READ(reg);
2569 temp &= ~FDI_RX_SYMBOL_LOCK;
2570 temp &= ~FDI_RX_BIT_LOCK;
2571 I915_WRITE(reg, temp);
2572
2573 POSTING_READ(reg);
2574 udelay(150);
2575
2576 /* enable CPU FDI TX and PCH FDI RX */
2577 reg = FDI_TX_CTL(pipe);
2578 temp = I915_READ(reg);
2579 temp &= ~(7 << 19);
2580 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2581 temp &= ~FDI_LINK_TRAIN_NONE;
2582 temp |= FDI_LINK_TRAIN_PATTERN_1;
2583 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2584 /* SNB-B */
2585 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2586 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2587
2588 I915_WRITE(FDI_RX_MISC(pipe),
2589 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2590
2591 reg = FDI_RX_CTL(pipe);
2592 temp = I915_READ(reg);
2593 if (HAS_PCH_CPT(dev)) {
2594 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2595 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2596 } else {
2597 temp &= ~FDI_LINK_TRAIN_NONE;
2598 temp |= FDI_LINK_TRAIN_PATTERN_1;
2599 }
2600 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2601
2602 POSTING_READ(reg);
2603 udelay(150);
2604
2605 for (i = 0; i < 4; i++) {
2606 reg = FDI_TX_CTL(pipe);
2607 temp = I915_READ(reg);
2608 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2609 temp |= snb_b_fdi_train_param[i];
2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
2613 udelay(500);
2614
2615 for (retry = 0; retry < 5; retry++) {
2616 reg = FDI_RX_IIR(pipe);
2617 temp = I915_READ(reg);
2618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2619 if (temp & FDI_RX_BIT_LOCK) {
2620 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2621 DRM_DEBUG_KMS("FDI train 1 done.\n");
2622 break;
2623 }
2624 udelay(50);
2625 }
2626 if (retry < 5)
2627 break;
2628 }
2629 if (i == 4)
2630 DRM_ERROR("FDI train 1 fail!\n");
2631
2632 /* Train 2 */
2633 reg = FDI_TX_CTL(pipe);
2634 temp = I915_READ(reg);
2635 temp &= ~FDI_LINK_TRAIN_NONE;
2636 temp |= FDI_LINK_TRAIN_PATTERN_2;
2637 if (IS_GEN6(dev)) {
2638 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639 /* SNB-B */
2640 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2641 }
2642 I915_WRITE(reg, temp);
2643
2644 reg = FDI_RX_CTL(pipe);
2645 temp = I915_READ(reg);
2646 if (HAS_PCH_CPT(dev)) {
2647 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2648 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2649 } else {
2650 temp &= ~FDI_LINK_TRAIN_NONE;
2651 temp |= FDI_LINK_TRAIN_PATTERN_2;
2652 }
2653 I915_WRITE(reg, temp);
2654
2655 POSTING_READ(reg);
2656 udelay(150);
2657
2658 for (i = 0; i < 4; i++) {
2659 reg = FDI_TX_CTL(pipe);
2660 temp = I915_READ(reg);
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= snb_b_fdi_train_param[i];
2663 I915_WRITE(reg, temp);
2664
2665 POSTING_READ(reg);
2666 udelay(500);
2667
2668 for (retry = 0; retry < 5; retry++) {
2669 reg = FDI_RX_IIR(pipe);
2670 temp = I915_READ(reg);
2671 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2672 if (temp & FDI_RX_SYMBOL_LOCK) {
2673 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2674 DRM_DEBUG_KMS("FDI train 2 done.\n");
2675 break;
2676 }
2677 udelay(50);
2678 }
2679 if (retry < 5)
2680 break;
2681 }
2682 if (i == 4)
2683 DRM_ERROR("FDI train 2 fail!\n");
2684
2685 DRM_DEBUG_KMS("FDI train done.\n");
2686 }
2687
2688 /* Manual link training for Ivy Bridge A0 parts */
2689 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2690 {
2691 struct drm_device *dev = crtc->dev;
2692 struct drm_i915_private *dev_priv = dev->dev_private;
2693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2694 int pipe = intel_crtc->pipe;
2695 u32 reg, temp, i;
2696
2697 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2698 for train result */
2699 reg = FDI_RX_IMR(pipe);
2700 temp = I915_READ(reg);
2701 temp &= ~FDI_RX_SYMBOL_LOCK;
2702 temp &= ~FDI_RX_BIT_LOCK;
2703 I915_WRITE(reg, temp);
2704
2705 POSTING_READ(reg);
2706 udelay(150);
2707
2708 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2709 I915_READ(FDI_RX_IIR(pipe)));
2710
2711 /* enable CPU FDI TX and PCH FDI RX */
2712 reg = FDI_TX_CTL(pipe);
2713 temp = I915_READ(reg);
2714 temp &= ~(7 << 19);
2715 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2716 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2717 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2718 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2719 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2720 temp |= FDI_COMPOSITE_SYNC;
2721 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2722
2723 I915_WRITE(FDI_RX_MISC(pipe),
2724 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2725
2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 temp &= ~FDI_LINK_TRAIN_AUTO;
2729 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2730 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2731 temp |= FDI_COMPOSITE_SYNC;
2732 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2733
2734 POSTING_READ(reg);
2735 udelay(150);
2736
2737 for (i = 0; i < 4; i++) {
2738 reg = FDI_TX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2741 temp |= snb_b_fdi_train_param[i];
2742 I915_WRITE(reg, temp);
2743
2744 POSTING_READ(reg);
2745 udelay(500);
2746
2747 reg = FDI_RX_IIR(pipe);
2748 temp = I915_READ(reg);
2749 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2750
2751 if (temp & FDI_RX_BIT_LOCK ||
2752 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2753 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2754 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2755 break;
2756 }
2757 }
2758 if (i == 4)
2759 DRM_ERROR("FDI train 1 fail!\n");
2760
2761 /* Train 2 */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2765 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2766 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2767 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2768 I915_WRITE(reg, temp);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2773 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2774 I915_WRITE(reg, temp);
2775
2776 POSTING_READ(reg);
2777 udelay(150);
2778
2779 for (i = 0; i < 4; i++) {
2780 reg = FDI_TX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2783 temp |= snb_b_fdi_train_param[i];
2784 I915_WRITE(reg, temp);
2785
2786 POSTING_READ(reg);
2787 udelay(500);
2788
2789 reg = FDI_RX_IIR(pipe);
2790 temp = I915_READ(reg);
2791 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2792
2793 if (temp & FDI_RX_SYMBOL_LOCK) {
2794 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2796 break;
2797 }
2798 }
2799 if (i == 4)
2800 DRM_ERROR("FDI train 2 fail!\n");
2801
2802 DRM_DEBUG_KMS("FDI train done.\n");
2803 }
2804
2805 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2806 {
2807 struct drm_device *dev = intel_crtc->base.dev;
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 int pipe = intel_crtc->pipe;
2810 u32 reg, temp;
2811
2812
2813 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~((0x7 << 19) | (0x7 << 16));
2817 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2818 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821 POSTING_READ(reg);
2822 udelay(200);
2823
2824 /* Switch from Rawclk to PCDclk */
2825 temp = I915_READ(reg);
2826 I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828 POSTING_READ(reg);
2829 udelay(200);
2830
2831 /* On Haswell, the PLL configuration for ports and pipes is handled
2832 * separately, as part of DDI setup */
2833 if (!IS_HASWELL(dev)) {
2834 /* Enable CPU FDI TX PLL, always on for Ironlake */
2835 reg = FDI_TX_CTL(pipe);
2836 temp = I915_READ(reg);
2837 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2839
2840 POSTING_READ(reg);
2841 udelay(100);
2842 }
2843 }
2844 }
2845
2846 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847 {
2848 struct drm_device *dev = intel_crtc->base.dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 int pipe = intel_crtc->pipe;
2851 u32 reg, temp;
2852
2853 /* Switch from PCDclk to Rawclk */
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858 /* Disable CPU FDI TX PLL */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870 /* Wait for the clocks to turn off. */
2871 POSTING_READ(reg);
2872 udelay(100);
2873 }
2874
2875 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2876 {
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 int pipe = intel_crtc->pipe;
2881 u32 reg, temp;
2882
2883 /* disable CPU FDI tx and PCH FDI rx */
2884 reg = FDI_TX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2887 POSTING_READ(reg);
2888
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 temp &= ~(0x7 << 16);
2892 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2893 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2894
2895 POSTING_READ(reg);
2896 udelay(100);
2897
2898 /* Ironlake workaround, disable clock pointer after downing FDI */
2899 if (HAS_PCH_IBX(dev)) {
2900 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2901 }
2902
2903 /* still set train pattern 1 */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908 I915_WRITE(reg, temp);
2909
2910 reg = FDI_RX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 if (HAS_PCH_CPT(dev)) {
2913 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2914 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2915 } else {
2916 temp &= ~FDI_LINK_TRAIN_NONE;
2917 temp |= FDI_LINK_TRAIN_PATTERN_1;
2918 }
2919 /* BPC in FDI rx is consistent with that in PIPECONF */
2920 temp &= ~(0x07 << 16);
2921 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2922 I915_WRITE(reg, temp);
2923
2924 POSTING_READ(reg);
2925 udelay(100);
2926 }
2927
2928 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2929 {
2930 struct drm_device *dev = crtc->dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 unsigned long flags;
2933 bool pending;
2934
2935 if (atomic_read(&dev_priv->mm.wedged))
2936 return false;
2937
2938 spin_lock_irqsave(&dev->event_lock, flags);
2939 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2940 spin_unlock_irqrestore(&dev->event_lock, flags);
2941
2942 return pending;
2943 }
2944
2945 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2946 {
2947 struct drm_device *dev = crtc->dev;
2948 struct drm_i915_private *dev_priv = dev->dev_private;
2949
2950 if (crtc->fb == NULL)
2951 return;
2952
2953 wait_event(dev_priv->pending_flip_queue,
2954 !intel_crtc_has_pending_flip(crtc));
2955
2956 mutex_lock(&dev->struct_mutex);
2957 intel_finish_fb(crtc->fb);
2958 mutex_unlock(&dev->struct_mutex);
2959 }
2960
2961 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2962 {
2963 struct drm_device *dev = crtc->dev;
2964 struct intel_encoder *intel_encoder;
2965
2966 /*
2967 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2968 * must be driven by its own crtc; no sharing is possible.
2969 */
2970 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2971 switch (intel_encoder->type) {
2972 case INTEL_OUTPUT_EDP:
2973 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2974 return false;
2975 continue;
2976 }
2977 }
2978
2979 return true;
2980 }
2981
2982 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2983 {
2984 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2985 }
2986
2987 /* Program iCLKIP clock to the desired frequency */
2988 static void lpt_program_iclkip(struct drm_crtc *crtc)
2989 {
2990 struct drm_device *dev = crtc->dev;
2991 struct drm_i915_private *dev_priv = dev->dev_private;
2992 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2993 u32 temp;
2994
2995 /* It is necessary to ungate the pixclk gate prior to programming
2996 * the divisors, and gate it back when it is done.
2997 */
2998 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2999
3000 /* Disable SSCCTL */
3001 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3002 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3003 SBI_SSCCTL_DISABLE,
3004 SBI_ICLK);
3005
3006 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3007 if (crtc->mode.clock == 20000) {
3008 auxdiv = 1;
3009 divsel = 0x41;
3010 phaseinc = 0x20;
3011 } else {
3012 /* The iCLK virtual clock root frequency is in MHz,
3013 * but the crtc->mode.clock in in KHz. To get the divisors,
3014 * it is necessary to divide one by another, so we
3015 * convert the virtual clock precision to KHz here for higher
3016 * precision.
3017 */
3018 u32 iclk_virtual_root_freq = 172800 * 1000;
3019 u32 iclk_pi_range = 64;
3020 u32 desired_divisor, msb_divisor_value, pi_value;
3021
3022 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3023 msb_divisor_value = desired_divisor / iclk_pi_range;
3024 pi_value = desired_divisor % iclk_pi_range;
3025
3026 auxdiv = 0;
3027 divsel = msb_divisor_value - 2;
3028 phaseinc = pi_value;
3029 }
3030
3031 /* This should not happen with any sane values */
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3033 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3034 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3035 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3036
3037 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3038 crtc->mode.clock,
3039 auxdiv,
3040 divsel,
3041 phasedir,
3042 phaseinc);
3043
3044 /* Program SSCDIVINTPHASE6 */
3045 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3046 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3047 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3048 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3049 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3050 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3051 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3052 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3053
3054 /* Program SSCAUXDIV */
3055 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3056 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3057 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3058 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3059
3060 /* Enable modulator and associated divider */
3061 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3062 temp &= ~SBI_SSCCTL_DISABLE;
3063 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3064
3065 /* Wait for initialization time */
3066 udelay(24);
3067
3068 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3069 }
3070
3071 /*
3072 * Enable PCH resources required for PCH ports:
3073 * - PCH PLLs
3074 * - FDI training & RX/TX
3075 * - update transcoder timings
3076 * - DP transcoding bits
3077 * - transcoder
3078 */
3079 static void ironlake_pch_enable(struct drm_crtc *crtc)
3080 {
3081 struct drm_device *dev = crtc->dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084 int pipe = intel_crtc->pipe;
3085 u32 reg, temp;
3086
3087 assert_transcoder_disabled(dev_priv, pipe);
3088
3089 /* Write the TU size bits before fdi link training, so that error
3090 * detection works. */
3091 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3092 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3093
3094 /* For PCH output, training FDI link */
3095 dev_priv->display.fdi_link_train(crtc);
3096
3097 /* XXX: pch pll's can be enabled any time before we enable the PCH
3098 * transcoder, and we actually should do this to not upset any PCH
3099 * transcoder that already use the clock when we share it.
3100 *
3101 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3102 * unconditionally resets the pll - we need that to have the right LVDS
3103 * enable sequence. */
3104 ironlake_enable_pch_pll(intel_crtc);
3105
3106 if (HAS_PCH_CPT(dev)) {
3107 u32 sel;
3108
3109 temp = I915_READ(PCH_DPLL_SEL);
3110 switch (pipe) {
3111 default:
3112 case 0:
3113 temp |= TRANSA_DPLL_ENABLE;
3114 sel = TRANSA_DPLLB_SEL;
3115 break;
3116 case 1:
3117 temp |= TRANSB_DPLL_ENABLE;
3118 sel = TRANSB_DPLLB_SEL;
3119 break;
3120 case 2:
3121 temp |= TRANSC_DPLL_ENABLE;
3122 sel = TRANSC_DPLLB_SEL;
3123 break;
3124 }
3125 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3126 temp |= sel;
3127 else
3128 temp &= ~sel;
3129 I915_WRITE(PCH_DPLL_SEL, temp);
3130 }
3131
3132 /* set transcoder timing, panel must allow it */
3133 assert_panel_unlocked(dev_priv, pipe);
3134 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3135 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3136 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3137
3138 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3139 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3140 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3141 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3142
3143 intel_fdi_normal_train(crtc);
3144
3145 /* For PCH DP, enable TRANS_DP_CTL */
3146 if (HAS_PCH_CPT(dev) &&
3147 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3148 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3149 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3150 reg = TRANS_DP_CTL(pipe);
3151 temp = I915_READ(reg);
3152 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3153 TRANS_DP_SYNC_MASK |
3154 TRANS_DP_BPC_MASK);
3155 temp |= (TRANS_DP_OUTPUT_ENABLE |
3156 TRANS_DP_ENH_FRAMING);
3157 temp |= bpc << 9; /* same format but at 11:9 */
3158
3159 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3160 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3161 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3162 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3163
3164 switch (intel_trans_dp_port_sel(crtc)) {
3165 case PCH_DP_B:
3166 temp |= TRANS_DP_PORT_SEL_B;
3167 break;
3168 case PCH_DP_C:
3169 temp |= TRANS_DP_PORT_SEL_C;
3170 break;
3171 case PCH_DP_D:
3172 temp |= TRANS_DP_PORT_SEL_D;
3173 break;
3174 default:
3175 BUG();
3176 }
3177
3178 I915_WRITE(reg, temp);
3179 }
3180
3181 ironlake_enable_pch_transcoder(dev_priv, pipe);
3182 }
3183
3184 static void lpt_pch_enable(struct drm_crtc *crtc)
3185 {
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3190
3191 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3192
3193 lpt_program_iclkip(crtc);
3194
3195 /* Set transcoder timing. */
3196 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3197 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3198 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3199
3200 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3201 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3202 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3203 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3204
3205 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3206 }
3207
3208 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3209 {
3210 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3211
3212 if (pll == NULL)
3213 return;
3214
3215 if (pll->refcount == 0) {
3216 WARN(1, "bad PCH PLL refcount\n");
3217 return;
3218 }
3219
3220 --pll->refcount;
3221 intel_crtc->pch_pll = NULL;
3222 }
3223
3224 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3225 {
3226 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3227 struct intel_pch_pll *pll;
3228 int i;
3229
3230 pll = intel_crtc->pch_pll;
3231 if (pll) {
3232 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3233 intel_crtc->base.base.id, pll->pll_reg);
3234 goto prepare;
3235 }
3236
3237 if (HAS_PCH_IBX(dev_priv->dev)) {
3238 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3239 i = intel_crtc->pipe;
3240 pll = &dev_priv->pch_plls[i];
3241
3242 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3243 intel_crtc->base.base.id, pll->pll_reg);
3244
3245 goto found;
3246 }
3247
3248 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3249 pll = &dev_priv->pch_plls[i];
3250
3251 /* Only want to check enabled timings first */
3252 if (pll->refcount == 0)
3253 continue;
3254
3255 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3256 fp == I915_READ(pll->fp0_reg)) {
3257 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3258 intel_crtc->base.base.id,
3259 pll->pll_reg, pll->refcount, pll->active);
3260
3261 goto found;
3262 }
3263 }
3264
3265 /* Ok no matching timings, maybe there's a free one? */
3266 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3267 pll = &dev_priv->pch_plls[i];
3268 if (pll->refcount == 0) {
3269 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3270 intel_crtc->base.base.id, pll->pll_reg);
3271 goto found;
3272 }
3273 }
3274
3275 return NULL;
3276
3277 found:
3278 intel_crtc->pch_pll = pll;
3279 pll->refcount++;
3280 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3281 prepare: /* separate function? */
3282 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3283
3284 /* Wait for the clocks to stabilize before rewriting the regs */
3285 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3286 POSTING_READ(pll->pll_reg);
3287 udelay(150);
3288
3289 I915_WRITE(pll->fp0_reg, fp);
3290 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3291 pll->on = false;
3292 return pll;
3293 }
3294
3295 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3296 {
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 int dslreg = PIPEDSL(pipe);
3299 u32 temp;
3300
3301 temp = I915_READ(dslreg);
3302 udelay(500);
3303 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3304 if (wait_for(I915_READ(dslreg) != temp, 5))
3305 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3306 }
3307 }
3308
3309 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3310 {
3311 struct drm_device *dev = crtc->dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3314 struct intel_encoder *encoder;
3315 int pipe = intel_crtc->pipe;
3316 int plane = intel_crtc->plane;
3317 u32 temp;
3318 bool is_pch_port;
3319
3320 WARN_ON(!crtc->enabled);
3321
3322 if (intel_crtc->active)
3323 return;
3324
3325 intel_crtc->active = true;
3326 intel_update_watermarks(dev);
3327
3328 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3329 temp = I915_READ(PCH_LVDS);
3330 if ((temp & LVDS_PORT_EN) == 0)
3331 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3332 }
3333
3334 is_pch_port = ironlake_crtc_driving_pch(crtc);
3335
3336 if (is_pch_port) {
3337 /* Note: FDI PLL enabling _must_ be done before we enable the
3338 * cpu pipes, hence this is separate from all the other fdi/pch
3339 * enabling. */
3340 ironlake_fdi_pll_enable(intel_crtc);
3341 } else {
3342 assert_fdi_tx_disabled(dev_priv, pipe);
3343 assert_fdi_rx_disabled(dev_priv, pipe);
3344 }
3345
3346 for_each_encoder_on_crtc(dev, crtc, encoder)
3347 if (encoder->pre_enable)
3348 encoder->pre_enable(encoder);
3349
3350 /* Enable panel fitting for LVDS */
3351 if (dev_priv->pch_pf_size &&
3352 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3353 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3354 /* Force use of hard-coded filter coefficients
3355 * as some pre-programmed values are broken,
3356 * e.g. x201.
3357 */
3358 if (IS_IVYBRIDGE(dev))
3359 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3360 PF_PIPE_SEL_IVB(pipe));
3361 else
3362 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3363 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3364 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3365 }
3366
3367 /*
3368 * On ILK+ LUT must be loaded before the pipe is running but with
3369 * clocks enabled
3370 */
3371 intel_crtc_load_lut(crtc);
3372
3373 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3374 intel_enable_plane(dev_priv, plane, pipe);
3375
3376 if (is_pch_port)
3377 ironlake_pch_enable(crtc);
3378
3379 mutex_lock(&dev->struct_mutex);
3380 intel_update_fbc(dev);
3381 mutex_unlock(&dev->struct_mutex);
3382
3383 intel_crtc_update_cursor(crtc, true);
3384
3385 for_each_encoder_on_crtc(dev, crtc, encoder)
3386 encoder->enable(encoder);
3387
3388 if (HAS_PCH_CPT(dev))
3389 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3390
3391 /*
3392 * There seems to be a race in PCH platform hw (at least on some
3393 * outputs) where an enabled pipe still completes any pageflip right
3394 * away (as if the pipe is off) instead of waiting for vblank. As soon
3395 * as the first vblank happend, everything works as expected. Hence just
3396 * wait for one vblank before returning to avoid strange things
3397 * happening.
3398 */
3399 intel_wait_for_vblank(dev, intel_crtc->pipe);
3400 }
3401
3402 static void haswell_crtc_enable(struct drm_crtc *crtc)
3403 {
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407 struct intel_encoder *encoder;
3408 int pipe = intel_crtc->pipe;
3409 int plane = intel_crtc->plane;
3410 bool is_pch_port;
3411
3412 WARN_ON(!crtc->enabled);
3413
3414 if (intel_crtc->active)
3415 return;
3416
3417 intel_crtc->active = true;
3418 intel_update_watermarks(dev);
3419
3420 is_pch_port = haswell_crtc_driving_pch(crtc);
3421
3422 if (is_pch_port)
3423 dev_priv->display.fdi_link_train(crtc);
3424
3425 for_each_encoder_on_crtc(dev, crtc, encoder)
3426 if (encoder->pre_enable)
3427 encoder->pre_enable(encoder);
3428
3429 intel_ddi_enable_pipe_clock(intel_crtc);
3430
3431 /* Enable panel fitting for eDP */
3432 if (dev_priv->pch_pf_size &&
3433 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3434 /* Force use of hard-coded filter coefficients
3435 * as some pre-programmed values are broken,
3436 * e.g. x201.
3437 */
3438 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3439 PF_PIPE_SEL_IVB(pipe));
3440 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3441 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3442 }
3443
3444 /*
3445 * On ILK+ LUT must be loaded before the pipe is running but with
3446 * clocks enabled
3447 */
3448 intel_crtc_load_lut(crtc);
3449
3450 intel_ddi_set_pipe_settings(crtc);
3451 intel_ddi_enable_pipe_func(crtc);
3452
3453 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3454 intel_enable_plane(dev_priv, plane, pipe);
3455
3456 if (is_pch_port)
3457 lpt_pch_enable(crtc);
3458
3459 mutex_lock(&dev->struct_mutex);
3460 intel_update_fbc(dev);
3461 mutex_unlock(&dev->struct_mutex);
3462
3463 intel_crtc_update_cursor(crtc, true);
3464
3465 for_each_encoder_on_crtc(dev, crtc, encoder)
3466 encoder->enable(encoder);
3467
3468 /*
3469 * There seems to be a race in PCH platform hw (at least on some
3470 * outputs) where an enabled pipe still completes any pageflip right
3471 * away (as if the pipe is off) instead of waiting for vblank. As soon
3472 * as the first vblank happend, everything works as expected. Hence just
3473 * wait for one vblank before returning to avoid strange things
3474 * happening.
3475 */
3476 intel_wait_for_vblank(dev, intel_crtc->pipe);
3477 }
3478
3479 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3480 {
3481 struct drm_device *dev = crtc->dev;
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3484 struct intel_encoder *encoder;
3485 int pipe = intel_crtc->pipe;
3486 int plane = intel_crtc->plane;
3487 u32 reg, temp;
3488
3489
3490 if (!intel_crtc->active)
3491 return;
3492
3493 for_each_encoder_on_crtc(dev, crtc, encoder)
3494 encoder->disable(encoder);
3495
3496 intel_crtc_wait_for_pending_flips(crtc);
3497 drm_vblank_off(dev, pipe);
3498 intel_crtc_update_cursor(crtc, false);
3499
3500 intel_disable_plane(dev_priv, plane, pipe);
3501
3502 if (dev_priv->cfb_plane == plane)
3503 intel_disable_fbc(dev);
3504
3505 intel_disable_pipe(dev_priv, pipe);
3506
3507 /* Disable PF */
3508 I915_WRITE(PF_CTL(pipe), 0);
3509 I915_WRITE(PF_WIN_SZ(pipe), 0);
3510
3511 for_each_encoder_on_crtc(dev, crtc, encoder)
3512 if (encoder->post_disable)
3513 encoder->post_disable(encoder);
3514
3515 ironlake_fdi_disable(crtc);
3516
3517 ironlake_disable_pch_transcoder(dev_priv, pipe);
3518
3519 if (HAS_PCH_CPT(dev)) {
3520 /* disable TRANS_DP_CTL */
3521 reg = TRANS_DP_CTL(pipe);
3522 temp = I915_READ(reg);
3523 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3524 temp |= TRANS_DP_PORT_SEL_NONE;
3525 I915_WRITE(reg, temp);
3526
3527 /* disable DPLL_SEL */
3528 temp = I915_READ(PCH_DPLL_SEL);
3529 switch (pipe) {
3530 case 0:
3531 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3532 break;
3533 case 1:
3534 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3535 break;
3536 case 2:
3537 /* C shares PLL A or B */
3538 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3539 break;
3540 default:
3541 BUG(); /* wtf */
3542 }
3543 I915_WRITE(PCH_DPLL_SEL, temp);
3544 }
3545
3546 /* disable PCH DPLL */
3547 intel_disable_pch_pll(intel_crtc);
3548
3549 ironlake_fdi_pll_disable(intel_crtc);
3550
3551 intel_crtc->active = false;
3552 intel_update_watermarks(dev);
3553
3554 mutex_lock(&dev->struct_mutex);
3555 intel_update_fbc(dev);
3556 mutex_unlock(&dev->struct_mutex);
3557 }
3558
3559 static void haswell_crtc_disable(struct drm_crtc *crtc)
3560 {
3561 struct drm_device *dev = crtc->dev;
3562 struct drm_i915_private *dev_priv = dev->dev_private;
3563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564 struct intel_encoder *encoder;
3565 int pipe = intel_crtc->pipe;
3566 int plane = intel_crtc->plane;
3567 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3568 bool is_pch_port;
3569
3570 if (!intel_crtc->active)
3571 return;
3572
3573 is_pch_port = haswell_crtc_driving_pch(crtc);
3574
3575 for_each_encoder_on_crtc(dev, crtc, encoder)
3576 encoder->disable(encoder);
3577
3578 intel_crtc_wait_for_pending_flips(crtc);
3579 drm_vblank_off(dev, pipe);
3580 intel_crtc_update_cursor(crtc, false);
3581
3582 intel_disable_plane(dev_priv, plane, pipe);
3583
3584 if (dev_priv->cfb_plane == plane)
3585 intel_disable_fbc(dev);
3586
3587 intel_disable_pipe(dev_priv, pipe);
3588
3589 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3590
3591 /* Disable PF */
3592 I915_WRITE(PF_CTL(pipe), 0);
3593 I915_WRITE(PF_WIN_SZ(pipe), 0);
3594
3595 intel_ddi_disable_pipe_clock(intel_crtc);
3596
3597 for_each_encoder_on_crtc(dev, crtc, encoder)
3598 if (encoder->post_disable)
3599 encoder->post_disable(encoder);
3600
3601 if (is_pch_port) {
3602 lpt_disable_pch_transcoder(dev_priv);
3603 intel_ddi_fdi_disable(crtc);
3604 }
3605
3606 intel_crtc->active = false;
3607 intel_update_watermarks(dev);
3608
3609 mutex_lock(&dev->struct_mutex);
3610 intel_update_fbc(dev);
3611 mutex_unlock(&dev->struct_mutex);
3612 }
3613
3614 static void ironlake_crtc_off(struct drm_crtc *crtc)
3615 {
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 intel_put_pch_pll(intel_crtc);
3618 }
3619
3620 static void haswell_crtc_off(struct drm_crtc *crtc)
3621 {
3622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3623
3624 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3625 * start using it. */
3626 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3627
3628 intel_ddi_put_crtc_pll(crtc);
3629 }
3630
3631 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3632 {
3633 if (!enable && intel_crtc->overlay) {
3634 struct drm_device *dev = intel_crtc->base.dev;
3635 struct drm_i915_private *dev_priv = dev->dev_private;
3636
3637 mutex_lock(&dev->struct_mutex);
3638 dev_priv->mm.interruptible = false;
3639 (void) intel_overlay_switch_off(intel_crtc->overlay);
3640 dev_priv->mm.interruptible = true;
3641 mutex_unlock(&dev->struct_mutex);
3642 }
3643
3644 /* Let userspace switch the overlay on again. In most cases userspace
3645 * has to recompute where to put it anyway.
3646 */
3647 }
3648
3649 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3650 {
3651 struct drm_device *dev = crtc->dev;
3652 struct drm_i915_private *dev_priv = dev->dev_private;
3653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3654 struct intel_encoder *encoder;
3655 int pipe = intel_crtc->pipe;
3656 int plane = intel_crtc->plane;
3657
3658 WARN_ON(!crtc->enabled);
3659
3660 if (intel_crtc->active)
3661 return;
3662
3663 intel_crtc->active = true;
3664 intel_update_watermarks(dev);
3665
3666 intel_enable_pll(dev_priv, pipe);
3667 intel_enable_pipe(dev_priv, pipe, false);
3668 intel_enable_plane(dev_priv, plane, pipe);
3669
3670 intel_crtc_load_lut(crtc);
3671 intel_update_fbc(dev);
3672
3673 /* Give the overlay scaler a chance to enable if it's on this pipe */
3674 intel_crtc_dpms_overlay(intel_crtc, true);
3675 intel_crtc_update_cursor(crtc, true);
3676
3677 for_each_encoder_on_crtc(dev, crtc, encoder)
3678 encoder->enable(encoder);
3679 }
3680
3681 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3682 {
3683 struct drm_device *dev = crtc->dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3686 struct intel_encoder *encoder;
3687 int pipe = intel_crtc->pipe;
3688 int plane = intel_crtc->plane;
3689
3690
3691 if (!intel_crtc->active)
3692 return;
3693
3694 for_each_encoder_on_crtc(dev, crtc, encoder)
3695 encoder->disable(encoder);
3696
3697 /* Give the overlay scaler a chance to disable if it's on this pipe */
3698 intel_crtc_wait_for_pending_flips(crtc);
3699 drm_vblank_off(dev, pipe);
3700 intel_crtc_dpms_overlay(intel_crtc, false);
3701 intel_crtc_update_cursor(crtc, false);
3702
3703 if (dev_priv->cfb_plane == plane)
3704 intel_disable_fbc(dev);
3705
3706 intel_disable_plane(dev_priv, plane, pipe);
3707 intel_disable_pipe(dev_priv, pipe);
3708 intel_disable_pll(dev_priv, pipe);
3709
3710 intel_crtc->active = false;
3711 intel_update_fbc(dev);
3712 intel_update_watermarks(dev);
3713 }
3714
3715 static void i9xx_crtc_off(struct drm_crtc *crtc)
3716 {
3717 }
3718
3719 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3720 bool enabled)
3721 {
3722 struct drm_device *dev = crtc->dev;
3723 struct drm_i915_master_private *master_priv;
3724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3725 int pipe = intel_crtc->pipe;
3726
3727 if (!dev->primary->master)
3728 return;
3729
3730 master_priv = dev->primary->master->driver_priv;
3731 if (!master_priv->sarea_priv)
3732 return;
3733
3734 switch (pipe) {
3735 case 0:
3736 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3737 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3738 break;
3739 case 1:
3740 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3741 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3742 break;
3743 default:
3744 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3745 break;
3746 }
3747 }
3748
3749 /**
3750 * Sets the power management mode of the pipe and plane.
3751 */
3752 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3753 {
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct intel_encoder *intel_encoder;
3757 bool enable = false;
3758
3759 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3760 enable |= intel_encoder->connectors_active;
3761
3762 if (enable)
3763 dev_priv->display.crtc_enable(crtc);
3764 else
3765 dev_priv->display.crtc_disable(crtc);
3766
3767 intel_crtc_update_sarea(crtc, enable);
3768 }
3769
3770 static void intel_crtc_noop(struct drm_crtc *crtc)
3771 {
3772 }
3773
3774 static void intel_crtc_disable(struct drm_crtc *crtc)
3775 {
3776 struct drm_device *dev = crtc->dev;
3777 struct drm_connector *connector;
3778 struct drm_i915_private *dev_priv = dev->dev_private;
3779
3780 /* crtc should still be enabled when we disable it. */
3781 WARN_ON(!crtc->enabled);
3782
3783 dev_priv->display.crtc_disable(crtc);
3784 intel_crtc_update_sarea(crtc, false);
3785 dev_priv->display.off(crtc);
3786
3787 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3788 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3789
3790 if (crtc->fb) {
3791 mutex_lock(&dev->struct_mutex);
3792 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3793 mutex_unlock(&dev->struct_mutex);
3794 crtc->fb = NULL;
3795 }
3796
3797 /* Update computed state. */
3798 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3799 if (!connector->encoder || !connector->encoder->crtc)
3800 continue;
3801
3802 if (connector->encoder->crtc != crtc)
3803 continue;
3804
3805 connector->dpms = DRM_MODE_DPMS_OFF;
3806 to_intel_encoder(connector->encoder)->connectors_active = false;
3807 }
3808 }
3809
3810 void intel_modeset_disable(struct drm_device *dev)
3811 {
3812 struct drm_crtc *crtc;
3813
3814 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3815 if (crtc->enabled)
3816 intel_crtc_disable(crtc);
3817 }
3818 }
3819
3820 void intel_encoder_noop(struct drm_encoder *encoder)
3821 {
3822 }
3823
3824 void intel_encoder_destroy(struct drm_encoder *encoder)
3825 {
3826 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3827
3828 drm_encoder_cleanup(encoder);
3829 kfree(intel_encoder);
3830 }
3831
3832 /* Simple dpms helper for encodres with just one connector, no cloning and only
3833 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3834 * state of the entire output pipe. */
3835 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3836 {
3837 if (mode == DRM_MODE_DPMS_ON) {
3838 encoder->connectors_active = true;
3839
3840 intel_crtc_update_dpms(encoder->base.crtc);
3841 } else {
3842 encoder->connectors_active = false;
3843
3844 intel_crtc_update_dpms(encoder->base.crtc);
3845 }
3846 }
3847
3848 /* Cross check the actual hw state with our own modeset state tracking (and it's
3849 * internal consistency). */
3850 static void intel_connector_check_state(struct intel_connector *connector)
3851 {
3852 if (connector->get_hw_state(connector)) {
3853 struct intel_encoder *encoder = connector->encoder;
3854 struct drm_crtc *crtc;
3855 bool encoder_enabled;
3856 enum pipe pipe;
3857
3858 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3859 connector->base.base.id,
3860 drm_get_connector_name(&connector->base));
3861
3862 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3863 "wrong connector dpms state\n");
3864 WARN(connector->base.encoder != &encoder->base,
3865 "active connector not linked to encoder\n");
3866 WARN(!encoder->connectors_active,
3867 "encoder->connectors_active not set\n");
3868
3869 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3870 WARN(!encoder_enabled, "encoder not enabled\n");
3871 if (WARN_ON(!encoder->base.crtc))
3872 return;
3873
3874 crtc = encoder->base.crtc;
3875
3876 WARN(!crtc->enabled, "crtc not enabled\n");
3877 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3878 WARN(pipe != to_intel_crtc(crtc)->pipe,
3879 "encoder active on the wrong pipe\n");
3880 }
3881 }
3882
3883 /* Even simpler default implementation, if there's really no special case to
3884 * consider. */
3885 void intel_connector_dpms(struct drm_connector *connector, int mode)
3886 {
3887 struct intel_encoder *encoder = intel_attached_encoder(connector);
3888
3889 /* All the simple cases only support two dpms states. */
3890 if (mode != DRM_MODE_DPMS_ON)
3891 mode = DRM_MODE_DPMS_OFF;
3892
3893 if (mode == connector->dpms)
3894 return;
3895
3896 connector->dpms = mode;
3897
3898 /* Only need to change hw state when actually enabled */
3899 if (encoder->base.crtc)
3900 intel_encoder_dpms(encoder, mode);
3901 else
3902 WARN_ON(encoder->connectors_active != false);
3903
3904 intel_modeset_check_state(connector->dev);
3905 }
3906
3907 /* Simple connector->get_hw_state implementation for encoders that support only
3908 * one connector and no cloning and hence the encoder state determines the state
3909 * of the connector. */
3910 bool intel_connector_get_hw_state(struct intel_connector *connector)
3911 {
3912 enum pipe pipe = 0;
3913 struct intel_encoder *encoder = connector->encoder;
3914
3915 return encoder->get_hw_state(encoder, &pipe);
3916 }
3917
3918 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3919 const struct drm_display_mode *mode,
3920 struct drm_display_mode *adjusted_mode)
3921 {
3922 struct drm_device *dev = crtc->dev;
3923
3924 if (HAS_PCH_SPLIT(dev)) {
3925 /* FDI link clock is fixed at 2.7G */
3926 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3927 return false;
3928 }
3929
3930 /* All interlaced capable intel hw wants timings in frames. Note though
3931 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3932 * timings, so we need to be careful not to clobber these.*/
3933 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3934 drm_mode_set_crtcinfo(adjusted_mode, 0);
3935
3936 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3937 * with a hsync front porch of 0.
3938 */
3939 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3940 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3941 return false;
3942
3943 return true;
3944 }
3945
3946 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3947 {
3948 return 400000; /* FIXME */
3949 }
3950
3951 static int i945_get_display_clock_speed(struct drm_device *dev)
3952 {
3953 return 400000;
3954 }
3955
3956 static int i915_get_display_clock_speed(struct drm_device *dev)
3957 {
3958 return 333000;
3959 }
3960
3961 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3962 {
3963 return 200000;
3964 }
3965
3966 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3967 {
3968 u16 gcfgc = 0;
3969
3970 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3971
3972 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3973 return 133000;
3974 else {
3975 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3976 case GC_DISPLAY_CLOCK_333_MHZ:
3977 return 333000;
3978 default:
3979 case GC_DISPLAY_CLOCK_190_200_MHZ:
3980 return 190000;
3981 }
3982 }
3983 }
3984
3985 static int i865_get_display_clock_speed(struct drm_device *dev)
3986 {
3987 return 266000;
3988 }
3989
3990 static int i855_get_display_clock_speed(struct drm_device *dev)
3991 {
3992 u16 hpllcc = 0;
3993 /* Assume that the hardware is in the high speed state. This
3994 * should be the default.
3995 */
3996 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3997 case GC_CLOCK_133_200:
3998 case GC_CLOCK_100_200:
3999 return 200000;
4000 case GC_CLOCK_166_250:
4001 return 250000;
4002 case GC_CLOCK_100_133:
4003 return 133000;
4004 }
4005
4006 /* Shouldn't happen */
4007 return 0;
4008 }
4009
4010 static int i830_get_display_clock_speed(struct drm_device *dev)
4011 {
4012 return 133000;
4013 }
4014
4015 struct fdi_m_n {
4016 u32 tu;
4017 u32 gmch_m;
4018 u32 gmch_n;
4019 u32 link_m;
4020 u32 link_n;
4021 };
4022
4023 static void
4024 fdi_reduce_ratio(u32 *num, u32 *den)
4025 {
4026 while (*num > 0xffffff || *den > 0xffffff) {
4027 *num >>= 1;
4028 *den >>= 1;
4029 }
4030 }
4031
4032 static void
4033 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4034 int link_clock, struct fdi_m_n *m_n)
4035 {
4036 m_n->tu = 64; /* default size */
4037
4038 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4039 m_n->gmch_m = bits_per_pixel * pixel_clock;
4040 m_n->gmch_n = link_clock * nlanes * 8;
4041 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4042
4043 m_n->link_m = pixel_clock;
4044 m_n->link_n = link_clock;
4045 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4046 }
4047
4048 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4049 {
4050 if (i915_panel_use_ssc >= 0)
4051 return i915_panel_use_ssc != 0;
4052 return dev_priv->lvds_use_ssc
4053 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4054 }
4055
4056 /**
4057 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4058 * @crtc: CRTC structure
4059 * @mode: requested mode
4060 *
4061 * A pipe may be connected to one or more outputs. Based on the depth of the
4062 * attached framebuffer, choose a good color depth to use on the pipe.
4063 *
4064 * If possible, match the pipe depth to the fb depth. In some cases, this
4065 * isn't ideal, because the connected output supports a lesser or restricted
4066 * set of depths. Resolve that here:
4067 * LVDS typically supports only 6bpc, so clamp down in that case
4068 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4069 * Displays may support a restricted set as well, check EDID and clamp as
4070 * appropriate.
4071 * DP may want to dither down to 6bpc to fit larger modes
4072 *
4073 * RETURNS:
4074 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4075 * true if they don't match).
4076 */
4077 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4078 struct drm_framebuffer *fb,
4079 unsigned int *pipe_bpp,
4080 struct drm_display_mode *mode)
4081 {
4082 struct drm_device *dev = crtc->dev;
4083 struct drm_i915_private *dev_priv = dev->dev_private;
4084 struct drm_connector *connector;
4085 struct intel_encoder *intel_encoder;
4086 unsigned int display_bpc = UINT_MAX, bpc;
4087
4088 /* Walk the encoders & connectors on this crtc, get min bpc */
4089 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4090
4091 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4092 unsigned int lvds_bpc;
4093
4094 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4095 LVDS_A3_POWER_UP)
4096 lvds_bpc = 8;
4097 else
4098 lvds_bpc = 6;
4099
4100 if (lvds_bpc < display_bpc) {
4101 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4102 display_bpc = lvds_bpc;
4103 }
4104 continue;
4105 }
4106
4107 /* Not one of the known troublemakers, check the EDID */
4108 list_for_each_entry(connector, &dev->mode_config.connector_list,
4109 head) {
4110 if (connector->encoder != &intel_encoder->base)
4111 continue;
4112
4113 /* Don't use an invalid EDID bpc value */
4114 if (connector->display_info.bpc &&
4115 connector->display_info.bpc < display_bpc) {
4116 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4117 display_bpc = connector->display_info.bpc;
4118 }
4119 }
4120
4121 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4122 /* Use VBT settings if we have an eDP panel */
4123 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4124
4125 if (edp_bpc && edp_bpc < display_bpc) {
4126 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4127 display_bpc = edp_bpc;
4128 }
4129 continue;
4130 }
4131
4132 /*
4133 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4134 * through, clamp it down. (Note: >12bpc will be caught below.)
4135 */
4136 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4137 if (display_bpc > 8 && display_bpc < 12) {
4138 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4139 display_bpc = 12;
4140 } else {
4141 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4142 display_bpc = 8;
4143 }
4144 }
4145 }
4146
4147 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4148 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4149 display_bpc = 6;
4150 }
4151
4152 /*
4153 * We could just drive the pipe at the highest bpc all the time and
4154 * enable dithering as needed, but that costs bandwidth. So choose
4155 * the minimum value that expresses the full color range of the fb but
4156 * also stays within the max display bpc discovered above.
4157 */
4158
4159 switch (fb->depth) {
4160 case 8:
4161 bpc = 8; /* since we go through a colormap */
4162 break;
4163 case 15:
4164 case 16:
4165 bpc = 6; /* min is 18bpp */
4166 break;
4167 case 24:
4168 bpc = 8;
4169 break;
4170 case 30:
4171 bpc = 10;
4172 break;
4173 case 48:
4174 bpc = 12;
4175 break;
4176 default:
4177 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4178 bpc = min((unsigned int)8, display_bpc);
4179 break;
4180 }
4181
4182 display_bpc = min(display_bpc, bpc);
4183
4184 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4185 bpc, display_bpc);
4186
4187 *pipe_bpp = display_bpc * 3;
4188
4189 return display_bpc != bpc;
4190 }
4191
4192 static int vlv_get_refclk(struct drm_crtc *crtc)
4193 {
4194 struct drm_device *dev = crtc->dev;
4195 struct drm_i915_private *dev_priv = dev->dev_private;
4196 int refclk = 27000; /* for DP & HDMI */
4197
4198 return 100000; /* only one validated so far */
4199
4200 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4201 refclk = 96000;
4202 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4203 if (intel_panel_use_ssc(dev_priv))
4204 refclk = 100000;
4205 else
4206 refclk = 96000;
4207 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4208 refclk = 100000;
4209 }
4210
4211 return refclk;
4212 }
4213
4214 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4215 {
4216 struct drm_device *dev = crtc->dev;
4217 struct drm_i915_private *dev_priv = dev->dev_private;
4218 int refclk;
4219
4220 if (IS_VALLEYVIEW(dev)) {
4221 refclk = vlv_get_refclk(crtc);
4222 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4223 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4224 refclk = dev_priv->lvds_ssc_freq * 1000;
4225 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4226 refclk / 1000);
4227 } else if (!IS_GEN2(dev)) {
4228 refclk = 96000;
4229 } else {
4230 refclk = 48000;
4231 }
4232
4233 return refclk;
4234 }
4235
4236 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4237 intel_clock_t *clock)
4238 {
4239 /* SDVO TV has fixed PLL values depend on its clock range,
4240 this mirrors vbios setting. */
4241 if (adjusted_mode->clock >= 100000
4242 && adjusted_mode->clock < 140500) {
4243 clock->p1 = 2;
4244 clock->p2 = 10;
4245 clock->n = 3;
4246 clock->m1 = 16;
4247 clock->m2 = 8;
4248 } else if (adjusted_mode->clock >= 140500
4249 && adjusted_mode->clock <= 200000) {
4250 clock->p1 = 1;
4251 clock->p2 = 10;
4252 clock->n = 6;
4253 clock->m1 = 12;
4254 clock->m2 = 8;
4255 }
4256 }
4257
4258 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4259 intel_clock_t *clock,
4260 intel_clock_t *reduced_clock)
4261 {
4262 struct drm_device *dev = crtc->dev;
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265 int pipe = intel_crtc->pipe;
4266 u32 fp, fp2 = 0;
4267
4268 if (IS_PINEVIEW(dev)) {
4269 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4270 if (reduced_clock)
4271 fp2 = (1 << reduced_clock->n) << 16 |
4272 reduced_clock->m1 << 8 | reduced_clock->m2;
4273 } else {
4274 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4275 if (reduced_clock)
4276 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4277 reduced_clock->m2;
4278 }
4279
4280 I915_WRITE(FP0(pipe), fp);
4281
4282 intel_crtc->lowfreq_avail = false;
4283 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4284 reduced_clock && i915_powersave) {
4285 I915_WRITE(FP1(pipe), fp2);
4286 intel_crtc->lowfreq_avail = true;
4287 } else {
4288 I915_WRITE(FP1(pipe), fp);
4289 }
4290 }
4291
4292 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4293 struct drm_display_mode *adjusted_mode)
4294 {
4295 struct drm_device *dev = crtc->dev;
4296 struct drm_i915_private *dev_priv = dev->dev_private;
4297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4298 int pipe = intel_crtc->pipe;
4299 u32 temp;
4300
4301 temp = I915_READ(LVDS);
4302 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4303 if (pipe == 1) {
4304 temp |= LVDS_PIPEB_SELECT;
4305 } else {
4306 temp &= ~LVDS_PIPEB_SELECT;
4307 }
4308 /* set the corresponsding LVDS_BORDER bit */
4309 temp |= dev_priv->lvds_border_bits;
4310 /* Set the B0-B3 data pairs corresponding to whether we're going to
4311 * set the DPLLs for dual-channel mode or not.
4312 */
4313 if (clock->p2 == 7)
4314 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4315 else
4316 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4317
4318 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4319 * appropriately here, but we need to look more thoroughly into how
4320 * panels behave in the two modes.
4321 */
4322 /* set the dithering flag on LVDS as needed */
4323 if (INTEL_INFO(dev)->gen >= 4) {
4324 if (dev_priv->lvds_dither)
4325 temp |= LVDS_ENABLE_DITHER;
4326 else
4327 temp &= ~LVDS_ENABLE_DITHER;
4328 }
4329 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4330 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4331 temp |= LVDS_HSYNC_POLARITY;
4332 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4333 temp |= LVDS_VSYNC_POLARITY;
4334 I915_WRITE(LVDS, temp);
4335 }
4336
4337 static void vlv_update_pll(struct drm_crtc *crtc,
4338 struct drm_display_mode *mode,
4339 struct drm_display_mode *adjusted_mode,
4340 intel_clock_t *clock, intel_clock_t *reduced_clock,
4341 int num_connectors)
4342 {
4343 struct drm_device *dev = crtc->dev;
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4346 int pipe = intel_crtc->pipe;
4347 u32 dpll, mdiv, pdiv;
4348 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4349 bool is_sdvo;
4350 u32 temp;
4351
4352 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4353 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4354
4355 dpll = DPLL_VGA_MODE_DIS;
4356 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4357 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4358 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4359
4360 I915_WRITE(DPLL(pipe), dpll);
4361 POSTING_READ(DPLL(pipe));
4362
4363 bestn = clock->n;
4364 bestm1 = clock->m1;
4365 bestm2 = clock->m2;
4366 bestp1 = clock->p1;
4367 bestp2 = clock->p2;
4368
4369 /*
4370 * In Valleyview PLL and program lane counter registers are exposed
4371 * through DPIO interface
4372 */
4373 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4374 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4375 mdiv |= ((bestn << DPIO_N_SHIFT));
4376 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4377 mdiv |= (1 << DPIO_K_SHIFT);
4378 mdiv |= DPIO_ENABLE_CALIBRATION;
4379 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4380
4381 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4382
4383 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4384 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4385 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4386 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4387 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4388
4389 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4390
4391 dpll |= DPLL_VCO_ENABLE;
4392 I915_WRITE(DPLL(pipe), dpll);
4393 POSTING_READ(DPLL(pipe));
4394 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4395 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4396
4397 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4398
4399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4400 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4401
4402 I915_WRITE(DPLL(pipe), dpll);
4403
4404 /* Wait for the clocks to stabilize. */
4405 POSTING_READ(DPLL(pipe));
4406 udelay(150);
4407
4408 temp = 0;
4409 if (is_sdvo) {
4410 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4411 if (temp > 1)
4412 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4413 else
4414 temp = 0;
4415 }
4416 I915_WRITE(DPLL_MD(pipe), temp);
4417 POSTING_READ(DPLL_MD(pipe));
4418
4419 /* Now program lane control registers */
4420 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4421 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4422 {
4423 temp = 0x1000C4;
4424 if(pipe == 1)
4425 temp |= (1 << 21);
4426 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4427 }
4428 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4429 {
4430 temp = 0x1000C4;
4431 if(pipe == 1)
4432 temp |= (1 << 21);
4433 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4434 }
4435 }
4436
4437 static void i9xx_update_pll(struct drm_crtc *crtc,
4438 struct drm_display_mode *mode,
4439 struct drm_display_mode *adjusted_mode,
4440 intel_clock_t *clock, intel_clock_t *reduced_clock,
4441 int num_connectors)
4442 {
4443 struct drm_device *dev = crtc->dev;
4444 struct drm_i915_private *dev_priv = dev->dev_private;
4445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4446 int pipe = intel_crtc->pipe;
4447 u32 dpll;
4448 bool is_sdvo;
4449
4450 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4451
4452 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4453 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4454
4455 dpll = DPLL_VGA_MODE_DIS;
4456
4457 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4458 dpll |= DPLLB_MODE_LVDS;
4459 else
4460 dpll |= DPLLB_MODE_DAC_SERIAL;
4461 if (is_sdvo) {
4462 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4463 if (pixel_multiplier > 1) {
4464 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4465 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4466 }
4467 dpll |= DPLL_DVO_HIGH_SPEED;
4468 }
4469 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4470 dpll |= DPLL_DVO_HIGH_SPEED;
4471
4472 /* compute bitmask from p1 value */
4473 if (IS_PINEVIEW(dev))
4474 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4475 else {
4476 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4477 if (IS_G4X(dev) && reduced_clock)
4478 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4479 }
4480 switch (clock->p2) {
4481 case 5:
4482 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4483 break;
4484 case 7:
4485 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4486 break;
4487 case 10:
4488 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4489 break;
4490 case 14:
4491 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4492 break;
4493 }
4494 if (INTEL_INFO(dev)->gen >= 4)
4495 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4496
4497 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4498 dpll |= PLL_REF_INPUT_TVCLKINBC;
4499 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4500 /* XXX: just matching BIOS for now */
4501 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4502 dpll |= 3;
4503 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4504 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4505 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4506 else
4507 dpll |= PLL_REF_INPUT_DREFCLK;
4508
4509 dpll |= DPLL_VCO_ENABLE;
4510 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4511 POSTING_READ(DPLL(pipe));
4512 udelay(150);
4513
4514 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4515 * This is an exception to the general rule that mode_set doesn't turn
4516 * things on.
4517 */
4518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4519 intel_update_lvds(crtc, clock, adjusted_mode);
4520
4521 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4522 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4523
4524 I915_WRITE(DPLL(pipe), dpll);
4525
4526 /* Wait for the clocks to stabilize. */
4527 POSTING_READ(DPLL(pipe));
4528 udelay(150);
4529
4530 if (INTEL_INFO(dev)->gen >= 4) {
4531 u32 temp = 0;
4532 if (is_sdvo) {
4533 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4534 if (temp > 1)
4535 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4536 else
4537 temp = 0;
4538 }
4539 I915_WRITE(DPLL_MD(pipe), temp);
4540 } else {
4541 /* The pixel multiplier can only be updated once the
4542 * DPLL is enabled and the clocks are stable.
4543 *
4544 * So write it again.
4545 */
4546 I915_WRITE(DPLL(pipe), dpll);
4547 }
4548 }
4549
4550 static void i8xx_update_pll(struct drm_crtc *crtc,
4551 struct drm_display_mode *adjusted_mode,
4552 intel_clock_t *clock, intel_clock_t *reduced_clock,
4553 int num_connectors)
4554 {
4555 struct drm_device *dev = crtc->dev;
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4558 int pipe = intel_crtc->pipe;
4559 u32 dpll;
4560
4561 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4562
4563 dpll = DPLL_VGA_MODE_DIS;
4564
4565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4566 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4567 } else {
4568 if (clock->p1 == 2)
4569 dpll |= PLL_P1_DIVIDE_BY_TWO;
4570 else
4571 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4572 if (clock->p2 == 4)
4573 dpll |= PLL_P2_DIVIDE_BY_4;
4574 }
4575
4576 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4577 /* XXX: just matching BIOS for now */
4578 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4579 dpll |= 3;
4580 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4581 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4582 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4583 else
4584 dpll |= PLL_REF_INPUT_DREFCLK;
4585
4586 dpll |= DPLL_VCO_ENABLE;
4587 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4588 POSTING_READ(DPLL(pipe));
4589 udelay(150);
4590
4591 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4592 * This is an exception to the general rule that mode_set doesn't turn
4593 * things on.
4594 */
4595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4596 intel_update_lvds(crtc, clock, adjusted_mode);
4597
4598 I915_WRITE(DPLL(pipe), dpll);
4599
4600 /* Wait for the clocks to stabilize. */
4601 POSTING_READ(DPLL(pipe));
4602 udelay(150);
4603
4604 /* The pixel multiplier can only be updated once the
4605 * DPLL is enabled and the clocks are stable.
4606 *
4607 * So write it again.
4608 */
4609 I915_WRITE(DPLL(pipe), dpll);
4610 }
4611
4612 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4613 struct drm_display_mode *mode,
4614 struct drm_display_mode *adjusted_mode)
4615 {
4616 struct drm_device *dev = intel_crtc->base.dev;
4617 struct drm_i915_private *dev_priv = dev->dev_private;
4618 enum pipe pipe = intel_crtc->pipe;
4619 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4620 uint32_t vsyncshift;
4621
4622 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4623 /* the chip adds 2 halflines automatically */
4624 adjusted_mode->crtc_vtotal -= 1;
4625 adjusted_mode->crtc_vblank_end -= 1;
4626 vsyncshift = adjusted_mode->crtc_hsync_start
4627 - adjusted_mode->crtc_htotal / 2;
4628 } else {
4629 vsyncshift = 0;
4630 }
4631
4632 if (INTEL_INFO(dev)->gen > 3)
4633 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4634
4635 I915_WRITE(HTOTAL(cpu_transcoder),
4636 (adjusted_mode->crtc_hdisplay - 1) |
4637 ((adjusted_mode->crtc_htotal - 1) << 16));
4638 I915_WRITE(HBLANK(cpu_transcoder),
4639 (adjusted_mode->crtc_hblank_start - 1) |
4640 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4641 I915_WRITE(HSYNC(cpu_transcoder),
4642 (adjusted_mode->crtc_hsync_start - 1) |
4643 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4644
4645 I915_WRITE(VTOTAL(cpu_transcoder),
4646 (adjusted_mode->crtc_vdisplay - 1) |
4647 ((adjusted_mode->crtc_vtotal - 1) << 16));
4648 I915_WRITE(VBLANK(cpu_transcoder),
4649 (adjusted_mode->crtc_vblank_start - 1) |
4650 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4651 I915_WRITE(VSYNC(cpu_transcoder),
4652 (adjusted_mode->crtc_vsync_start - 1) |
4653 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4654
4655 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4656 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4657 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4658 * bits. */
4659 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4660 (pipe == PIPE_B || pipe == PIPE_C))
4661 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4662
4663 /* pipesrc controls the size that is scaled from, which should
4664 * always be the user's requested size.
4665 */
4666 I915_WRITE(PIPESRC(pipe),
4667 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4668 }
4669
4670 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4671 struct drm_display_mode *mode,
4672 struct drm_display_mode *adjusted_mode,
4673 int x, int y,
4674 struct drm_framebuffer *fb)
4675 {
4676 struct drm_device *dev = crtc->dev;
4677 struct drm_i915_private *dev_priv = dev->dev_private;
4678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4679 int pipe = intel_crtc->pipe;
4680 int plane = intel_crtc->plane;
4681 int refclk, num_connectors = 0;
4682 intel_clock_t clock, reduced_clock;
4683 u32 dspcntr, pipeconf;
4684 bool ok, has_reduced_clock = false, is_sdvo = false;
4685 bool is_lvds = false, is_tv = false, is_dp = false;
4686 struct intel_encoder *encoder;
4687 const intel_limit_t *limit;
4688 int ret;
4689
4690 for_each_encoder_on_crtc(dev, crtc, encoder) {
4691 switch (encoder->type) {
4692 case INTEL_OUTPUT_LVDS:
4693 is_lvds = true;
4694 break;
4695 case INTEL_OUTPUT_SDVO:
4696 case INTEL_OUTPUT_HDMI:
4697 is_sdvo = true;
4698 if (encoder->needs_tv_clock)
4699 is_tv = true;
4700 break;
4701 case INTEL_OUTPUT_TVOUT:
4702 is_tv = true;
4703 break;
4704 case INTEL_OUTPUT_DISPLAYPORT:
4705 is_dp = true;
4706 break;
4707 }
4708
4709 num_connectors++;
4710 }
4711
4712 refclk = i9xx_get_refclk(crtc, num_connectors);
4713
4714 /*
4715 * Returns a set of divisors for the desired target clock with the given
4716 * refclk, or FALSE. The returned values represent the clock equation:
4717 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4718 */
4719 limit = intel_limit(crtc, refclk);
4720 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4721 &clock);
4722 if (!ok) {
4723 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4724 return -EINVAL;
4725 }
4726
4727 /* Ensure that the cursor is valid for the new mode before changing... */
4728 intel_crtc_update_cursor(crtc, true);
4729
4730 if (is_lvds && dev_priv->lvds_downclock_avail) {
4731 /*
4732 * Ensure we match the reduced clock's P to the target clock.
4733 * If the clocks don't match, we can't switch the display clock
4734 * by using the FP0/FP1. In such case we will disable the LVDS
4735 * downclock feature.
4736 */
4737 has_reduced_clock = limit->find_pll(limit, crtc,
4738 dev_priv->lvds_downclock,
4739 refclk,
4740 &clock,
4741 &reduced_clock);
4742 }
4743
4744 if (is_sdvo && is_tv)
4745 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4746
4747 if (IS_GEN2(dev))
4748 i8xx_update_pll(crtc, adjusted_mode, &clock,
4749 has_reduced_clock ? &reduced_clock : NULL,
4750 num_connectors);
4751 else if (IS_VALLEYVIEW(dev))
4752 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4753 has_reduced_clock ? &reduced_clock : NULL,
4754 num_connectors);
4755 else
4756 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4757 has_reduced_clock ? &reduced_clock : NULL,
4758 num_connectors);
4759
4760 /* setup pipeconf */
4761 pipeconf = I915_READ(PIPECONF(pipe));
4762
4763 /* Set up the display plane register */
4764 dspcntr = DISPPLANE_GAMMA_ENABLE;
4765
4766 if (pipe == 0)
4767 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4768 else
4769 dspcntr |= DISPPLANE_SEL_PIPE_B;
4770
4771 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4772 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4773 * core speed.
4774 *
4775 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4776 * pipe == 0 check?
4777 */
4778 if (mode->clock >
4779 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4780 pipeconf |= PIPECONF_DOUBLE_WIDE;
4781 else
4782 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4783 }
4784
4785 /* default to 8bpc */
4786 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4787 if (is_dp) {
4788 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4789 pipeconf |= PIPECONF_BPP_6 |
4790 PIPECONF_DITHER_EN |
4791 PIPECONF_DITHER_TYPE_SP;
4792 }
4793 }
4794
4795 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4796 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4797 pipeconf |= PIPECONF_BPP_6 |
4798 PIPECONF_ENABLE |
4799 I965_PIPECONF_ACTIVE;
4800 }
4801 }
4802
4803 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4804 drm_mode_debug_printmodeline(mode);
4805
4806 if (HAS_PIPE_CXSR(dev)) {
4807 if (intel_crtc->lowfreq_avail) {
4808 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4809 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4810 } else {
4811 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4812 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4813 }
4814 }
4815
4816 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4817 if (!IS_GEN2(dev) &&
4818 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4819 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4820 else
4821 pipeconf |= PIPECONF_PROGRESSIVE;
4822
4823 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4824
4825 /* pipesrc and dspsize control the size that is scaled from,
4826 * which should always be the user's requested size.
4827 */
4828 I915_WRITE(DSPSIZE(plane),
4829 ((mode->vdisplay - 1) << 16) |
4830 (mode->hdisplay - 1));
4831 I915_WRITE(DSPPOS(plane), 0);
4832
4833 I915_WRITE(PIPECONF(pipe), pipeconf);
4834 POSTING_READ(PIPECONF(pipe));
4835 intel_enable_pipe(dev_priv, pipe, false);
4836
4837 intel_wait_for_vblank(dev, pipe);
4838
4839 I915_WRITE(DSPCNTR(plane), dspcntr);
4840 POSTING_READ(DSPCNTR(plane));
4841
4842 ret = intel_pipe_set_base(crtc, x, y, fb);
4843
4844 intel_update_watermarks(dev);
4845
4846 return ret;
4847 }
4848
4849 static void ironlake_init_pch_refclk(struct drm_device *dev)
4850 {
4851 struct drm_i915_private *dev_priv = dev->dev_private;
4852 struct drm_mode_config *mode_config = &dev->mode_config;
4853 struct intel_encoder *encoder;
4854 u32 temp;
4855 bool has_lvds = false;
4856 bool has_cpu_edp = false;
4857 bool has_pch_edp = false;
4858 bool has_panel = false;
4859 bool has_ck505 = false;
4860 bool can_ssc = false;
4861
4862 /* We need to take the global config into account */
4863 list_for_each_entry(encoder, &mode_config->encoder_list,
4864 base.head) {
4865 switch (encoder->type) {
4866 case INTEL_OUTPUT_LVDS:
4867 has_panel = true;
4868 has_lvds = true;
4869 break;
4870 case INTEL_OUTPUT_EDP:
4871 has_panel = true;
4872 if (intel_encoder_is_pch_edp(&encoder->base))
4873 has_pch_edp = true;
4874 else
4875 has_cpu_edp = true;
4876 break;
4877 }
4878 }
4879
4880 if (HAS_PCH_IBX(dev)) {
4881 has_ck505 = dev_priv->display_clock_mode;
4882 can_ssc = has_ck505;
4883 } else {
4884 has_ck505 = false;
4885 can_ssc = true;
4886 }
4887
4888 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4889 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4890 has_ck505);
4891
4892 /* Ironlake: try to setup display ref clock before DPLL
4893 * enabling. This is only under driver's control after
4894 * PCH B stepping, previous chipset stepping should be
4895 * ignoring this setting.
4896 */
4897 temp = I915_READ(PCH_DREF_CONTROL);
4898 /* Always enable nonspread source */
4899 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4900
4901 if (has_ck505)
4902 temp |= DREF_NONSPREAD_CK505_ENABLE;
4903 else
4904 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4905
4906 if (has_panel) {
4907 temp &= ~DREF_SSC_SOURCE_MASK;
4908 temp |= DREF_SSC_SOURCE_ENABLE;
4909
4910 /* SSC must be turned on before enabling the CPU output */
4911 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4912 DRM_DEBUG_KMS("Using SSC on panel\n");
4913 temp |= DREF_SSC1_ENABLE;
4914 } else
4915 temp &= ~DREF_SSC1_ENABLE;
4916
4917 /* Get SSC going before enabling the outputs */
4918 I915_WRITE(PCH_DREF_CONTROL, temp);
4919 POSTING_READ(PCH_DREF_CONTROL);
4920 udelay(200);
4921
4922 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4923
4924 /* Enable CPU source on CPU attached eDP */
4925 if (has_cpu_edp) {
4926 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4927 DRM_DEBUG_KMS("Using SSC on eDP\n");
4928 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4929 }
4930 else
4931 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4932 } else
4933 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4934
4935 I915_WRITE(PCH_DREF_CONTROL, temp);
4936 POSTING_READ(PCH_DREF_CONTROL);
4937 udelay(200);
4938 } else {
4939 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4940
4941 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4942
4943 /* Turn off CPU output */
4944 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4945
4946 I915_WRITE(PCH_DREF_CONTROL, temp);
4947 POSTING_READ(PCH_DREF_CONTROL);
4948 udelay(200);
4949
4950 /* Turn off the SSC source */
4951 temp &= ~DREF_SSC_SOURCE_MASK;
4952 temp |= DREF_SSC_SOURCE_DISABLE;
4953
4954 /* Turn off SSC1 */
4955 temp &= ~ DREF_SSC1_ENABLE;
4956
4957 I915_WRITE(PCH_DREF_CONTROL, temp);
4958 POSTING_READ(PCH_DREF_CONTROL);
4959 udelay(200);
4960 }
4961 }
4962
4963 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4964 static void lpt_init_pch_refclk(struct drm_device *dev)
4965 {
4966 struct drm_i915_private *dev_priv = dev->dev_private;
4967 struct drm_mode_config *mode_config = &dev->mode_config;
4968 struct intel_encoder *encoder;
4969 bool has_vga = false;
4970 bool is_sdv = false;
4971 u32 tmp;
4972
4973 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4974 switch (encoder->type) {
4975 case INTEL_OUTPUT_ANALOG:
4976 has_vga = true;
4977 break;
4978 }
4979 }
4980
4981 if (!has_vga)
4982 return;
4983
4984 /* XXX: Rip out SDV support once Haswell ships for real. */
4985 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4986 is_sdv = true;
4987
4988 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4989 tmp &= ~SBI_SSCCTL_DISABLE;
4990 tmp |= SBI_SSCCTL_PATHALT;
4991 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4992
4993 udelay(24);
4994
4995 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4996 tmp &= ~SBI_SSCCTL_PATHALT;
4997 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4998
4999 if (!is_sdv) {
5000 tmp = I915_READ(SOUTH_CHICKEN2);
5001 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5002 I915_WRITE(SOUTH_CHICKEN2, tmp);
5003
5004 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5005 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5006 DRM_ERROR("FDI mPHY reset assert timeout\n");
5007
5008 tmp = I915_READ(SOUTH_CHICKEN2);
5009 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5010 I915_WRITE(SOUTH_CHICKEN2, tmp);
5011
5012 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5013 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5014 100))
5015 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5016 }
5017
5018 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5019 tmp &= ~(0xFF << 24);
5020 tmp |= (0x12 << 24);
5021 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5022
5023 if (!is_sdv) {
5024 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
5025 tmp &= ~(0x3 << 6);
5026 tmp |= (1 << 6) | (1 << 0);
5027 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
5028 }
5029
5030 if (is_sdv) {
5031 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5032 tmp |= 0x7FFF;
5033 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5034 }
5035
5036 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5037 tmp |= (1 << 11);
5038 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5039
5040 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5041 tmp |= (1 << 11);
5042 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5043
5044 if (is_sdv) {
5045 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5046 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5047 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5048
5049 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5050 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5051 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5052
5053 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5054 tmp |= (0x3F << 8);
5055 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5056
5057 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5058 tmp |= (0x3F << 8);
5059 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5060 }
5061
5062 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5063 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5064 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5065
5066 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5067 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5068 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5069
5070 if (!is_sdv) {
5071 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5072 tmp &= ~(7 << 13);
5073 tmp |= (5 << 13);
5074 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5075
5076 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5077 tmp &= ~(7 << 13);
5078 tmp |= (5 << 13);
5079 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5080 }
5081
5082 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5083 tmp &= ~0xFF;
5084 tmp |= 0x1C;
5085 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5086
5087 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5088 tmp &= ~0xFF;
5089 tmp |= 0x1C;
5090 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5091
5092 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5093 tmp &= ~(0xFF << 16);
5094 tmp |= (0x1C << 16);
5095 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5096
5097 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5098 tmp &= ~(0xFF << 16);
5099 tmp |= (0x1C << 16);
5100 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5101
5102 if (!is_sdv) {
5103 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5104 tmp |= (1 << 27);
5105 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5106
5107 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5108 tmp |= (1 << 27);
5109 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5110
5111 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5112 tmp &= ~(0xF << 28);
5113 tmp |= (4 << 28);
5114 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5115
5116 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5117 tmp &= ~(0xF << 28);
5118 tmp |= (4 << 28);
5119 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5120 }
5121
5122 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5123 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5124 tmp |= SBI_DBUFF0_ENABLE;
5125 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5126 }
5127
5128 /*
5129 * Initialize reference clocks when the driver loads
5130 */
5131 void intel_init_pch_refclk(struct drm_device *dev)
5132 {
5133 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5134 ironlake_init_pch_refclk(dev);
5135 else if (HAS_PCH_LPT(dev))
5136 lpt_init_pch_refclk(dev);
5137 }
5138
5139 static int ironlake_get_refclk(struct drm_crtc *crtc)
5140 {
5141 struct drm_device *dev = crtc->dev;
5142 struct drm_i915_private *dev_priv = dev->dev_private;
5143 struct intel_encoder *encoder;
5144 struct intel_encoder *edp_encoder = NULL;
5145 int num_connectors = 0;
5146 bool is_lvds = false;
5147
5148 for_each_encoder_on_crtc(dev, crtc, encoder) {
5149 switch (encoder->type) {
5150 case INTEL_OUTPUT_LVDS:
5151 is_lvds = true;
5152 break;
5153 case INTEL_OUTPUT_EDP:
5154 edp_encoder = encoder;
5155 break;
5156 }
5157 num_connectors++;
5158 }
5159
5160 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5161 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5162 dev_priv->lvds_ssc_freq);
5163 return dev_priv->lvds_ssc_freq * 1000;
5164 }
5165
5166 return 120000;
5167 }
5168
5169 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5170 struct drm_display_mode *adjusted_mode,
5171 bool dither)
5172 {
5173 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5175 int pipe = intel_crtc->pipe;
5176 uint32_t val;
5177
5178 val = I915_READ(PIPECONF(pipe));
5179
5180 val &= ~PIPE_BPC_MASK;
5181 switch (intel_crtc->bpp) {
5182 case 18:
5183 val |= PIPE_6BPC;
5184 break;
5185 case 24:
5186 val |= PIPE_8BPC;
5187 break;
5188 case 30:
5189 val |= PIPE_10BPC;
5190 break;
5191 case 36:
5192 val |= PIPE_12BPC;
5193 break;
5194 default:
5195 /* Case prevented by intel_choose_pipe_bpp_dither. */
5196 BUG();
5197 }
5198
5199 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5200 if (dither)
5201 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5202
5203 val &= ~PIPECONF_INTERLACE_MASK;
5204 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5205 val |= PIPECONF_INTERLACED_ILK;
5206 else
5207 val |= PIPECONF_PROGRESSIVE;
5208
5209 I915_WRITE(PIPECONF(pipe), val);
5210 POSTING_READ(PIPECONF(pipe));
5211 }
5212
5213 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5214 struct drm_display_mode *adjusted_mode,
5215 bool dither)
5216 {
5217 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5219 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5220 uint32_t val;
5221
5222 val = I915_READ(PIPECONF(cpu_transcoder));
5223
5224 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5225 if (dither)
5226 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5227
5228 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5229 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5230 val |= PIPECONF_INTERLACED_ILK;
5231 else
5232 val |= PIPECONF_PROGRESSIVE;
5233
5234 I915_WRITE(PIPECONF(cpu_transcoder), val);
5235 POSTING_READ(PIPECONF(cpu_transcoder));
5236 }
5237
5238 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5239 struct drm_display_mode *adjusted_mode,
5240 intel_clock_t *clock,
5241 bool *has_reduced_clock,
5242 intel_clock_t *reduced_clock)
5243 {
5244 struct drm_device *dev = crtc->dev;
5245 struct drm_i915_private *dev_priv = dev->dev_private;
5246 struct intel_encoder *intel_encoder;
5247 int refclk;
5248 const intel_limit_t *limit;
5249 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5250
5251 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5252 switch (intel_encoder->type) {
5253 case INTEL_OUTPUT_LVDS:
5254 is_lvds = true;
5255 break;
5256 case INTEL_OUTPUT_SDVO:
5257 case INTEL_OUTPUT_HDMI:
5258 is_sdvo = true;
5259 if (intel_encoder->needs_tv_clock)
5260 is_tv = true;
5261 break;
5262 case INTEL_OUTPUT_TVOUT:
5263 is_tv = true;
5264 break;
5265 }
5266 }
5267
5268 refclk = ironlake_get_refclk(crtc);
5269
5270 /*
5271 * Returns a set of divisors for the desired target clock with the given
5272 * refclk, or FALSE. The returned values represent the clock equation:
5273 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5274 */
5275 limit = intel_limit(crtc, refclk);
5276 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5277 clock);
5278 if (!ret)
5279 return false;
5280
5281 if (is_lvds && dev_priv->lvds_downclock_avail) {
5282 /*
5283 * Ensure we match the reduced clock's P to the target clock.
5284 * If the clocks don't match, we can't switch the display clock
5285 * by using the FP0/FP1. In such case we will disable the LVDS
5286 * downclock feature.
5287 */
5288 *has_reduced_clock = limit->find_pll(limit, crtc,
5289 dev_priv->lvds_downclock,
5290 refclk,
5291 clock,
5292 reduced_clock);
5293 }
5294
5295 if (is_sdvo && is_tv)
5296 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5297
5298 return true;
5299 }
5300
5301 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5302 {
5303 struct drm_i915_private *dev_priv = dev->dev_private;
5304 uint32_t temp;
5305
5306 temp = I915_READ(SOUTH_CHICKEN1);
5307 if (temp & FDI_BC_BIFURCATION_SELECT)
5308 return;
5309
5310 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5311 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5312
5313 temp |= FDI_BC_BIFURCATION_SELECT;
5314 DRM_DEBUG_KMS("enabling fdi C rx\n");
5315 I915_WRITE(SOUTH_CHICKEN1, temp);
5316 POSTING_READ(SOUTH_CHICKEN1);
5317 }
5318
5319 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5320 {
5321 struct drm_device *dev = intel_crtc->base.dev;
5322 struct drm_i915_private *dev_priv = dev->dev_private;
5323 struct intel_crtc *pipe_B_crtc =
5324 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5325
5326 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5327 intel_crtc->pipe, intel_crtc->fdi_lanes);
5328 if (intel_crtc->fdi_lanes > 4) {
5329 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5330 intel_crtc->pipe, intel_crtc->fdi_lanes);
5331 /* Clamp lanes to avoid programming the hw with bogus values. */
5332 intel_crtc->fdi_lanes = 4;
5333
5334 return false;
5335 }
5336
5337 if (dev_priv->num_pipe == 2)
5338 return true;
5339
5340 switch (intel_crtc->pipe) {
5341 case PIPE_A:
5342 return true;
5343 case PIPE_B:
5344 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5345 intel_crtc->fdi_lanes > 2) {
5346 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5347 intel_crtc->pipe, intel_crtc->fdi_lanes);
5348 /* Clamp lanes to avoid programming the hw with bogus values. */
5349 intel_crtc->fdi_lanes = 2;
5350
5351 return false;
5352 }
5353
5354 if (intel_crtc->fdi_lanes > 2)
5355 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5356 else
5357 cpt_enable_fdi_bc_bifurcation(dev);
5358
5359 return true;
5360 case PIPE_C:
5361 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5362 if (intel_crtc->fdi_lanes > 2) {
5363 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5364 intel_crtc->pipe, intel_crtc->fdi_lanes);
5365 /* Clamp lanes to avoid programming the hw with bogus values. */
5366 intel_crtc->fdi_lanes = 2;
5367
5368 return false;
5369 }
5370 } else {
5371 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5372 return false;
5373 }
5374
5375 cpt_enable_fdi_bc_bifurcation(dev);
5376
5377 return true;
5378 default:
5379 BUG();
5380 }
5381 }
5382
5383 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5384 {
5385 /*
5386 * Account for spread spectrum to avoid
5387 * oversubscribing the link. Max center spread
5388 * is 2.5%; use 5% for safety's sake.
5389 */
5390 u32 bps = target_clock * bpp * 21 / 20;
5391 return bps / (link_bw * 8) + 1;
5392 }
5393
5394 static void ironlake_set_m_n(struct drm_crtc *crtc,
5395 struct drm_display_mode *mode,
5396 struct drm_display_mode *adjusted_mode)
5397 {
5398 struct drm_device *dev = crtc->dev;
5399 struct drm_i915_private *dev_priv = dev->dev_private;
5400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5401 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5402 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5403 struct fdi_m_n m_n = {0};
5404 int target_clock, pixel_multiplier, lane, link_bw;
5405 bool is_dp = false, is_cpu_edp = false;
5406
5407 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5408 switch (intel_encoder->type) {
5409 case INTEL_OUTPUT_DISPLAYPORT:
5410 is_dp = true;
5411 break;
5412 case INTEL_OUTPUT_EDP:
5413 is_dp = true;
5414 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5415 is_cpu_edp = true;
5416 edp_encoder = intel_encoder;
5417 break;
5418 }
5419 }
5420
5421 /* FDI link */
5422 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5423 lane = 0;
5424 /* CPU eDP doesn't require FDI link, so just set DP M/N
5425 according to current link config */
5426 if (is_cpu_edp) {
5427 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5428 } else {
5429 /* FDI is a binary signal running at ~2.7GHz, encoding
5430 * each output octet as 10 bits. The actual frequency
5431 * is stored as a divider into a 100MHz clock, and the
5432 * mode pixel clock is stored in units of 1KHz.
5433 * Hence the bw of each lane in terms of the mode signal
5434 * is:
5435 */
5436 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5437 }
5438
5439 /* [e]DP over FDI requires target mode clock instead of link clock. */
5440 if (edp_encoder)
5441 target_clock = intel_edp_target_clock(edp_encoder, mode);
5442 else if (is_dp)
5443 target_clock = mode->clock;
5444 else
5445 target_clock = adjusted_mode->clock;
5446
5447 if (!lane)
5448 lane = ironlake_get_lanes_required(target_clock, link_bw,
5449 intel_crtc->bpp);
5450
5451 intel_crtc->fdi_lanes = lane;
5452
5453 if (pixel_multiplier > 1)
5454 link_bw *= pixel_multiplier;
5455 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5456 &m_n);
5457
5458 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5459 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5460 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5461 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5462 }
5463
5464 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5465 struct drm_display_mode *adjusted_mode,
5466 intel_clock_t *clock, u32 fp)
5467 {
5468 struct drm_crtc *crtc = &intel_crtc->base;
5469 struct drm_device *dev = crtc->dev;
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 struct intel_encoder *intel_encoder;
5472 uint32_t dpll;
5473 int factor, pixel_multiplier, num_connectors = 0;
5474 bool is_lvds = false, is_sdvo = false, is_tv = false;
5475 bool is_dp = false, is_cpu_edp = false;
5476
5477 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5478 switch (intel_encoder->type) {
5479 case INTEL_OUTPUT_LVDS:
5480 is_lvds = true;
5481 break;
5482 case INTEL_OUTPUT_SDVO:
5483 case INTEL_OUTPUT_HDMI:
5484 is_sdvo = true;
5485 if (intel_encoder->needs_tv_clock)
5486 is_tv = true;
5487 break;
5488 case INTEL_OUTPUT_TVOUT:
5489 is_tv = true;
5490 break;
5491 case INTEL_OUTPUT_DISPLAYPORT:
5492 is_dp = true;
5493 break;
5494 case INTEL_OUTPUT_EDP:
5495 is_dp = true;
5496 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5497 is_cpu_edp = true;
5498 break;
5499 }
5500
5501 num_connectors++;
5502 }
5503
5504 /* Enable autotuning of the PLL clock (if permissible) */
5505 factor = 21;
5506 if (is_lvds) {
5507 if ((intel_panel_use_ssc(dev_priv) &&
5508 dev_priv->lvds_ssc_freq == 100) ||
5509 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5510 factor = 25;
5511 } else if (is_sdvo && is_tv)
5512 factor = 20;
5513
5514 if (clock->m < factor * clock->n)
5515 fp |= FP_CB_TUNE;
5516
5517 dpll = 0;
5518
5519 if (is_lvds)
5520 dpll |= DPLLB_MODE_LVDS;
5521 else
5522 dpll |= DPLLB_MODE_DAC_SERIAL;
5523 if (is_sdvo) {
5524 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5525 if (pixel_multiplier > 1) {
5526 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5527 }
5528 dpll |= DPLL_DVO_HIGH_SPEED;
5529 }
5530 if (is_dp && !is_cpu_edp)
5531 dpll |= DPLL_DVO_HIGH_SPEED;
5532
5533 /* compute bitmask from p1 value */
5534 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5535 /* also FPA1 */
5536 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5537
5538 switch (clock->p2) {
5539 case 5:
5540 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5541 break;
5542 case 7:
5543 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5544 break;
5545 case 10:
5546 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5547 break;
5548 case 14:
5549 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5550 break;
5551 }
5552
5553 if (is_sdvo && is_tv)
5554 dpll |= PLL_REF_INPUT_TVCLKINBC;
5555 else if (is_tv)
5556 /* XXX: just matching BIOS for now */
5557 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5558 dpll |= 3;
5559 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5560 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5561 else
5562 dpll |= PLL_REF_INPUT_DREFCLK;
5563
5564 return dpll;
5565 }
5566
5567 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5568 struct drm_display_mode *mode,
5569 struct drm_display_mode *adjusted_mode,
5570 int x, int y,
5571 struct drm_framebuffer *fb)
5572 {
5573 struct drm_device *dev = crtc->dev;
5574 struct drm_i915_private *dev_priv = dev->dev_private;
5575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5576 int pipe = intel_crtc->pipe;
5577 int plane = intel_crtc->plane;
5578 int num_connectors = 0;
5579 intel_clock_t clock, reduced_clock;
5580 u32 dpll, fp = 0, fp2 = 0;
5581 bool ok, has_reduced_clock = false;
5582 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5583 struct intel_encoder *encoder;
5584 u32 temp;
5585 int ret;
5586 bool dither, fdi_config_ok;
5587
5588 for_each_encoder_on_crtc(dev, crtc, encoder) {
5589 switch (encoder->type) {
5590 case INTEL_OUTPUT_LVDS:
5591 is_lvds = true;
5592 break;
5593 case INTEL_OUTPUT_DISPLAYPORT:
5594 is_dp = true;
5595 break;
5596 case INTEL_OUTPUT_EDP:
5597 is_dp = true;
5598 if (!intel_encoder_is_pch_edp(&encoder->base))
5599 is_cpu_edp = true;
5600 break;
5601 }
5602
5603 num_connectors++;
5604 }
5605
5606 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5607 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5608
5609 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5610 &has_reduced_clock, &reduced_clock);
5611 if (!ok) {
5612 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5613 return -EINVAL;
5614 }
5615
5616 /* Ensure that the cursor is valid for the new mode before changing... */
5617 intel_crtc_update_cursor(crtc, true);
5618
5619 /* determine panel color depth */
5620 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5621 adjusted_mode);
5622 if (is_lvds && dev_priv->lvds_dither)
5623 dither = true;
5624
5625 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5626 if (has_reduced_clock)
5627 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5628 reduced_clock.m2;
5629
5630 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5631
5632 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5633 drm_mode_debug_printmodeline(mode);
5634
5635 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5636 if (!is_cpu_edp) {
5637 struct intel_pch_pll *pll;
5638
5639 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5640 if (pll == NULL) {
5641 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5642 pipe);
5643 return -EINVAL;
5644 }
5645 } else
5646 intel_put_pch_pll(intel_crtc);
5647
5648 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5649 * This is an exception to the general rule that mode_set doesn't turn
5650 * things on.
5651 */
5652 if (is_lvds) {
5653 temp = I915_READ(PCH_LVDS);
5654 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5655 if (HAS_PCH_CPT(dev)) {
5656 temp &= ~PORT_TRANS_SEL_MASK;
5657 temp |= PORT_TRANS_SEL_CPT(pipe);
5658 } else {
5659 if (pipe == 1)
5660 temp |= LVDS_PIPEB_SELECT;
5661 else
5662 temp &= ~LVDS_PIPEB_SELECT;
5663 }
5664
5665 /* set the corresponsding LVDS_BORDER bit */
5666 temp |= dev_priv->lvds_border_bits;
5667 /* Set the B0-B3 data pairs corresponding to whether we're going to
5668 * set the DPLLs for dual-channel mode or not.
5669 */
5670 if (clock.p2 == 7)
5671 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5672 else
5673 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5674
5675 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5676 * appropriately here, but we need to look more thoroughly into how
5677 * panels behave in the two modes.
5678 */
5679 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5680 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5681 temp |= LVDS_HSYNC_POLARITY;
5682 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5683 temp |= LVDS_VSYNC_POLARITY;
5684 I915_WRITE(PCH_LVDS, temp);
5685 }
5686
5687 if (is_dp && !is_cpu_edp) {
5688 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5689 } else {
5690 /* For non-DP output, clear any trans DP clock recovery setting.*/
5691 I915_WRITE(TRANSDATA_M1(pipe), 0);
5692 I915_WRITE(TRANSDATA_N1(pipe), 0);
5693 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5694 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5695 }
5696
5697 if (intel_crtc->pch_pll) {
5698 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5699
5700 /* Wait for the clocks to stabilize. */
5701 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5702 udelay(150);
5703
5704 /* The pixel multiplier can only be updated once the
5705 * DPLL is enabled and the clocks are stable.
5706 *
5707 * So write it again.
5708 */
5709 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5710 }
5711
5712 intel_crtc->lowfreq_avail = false;
5713 if (intel_crtc->pch_pll) {
5714 if (is_lvds && has_reduced_clock && i915_powersave) {
5715 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5716 intel_crtc->lowfreq_avail = true;
5717 } else {
5718 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5719 }
5720 }
5721
5722 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5723
5724 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5725 * ironlake_check_fdi_lanes. */
5726 ironlake_set_m_n(crtc, mode, adjusted_mode);
5727
5728 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5729
5730 if (is_cpu_edp)
5731 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5732
5733 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5734
5735 intel_wait_for_vblank(dev, pipe);
5736
5737 /* Set up the display plane register */
5738 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5739 POSTING_READ(DSPCNTR(plane));
5740
5741 ret = intel_pipe_set_base(crtc, x, y, fb);
5742
5743 intel_update_watermarks(dev);
5744
5745 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5746
5747 return fdi_config_ok ? ret : -EINVAL;
5748 }
5749
5750 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5751 struct drm_display_mode *mode,
5752 struct drm_display_mode *adjusted_mode,
5753 int x, int y,
5754 struct drm_framebuffer *fb)
5755 {
5756 struct drm_device *dev = crtc->dev;
5757 struct drm_i915_private *dev_priv = dev->dev_private;
5758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5759 int pipe = intel_crtc->pipe;
5760 int plane = intel_crtc->plane;
5761 int num_connectors = 0;
5762 intel_clock_t clock, reduced_clock;
5763 u32 dpll = 0, fp = 0, fp2 = 0;
5764 bool ok, has_reduced_clock = false;
5765 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5766 struct intel_encoder *encoder;
5767 u32 temp;
5768 int ret;
5769 bool dither;
5770
5771 for_each_encoder_on_crtc(dev, crtc, encoder) {
5772 switch (encoder->type) {
5773 case INTEL_OUTPUT_LVDS:
5774 is_lvds = true;
5775 break;
5776 case INTEL_OUTPUT_DISPLAYPORT:
5777 is_dp = true;
5778 break;
5779 case INTEL_OUTPUT_EDP:
5780 is_dp = true;
5781 if (!intel_encoder_is_pch_edp(&encoder->base))
5782 is_cpu_edp = true;
5783 break;
5784 }
5785
5786 num_connectors++;
5787 }
5788
5789 if (is_cpu_edp)
5790 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5791 else
5792 intel_crtc->cpu_transcoder = pipe;
5793
5794 /* We are not sure yet this won't happen. */
5795 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5796 INTEL_PCH_TYPE(dev));
5797
5798 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5799 num_connectors, pipe_name(pipe));
5800
5801 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5802 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5803
5804 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5805
5806 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5807 return -EINVAL;
5808
5809 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5810 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5811 &has_reduced_clock,
5812 &reduced_clock);
5813 if (!ok) {
5814 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5815 return -EINVAL;
5816 }
5817 }
5818
5819 /* Ensure that the cursor is valid for the new mode before changing... */
5820 intel_crtc_update_cursor(crtc, true);
5821
5822 /* determine panel color depth */
5823 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5824 adjusted_mode);
5825 if (is_lvds && dev_priv->lvds_dither)
5826 dither = true;
5827
5828 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5829 drm_mode_debug_printmodeline(mode);
5830
5831 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5832 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5833 if (has_reduced_clock)
5834 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5835 reduced_clock.m2;
5836
5837 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5838 fp);
5839
5840 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5841 * own on pre-Haswell/LPT generation */
5842 if (!is_cpu_edp) {
5843 struct intel_pch_pll *pll;
5844
5845 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5846 if (pll == NULL) {
5847 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5848 pipe);
5849 return -EINVAL;
5850 }
5851 } else
5852 intel_put_pch_pll(intel_crtc);
5853
5854 /* The LVDS pin pair needs to be on before the DPLLs are
5855 * enabled. This is an exception to the general rule that
5856 * mode_set doesn't turn things on.
5857 */
5858 if (is_lvds) {
5859 temp = I915_READ(PCH_LVDS);
5860 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5861 if (HAS_PCH_CPT(dev)) {
5862 temp &= ~PORT_TRANS_SEL_MASK;
5863 temp |= PORT_TRANS_SEL_CPT(pipe);
5864 } else {
5865 if (pipe == 1)
5866 temp |= LVDS_PIPEB_SELECT;
5867 else
5868 temp &= ~LVDS_PIPEB_SELECT;
5869 }
5870
5871 /* set the corresponsding LVDS_BORDER bit */
5872 temp |= dev_priv->lvds_border_bits;
5873 /* Set the B0-B3 data pairs corresponding to whether
5874 * we're going to set the DPLLs for dual-channel mode or
5875 * not.
5876 */
5877 if (clock.p2 == 7)
5878 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5879 else
5880 temp &= ~(LVDS_B0B3_POWER_UP |
5881 LVDS_CLKB_POWER_UP);
5882
5883 /* It would be nice to set 24 vs 18-bit mode
5884 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5885 * look more thoroughly into how panels behave in the
5886 * two modes.
5887 */
5888 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5889 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5890 temp |= LVDS_HSYNC_POLARITY;
5891 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5892 temp |= LVDS_VSYNC_POLARITY;
5893 I915_WRITE(PCH_LVDS, temp);
5894 }
5895 }
5896
5897 if (is_dp && !is_cpu_edp) {
5898 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5899 } else {
5900 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5901 /* For non-DP output, clear any trans DP clock recovery
5902 * setting.*/
5903 I915_WRITE(TRANSDATA_M1(pipe), 0);
5904 I915_WRITE(TRANSDATA_N1(pipe), 0);
5905 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5906 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5907 }
5908 }
5909
5910 intel_crtc->lowfreq_avail = false;
5911 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5912 if (intel_crtc->pch_pll) {
5913 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5914
5915 /* Wait for the clocks to stabilize. */
5916 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5917 udelay(150);
5918
5919 /* The pixel multiplier can only be updated once the
5920 * DPLL is enabled and the clocks are stable.
5921 *
5922 * So write it again.
5923 */
5924 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5925 }
5926
5927 if (intel_crtc->pch_pll) {
5928 if (is_lvds && has_reduced_clock && i915_powersave) {
5929 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5930 intel_crtc->lowfreq_avail = true;
5931 } else {
5932 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5933 }
5934 }
5935 }
5936
5937 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5938
5939 if (!is_dp || is_cpu_edp)
5940 ironlake_set_m_n(crtc, mode, adjusted_mode);
5941
5942 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5943 if (is_cpu_edp)
5944 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5945
5946 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5947
5948 /* Set up the display plane register */
5949 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5950 POSTING_READ(DSPCNTR(plane));
5951
5952 ret = intel_pipe_set_base(crtc, x, y, fb);
5953
5954 intel_update_watermarks(dev);
5955
5956 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5957
5958 return ret;
5959 }
5960
5961 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5962 struct drm_display_mode *mode,
5963 struct drm_display_mode *adjusted_mode,
5964 int x, int y,
5965 struct drm_framebuffer *fb)
5966 {
5967 struct drm_device *dev = crtc->dev;
5968 struct drm_i915_private *dev_priv = dev->dev_private;
5969 struct drm_encoder_helper_funcs *encoder_funcs;
5970 struct intel_encoder *encoder;
5971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5972 int pipe = intel_crtc->pipe;
5973 int ret;
5974
5975 drm_vblank_pre_modeset(dev, pipe);
5976
5977 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5978 x, y, fb);
5979 drm_vblank_post_modeset(dev, pipe);
5980
5981 if (ret != 0)
5982 return ret;
5983
5984 for_each_encoder_on_crtc(dev, crtc, encoder) {
5985 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5986 encoder->base.base.id,
5987 drm_get_encoder_name(&encoder->base),
5988 mode->base.id, mode->name);
5989 encoder_funcs = encoder->base.helper_private;
5990 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5991 }
5992
5993 return 0;
5994 }
5995
5996 static bool intel_eld_uptodate(struct drm_connector *connector,
5997 int reg_eldv, uint32_t bits_eldv,
5998 int reg_elda, uint32_t bits_elda,
5999 int reg_edid)
6000 {
6001 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6002 uint8_t *eld = connector->eld;
6003 uint32_t i;
6004
6005 i = I915_READ(reg_eldv);
6006 i &= bits_eldv;
6007
6008 if (!eld[0])
6009 return !i;
6010
6011 if (!i)
6012 return false;
6013
6014 i = I915_READ(reg_elda);
6015 i &= ~bits_elda;
6016 I915_WRITE(reg_elda, i);
6017
6018 for (i = 0; i < eld[2]; i++)
6019 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6020 return false;
6021
6022 return true;
6023 }
6024
6025 static void g4x_write_eld(struct drm_connector *connector,
6026 struct drm_crtc *crtc)
6027 {
6028 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6029 uint8_t *eld = connector->eld;
6030 uint32_t eldv;
6031 uint32_t len;
6032 uint32_t i;
6033
6034 i = I915_READ(G4X_AUD_VID_DID);
6035
6036 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6037 eldv = G4X_ELDV_DEVCL_DEVBLC;
6038 else
6039 eldv = G4X_ELDV_DEVCTG;
6040
6041 if (intel_eld_uptodate(connector,
6042 G4X_AUD_CNTL_ST, eldv,
6043 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6044 G4X_HDMIW_HDMIEDID))
6045 return;
6046
6047 i = I915_READ(G4X_AUD_CNTL_ST);
6048 i &= ~(eldv | G4X_ELD_ADDR);
6049 len = (i >> 9) & 0x1f; /* ELD buffer size */
6050 I915_WRITE(G4X_AUD_CNTL_ST, i);
6051
6052 if (!eld[0])
6053 return;
6054
6055 len = min_t(uint8_t, eld[2], len);
6056 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6057 for (i = 0; i < len; i++)
6058 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6059
6060 i = I915_READ(G4X_AUD_CNTL_ST);
6061 i |= eldv;
6062 I915_WRITE(G4X_AUD_CNTL_ST, i);
6063 }
6064
6065 static void haswell_write_eld(struct drm_connector *connector,
6066 struct drm_crtc *crtc)
6067 {
6068 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6069 uint8_t *eld = connector->eld;
6070 struct drm_device *dev = crtc->dev;
6071 uint32_t eldv;
6072 uint32_t i;
6073 int len;
6074 int pipe = to_intel_crtc(crtc)->pipe;
6075 int tmp;
6076
6077 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6078 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6079 int aud_config = HSW_AUD_CFG(pipe);
6080 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6081
6082
6083 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6084
6085 /* Audio output enable */
6086 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6087 tmp = I915_READ(aud_cntrl_st2);
6088 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6089 I915_WRITE(aud_cntrl_st2, tmp);
6090
6091 /* Wait for 1 vertical blank */
6092 intel_wait_for_vblank(dev, pipe);
6093
6094 /* Set ELD valid state */
6095 tmp = I915_READ(aud_cntrl_st2);
6096 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6097 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6098 I915_WRITE(aud_cntrl_st2, tmp);
6099 tmp = I915_READ(aud_cntrl_st2);
6100 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6101
6102 /* Enable HDMI mode */
6103 tmp = I915_READ(aud_config);
6104 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6105 /* clear N_programing_enable and N_value_index */
6106 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6107 I915_WRITE(aud_config, tmp);
6108
6109 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6110
6111 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6112
6113 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6114 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6115 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6116 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6117 } else
6118 I915_WRITE(aud_config, 0);
6119
6120 if (intel_eld_uptodate(connector,
6121 aud_cntrl_st2, eldv,
6122 aud_cntl_st, IBX_ELD_ADDRESS,
6123 hdmiw_hdmiedid))
6124 return;
6125
6126 i = I915_READ(aud_cntrl_st2);
6127 i &= ~eldv;
6128 I915_WRITE(aud_cntrl_st2, i);
6129
6130 if (!eld[0])
6131 return;
6132
6133 i = I915_READ(aud_cntl_st);
6134 i &= ~IBX_ELD_ADDRESS;
6135 I915_WRITE(aud_cntl_st, i);
6136 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6137 DRM_DEBUG_DRIVER("port num:%d\n", i);
6138
6139 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6140 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6141 for (i = 0; i < len; i++)
6142 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6143
6144 i = I915_READ(aud_cntrl_st2);
6145 i |= eldv;
6146 I915_WRITE(aud_cntrl_st2, i);
6147
6148 }
6149
6150 static void ironlake_write_eld(struct drm_connector *connector,
6151 struct drm_crtc *crtc)
6152 {
6153 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6154 uint8_t *eld = connector->eld;
6155 uint32_t eldv;
6156 uint32_t i;
6157 int len;
6158 int hdmiw_hdmiedid;
6159 int aud_config;
6160 int aud_cntl_st;
6161 int aud_cntrl_st2;
6162 int pipe = to_intel_crtc(crtc)->pipe;
6163
6164 if (HAS_PCH_IBX(connector->dev)) {
6165 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6166 aud_config = IBX_AUD_CFG(pipe);
6167 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6168 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6169 } else {
6170 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6171 aud_config = CPT_AUD_CFG(pipe);
6172 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6173 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6174 }
6175
6176 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6177
6178 i = I915_READ(aud_cntl_st);
6179 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6180 if (!i) {
6181 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6182 /* operate blindly on all ports */
6183 eldv = IBX_ELD_VALIDB;
6184 eldv |= IBX_ELD_VALIDB << 4;
6185 eldv |= IBX_ELD_VALIDB << 8;
6186 } else {
6187 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6188 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6189 }
6190
6191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6192 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6193 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6194 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6195 } else
6196 I915_WRITE(aud_config, 0);
6197
6198 if (intel_eld_uptodate(connector,
6199 aud_cntrl_st2, eldv,
6200 aud_cntl_st, IBX_ELD_ADDRESS,
6201 hdmiw_hdmiedid))
6202 return;
6203
6204 i = I915_READ(aud_cntrl_st2);
6205 i &= ~eldv;
6206 I915_WRITE(aud_cntrl_st2, i);
6207
6208 if (!eld[0])
6209 return;
6210
6211 i = I915_READ(aud_cntl_st);
6212 i &= ~IBX_ELD_ADDRESS;
6213 I915_WRITE(aud_cntl_st, i);
6214
6215 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6216 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6217 for (i = 0; i < len; i++)
6218 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6219
6220 i = I915_READ(aud_cntrl_st2);
6221 i |= eldv;
6222 I915_WRITE(aud_cntrl_st2, i);
6223 }
6224
6225 void intel_write_eld(struct drm_encoder *encoder,
6226 struct drm_display_mode *mode)
6227 {
6228 struct drm_crtc *crtc = encoder->crtc;
6229 struct drm_connector *connector;
6230 struct drm_device *dev = encoder->dev;
6231 struct drm_i915_private *dev_priv = dev->dev_private;
6232
6233 connector = drm_select_eld(encoder, mode);
6234 if (!connector)
6235 return;
6236
6237 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6238 connector->base.id,
6239 drm_get_connector_name(connector),
6240 connector->encoder->base.id,
6241 drm_get_encoder_name(connector->encoder));
6242
6243 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6244
6245 if (dev_priv->display.write_eld)
6246 dev_priv->display.write_eld(connector, crtc);
6247 }
6248
6249 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6250 void intel_crtc_load_lut(struct drm_crtc *crtc)
6251 {
6252 struct drm_device *dev = crtc->dev;
6253 struct drm_i915_private *dev_priv = dev->dev_private;
6254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6255 int palreg = PALETTE(intel_crtc->pipe);
6256 int i;
6257
6258 /* The clocks have to be on to load the palette. */
6259 if (!crtc->enabled || !intel_crtc->active)
6260 return;
6261
6262 /* use legacy palette for Ironlake */
6263 if (HAS_PCH_SPLIT(dev))
6264 palreg = LGC_PALETTE(intel_crtc->pipe);
6265
6266 for (i = 0; i < 256; i++) {
6267 I915_WRITE(palreg + 4 * i,
6268 (intel_crtc->lut_r[i] << 16) |
6269 (intel_crtc->lut_g[i] << 8) |
6270 intel_crtc->lut_b[i]);
6271 }
6272 }
6273
6274 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6275 {
6276 struct drm_device *dev = crtc->dev;
6277 struct drm_i915_private *dev_priv = dev->dev_private;
6278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6279 bool visible = base != 0;
6280 u32 cntl;
6281
6282 if (intel_crtc->cursor_visible == visible)
6283 return;
6284
6285 cntl = I915_READ(_CURACNTR);
6286 if (visible) {
6287 /* On these chipsets we can only modify the base whilst
6288 * the cursor is disabled.
6289 */
6290 I915_WRITE(_CURABASE, base);
6291
6292 cntl &= ~(CURSOR_FORMAT_MASK);
6293 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6294 cntl |= CURSOR_ENABLE |
6295 CURSOR_GAMMA_ENABLE |
6296 CURSOR_FORMAT_ARGB;
6297 } else
6298 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6299 I915_WRITE(_CURACNTR, cntl);
6300
6301 intel_crtc->cursor_visible = visible;
6302 }
6303
6304 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6305 {
6306 struct drm_device *dev = crtc->dev;
6307 struct drm_i915_private *dev_priv = dev->dev_private;
6308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6309 int pipe = intel_crtc->pipe;
6310 bool visible = base != 0;
6311
6312 if (intel_crtc->cursor_visible != visible) {
6313 uint32_t cntl = I915_READ(CURCNTR(pipe));
6314 if (base) {
6315 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6316 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6317 cntl |= pipe << 28; /* Connect to correct pipe */
6318 } else {
6319 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6320 cntl |= CURSOR_MODE_DISABLE;
6321 }
6322 I915_WRITE(CURCNTR(pipe), cntl);
6323
6324 intel_crtc->cursor_visible = visible;
6325 }
6326 /* and commit changes on next vblank */
6327 I915_WRITE(CURBASE(pipe), base);
6328 }
6329
6330 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6331 {
6332 struct drm_device *dev = crtc->dev;
6333 struct drm_i915_private *dev_priv = dev->dev_private;
6334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6335 int pipe = intel_crtc->pipe;
6336 bool visible = base != 0;
6337
6338 if (intel_crtc->cursor_visible != visible) {
6339 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6340 if (base) {
6341 cntl &= ~CURSOR_MODE;
6342 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6343 } else {
6344 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6345 cntl |= CURSOR_MODE_DISABLE;
6346 }
6347 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6348
6349 intel_crtc->cursor_visible = visible;
6350 }
6351 /* and commit changes on next vblank */
6352 I915_WRITE(CURBASE_IVB(pipe), base);
6353 }
6354
6355 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6356 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6357 bool on)
6358 {
6359 struct drm_device *dev = crtc->dev;
6360 struct drm_i915_private *dev_priv = dev->dev_private;
6361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6362 int pipe = intel_crtc->pipe;
6363 int x = intel_crtc->cursor_x;
6364 int y = intel_crtc->cursor_y;
6365 u32 base, pos;
6366 bool visible;
6367
6368 pos = 0;
6369
6370 if (on && crtc->enabled && crtc->fb) {
6371 base = intel_crtc->cursor_addr;
6372 if (x > (int) crtc->fb->width)
6373 base = 0;
6374
6375 if (y > (int) crtc->fb->height)
6376 base = 0;
6377 } else
6378 base = 0;
6379
6380 if (x < 0) {
6381 if (x + intel_crtc->cursor_width < 0)
6382 base = 0;
6383
6384 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6385 x = -x;
6386 }
6387 pos |= x << CURSOR_X_SHIFT;
6388
6389 if (y < 0) {
6390 if (y + intel_crtc->cursor_height < 0)
6391 base = 0;
6392
6393 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6394 y = -y;
6395 }
6396 pos |= y << CURSOR_Y_SHIFT;
6397
6398 visible = base != 0;
6399 if (!visible && !intel_crtc->cursor_visible)
6400 return;
6401
6402 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6403 I915_WRITE(CURPOS_IVB(pipe), pos);
6404 ivb_update_cursor(crtc, base);
6405 } else {
6406 I915_WRITE(CURPOS(pipe), pos);
6407 if (IS_845G(dev) || IS_I865G(dev))
6408 i845_update_cursor(crtc, base);
6409 else
6410 i9xx_update_cursor(crtc, base);
6411 }
6412 }
6413
6414 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6415 struct drm_file *file,
6416 uint32_t handle,
6417 uint32_t width, uint32_t height)
6418 {
6419 struct drm_device *dev = crtc->dev;
6420 struct drm_i915_private *dev_priv = dev->dev_private;
6421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6422 struct drm_i915_gem_object *obj;
6423 uint32_t addr;
6424 int ret;
6425
6426 /* if we want to turn off the cursor ignore width and height */
6427 if (!handle) {
6428 DRM_DEBUG_KMS("cursor off\n");
6429 addr = 0;
6430 obj = NULL;
6431 mutex_lock(&dev->struct_mutex);
6432 goto finish;
6433 }
6434
6435 /* Currently we only support 64x64 cursors */
6436 if (width != 64 || height != 64) {
6437 DRM_ERROR("we currently only support 64x64 cursors\n");
6438 return -EINVAL;
6439 }
6440
6441 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6442 if (&obj->base == NULL)
6443 return -ENOENT;
6444
6445 if (obj->base.size < width * height * 4) {
6446 DRM_ERROR("buffer is to small\n");
6447 ret = -ENOMEM;
6448 goto fail;
6449 }
6450
6451 /* we only need to pin inside GTT if cursor is non-phy */
6452 mutex_lock(&dev->struct_mutex);
6453 if (!dev_priv->info->cursor_needs_physical) {
6454 if (obj->tiling_mode) {
6455 DRM_ERROR("cursor cannot be tiled\n");
6456 ret = -EINVAL;
6457 goto fail_locked;
6458 }
6459
6460 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6461 if (ret) {
6462 DRM_ERROR("failed to move cursor bo into the GTT\n");
6463 goto fail_locked;
6464 }
6465
6466 ret = i915_gem_object_put_fence(obj);
6467 if (ret) {
6468 DRM_ERROR("failed to release fence for cursor");
6469 goto fail_unpin;
6470 }
6471
6472 addr = obj->gtt_offset;
6473 } else {
6474 int align = IS_I830(dev) ? 16 * 1024 : 256;
6475 ret = i915_gem_attach_phys_object(dev, obj,
6476 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6477 align);
6478 if (ret) {
6479 DRM_ERROR("failed to attach phys object\n");
6480 goto fail_locked;
6481 }
6482 addr = obj->phys_obj->handle->busaddr;
6483 }
6484
6485 if (IS_GEN2(dev))
6486 I915_WRITE(CURSIZE, (height << 12) | width);
6487
6488 finish:
6489 if (intel_crtc->cursor_bo) {
6490 if (dev_priv->info->cursor_needs_physical) {
6491 if (intel_crtc->cursor_bo != obj)
6492 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6493 } else
6494 i915_gem_object_unpin(intel_crtc->cursor_bo);
6495 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6496 }
6497
6498 mutex_unlock(&dev->struct_mutex);
6499
6500 intel_crtc->cursor_addr = addr;
6501 intel_crtc->cursor_bo = obj;
6502 intel_crtc->cursor_width = width;
6503 intel_crtc->cursor_height = height;
6504
6505 intel_crtc_update_cursor(crtc, true);
6506
6507 return 0;
6508 fail_unpin:
6509 i915_gem_object_unpin(obj);
6510 fail_locked:
6511 mutex_unlock(&dev->struct_mutex);
6512 fail:
6513 drm_gem_object_unreference_unlocked(&obj->base);
6514 return ret;
6515 }
6516
6517 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6518 {
6519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6520
6521 intel_crtc->cursor_x = x;
6522 intel_crtc->cursor_y = y;
6523
6524 intel_crtc_update_cursor(crtc, true);
6525
6526 return 0;
6527 }
6528
6529 /** Sets the color ramps on behalf of RandR */
6530 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6531 u16 blue, int regno)
6532 {
6533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6534
6535 intel_crtc->lut_r[regno] = red >> 8;
6536 intel_crtc->lut_g[regno] = green >> 8;
6537 intel_crtc->lut_b[regno] = blue >> 8;
6538 }
6539
6540 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6541 u16 *blue, int regno)
6542 {
6543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6544
6545 *red = intel_crtc->lut_r[regno] << 8;
6546 *green = intel_crtc->lut_g[regno] << 8;
6547 *blue = intel_crtc->lut_b[regno] << 8;
6548 }
6549
6550 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6551 u16 *blue, uint32_t start, uint32_t size)
6552 {
6553 int end = (start + size > 256) ? 256 : start + size, i;
6554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6555
6556 for (i = start; i < end; i++) {
6557 intel_crtc->lut_r[i] = red[i] >> 8;
6558 intel_crtc->lut_g[i] = green[i] >> 8;
6559 intel_crtc->lut_b[i] = blue[i] >> 8;
6560 }
6561
6562 intel_crtc_load_lut(crtc);
6563 }
6564
6565 /**
6566 * Get a pipe with a simple mode set on it for doing load-based monitor
6567 * detection.
6568 *
6569 * It will be up to the load-detect code to adjust the pipe as appropriate for
6570 * its requirements. The pipe will be connected to no other encoders.
6571 *
6572 * Currently this code will only succeed if there is a pipe with no encoders
6573 * configured for it. In the future, it could choose to temporarily disable
6574 * some outputs to free up a pipe for its use.
6575 *
6576 * \return crtc, or NULL if no pipes are available.
6577 */
6578
6579 /* VESA 640x480x72Hz mode to set on the pipe */
6580 static struct drm_display_mode load_detect_mode = {
6581 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6582 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6583 };
6584
6585 static struct drm_framebuffer *
6586 intel_framebuffer_create(struct drm_device *dev,
6587 struct drm_mode_fb_cmd2 *mode_cmd,
6588 struct drm_i915_gem_object *obj)
6589 {
6590 struct intel_framebuffer *intel_fb;
6591 int ret;
6592
6593 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6594 if (!intel_fb) {
6595 drm_gem_object_unreference_unlocked(&obj->base);
6596 return ERR_PTR(-ENOMEM);
6597 }
6598
6599 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6600 if (ret) {
6601 drm_gem_object_unreference_unlocked(&obj->base);
6602 kfree(intel_fb);
6603 return ERR_PTR(ret);
6604 }
6605
6606 return &intel_fb->base;
6607 }
6608
6609 static u32
6610 intel_framebuffer_pitch_for_width(int width, int bpp)
6611 {
6612 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6613 return ALIGN(pitch, 64);
6614 }
6615
6616 static u32
6617 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6618 {
6619 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6620 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6621 }
6622
6623 static struct drm_framebuffer *
6624 intel_framebuffer_create_for_mode(struct drm_device *dev,
6625 struct drm_display_mode *mode,
6626 int depth, int bpp)
6627 {
6628 struct drm_i915_gem_object *obj;
6629 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6630
6631 obj = i915_gem_alloc_object(dev,
6632 intel_framebuffer_size_for_mode(mode, bpp));
6633 if (obj == NULL)
6634 return ERR_PTR(-ENOMEM);
6635
6636 mode_cmd.width = mode->hdisplay;
6637 mode_cmd.height = mode->vdisplay;
6638 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6639 bpp);
6640 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6641
6642 return intel_framebuffer_create(dev, &mode_cmd, obj);
6643 }
6644
6645 static struct drm_framebuffer *
6646 mode_fits_in_fbdev(struct drm_device *dev,
6647 struct drm_display_mode *mode)
6648 {
6649 struct drm_i915_private *dev_priv = dev->dev_private;
6650 struct drm_i915_gem_object *obj;
6651 struct drm_framebuffer *fb;
6652
6653 if (dev_priv->fbdev == NULL)
6654 return NULL;
6655
6656 obj = dev_priv->fbdev->ifb.obj;
6657 if (obj == NULL)
6658 return NULL;
6659
6660 fb = &dev_priv->fbdev->ifb.base;
6661 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6662 fb->bits_per_pixel))
6663 return NULL;
6664
6665 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6666 return NULL;
6667
6668 return fb;
6669 }
6670
6671 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6672 struct drm_display_mode *mode,
6673 struct intel_load_detect_pipe *old)
6674 {
6675 struct intel_crtc *intel_crtc;
6676 struct intel_encoder *intel_encoder =
6677 intel_attached_encoder(connector);
6678 struct drm_crtc *possible_crtc;
6679 struct drm_encoder *encoder = &intel_encoder->base;
6680 struct drm_crtc *crtc = NULL;
6681 struct drm_device *dev = encoder->dev;
6682 struct drm_framebuffer *fb;
6683 int i = -1;
6684
6685 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6686 connector->base.id, drm_get_connector_name(connector),
6687 encoder->base.id, drm_get_encoder_name(encoder));
6688
6689 /*
6690 * Algorithm gets a little messy:
6691 *
6692 * - if the connector already has an assigned crtc, use it (but make
6693 * sure it's on first)
6694 *
6695 * - try to find the first unused crtc that can drive this connector,
6696 * and use that if we find one
6697 */
6698
6699 /* See if we already have a CRTC for this connector */
6700 if (encoder->crtc) {
6701 crtc = encoder->crtc;
6702
6703 old->dpms_mode = connector->dpms;
6704 old->load_detect_temp = false;
6705
6706 /* Make sure the crtc and connector are running */
6707 if (connector->dpms != DRM_MODE_DPMS_ON)
6708 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6709
6710 return true;
6711 }
6712
6713 /* Find an unused one (if possible) */
6714 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6715 i++;
6716 if (!(encoder->possible_crtcs & (1 << i)))
6717 continue;
6718 if (!possible_crtc->enabled) {
6719 crtc = possible_crtc;
6720 break;
6721 }
6722 }
6723
6724 /*
6725 * If we didn't find an unused CRTC, don't use any.
6726 */
6727 if (!crtc) {
6728 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6729 return false;
6730 }
6731
6732 intel_encoder->new_crtc = to_intel_crtc(crtc);
6733 to_intel_connector(connector)->new_encoder = intel_encoder;
6734
6735 intel_crtc = to_intel_crtc(crtc);
6736 old->dpms_mode = connector->dpms;
6737 old->load_detect_temp = true;
6738 old->release_fb = NULL;
6739
6740 if (!mode)
6741 mode = &load_detect_mode;
6742
6743 /* We need a framebuffer large enough to accommodate all accesses
6744 * that the plane may generate whilst we perform load detection.
6745 * We can not rely on the fbcon either being present (we get called
6746 * during its initialisation to detect all boot displays, or it may
6747 * not even exist) or that it is large enough to satisfy the
6748 * requested mode.
6749 */
6750 fb = mode_fits_in_fbdev(dev, mode);
6751 if (fb == NULL) {
6752 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6753 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6754 old->release_fb = fb;
6755 } else
6756 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6757 if (IS_ERR(fb)) {
6758 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6759 return false;
6760 }
6761
6762 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6763 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6764 if (old->release_fb)
6765 old->release_fb->funcs->destroy(old->release_fb);
6766 return false;
6767 }
6768
6769 /* let the connector get through one full cycle before testing */
6770 intel_wait_for_vblank(dev, intel_crtc->pipe);
6771 return true;
6772 }
6773
6774 void intel_release_load_detect_pipe(struct drm_connector *connector,
6775 struct intel_load_detect_pipe *old)
6776 {
6777 struct intel_encoder *intel_encoder =
6778 intel_attached_encoder(connector);
6779 struct drm_encoder *encoder = &intel_encoder->base;
6780
6781 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6782 connector->base.id, drm_get_connector_name(connector),
6783 encoder->base.id, drm_get_encoder_name(encoder));
6784
6785 if (old->load_detect_temp) {
6786 struct drm_crtc *crtc = encoder->crtc;
6787
6788 to_intel_connector(connector)->new_encoder = NULL;
6789 intel_encoder->new_crtc = NULL;
6790 intel_set_mode(crtc, NULL, 0, 0, NULL);
6791
6792 if (old->release_fb)
6793 old->release_fb->funcs->destroy(old->release_fb);
6794
6795 return;
6796 }
6797
6798 /* Switch crtc and encoder back off if necessary */
6799 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6800 connector->funcs->dpms(connector, old->dpms_mode);
6801 }
6802
6803 /* Returns the clock of the currently programmed mode of the given pipe. */
6804 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6805 {
6806 struct drm_i915_private *dev_priv = dev->dev_private;
6807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6808 int pipe = intel_crtc->pipe;
6809 u32 dpll = I915_READ(DPLL(pipe));
6810 u32 fp;
6811 intel_clock_t clock;
6812
6813 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6814 fp = I915_READ(FP0(pipe));
6815 else
6816 fp = I915_READ(FP1(pipe));
6817
6818 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6819 if (IS_PINEVIEW(dev)) {
6820 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6821 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6822 } else {
6823 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6824 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6825 }
6826
6827 if (!IS_GEN2(dev)) {
6828 if (IS_PINEVIEW(dev))
6829 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6830 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6831 else
6832 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6833 DPLL_FPA01_P1_POST_DIV_SHIFT);
6834
6835 switch (dpll & DPLL_MODE_MASK) {
6836 case DPLLB_MODE_DAC_SERIAL:
6837 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6838 5 : 10;
6839 break;
6840 case DPLLB_MODE_LVDS:
6841 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6842 7 : 14;
6843 break;
6844 default:
6845 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6846 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6847 return 0;
6848 }
6849
6850 /* XXX: Handle the 100Mhz refclk */
6851 intel_clock(dev, 96000, &clock);
6852 } else {
6853 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6854
6855 if (is_lvds) {
6856 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6857 DPLL_FPA01_P1_POST_DIV_SHIFT);
6858 clock.p2 = 14;
6859
6860 if ((dpll & PLL_REF_INPUT_MASK) ==
6861 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6862 /* XXX: might not be 66MHz */
6863 intel_clock(dev, 66000, &clock);
6864 } else
6865 intel_clock(dev, 48000, &clock);
6866 } else {
6867 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6868 clock.p1 = 2;
6869 else {
6870 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6871 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6872 }
6873 if (dpll & PLL_P2_DIVIDE_BY_4)
6874 clock.p2 = 4;
6875 else
6876 clock.p2 = 2;
6877
6878 intel_clock(dev, 48000, &clock);
6879 }
6880 }
6881
6882 /* XXX: It would be nice to validate the clocks, but we can't reuse
6883 * i830PllIsValid() because it relies on the xf86_config connector
6884 * configuration being accurate, which it isn't necessarily.
6885 */
6886
6887 return clock.dot;
6888 }
6889
6890 /** Returns the currently programmed mode of the given pipe. */
6891 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6892 struct drm_crtc *crtc)
6893 {
6894 struct drm_i915_private *dev_priv = dev->dev_private;
6895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6896 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6897 struct drm_display_mode *mode;
6898 int htot = I915_READ(HTOTAL(cpu_transcoder));
6899 int hsync = I915_READ(HSYNC(cpu_transcoder));
6900 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6901 int vsync = I915_READ(VSYNC(cpu_transcoder));
6902
6903 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6904 if (!mode)
6905 return NULL;
6906
6907 mode->clock = intel_crtc_clock_get(dev, crtc);
6908 mode->hdisplay = (htot & 0xffff) + 1;
6909 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6910 mode->hsync_start = (hsync & 0xffff) + 1;
6911 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6912 mode->vdisplay = (vtot & 0xffff) + 1;
6913 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6914 mode->vsync_start = (vsync & 0xffff) + 1;
6915 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6916
6917 drm_mode_set_name(mode);
6918
6919 return mode;
6920 }
6921
6922 static void intel_increase_pllclock(struct drm_crtc *crtc)
6923 {
6924 struct drm_device *dev = crtc->dev;
6925 drm_i915_private_t *dev_priv = dev->dev_private;
6926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6927 int pipe = intel_crtc->pipe;
6928 int dpll_reg = DPLL(pipe);
6929 int dpll;
6930
6931 if (HAS_PCH_SPLIT(dev))
6932 return;
6933
6934 if (!dev_priv->lvds_downclock_avail)
6935 return;
6936
6937 dpll = I915_READ(dpll_reg);
6938 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6939 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6940
6941 assert_panel_unlocked(dev_priv, pipe);
6942
6943 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6944 I915_WRITE(dpll_reg, dpll);
6945 intel_wait_for_vblank(dev, pipe);
6946
6947 dpll = I915_READ(dpll_reg);
6948 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6949 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6950 }
6951 }
6952
6953 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6954 {
6955 struct drm_device *dev = crtc->dev;
6956 drm_i915_private_t *dev_priv = dev->dev_private;
6957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6958
6959 if (HAS_PCH_SPLIT(dev))
6960 return;
6961
6962 if (!dev_priv->lvds_downclock_avail)
6963 return;
6964
6965 /*
6966 * Since this is called by a timer, we should never get here in
6967 * the manual case.
6968 */
6969 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6970 int pipe = intel_crtc->pipe;
6971 int dpll_reg = DPLL(pipe);
6972 int dpll;
6973
6974 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6975
6976 assert_panel_unlocked(dev_priv, pipe);
6977
6978 dpll = I915_READ(dpll_reg);
6979 dpll |= DISPLAY_RATE_SELECT_FPA1;
6980 I915_WRITE(dpll_reg, dpll);
6981 intel_wait_for_vblank(dev, pipe);
6982 dpll = I915_READ(dpll_reg);
6983 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6984 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6985 }
6986
6987 }
6988
6989 void intel_mark_busy(struct drm_device *dev)
6990 {
6991 i915_update_gfx_val(dev->dev_private);
6992 }
6993
6994 void intel_mark_idle(struct drm_device *dev)
6995 {
6996 }
6997
6998 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6999 {
7000 struct drm_device *dev = obj->base.dev;
7001 struct drm_crtc *crtc;
7002
7003 if (!i915_powersave)
7004 return;
7005
7006 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7007 if (!crtc->fb)
7008 continue;
7009
7010 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7011 intel_increase_pllclock(crtc);
7012 }
7013 }
7014
7015 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
7016 {
7017 struct drm_device *dev = obj->base.dev;
7018 struct drm_crtc *crtc;
7019
7020 if (!i915_powersave)
7021 return;
7022
7023 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7024 if (!crtc->fb)
7025 continue;
7026
7027 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7028 intel_decrease_pllclock(crtc);
7029 }
7030 }
7031
7032 static void intel_crtc_destroy(struct drm_crtc *crtc)
7033 {
7034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7035 struct drm_device *dev = crtc->dev;
7036 struct intel_unpin_work *work;
7037 unsigned long flags;
7038
7039 spin_lock_irqsave(&dev->event_lock, flags);
7040 work = intel_crtc->unpin_work;
7041 intel_crtc->unpin_work = NULL;
7042 spin_unlock_irqrestore(&dev->event_lock, flags);
7043
7044 if (work) {
7045 cancel_work_sync(&work->work);
7046 kfree(work);
7047 }
7048
7049 drm_crtc_cleanup(crtc);
7050
7051 kfree(intel_crtc);
7052 }
7053
7054 static void intel_unpin_work_fn(struct work_struct *__work)
7055 {
7056 struct intel_unpin_work *work =
7057 container_of(__work, struct intel_unpin_work, work);
7058 struct drm_device *dev = work->crtc->dev;
7059
7060 mutex_lock(&dev->struct_mutex);
7061 intel_unpin_fb_obj(work->old_fb_obj);
7062 drm_gem_object_unreference(&work->pending_flip_obj->base);
7063 drm_gem_object_unreference(&work->old_fb_obj->base);
7064
7065 intel_update_fbc(dev);
7066 mutex_unlock(&dev->struct_mutex);
7067
7068 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7069 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7070
7071 kfree(work);
7072 }
7073
7074 static void do_intel_finish_page_flip(struct drm_device *dev,
7075 struct drm_crtc *crtc)
7076 {
7077 drm_i915_private_t *dev_priv = dev->dev_private;
7078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7079 struct intel_unpin_work *work;
7080 struct drm_i915_gem_object *obj;
7081 unsigned long flags;
7082
7083 /* Ignore early vblank irqs */
7084 if (intel_crtc == NULL)
7085 return;
7086
7087 spin_lock_irqsave(&dev->event_lock, flags);
7088 work = intel_crtc->unpin_work;
7089
7090 /* Ensure we don't miss a work->pending update ... */
7091 smp_rmb();
7092
7093 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7094 spin_unlock_irqrestore(&dev->event_lock, flags);
7095 return;
7096 }
7097
7098 /* and that the unpin work is consistent wrt ->pending. */
7099 smp_rmb();
7100
7101 intel_crtc->unpin_work = NULL;
7102
7103 if (work->event)
7104 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7105
7106 drm_vblank_put(dev, intel_crtc->pipe);
7107
7108 spin_unlock_irqrestore(&dev->event_lock, flags);
7109
7110 obj = work->old_fb_obj;
7111
7112 atomic_clear_mask(1 << intel_crtc->plane,
7113 &obj->pending_flip.counter);
7114 wake_up(&dev_priv->pending_flip_queue);
7115
7116 queue_work(dev_priv->wq, &work->work);
7117
7118 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7119 }
7120
7121 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7122 {
7123 drm_i915_private_t *dev_priv = dev->dev_private;
7124 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7125
7126 do_intel_finish_page_flip(dev, crtc);
7127 }
7128
7129 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7130 {
7131 drm_i915_private_t *dev_priv = dev->dev_private;
7132 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7133
7134 do_intel_finish_page_flip(dev, crtc);
7135 }
7136
7137 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7138 {
7139 drm_i915_private_t *dev_priv = dev->dev_private;
7140 struct intel_crtc *intel_crtc =
7141 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7142 unsigned long flags;
7143
7144 /* NB: An MMIO update of the plane base pointer will also
7145 * generate a page-flip completion irq, i.e. every modeset
7146 * is also accompanied by a spurious intel_prepare_page_flip().
7147 */
7148 spin_lock_irqsave(&dev->event_lock, flags);
7149 if (intel_crtc->unpin_work)
7150 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7151 spin_unlock_irqrestore(&dev->event_lock, flags);
7152 }
7153
7154 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7155 {
7156 /* Ensure that the work item is consistent when activating it ... */
7157 smp_wmb();
7158 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7159 /* and that it is marked active as soon as the irq could fire. */
7160 smp_wmb();
7161 }
7162
7163 static int intel_gen2_queue_flip(struct drm_device *dev,
7164 struct drm_crtc *crtc,
7165 struct drm_framebuffer *fb,
7166 struct drm_i915_gem_object *obj)
7167 {
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7170 u32 flip_mask;
7171 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7172 int ret;
7173
7174 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7175 if (ret)
7176 goto err;
7177
7178 ret = intel_ring_begin(ring, 6);
7179 if (ret)
7180 goto err_unpin;
7181
7182 /* Can't queue multiple flips, so wait for the previous
7183 * one to finish before executing the next.
7184 */
7185 if (intel_crtc->plane)
7186 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7187 else
7188 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7189 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7190 intel_ring_emit(ring, MI_NOOP);
7191 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7192 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7193 intel_ring_emit(ring, fb->pitches[0]);
7194 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7195 intel_ring_emit(ring, 0); /* aux display base address, unused */
7196
7197 intel_mark_page_flip_active(intel_crtc);
7198 intel_ring_advance(ring);
7199 return 0;
7200
7201 err_unpin:
7202 intel_unpin_fb_obj(obj);
7203 err:
7204 return ret;
7205 }
7206
7207 static int intel_gen3_queue_flip(struct drm_device *dev,
7208 struct drm_crtc *crtc,
7209 struct drm_framebuffer *fb,
7210 struct drm_i915_gem_object *obj)
7211 {
7212 struct drm_i915_private *dev_priv = dev->dev_private;
7213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7214 u32 flip_mask;
7215 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7216 int ret;
7217
7218 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7219 if (ret)
7220 goto err;
7221
7222 ret = intel_ring_begin(ring, 6);
7223 if (ret)
7224 goto err_unpin;
7225
7226 if (intel_crtc->plane)
7227 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7228 else
7229 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7230 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7231 intel_ring_emit(ring, MI_NOOP);
7232 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7233 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7234 intel_ring_emit(ring, fb->pitches[0]);
7235 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7236 intel_ring_emit(ring, MI_NOOP);
7237
7238 intel_mark_page_flip_active(intel_crtc);
7239 intel_ring_advance(ring);
7240 return 0;
7241
7242 err_unpin:
7243 intel_unpin_fb_obj(obj);
7244 err:
7245 return ret;
7246 }
7247
7248 static int intel_gen4_queue_flip(struct drm_device *dev,
7249 struct drm_crtc *crtc,
7250 struct drm_framebuffer *fb,
7251 struct drm_i915_gem_object *obj)
7252 {
7253 struct drm_i915_private *dev_priv = dev->dev_private;
7254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7255 uint32_t pf, pipesrc;
7256 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7257 int ret;
7258
7259 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7260 if (ret)
7261 goto err;
7262
7263 ret = intel_ring_begin(ring, 4);
7264 if (ret)
7265 goto err_unpin;
7266
7267 /* i965+ uses the linear or tiled offsets from the
7268 * Display Registers (which do not change across a page-flip)
7269 * so we need only reprogram the base address.
7270 */
7271 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7272 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7273 intel_ring_emit(ring, fb->pitches[0]);
7274 intel_ring_emit(ring,
7275 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7276 obj->tiling_mode);
7277
7278 /* XXX Enabling the panel-fitter across page-flip is so far
7279 * untested on non-native modes, so ignore it for now.
7280 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7281 */
7282 pf = 0;
7283 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7284 intel_ring_emit(ring, pf | pipesrc);
7285
7286 intel_mark_page_flip_active(intel_crtc);
7287 intel_ring_advance(ring);
7288 return 0;
7289
7290 err_unpin:
7291 intel_unpin_fb_obj(obj);
7292 err:
7293 return ret;
7294 }
7295
7296 static int intel_gen6_queue_flip(struct drm_device *dev,
7297 struct drm_crtc *crtc,
7298 struct drm_framebuffer *fb,
7299 struct drm_i915_gem_object *obj)
7300 {
7301 struct drm_i915_private *dev_priv = dev->dev_private;
7302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7303 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7304 uint32_t pf, pipesrc;
7305 int ret;
7306
7307 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7308 if (ret)
7309 goto err;
7310
7311 ret = intel_ring_begin(ring, 4);
7312 if (ret)
7313 goto err_unpin;
7314
7315 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7316 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7317 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7318 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7319
7320 /* Contrary to the suggestions in the documentation,
7321 * "Enable Panel Fitter" does not seem to be required when page
7322 * flipping with a non-native mode, and worse causes a normal
7323 * modeset to fail.
7324 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7325 */
7326 pf = 0;
7327 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7328 intel_ring_emit(ring, pf | pipesrc);
7329
7330 intel_mark_page_flip_active(intel_crtc);
7331 intel_ring_advance(ring);
7332 return 0;
7333
7334 err_unpin:
7335 intel_unpin_fb_obj(obj);
7336 err:
7337 return ret;
7338 }
7339
7340 /*
7341 * On gen7 we currently use the blit ring because (in early silicon at least)
7342 * the render ring doesn't give us interrpts for page flip completion, which
7343 * means clients will hang after the first flip is queued. Fortunately the
7344 * blit ring generates interrupts properly, so use it instead.
7345 */
7346 static int intel_gen7_queue_flip(struct drm_device *dev,
7347 struct drm_crtc *crtc,
7348 struct drm_framebuffer *fb,
7349 struct drm_i915_gem_object *obj)
7350 {
7351 struct drm_i915_private *dev_priv = dev->dev_private;
7352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7353 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7354 uint32_t plane_bit = 0;
7355 int ret;
7356
7357 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7358 if (ret)
7359 goto err;
7360
7361 switch(intel_crtc->plane) {
7362 case PLANE_A:
7363 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7364 break;
7365 case PLANE_B:
7366 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7367 break;
7368 case PLANE_C:
7369 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7370 break;
7371 default:
7372 WARN_ONCE(1, "unknown plane in flip command\n");
7373 ret = -ENODEV;
7374 goto err_unpin;
7375 }
7376
7377 ret = intel_ring_begin(ring, 4);
7378 if (ret)
7379 goto err_unpin;
7380
7381 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7382 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7383 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7384 intel_ring_emit(ring, (MI_NOOP));
7385
7386 intel_mark_page_flip_active(intel_crtc);
7387 intel_ring_advance(ring);
7388 return 0;
7389
7390 err_unpin:
7391 intel_unpin_fb_obj(obj);
7392 err:
7393 return ret;
7394 }
7395
7396 static int intel_default_queue_flip(struct drm_device *dev,
7397 struct drm_crtc *crtc,
7398 struct drm_framebuffer *fb,
7399 struct drm_i915_gem_object *obj)
7400 {
7401 return -ENODEV;
7402 }
7403
7404 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7405 struct drm_framebuffer *fb,
7406 struct drm_pending_vblank_event *event)
7407 {
7408 struct drm_device *dev = crtc->dev;
7409 struct drm_i915_private *dev_priv = dev->dev_private;
7410 struct intel_framebuffer *intel_fb;
7411 struct drm_i915_gem_object *obj;
7412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7413 struct intel_unpin_work *work;
7414 unsigned long flags;
7415 int ret;
7416
7417 /* Can't change pixel format via MI display flips. */
7418 if (fb->pixel_format != crtc->fb->pixel_format)
7419 return -EINVAL;
7420
7421 /*
7422 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7423 * Note that pitch changes could also affect these register.
7424 */
7425 if (INTEL_INFO(dev)->gen > 3 &&
7426 (fb->offsets[0] != crtc->fb->offsets[0] ||
7427 fb->pitches[0] != crtc->fb->pitches[0]))
7428 return -EINVAL;
7429
7430 work = kzalloc(sizeof *work, GFP_KERNEL);
7431 if (work == NULL)
7432 return -ENOMEM;
7433
7434 work->event = event;
7435 work->crtc = crtc;
7436 intel_fb = to_intel_framebuffer(crtc->fb);
7437 work->old_fb_obj = intel_fb->obj;
7438 INIT_WORK(&work->work, intel_unpin_work_fn);
7439
7440 ret = drm_vblank_get(dev, intel_crtc->pipe);
7441 if (ret)
7442 goto free_work;
7443
7444 /* We borrow the event spin lock for protecting unpin_work */
7445 spin_lock_irqsave(&dev->event_lock, flags);
7446 if (intel_crtc->unpin_work) {
7447 spin_unlock_irqrestore(&dev->event_lock, flags);
7448 kfree(work);
7449 drm_vblank_put(dev, intel_crtc->pipe);
7450
7451 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7452 return -EBUSY;
7453 }
7454 intel_crtc->unpin_work = work;
7455 spin_unlock_irqrestore(&dev->event_lock, flags);
7456
7457 intel_fb = to_intel_framebuffer(fb);
7458 obj = intel_fb->obj;
7459
7460 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7461 flush_workqueue(dev_priv->wq);
7462
7463 ret = i915_mutex_lock_interruptible(dev);
7464 if (ret)
7465 goto cleanup;
7466
7467 /* Reference the objects for the scheduled work. */
7468 drm_gem_object_reference(&work->old_fb_obj->base);
7469 drm_gem_object_reference(&obj->base);
7470
7471 crtc->fb = fb;
7472
7473 work->pending_flip_obj = obj;
7474
7475 work->enable_stall_check = true;
7476
7477 /* Block clients from rendering to the new back buffer until
7478 * the flip occurs and the object is no longer visible.
7479 */
7480 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7481 atomic_inc(&intel_crtc->unpin_work_count);
7482
7483 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7484 if (ret)
7485 goto cleanup_pending;
7486
7487 intel_disable_fbc(dev);
7488 intel_mark_fb_busy(obj);
7489 mutex_unlock(&dev->struct_mutex);
7490
7491 trace_i915_flip_request(intel_crtc->plane, obj);
7492
7493 return 0;
7494
7495 cleanup_pending:
7496 atomic_dec(&intel_crtc->unpin_work_count);
7497 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7498 drm_gem_object_unreference(&work->old_fb_obj->base);
7499 drm_gem_object_unreference(&obj->base);
7500 mutex_unlock(&dev->struct_mutex);
7501
7502 cleanup:
7503 spin_lock_irqsave(&dev->event_lock, flags);
7504 intel_crtc->unpin_work = NULL;
7505 spin_unlock_irqrestore(&dev->event_lock, flags);
7506
7507 drm_vblank_put(dev, intel_crtc->pipe);
7508 free_work:
7509 kfree(work);
7510
7511 return ret;
7512 }
7513
7514 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7515 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7516 .load_lut = intel_crtc_load_lut,
7517 .disable = intel_crtc_noop,
7518 };
7519
7520 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7521 {
7522 struct intel_encoder *other_encoder;
7523 struct drm_crtc *crtc = &encoder->new_crtc->base;
7524
7525 if (WARN_ON(!crtc))
7526 return false;
7527
7528 list_for_each_entry(other_encoder,
7529 &crtc->dev->mode_config.encoder_list,
7530 base.head) {
7531
7532 if (&other_encoder->new_crtc->base != crtc ||
7533 encoder == other_encoder)
7534 continue;
7535 else
7536 return true;
7537 }
7538
7539 return false;
7540 }
7541
7542 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7543 struct drm_crtc *crtc)
7544 {
7545 struct drm_device *dev;
7546 struct drm_crtc *tmp;
7547 int crtc_mask = 1;
7548
7549 WARN(!crtc, "checking null crtc?\n");
7550
7551 dev = crtc->dev;
7552
7553 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7554 if (tmp == crtc)
7555 break;
7556 crtc_mask <<= 1;
7557 }
7558
7559 if (encoder->possible_crtcs & crtc_mask)
7560 return true;
7561 return false;
7562 }
7563
7564 /**
7565 * intel_modeset_update_staged_output_state
7566 *
7567 * Updates the staged output configuration state, e.g. after we've read out the
7568 * current hw state.
7569 */
7570 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7571 {
7572 struct intel_encoder *encoder;
7573 struct intel_connector *connector;
7574
7575 list_for_each_entry(connector, &dev->mode_config.connector_list,
7576 base.head) {
7577 connector->new_encoder =
7578 to_intel_encoder(connector->base.encoder);
7579 }
7580
7581 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7582 base.head) {
7583 encoder->new_crtc =
7584 to_intel_crtc(encoder->base.crtc);
7585 }
7586 }
7587
7588 /**
7589 * intel_modeset_commit_output_state
7590 *
7591 * This function copies the stage display pipe configuration to the real one.
7592 */
7593 static void intel_modeset_commit_output_state(struct drm_device *dev)
7594 {
7595 struct intel_encoder *encoder;
7596 struct intel_connector *connector;
7597
7598 list_for_each_entry(connector, &dev->mode_config.connector_list,
7599 base.head) {
7600 connector->base.encoder = &connector->new_encoder->base;
7601 }
7602
7603 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7604 base.head) {
7605 encoder->base.crtc = &encoder->new_crtc->base;
7606 }
7607 }
7608
7609 static struct drm_display_mode *
7610 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7611 struct drm_display_mode *mode)
7612 {
7613 struct drm_device *dev = crtc->dev;
7614 struct drm_display_mode *adjusted_mode;
7615 struct drm_encoder_helper_funcs *encoder_funcs;
7616 struct intel_encoder *encoder;
7617
7618 adjusted_mode = drm_mode_duplicate(dev, mode);
7619 if (!adjusted_mode)
7620 return ERR_PTR(-ENOMEM);
7621
7622 /* Pass our mode to the connectors and the CRTC to give them a chance to
7623 * adjust it according to limitations or connector properties, and also
7624 * a chance to reject the mode entirely.
7625 */
7626 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7627 base.head) {
7628
7629 if (&encoder->new_crtc->base != crtc)
7630 continue;
7631 encoder_funcs = encoder->base.helper_private;
7632 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7633 adjusted_mode))) {
7634 DRM_DEBUG_KMS("Encoder fixup failed\n");
7635 goto fail;
7636 }
7637 }
7638
7639 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7640 DRM_DEBUG_KMS("CRTC fixup failed\n");
7641 goto fail;
7642 }
7643 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7644
7645 return adjusted_mode;
7646 fail:
7647 drm_mode_destroy(dev, adjusted_mode);
7648 return ERR_PTR(-EINVAL);
7649 }
7650
7651 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7652 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7653 static void
7654 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7655 unsigned *prepare_pipes, unsigned *disable_pipes)
7656 {
7657 struct intel_crtc *intel_crtc;
7658 struct drm_device *dev = crtc->dev;
7659 struct intel_encoder *encoder;
7660 struct intel_connector *connector;
7661 struct drm_crtc *tmp_crtc;
7662
7663 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7664
7665 /* Check which crtcs have changed outputs connected to them, these need
7666 * to be part of the prepare_pipes mask. We don't (yet) support global
7667 * modeset across multiple crtcs, so modeset_pipes will only have one
7668 * bit set at most. */
7669 list_for_each_entry(connector, &dev->mode_config.connector_list,
7670 base.head) {
7671 if (connector->base.encoder == &connector->new_encoder->base)
7672 continue;
7673
7674 if (connector->base.encoder) {
7675 tmp_crtc = connector->base.encoder->crtc;
7676
7677 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7678 }
7679
7680 if (connector->new_encoder)
7681 *prepare_pipes |=
7682 1 << connector->new_encoder->new_crtc->pipe;
7683 }
7684
7685 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7686 base.head) {
7687 if (encoder->base.crtc == &encoder->new_crtc->base)
7688 continue;
7689
7690 if (encoder->base.crtc) {
7691 tmp_crtc = encoder->base.crtc;
7692
7693 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7694 }
7695
7696 if (encoder->new_crtc)
7697 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7698 }
7699
7700 /* Check for any pipes that will be fully disabled ... */
7701 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7702 base.head) {
7703 bool used = false;
7704
7705 /* Don't try to disable disabled crtcs. */
7706 if (!intel_crtc->base.enabled)
7707 continue;
7708
7709 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7710 base.head) {
7711 if (encoder->new_crtc == intel_crtc)
7712 used = true;
7713 }
7714
7715 if (!used)
7716 *disable_pipes |= 1 << intel_crtc->pipe;
7717 }
7718
7719
7720 /* set_mode is also used to update properties on life display pipes. */
7721 intel_crtc = to_intel_crtc(crtc);
7722 if (crtc->enabled)
7723 *prepare_pipes |= 1 << intel_crtc->pipe;
7724
7725 /* We only support modeset on one single crtc, hence we need to do that
7726 * only for the passed in crtc iff we change anything else than just
7727 * disable crtcs.
7728 *
7729 * This is actually not true, to be fully compatible with the old crtc
7730 * helper we automatically disable _any_ output (i.e. doesn't need to be
7731 * connected to the crtc we're modesetting on) if it's disconnected.
7732 * Which is a rather nutty api (since changed the output configuration
7733 * without userspace's explicit request can lead to confusion), but
7734 * alas. Hence we currently need to modeset on all pipes we prepare. */
7735 if (*prepare_pipes)
7736 *modeset_pipes = *prepare_pipes;
7737
7738 /* ... and mask these out. */
7739 *modeset_pipes &= ~(*disable_pipes);
7740 *prepare_pipes &= ~(*disable_pipes);
7741 }
7742
7743 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7744 {
7745 struct drm_encoder *encoder;
7746 struct drm_device *dev = crtc->dev;
7747
7748 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7749 if (encoder->crtc == crtc)
7750 return true;
7751
7752 return false;
7753 }
7754
7755 static void
7756 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7757 {
7758 struct intel_encoder *intel_encoder;
7759 struct intel_crtc *intel_crtc;
7760 struct drm_connector *connector;
7761
7762 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7763 base.head) {
7764 if (!intel_encoder->base.crtc)
7765 continue;
7766
7767 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7768
7769 if (prepare_pipes & (1 << intel_crtc->pipe))
7770 intel_encoder->connectors_active = false;
7771 }
7772
7773 intel_modeset_commit_output_state(dev);
7774
7775 /* Update computed state. */
7776 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7777 base.head) {
7778 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7779 }
7780
7781 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7782 if (!connector->encoder || !connector->encoder->crtc)
7783 continue;
7784
7785 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7786
7787 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7788 struct drm_property *dpms_property =
7789 dev->mode_config.dpms_property;
7790
7791 connector->dpms = DRM_MODE_DPMS_ON;
7792 drm_object_property_set_value(&connector->base,
7793 dpms_property,
7794 DRM_MODE_DPMS_ON);
7795
7796 intel_encoder = to_intel_encoder(connector->encoder);
7797 intel_encoder->connectors_active = true;
7798 }
7799 }
7800
7801 }
7802
7803 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7804 list_for_each_entry((intel_crtc), \
7805 &(dev)->mode_config.crtc_list, \
7806 base.head) \
7807 if (mask & (1 <<(intel_crtc)->pipe)) \
7808
7809 void
7810 intel_modeset_check_state(struct drm_device *dev)
7811 {
7812 struct intel_crtc *crtc;
7813 struct intel_encoder *encoder;
7814 struct intel_connector *connector;
7815
7816 list_for_each_entry(connector, &dev->mode_config.connector_list,
7817 base.head) {
7818 /* This also checks the encoder/connector hw state with the
7819 * ->get_hw_state callbacks. */
7820 intel_connector_check_state(connector);
7821
7822 WARN(&connector->new_encoder->base != connector->base.encoder,
7823 "connector's staged encoder doesn't match current encoder\n");
7824 }
7825
7826 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7827 base.head) {
7828 bool enabled = false;
7829 bool active = false;
7830 enum pipe pipe, tracked_pipe;
7831
7832 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7833 encoder->base.base.id,
7834 drm_get_encoder_name(&encoder->base));
7835
7836 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7837 "encoder's stage crtc doesn't match current crtc\n");
7838 WARN(encoder->connectors_active && !encoder->base.crtc,
7839 "encoder's active_connectors set, but no crtc\n");
7840
7841 list_for_each_entry(connector, &dev->mode_config.connector_list,
7842 base.head) {
7843 if (connector->base.encoder != &encoder->base)
7844 continue;
7845 enabled = true;
7846 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7847 active = true;
7848 }
7849 WARN(!!encoder->base.crtc != enabled,
7850 "encoder's enabled state mismatch "
7851 "(expected %i, found %i)\n",
7852 !!encoder->base.crtc, enabled);
7853 WARN(active && !encoder->base.crtc,
7854 "active encoder with no crtc\n");
7855
7856 WARN(encoder->connectors_active != active,
7857 "encoder's computed active state doesn't match tracked active state "
7858 "(expected %i, found %i)\n", active, encoder->connectors_active);
7859
7860 active = encoder->get_hw_state(encoder, &pipe);
7861 WARN(active != encoder->connectors_active,
7862 "encoder's hw state doesn't match sw tracking "
7863 "(expected %i, found %i)\n",
7864 encoder->connectors_active, active);
7865
7866 if (!encoder->base.crtc)
7867 continue;
7868
7869 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7870 WARN(active && pipe != tracked_pipe,
7871 "active encoder's pipe doesn't match"
7872 "(expected %i, found %i)\n",
7873 tracked_pipe, pipe);
7874
7875 }
7876
7877 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7878 base.head) {
7879 bool enabled = false;
7880 bool active = false;
7881
7882 DRM_DEBUG_KMS("[CRTC:%d]\n",
7883 crtc->base.base.id);
7884
7885 WARN(crtc->active && !crtc->base.enabled,
7886 "active crtc, but not enabled in sw tracking\n");
7887
7888 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7889 base.head) {
7890 if (encoder->base.crtc != &crtc->base)
7891 continue;
7892 enabled = true;
7893 if (encoder->connectors_active)
7894 active = true;
7895 }
7896 WARN(active != crtc->active,
7897 "crtc's computed active state doesn't match tracked active state "
7898 "(expected %i, found %i)\n", active, crtc->active);
7899 WARN(enabled != crtc->base.enabled,
7900 "crtc's computed enabled state doesn't match tracked enabled state "
7901 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7902
7903 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7904 }
7905 }
7906
7907 bool intel_set_mode(struct drm_crtc *crtc,
7908 struct drm_display_mode *mode,
7909 int x, int y, struct drm_framebuffer *fb)
7910 {
7911 struct drm_device *dev = crtc->dev;
7912 drm_i915_private_t *dev_priv = dev->dev_private;
7913 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7914 struct intel_crtc *intel_crtc;
7915 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7916 bool ret = true;
7917
7918 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7919 &prepare_pipes, &disable_pipes);
7920
7921 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7922 modeset_pipes, prepare_pipes, disable_pipes);
7923
7924 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7925 intel_crtc_disable(&intel_crtc->base);
7926
7927 saved_hwmode = crtc->hwmode;
7928 saved_mode = crtc->mode;
7929
7930 /* Hack: Because we don't (yet) support global modeset on multiple
7931 * crtcs, we don't keep track of the new mode for more than one crtc.
7932 * Hence simply check whether any bit is set in modeset_pipes in all the
7933 * pieces of code that are not yet converted to deal with mutliple crtcs
7934 * changing their mode at the same time. */
7935 adjusted_mode = NULL;
7936 if (modeset_pipes) {
7937 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7938 if (IS_ERR(adjusted_mode)) {
7939 return false;
7940 }
7941 }
7942
7943 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7944 if (intel_crtc->base.enabled)
7945 dev_priv->display.crtc_disable(&intel_crtc->base);
7946 }
7947
7948 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7949 * to set it here already despite that we pass it down the callchain.
7950 */
7951 if (modeset_pipes)
7952 crtc->mode = *mode;
7953
7954 /* Only after disabling all output pipelines that will be changed can we
7955 * update the the output configuration. */
7956 intel_modeset_update_state(dev, prepare_pipes);
7957
7958 if (dev_priv->display.modeset_global_resources)
7959 dev_priv->display.modeset_global_resources(dev);
7960
7961 /* Set up the DPLL and any encoders state that needs to adjust or depend
7962 * on the DPLL.
7963 */
7964 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7965 ret = !intel_crtc_mode_set(&intel_crtc->base,
7966 mode, adjusted_mode,
7967 x, y, fb);
7968 if (!ret)
7969 goto done;
7970 }
7971
7972 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7973 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7974 dev_priv->display.crtc_enable(&intel_crtc->base);
7975
7976 if (modeset_pipes) {
7977 /* Store real post-adjustment hardware mode. */
7978 crtc->hwmode = *adjusted_mode;
7979
7980 /* Calculate and store various constants which
7981 * are later needed by vblank and swap-completion
7982 * timestamping. They are derived from true hwmode.
7983 */
7984 drm_calc_timestamping_constants(crtc);
7985 }
7986
7987 /* FIXME: add subpixel order */
7988 done:
7989 drm_mode_destroy(dev, adjusted_mode);
7990 if (!ret && crtc->enabled) {
7991 crtc->hwmode = saved_hwmode;
7992 crtc->mode = saved_mode;
7993 } else {
7994 intel_modeset_check_state(dev);
7995 }
7996
7997 return ret;
7998 }
7999
8000 #undef for_each_intel_crtc_masked
8001
8002 static void intel_set_config_free(struct intel_set_config *config)
8003 {
8004 if (!config)
8005 return;
8006
8007 kfree(config->save_connector_encoders);
8008 kfree(config->save_encoder_crtcs);
8009 kfree(config);
8010 }
8011
8012 static int intel_set_config_save_state(struct drm_device *dev,
8013 struct intel_set_config *config)
8014 {
8015 struct drm_encoder *encoder;
8016 struct drm_connector *connector;
8017 int count;
8018
8019 config->save_encoder_crtcs =
8020 kcalloc(dev->mode_config.num_encoder,
8021 sizeof(struct drm_crtc *), GFP_KERNEL);
8022 if (!config->save_encoder_crtcs)
8023 return -ENOMEM;
8024
8025 config->save_connector_encoders =
8026 kcalloc(dev->mode_config.num_connector,
8027 sizeof(struct drm_encoder *), GFP_KERNEL);
8028 if (!config->save_connector_encoders)
8029 return -ENOMEM;
8030
8031 /* Copy data. Note that driver private data is not affected.
8032 * Should anything bad happen only the expected state is
8033 * restored, not the drivers personal bookkeeping.
8034 */
8035 count = 0;
8036 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8037 config->save_encoder_crtcs[count++] = encoder->crtc;
8038 }
8039
8040 count = 0;
8041 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8042 config->save_connector_encoders[count++] = connector->encoder;
8043 }
8044
8045 return 0;
8046 }
8047
8048 static void intel_set_config_restore_state(struct drm_device *dev,
8049 struct intel_set_config *config)
8050 {
8051 struct intel_encoder *encoder;
8052 struct intel_connector *connector;
8053 int count;
8054
8055 count = 0;
8056 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8057 encoder->new_crtc =
8058 to_intel_crtc(config->save_encoder_crtcs[count++]);
8059 }
8060
8061 count = 0;
8062 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8063 connector->new_encoder =
8064 to_intel_encoder(config->save_connector_encoders[count++]);
8065 }
8066 }
8067
8068 static void
8069 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8070 struct intel_set_config *config)
8071 {
8072
8073 /* We should be able to check here if the fb has the same properties
8074 * and then just flip_or_move it */
8075 if (set->crtc->fb != set->fb) {
8076 /* If we have no fb then treat it as a full mode set */
8077 if (set->crtc->fb == NULL) {
8078 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8079 config->mode_changed = true;
8080 } else if (set->fb == NULL) {
8081 config->mode_changed = true;
8082 } else if (set->fb->depth != set->crtc->fb->depth) {
8083 config->mode_changed = true;
8084 } else if (set->fb->bits_per_pixel !=
8085 set->crtc->fb->bits_per_pixel) {
8086 config->mode_changed = true;
8087 } else
8088 config->fb_changed = true;
8089 }
8090
8091 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8092 config->fb_changed = true;
8093
8094 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8095 DRM_DEBUG_KMS("modes are different, full mode set\n");
8096 drm_mode_debug_printmodeline(&set->crtc->mode);
8097 drm_mode_debug_printmodeline(set->mode);
8098 config->mode_changed = true;
8099 }
8100 }
8101
8102 static int
8103 intel_modeset_stage_output_state(struct drm_device *dev,
8104 struct drm_mode_set *set,
8105 struct intel_set_config *config)
8106 {
8107 struct drm_crtc *new_crtc;
8108 struct intel_connector *connector;
8109 struct intel_encoder *encoder;
8110 int count, ro;
8111
8112 /* The upper layers ensure that we either disabl a crtc or have a list
8113 * of connectors. For paranoia, double-check this. */
8114 WARN_ON(!set->fb && (set->num_connectors != 0));
8115 WARN_ON(set->fb && (set->num_connectors == 0));
8116
8117 count = 0;
8118 list_for_each_entry(connector, &dev->mode_config.connector_list,
8119 base.head) {
8120 /* Otherwise traverse passed in connector list and get encoders
8121 * for them. */
8122 for (ro = 0; ro < set->num_connectors; ro++) {
8123 if (set->connectors[ro] == &connector->base) {
8124 connector->new_encoder = connector->encoder;
8125 break;
8126 }
8127 }
8128
8129 /* If we disable the crtc, disable all its connectors. Also, if
8130 * the connector is on the changing crtc but not on the new
8131 * connector list, disable it. */
8132 if ((!set->fb || ro == set->num_connectors) &&
8133 connector->base.encoder &&
8134 connector->base.encoder->crtc == set->crtc) {
8135 connector->new_encoder = NULL;
8136
8137 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8138 connector->base.base.id,
8139 drm_get_connector_name(&connector->base));
8140 }
8141
8142
8143 if (&connector->new_encoder->base != connector->base.encoder) {
8144 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8145 config->mode_changed = true;
8146 }
8147
8148 /* Disable all disconnected encoders. */
8149 if (connector->base.status == connector_status_disconnected)
8150 connector->new_encoder = NULL;
8151 }
8152 /* connector->new_encoder is now updated for all connectors. */
8153
8154 /* Update crtc of enabled connectors. */
8155 count = 0;
8156 list_for_each_entry(connector, &dev->mode_config.connector_list,
8157 base.head) {
8158 if (!connector->new_encoder)
8159 continue;
8160
8161 new_crtc = connector->new_encoder->base.crtc;
8162
8163 for (ro = 0; ro < set->num_connectors; ro++) {
8164 if (set->connectors[ro] == &connector->base)
8165 new_crtc = set->crtc;
8166 }
8167
8168 /* Make sure the new CRTC will work with the encoder */
8169 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8170 new_crtc)) {
8171 return -EINVAL;
8172 }
8173 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8174
8175 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8176 connector->base.base.id,
8177 drm_get_connector_name(&connector->base),
8178 new_crtc->base.id);
8179 }
8180
8181 /* Check for any encoders that needs to be disabled. */
8182 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8183 base.head) {
8184 list_for_each_entry(connector,
8185 &dev->mode_config.connector_list,
8186 base.head) {
8187 if (connector->new_encoder == encoder) {
8188 WARN_ON(!connector->new_encoder->new_crtc);
8189
8190 goto next_encoder;
8191 }
8192 }
8193 encoder->new_crtc = NULL;
8194 next_encoder:
8195 /* Only now check for crtc changes so we don't miss encoders
8196 * that will be disabled. */
8197 if (&encoder->new_crtc->base != encoder->base.crtc) {
8198 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8199 config->mode_changed = true;
8200 }
8201 }
8202 /* Now we've also updated encoder->new_crtc for all encoders. */
8203
8204 return 0;
8205 }
8206
8207 static int intel_crtc_set_config(struct drm_mode_set *set)
8208 {
8209 struct drm_device *dev;
8210 struct drm_mode_set save_set;
8211 struct intel_set_config *config;
8212 int ret;
8213
8214 BUG_ON(!set);
8215 BUG_ON(!set->crtc);
8216 BUG_ON(!set->crtc->helper_private);
8217
8218 if (!set->mode)
8219 set->fb = NULL;
8220
8221 /* The fb helper likes to play gross jokes with ->mode_set_config.
8222 * Unfortunately the crtc helper doesn't do much at all for this case,
8223 * so we have to cope with this madness until the fb helper is fixed up. */
8224 if (set->fb && set->num_connectors == 0)
8225 return 0;
8226
8227 if (set->fb) {
8228 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8229 set->crtc->base.id, set->fb->base.id,
8230 (int)set->num_connectors, set->x, set->y);
8231 } else {
8232 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8233 }
8234
8235 dev = set->crtc->dev;
8236
8237 ret = -ENOMEM;
8238 config = kzalloc(sizeof(*config), GFP_KERNEL);
8239 if (!config)
8240 goto out_config;
8241
8242 ret = intel_set_config_save_state(dev, config);
8243 if (ret)
8244 goto out_config;
8245
8246 save_set.crtc = set->crtc;
8247 save_set.mode = &set->crtc->mode;
8248 save_set.x = set->crtc->x;
8249 save_set.y = set->crtc->y;
8250 save_set.fb = set->crtc->fb;
8251
8252 /* Compute whether we need a full modeset, only an fb base update or no
8253 * change at all. In the future we might also check whether only the
8254 * mode changed, e.g. for LVDS where we only change the panel fitter in
8255 * such cases. */
8256 intel_set_config_compute_mode_changes(set, config);
8257
8258 ret = intel_modeset_stage_output_state(dev, set, config);
8259 if (ret)
8260 goto fail;
8261
8262 if (config->mode_changed) {
8263 if (set->mode) {
8264 DRM_DEBUG_KMS("attempting to set mode from"
8265 " userspace\n");
8266 drm_mode_debug_printmodeline(set->mode);
8267 }
8268
8269 if (!intel_set_mode(set->crtc, set->mode,
8270 set->x, set->y, set->fb)) {
8271 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8272 set->crtc->base.id);
8273 ret = -EINVAL;
8274 goto fail;
8275 }
8276 } else if (config->fb_changed) {
8277 ret = intel_pipe_set_base(set->crtc,
8278 set->x, set->y, set->fb);
8279 }
8280
8281 intel_set_config_free(config);
8282
8283 return 0;
8284
8285 fail:
8286 intel_set_config_restore_state(dev, config);
8287
8288 /* Try to restore the config */
8289 if (config->mode_changed &&
8290 !intel_set_mode(save_set.crtc, save_set.mode,
8291 save_set.x, save_set.y, save_set.fb))
8292 DRM_ERROR("failed to restore config after modeset failure\n");
8293
8294 out_config:
8295 intel_set_config_free(config);
8296 return ret;
8297 }
8298
8299 static const struct drm_crtc_funcs intel_crtc_funcs = {
8300 .cursor_set = intel_crtc_cursor_set,
8301 .cursor_move = intel_crtc_cursor_move,
8302 .gamma_set = intel_crtc_gamma_set,
8303 .set_config = intel_crtc_set_config,
8304 .destroy = intel_crtc_destroy,
8305 .page_flip = intel_crtc_page_flip,
8306 };
8307
8308 static void intel_cpu_pll_init(struct drm_device *dev)
8309 {
8310 if (IS_HASWELL(dev))
8311 intel_ddi_pll_init(dev);
8312 }
8313
8314 static void intel_pch_pll_init(struct drm_device *dev)
8315 {
8316 drm_i915_private_t *dev_priv = dev->dev_private;
8317 int i;
8318
8319 if (dev_priv->num_pch_pll == 0) {
8320 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8321 return;
8322 }
8323
8324 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8325 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8326 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8327 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8328 }
8329 }
8330
8331 static void intel_crtc_init(struct drm_device *dev, int pipe)
8332 {
8333 drm_i915_private_t *dev_priv = dev->dev_private;
8334 struct intel_crtc *intel_crtc;
8335 int i;
8336
8337 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8338 if (intel_crtc == NULL)
8339 return;
8340
8341 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8342
8343 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8344 for (i = 0; i < 256; i++) {
8345 intel_crtc->lut_r[i] = i;
8346 intel_crtc->lut_g[i] = i;
8347 intel_crtc->lut_b[i] = i;
8348 }
8349
8350 /* Swap pipes & planes for FBC on pre-965 */
8351 intel_crtc->pipe = pipe;
8352 intel_crtc->plane = pipe;
8353 intel_crtc->cpu_transcoder = pipe;
8354 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8355 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8356 intel_crtc->plane = !pipe;
8357 }
8358
8359 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8360 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8361 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8362 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8363
8364 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8365
8366 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8367 }
8368
8369 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8370 struct drm_file *file)
8371 {
8372 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8373 struct drm_mode_object *drmmode_obj;
8374 struct intel_crtc *crtc;
8375
8376 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8377 return -ENODEV;
8378
8379 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8380 DRM_MODE_OBJECT_CRTC);
8381
8382 if (!drmmode_obj) {
8383 DRM_ERROR("no such CRTC id\n");
8384 return -EINVAL;
8385 }
8386
8387 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8388 pipe_from_crtc_id->pipe = crtc->pipe;
8389
8390 return 0;
8391 }
8392
8393 static int intel_encoder_clones(struct intel_encoder *encoder)
8394 {
8395 struct drm_device *dev = encoder->base.dev;
8396 struct intel_encoder *source_encoder;
8397 int index_mask = 0;
8398 int entry = 0;
8399
8400 list_for_each_entry(source_encoder,
8401 &dev->mode_config.encoder_list, base.head) {
8402
8403 if (encoder == source_encoder)
8404 index_mask |= (1 << entry);
8405
8406 /* Intel hw has only one MUX where enocoders could be cloned. */
8407 if (encoder->cloneable && source_encoder->cloneable)
8408 index_mask |= (1 << entry);
8409
8410 entry++;
8411 }
8412
8413 return index_mask;
8414 }
8415
8416 static bool has_edp_a(struct drm_device *dev)
8417 {
8418 struct drm_i915_private *dev_priv = dev->dev_private;
8419
8420 if (!IS_MOBILE(dev))
8421 return false;
8422
8423 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8424 return false;
8425
8426 if (IS_GEN5(dev) &&
8427 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8428 return false;
8429
8430 return true;
8431 }
8432
8433 static void intel_setup_outputs(struct drm_device *dev)
8434 {
8435 struct drm_i915_private *dev_priv = dev->dev_private;
8436 struct intel_encoder *encoder;
8437 bool dpd_is_edp = false;
8438 bool has_lvds;
8439
8440 has_lvds = intel_lvds_init(dev);
8441 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8442 /* disable the panel fitter on everything but LVDS */
8443 I915_WRITE(PFIT_CONTROL, 0);
8444 }
8445
8446 if (!(IS_HASWELL(dev) &&
8447 (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8448 intel_crt_init(dev);
8449
8450 if (IS_HASWELL(dev)) {
8451 int found;
8452
8453 /* Haswell uses DDI functions to detect digital outputs */
8454 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8455 /* DDI A only supports eDP */
8456 if (found)
8457 intel_ddi_init(dev, PORT_A);
8458
8459 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8460 * register */
8461 found = I915_READ(SFUSE_STRAP);
8462
8463 if (found & SFUSE_STRAP_DDIB_DETECTED)
8464 intel_ddi_init(dev, PORT_B);
8465 if (found & SFUSE_STRAP_DDIC_DETECTED)
8466 intel_ddi_init(dev, PORT_C);
8467 if (found & SFUSE_STRAP_DDID_DETECTED)
8468 intel_ddi_init(dev, PORT_D);
8469 } else if (HAS_PCH_SPLIT(dev)) {
8470 int found;
8471 dpd_is_edp = intel_dpd_is_edp(dev);
8472
8473 if (has_edp_a(dev))
8474 intel_dp_init(dev, DP_A, PORT_A);
8475
8476 if (I915_READ(HDMIB) & PORT_DETECTED) {
8477 /* PCH SDVOB multiplex with HDMIB */
8478 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8479 if (!found)
8480 intel_hdmi_init(dev, HDMIB, PORT_B);
8481 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8482 intel_dp_init(dev, PCH_DP_B, PORT_B);
8483 }
8484
8485 if (I915_READ(HDMIC) & PORT_DETECTED)
8486 intel_hdmi_init(dev, HDMIC, PORT_C);
8487
8488 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8489 intel_hdmi_init(dev, HDMID, PORT_D);
8490
8491 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8492 intel_dp_init(dev, PCH_DP_C, PORT_C);
8493
8494 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8495 intel_dp_init(dev, PCH_DP_D, PORT_D);
8496 } else if (IS_VALLEYVIEW(dev)) {
8497 int found;
8498
8499 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8500 if (I915_READ(DP_C) & DP_DETECTED)
8501 intel_dp_init(dev, DP_C, PORT_C);
8502
8503 if (I915_READ(SDVOB) & PORT_DETECTED) {
8504 /* SDVOB multiplex with HDMIB */
8505 found = intel_sdvo_init(dev, SDVOB, true);
8506 if (!found)
8507 intel_hdmi_init(dev, SDVOB, PORT_B);
8508 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8509 intel_dp_init(dev, DP_B, PORT_B);
8510 }
8511
8512 if (I915_READ(SDVOC) & PORT_DETECTED)
8513 intel_hdmi_init(dev, SDVOC, PORT_C);
8514
8515 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8516 bool found = false;
8517
8518 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8519 DRM_DEBUG_KMS("probing SDVOB\n");
8520 found = intel_sdvo_init(dev, SDVOB, true);
8521 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8522 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8523 intel_hdmi_init(dev, SDVOB, PORT_B);
8524 }
8525
8526 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8527 DRM_DEBUG_KMS("probing DP_B\n");
8528 intel_dp_init(dev, DP_B, PORT_B);
8529 }
8530 }
8531
8532 /* Before G4X SDVOC doesn't have its own detect register */
8533
8534 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8535 DRM_DEBUG_KMS("probing SDVOC\n");
8536 found = intel_sdvo_init(dev, SDVOC, false);
8537 }
8538
8539 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8540
8541 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8542 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8543 intel_hdmi_init(dev, SDVOC, PORT_C);
8544 }
8545 if (SUPPORTS_INTEGRATED_DP(dev)) {
8546 DRM_DEBUG_KMS("probing DP_C\n");
8547 intel_dp_init(dev, DP_C, PORT_C);
8548 }
8549 }
8550
8551 if (SUPPORTS_INTEGRATED_DP(dev) &&
8552 (I915_READ(DP_D) & DP_DETECTED)) {
8553 DRM_DEBUG_KMS("probing DP_D\n");
8554 intel_dp_init(dev, DP_D, PORT_D);
8555 }
8556 } else if (IS_GEN2(dev))
8557 intel_dvo_init(dev);
8558
8559 if (SUPPORTS_TV(dev))
8560 intel_tv_init(dev);
8561
8562 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8563 encoder->base.possible_crtcs = encoder->crtc_mask;
8564 encoder->base.possible_clones =
8565 intel_encoder_clones(encoder);
8566 }
8567
8568 intel_init_pch_refclk(dev);
8569
8570 drm_helper_move_panel_connectors_to_head(dev);
8571 }
8572
8573 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8574 {
8575 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8576
8577 drm_framebuffer_cleanup(fb);
8578 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8579
8580 kfree(intel_fb);
8581 }
8582
8583 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8584 struct drm_file *file,
8585 unsigned int *handle)
8586 {
8587 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8588 struct drm_i915_gem_object *obj = intel_fb->obj;
8589
8590 return drm_gem_handle_create(file, &obj->base, handle);
8591 }
8592
8593 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8594 .destroy = intel_user_framebuffer_destroy,
8595 .create_handle = intel_user_framebuffer_create_handle,
8596 };
8597
8598 int intel_framebuffer_init(struct drm_device *dev,
8599 struct intel_framebuffer *intel_fb,
8600 struct drm_mode_fb_cmd2 *mode_cmd,
8601 struct drm_i915_gem_object *obj)
8602 {
8603 int ret;
8604
8605 if (obj->tiling_mode == I915_TILING_Y)
8606 return -EINVAL;
8607
8608 if (mode_cmd->pitches[0] & 63)
8609 return -EINVAL;
8610
8611 /* FIXME <= Gen4 stride limits are bit unclear */
8612 if (mode_cmd->pitches[0] > 32768)
8613 return -EINVAL;
8614
8615 if (obj->tiling_mode != I915_TILING_NONE &&
8616 mode_cmd->pitches[0] != obj->stride)
8617 return -EINVAL;
8618
8619 /* Reject formats not supported by any plane early. */
8620 switch (mode_cmd->pixel_format) {
8621 case DRM_FORMAT_C8:
8622 case DRM_FORMAT_RGB565:
8623 case DRM_FORMAT_XRGB8888:
8624 case DRM_FORMAT_ARGB8888:
8625 break;
8626 case DRM_FORMAT_XRGB1555:
8627 case DRM_FORMAT_ARGB1555:
8628 if (INTEL_INFO(dev)->gen > 3)
8629 return -EINVAL;
8630 break;
8631 case DRM_FORMAT_XBGR8888:
8632 case DRM_FORMAT_ABGR8888:
8633 case DRM_FORMAT_XRGB2101010:
8634 case DRM_FORMAT_ARGB2101010:
8635 case DRM_FORMAT_XBGR2101010:
8636 case DRM_FORMAT_ABGR2101010:
8637 if (INTEL_INFO(dev)->gen < 4)
8638 return -EINVAL;
8639 break;
8640 case DRM_FORMAT_YUYV:
8641 case DRM_FORMAT_UYVY:
8642 case DRM_FORMAT_YVYU:
8643 case DRM_FORMAT_VYUY:
8644 if (INTEL_INFO(dev)->gen < 6)
8645 return -EINVAL;
8646 break;
8647 default:
8648 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8649 return -EINVAL;
8650 }
8651
8652 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8653 if (mode_cmd->offsets[0] != 0)
8654 return -EINVAL;
8655
8656 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8657 if (ret) {
8658 DRM_ERROR("framebuffer init failed %d\n", ret);
8659 return ret;
8660 }
8661
8662 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8663 intel_fb->obj = obj;
8664 return 0;
8665 }
8666
8667 static struct drm_framebuffer *
8668 intel_user_framebuffer_create(struct drm_device *dev,
8669 struct drm_file *filp,
8670 struct drm_mode_fb_cmd2 *mode_cmd)
8671 {
8672 struct drm_i915_gem_object *obj;
8673
8674 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8675 mode_cmd->handles[0]));
8676 if (&obj->base == NULL)
8677 return ERR_PTR(-ENOENT);
8678
8679 return intel_framebuffer_create(dev, mode_cmd, obj);
8680 }
8681
8682 static const struct drm_mode_config_funcs intel_mode_funcs = {
8683 .fb_create = intel_user_framebuffer_create,
8684 .output_poll_changed = intel_fb_output_poll_changed,
8685 };
8686
8687 /* Set up chip specific display functions */
8688 static void intel_init_display(struct drm_device *dev)
8689 {
8690 struct drm_i915_private *dev_priv = dev->dev_private;
8691
8692 /* We always want a DPMS function */
8693 if (IS_HASWELL(dev)) {
8694 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8695 dev_priv->display.crtc_enable = haswell_crtc_enable;
8696 dev_priv->display.crtc_disable = haswell_crtc_disable;
8697 dev_priv->display.off = haswell_crtc_off;
8698 dev_priv->display.update_plane = ironlake_update_plane;
8699 } else if (HAS_PCH_SPLIT(dev)) {
8700 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8701 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8702 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8703 dev_priv->display.off = ironlake_crtc_off;
8704 dev_priv->display.update_plane = ironlake_update_plane;
8705 } else {
8706 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8707 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8708 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8709 dev_priv->display.off = i9xx_crtc_off;
8710 dev_priv->display.update_plane = i9xx_update_plane;
8711 }
8712
8713 /* Returns the core display clock speed */
8714 if (IS_VALLEYVIEW(dev))
8715 dev_priv->display.get_display_clock_speed =
8716 valleyview_get_display_clock_speed;
8717 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8718 dev_priv->display.get_display_clock_speed =
8719 i945_get_display_clock_speed;
8720 else if (IS_I915G(dev))
8721 dev_priv->display.get_display_clock_speed =
8722 i915_get_display_clock_speed;
8723 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8724 dev_priv->display.get_display_clock_speed =
8725 i9xx_misc_get_display_clock_speed;
8726 else if (IS_I915GM(dev))
8727 dev_priv->display.get_display_clock_speed =
8728 i915gm_get_display_clock_speed;
8729 else if (IS_I865G(dev))
8730 dev_priv->display.get_display_clock_speed =
8731 i865_get_display_clock_speed;
8732 else if (IS_I85X(dev))
8733 dev_priv->display.get_display_clock_speed =
8734 i855_get_display_clock_speed;
8735 else /* 852, 830 */
8736 dev_priv->display.get_display_clock_speed =
8737 i830_get_display_clock_speed;
8738
8739 if (HAS_PCH_SPLIT(dev)) {
8740 if (IS_GEN5(dev)) {
8741 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8742 dev_priv->display.write_eld = ironlake_write_eld;
8743 } else if (IS_GEN6(dev)) {
8744 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8745 dev_priv->display.write_eld = ironlake_write_eld;
8746 } else if (IS_IVYBRIDGE(dev)) {
8747 /* FIXME: detect B0+ stepping and use auto training */
8748 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8749 dev_priv->display.write_eld = ironlake_write_eld;
8750 dev_priv->display.modeset_global_resources =
8751 ivb_modeset_global_resources;
8752 } else if (IS_HASWELL(dev)) {
8753 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8754 dev_priv->display.write_eld = haswell_write_eld;
8755 } else
8756 dev_priv->display.update_wm = NULL;
8757 } else if (IS_G4X(dev)) {
8758 dev_priv->display.write_eld = g4x_write_eld;
8759 }
8760
8761 /* Default just returns -ENODEV to indicate unsupported */
8762 dev_priv->display.queue_flip = intel_default_queue_flip;
8763
8764 switch (INTEL_INFO(dev)->gen) {
8765 case 2:
8766 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8767 break;
8768
8769 case 3:
8770 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8771 break;
8772
8773 case 4:
8774 case 5:
8775 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8776 break;
8777
8778 case 6:
8779 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8780 break;
8781 case 7:
8782 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8783 break;
8784 }
8785 }
8786
8787 /*
8788 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8789 * resume, or other times. This quirk makes sure that's the case for
8790 * affected systems.
8791 */
8792 static void quirk_pipea_force(struct drm_device *dev)
8793 {
8794 struct drm_i915_private *dev_priv = dev->dev_private;
8795
8796 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8797 DRM_INFO("applying pipe a force quirk\n");
8798 }
8799
8800 /*
8801 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8802 */
8803 static void quirk_ssc_force_disable(struct drm_device *dev)
8804 {
8805 struct drm_i915_private *dev_priv = dev->dev_private;
8806 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8807 DRM_INFO("applying lvds SSC disable quirk\n");
8808 }
8809
8810 /*
8811 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8812 * brightness value
8813 */
8814 static void quirk_invert_brightness(struct drm_device *dev)
8815 {
8816 struct drm_i915_private *dev_priv = dev->dev_private;
8817 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8818 DRM_INFO("applying inverted panel brightness quirk\n");
8819 }
8820
8821 struct intel_quirk {
8822 int device;
8823 int subsystem_vendor;
8824 int subsystem_device;
8825 void (*hook)(struct drm_device *dev);
8826 };
8827
8828 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8829 struct intel_dmi_quirk {
8830 void (*hook)(struct drm_device *dev);
8831 const struct dmi_system_id (*dmi_id_list)[];
8832 };
8833
8834 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8835 {
8836 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8837 return 1;
8838 }
8839
8840 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8841 {
8842 .dmi_id_list = &(const struct dmi_system_id[]) {
8843 {
8844 .callback = intel_dmi_reverse_brightness,
8845 .ident = "NCR Corporation",
8846 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8847 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8848 },
8849 },
8850 { } /* terminating entry */
8851 },
8852 .hook = quirk_invert_brightness,
8853 },
8854 };
8855
8856 static struct intel_quirk intel_quirks[] = {
8857 /* HP Mini needs pipe A force quirk (LP: #322104) */
8858 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8859
8860 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8861 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8862
8863 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8864 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8865
8866 /* 830/845 need to leave pipe A & dpll A up */
8867 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8868 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8869
8870 /* Lenovo U160 cannot use SSC on LVDS */
8871 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8872
8873 /* Sony Vaio Y cannot use SSC on LVDS */
8874 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8875
8876 /* Acer Aspire 5734Z must invert backlight brightness */
8877 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8878 };
8879
8880 static void intel_init_quirks(struct drm_device *dev)
8881 {
8882 struct pci_dev *d = dev->pdev;
8883 int i;
8884
8885 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8886 struct intel_quirk *q = &intel_quirks[i];
8887
8888 if (d->device == q->device &&
8889 (d->subsystem_vendor == q->subsystem_vendor ||
8890 q->subsystem_vendor == PCI_ANY_ID) &&
8891 (d->subsystem_device == q->subsystem_device ||
8892 q->subsystem_device == PCI_ANY_ID))
8893 q->hook(dev);
8894 }
8895 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8896 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8897 intel_dmi_quirks[i].hook(dev);
8898 }
8899 }
8900
8901 /* Disable the VGA plane that we never use */
8902 static void i915_disable_vga(struct drm_device *dev)
8903 {
8904 struct drm_i915_private *dev_priv = dev->dev_private;
8905 u8 sr1;
8906 u32 vga_reg;
8907
8908 if (HAS_PCH_SPLIT(dev))
8909 vga_reg = CPU_VGACNTRL;
8910 else
8911 vga_reg = VGACNTRL;
8912
8913 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8914 outb(SR01, VGA_SR_INDEX);
8915 sr1 = inb(VGA_SR_DATA);
8916 outb(sr1 | 1<<5, VGA_SR_DATA);
8917 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8918 udelay(300);
8919
8920 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8921 POSTING_READ(vga_reg);
8922 }
8923
8924 void intel_modeset_init_hw(struct drm_device *dev)
8925 {
8926 /* We attempt to init the necessary power wells early in the initialization
8927 * time, so the subsystems that expect power to be enabled can work.
8928 */
8929 intel_init_power_wells(dev);
8930
8931 intel_prepare_ddi(dev);
8932
8933 intel_init_clock_gating(dev);
8934
8935 mutex_lock(&dev->struct_mutex);
8936 intel_enable_gt_powersave(dev);
8937 mutex_unlock(&dev->struct_mutex);
8938 }
8939
8940 void intel_modeset_init(struct drm_device *dev)
8941 {
8942 struct drm_i915_private *dev_priv = dev->dev_private;
8943 int i, ret;
8944
8945 drm_mode_config_init(dev);
8946
8947 dev->mode_config.min_width = 0;
8948 dev->mode_config.min_height = 0;
8949
8950 dev->mode_config.preferred_depth = 24;
8951 dev->mode_config.prefer_shadow = 1;
8952
8953 dev->mode_config.funcs = &intel_mode_funcs;
8954
8955 intel_init_quirks(dev);
8956
8957 intel_init_pm(dev);
8958
8959 intel_init_display(dev);
8960
8961 if (IS_GEN2(dev)) {
8962 dev->mode_config.max_width = 2048;
8963 dev->mode_config.max_height = 2048;
8964 } else if (IS_GEN3(dev)) {
8965 dev->mode_config.max_width = 4096;
8966 dev->mode_config.max_height = 4096;
8967 } else {
8968 dev->mode_config.max_width = 8192;
8969 dev->mode_config.max_height = 8192;
8970 }
8971 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8972
8973 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8974 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8975
8976 for (i = 0; i < dev_priv->num_pipe; i++) {
8977 intel_crtc_init(dev, i);
8978 ret = intel_plane_init(dev, i);
8979 if (ret)
8980 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8981 }
8982
8983 intel_cpu_pll_init(dev);
8984 intel_pch_pll_init(dev);
8985
8986 /* Just disable it once at startup */
8987 i915_disable_vga(dev);
8988 intel_setup_outputs(dev);
8989 }
8990
8991 static void
8992 intel_connector_break_all_links(struct intel_connector *connector)
8993 {
8994 connector->base.dpms = DRM_MODE_DPMS_OFF;
8995 connector->base.encoder = NULL;
8996 connector->encoder->connectors_active = false;
8997 connector->encoder->base.crtc = NULL;
8998 }
8999
9000 static void intel_enable_pipe_a(struct drm_device *dev)
9001 {
9002 struct intel_connector *connector;
9003 struct drm_connector *crt = NULL;
9004 struct intel_load_detect_pipe load_detect_temp;
9005
9006 /* We can't just switch on the pipe A, we need to set things up with a
9007 * proper mode and output configuration. As a gross hack, enable pipe A
9008 * by enabling the load detect pipe once. */
9009 list_for_each_entry(connector,
9010 &dev->mode_config.connector_list,
9011 base.head) {
9012 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9013 crt = &connector->base;
9014 break;
9015 }
9016 }
9017
9018 if (!crt)
9019 return;
9020
9021 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9022 intel_release_load_detect_pipe(crt, &load_detect_temp);
9023
9024
9025 }
9026
9027 static bool
9028 intel_check_plane_mapping(struct intel_crtc *crtc)
9029 {
9030 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
9031 u32 reg, val;
9032
9033 if (dev_priv->num_pipe == 1)
9034 return true;
9035
9036 reg = DSPCNTR(!crtc->plane);
9037 val = I915_READ(reg);
9038
9039 if ((val & DISPLAY_PLANE_ENABLE) &&
9040 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9041 return false;
9042
9043 return true;
9044 }
9045
9046 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9047 {
9048 struct drm_device *dev = crtc->base.dev;
9049 struct drm_i915_private *dev_priv = dev->dev_private;
9050 u32 reg;
9051
9052 /* Clear any frame start delays used for debugging left by the BIOS */
9053 reg = PIPECONF(crtc->cpu_transcoder);
9054 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9055
9056 /* We need to sanitize the plane -> pipe mapping first because this will
9057 * disable the crtc (and hence change the state) if it is wrong. Note
9058 * that gen4+ has a fixed plane -> pipe mapping. */
9059 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9060 struct intel_connector *connector;
9061 bool plane;
9062
9063 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9064 crtc->base.base.id);
9065
9066 /* Pipe has the wrong plane attached and the plane is active.
9067 * Temporarily change the plane mapping and disable everything
9068 * ... */
9069 plane = crtc->plane;
9070 crtc->plane = !plane;
9071 dev_priv->display.crtc_disable(&crtc->base);
9072 crtc->plane = plane;
9073
9074 /* ... and break all links. */
9075 list_for_each_entry(connector, &dev->mode_config.connector_list,
9076 base.head) {
9077 if (connector->encoder->base.crtc != &crtc->base)
9078 continue;
9079
9080 intel_connector_break_all_links(connector);
9081 }
9082
9083 WARN_ON(crtc->active);
9084 crtc->base.enabled = false;
9085 }
9086
9087 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9088 crtc->pipe == PIPE_A && !crtc->active) {
9089 /* BIOS forgot to enable pipe A, this mostly happens after
9090 * resume. Force-enable the pipe to fix this, the update_dpms
9091 * call below we restore the pipe to the right state, but leave
9092 * the required bits on. */
9093 intel_enable_pipe_a(dev);
9094 }
9095
9096 /* Adjust the state of the output pipe according to whether we
9097 * have active connectors/encoders. */
9098 intel_crtc_update_dpms(&crtc->base);
9099
9100 if (crtc->active != crtc->base.enabled) {
9101 struct intel_encoder *encoder;
9102
9103 /* This can happen either due to bugs in the get_hw_state
9104 * functions or because the pipe is force-enabled due to the
9105 * pipe A quirk. */
9106 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9107 crtc->base.base.id,
9108 crtc->base.enabled ? "enabled" : "disabled",
9109 crtc->active ? "enabled" : "disabled");
9110
9111 crtc->base.enabled = crtc->active;
9112
9113 /* Because we only establish the connector -> encoder ->
9114 * crtc links if something is active, this means the
9115 * crtc is now deactivated. Break the links. connector
9116 * -> encoder links are only establish when things are
9117 * actually up, hence no need to break them. */
9118 WARN_ON(crtc->active);
9119
9120 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9121 WARN_ON(encoder->connectors_active);
9122 encoder->base.crtc = NULL;
9123 }
9124 }
9125 }
9126
9127 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9128 {
9129 struct intel_connector *connector;
9130 struct drm_device *dev = encoder->base.dev;
9131
9132 /* We need to check both for a crtc link (meaning that the
9133 * encoder is active and trying to read from a pipe) and the
9134 * pipe itself being active. */
9135 bool has_active_crtc = encoder->base.crtc &&
9136 to_intel_crtc(encoder->base.crtc)->active;
9137
9138 if (encoder->connectors_active && !has_active_crtc) {
9139 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9140 encoder->base.base.id,
9141 drm_get_encoder_name(&encoder->base));
9142
9143 /* Connector is active, but has no active pipe. This is
9144 * fallout from our resume register restoring. Disable
9145 * the encoder manually again. */
9146 if (encoder->base.crtc) {
9147 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9148 encoder->base.base.id,
9149 drm_get_encoder_name(&encoder->base));
9150 encoder->disable(encoder);
9151 }
9152
9153 /* Inconsistent output/port/pipe state happens presumably due to
9154 * a bug in one of the get_hw_state functions. Or someplace else
9155 * in our code, like the register restore mess on resume. Clamp
9156 * things to off as a safer default. */
9157 list_for_each_entry(connector,
9158 &dev->mode_config.connector_list,
9159 base.head) {
9160 if (connector->encoder != encoder)
9161 continue;
9162
9163 intel_connector_break_all_links(connector);
9164 }
9165 }
9166 /* Enabled encoders without active connectors will be fixed in
9167 * the crtc fixup. */
9168 }
9169
9170 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9171 * and i915 state tracking structures. */
9172 void intel_modeset_setup_hw_state(struct drm_device *dev,
9173 bool force_restore)
9174 {
9175 struct drm_i915_private *dev_priv = dev->dev_private;
9176 enum pipe pipe;
9177 u32 tmp;
9178 struct intel_crtc *crtc;
9179 struct intel_encoder *encoder;
9180 struct intel_connector *connector;
9181
9182 if (IS_HASWELL(dev)) {
9183 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9184
9185 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9186 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9187 case TRANS_DDI_EDP_INPUT_A_ON:
9188 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9189 pipe = PIPE_A;
9190 break;
9191 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9192 pipe = PIPE_B;
9193 break;
9194 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9195 pipe = PIPE_C;
9196 break;
9197 }
9198
9199 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9200 crtc->cpu_transcoder = TRANSCODER_EDP;
9201
9202 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9203 pipe_name(pipe));
9204 }
9205 }
9206
9207 for_each_pipe(pipe) {
9208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9209
9210 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9211 if (tmp & PIPECONF_ENABLE)
9212 crtc->active = true;
9213 else
9214 crtc->active = false;
9215
9216 crtc->base.enabled = crtc->active;
9217
9218 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9219 crtc->base.base.id,
9220 crtc->active ? "enabled" : "disabled");
9221 }
9222
9223 if (IS_HASWELL(dev))
9224 intel_ddi_setup_hw_pll_state(dev);
9225
9226 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9227 base.head) {
9228 pipe = 0;
9229
9230 if (encoder->get_hw_state(encoder, &pipe)) {
9231 encoder->base.crtc =
9232 dev_priv->pipe_to_crtc_mapping[pipe];
9233 } else {
9234 encoder->base.crtc = NULL;
9235 }
9236
9237 encoder->connectors_active = false;
9238 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9239 encoder->base.base.id,
9240 drm_get_encoder_name(&encoder->base),
9241 encoder->base.crtc ? "enabled" : "disabled",
9242 pipe);
9243 }
9244
9245 list_for_each_entry(connector, &dev->mode_config.connector_list,
9246 base.head) {
9247 if (connector->get_hw_state(connector)) {
9248 connector->base.dpms = DRM_MODE_DPMS_ON;
9249 connector->encoder->connectors_active = true;
9250 connector->base.encoder = &connector->encoder->base;
9251 } else {
9252 connector->base.dpms = DRM_MODE_DPMS_OFF;
9253 connector->base.encoder = NULL;
9254 }
9255 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9256 connector->base.base.id,
9257 drm_get_connector_name(&connector->base),
9258 connector->base.encoder ? "enabled" : "disabled");
9259 }
9260
9261 /* HW state is read out, now we need to sanitize this mess. */
9262 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9263 base.head) {
9264 intel_sanitize_encoder(encoder);
9265 }
9266
9267 for_each_pipe(pipe) {
9268 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9269 intel_sanitize_crtc(crtc);
9270 }
9271
9272 if (force_restore) {
9273 for_each_pipe(pipe) {
9274 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9275 intel_set_mode(&crtc->base, &crtc->base.mode,
9276 crtc->base.x, crtc->base.y, crtc->base.fb);
9277 }
9278 } else {
9279 intel_modeset_update_staged_output_state(dev);
9280 }
9281
9282 intel_modeset_check_state(dev);
9283
9284 drm_mode_config_reset(dev);
9285 }
9286
9287 void intel_modeset_gem_init(struct drm_device *dev)
9288 {
9289 intel_modeset_init_hw(dev);
9290
9291 intel_setup_overlay(dev);
9292
9293 intel_modeset_setup_hw_state(dev, false);
9294 }
9295
9296 void intel_modeset_cleanup(struct drm_device *dev)
9297 {
9298 struct drm_i915_private *dev_priv = dev->dev_private;
9299 struct drm_crtc *crtc;
9300 struct intel_crtc *intel_crtc;
9301
9302 drm_kms_helper_poll_fini(dev);
9303 mutex_lock(&dev->struct_mutex);
9304
9305 intel_unregister_dsm_handler();
9306
9307
9308 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9309 /* Skip inactive CRTCs */
9310 if (!crtc->fb)
9311 continue;
9312
9313 intel_crtc = to_intel_crtc(crtc);
9314 intel_increase_pllclock(crtc);
9315 }
9316
9317 intel_disable_fbc(dev);
9318
9319 intel_disable_gt_powersave(dev);
9320
9321 ironlake_teardown_rc6(dev);
9322
9323 if (IS_VALLEYVIEW(dev))
9324 vlv_init_dpio(dev);
9325
9326 mutex_unlock(&dev->struct_mutex);
9327
9328 /* Disable the irq before mode object teardown, for the irq might
9329 * enqueue unpin/hotplug work. */
9330 drm_irq_uninstall(dev);
9331 cancel_work_sync(&dev_priv->hotplug_work);
9332 cancel_work_sync(&dev_priv->rps.work);
9333
9334 /* flush any delayed tasks or pending work */
9335 flush_scheduled_work();
9336
9337 drm_mode_config_cleanup(dev);
9338 }
9339
9340 /*
9341 * Return which encoder is currently attached for connector.
9342 */
9343 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9344 {
9345 return &intel_attached_encoder(connector)->base;
9346 }
9347
9348 void intel_connector_attach_encoder(struct intel_connector *connector,
9349 struct intel_encoder *encoder)
9350 {
9351 connector->encoder = encoder;
9352 drm_mode_connector_attach_encoder(&connector->base,
9353 &encoder->base);
9354 }
9355
9356 /*
9357 * set vga decode state - true == enable VGA decode
9358 */
9359 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9360 {
9361 struct drm_i915_private *dev_priv = dev->dev_private;
9362 u16 gmch_ctrl;
9363
9364 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9365 if (state)
9366 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9367 else
9368 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9369 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9370 return 0;
9371 }
9372
9373 #ifdef CONFIG_DEBUG_FS
9374 #include <linux/seq_file.h>
9375
9376 struct intel_display_error_state {
9377 struct intel_cursor_error_state {
9378 u32 control;
9379 u32 position;
9380 u32 base;
9381 u32 size;
9382 } cursor[I915_MAX_PIPES];
9383
9384 struct intel_pipe_error_state {
9385 u32 conf;
9386 u32 source;
9387
9388 u32 htotal;
9389 u32 hblank;
9390 u32 hsync;
9391 u32 vtotal;
9392 u32 vblank;
9393 u32 vsync;
9394 } pipe[I915_MAX_PIPES];
9395
9396 struct intel_plane_error_state {
9397 u32 control;
9398 u32 stride;
9399 u32 size;
9400 u32 pos;
9401 u32 addr;
9402 u32 surface;
9403 u32 tile_offset;
9404 } plane[I915_MAX_PIPES];
9405 };
9406
9407 struct intel_display_error_state *
9408 intel_display_capture_error_state(struct drm_device *dev)
9409 {
9410 drm_i915_private_t *dev_priv = dev->dev_private;
9411 struct intel_display_error_state *error;
9412 enum transcoder cpu_transcoder;
9413 int i;
9414
9415 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9416 if (error == NULL)
9417 return NULL;
9418
9419 for_each_pipe(i) {
9420 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9421
9422 error->cursor[i].control = I915_READ(CURCNTR(i));
9423 error->cursor[i].position = I915_READ(CURPOS(i));
9424 error->cursor[i].base = I915_READ(CURBASE(i));
9425
9426 error->plane[i].control = I915_READ(DSPCNTR(i));
9427 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9428 error->plane[i].size = I915_READ(DSPSIZE(i));
9429 error->plane[i].pos = I915_READ(DSPPOS(i));
9430 error->plane[i].addr = I915_READ(DSPADDR(i));
9431 if (INTEL_INFO(dev)->gen >= 4) {
9432 error->plane[i].surface = I915_READ(DSPSURF(i));
9433 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9434 }
9435
9436 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9437 error->pipe[i].source = I915_READ(PIPESRC(i));
9438 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9439 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9440 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9441 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9442 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9443 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9444 }
9445
9446 return error;
9447 }
9448
9449 void
9450 intel_display_print_error_state(struct seq_file *m,
9451 struct drm_device *dev,
9452 struct intel_display_error_state *error)
9453 {
9454 drm_i915_private_t *dev_priv = dev->dev_private;
9455 int i;
9456
9457 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9458 for_each_pipe(i) {
9459 seq_printf(m, "Pipe [%d]:\n", i);
9460 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9461 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9462 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9463 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9464 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9465 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9466 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9467 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9468
9469 seq_printf(m, "Plane [%d]:\n", i);
9470 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9471 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9472 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9473 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9474 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9475 if (INTEL_INFO(dev)->gen >= 4) {
9476 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9477 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9478 }
9479
9480 seq_printf(m, "Cursor [%d]:\n", i);
9481 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9482 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9483 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9484 }
9485 }
9486 #endif
Linux 2.6 libata-dev (mirror)