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wl18xx: implement hw op to read PG version
[linux-2.6/libata-dev.git] / drivers / net / wireless / ti / wl18xx / main.c
blob9aae0af25fefe95325fffab5ef610d1b9b2dff98
1 /*
2 * This file is part of wl18xx
3 *
4 * Copyright (C) 2011 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/ip.h>
25
26 #include "../wlcore/wlcore.h"
27 #include "../wlcore/debug.h"
28 #include "../wlcore/io.h"
29 #include "../wlcore/acx.h"
30 #include "../wlcore/tx.h"
31 #include "../wlcore/rx.h"
32 #include "../wlcore/io.h"
33 #include "../wlcore/boot.h"
34
35 #include "reg.h"
36 #include "conf.h"
37 #include "acx.h"
38 #include "tx.h"
39 #include "wl18xx.h"
40 #include "io.h"
41
42
43 #define WL18XX_RX_CHECKSUM_MASK 0x40
44
45 static char *ht_mode_param;
46 static char *board_type_param;
47
48 static const u32 wl18xx_board_type_to_scrpad2[NUM_BOARD_TYPES] = {
49 [BOARD_TYPE_FPGA_18XX] = SCR_PAD2_BOARD_TYPE_FPGA,
50 [BOARD_TYPE_HDK_18XX] = SCR_PAD2_BOARD_TYPE_HDK,
51 [BOARD_TYPE_DVP_EVB_18XX] = SCR_PAD2_BOARD_TYPE_DVP_EVB,
52 };
53
54 static const u8 wl18xx_rate_to_idx_2ghz[] = {
55 /* MCS rates are used only with 11n */
56 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
57 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
58 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
59 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
60 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
61 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
62 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
63 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
64 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
65 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
66 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
67 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
68 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
69 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
70 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
71 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
72
73 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
74 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
75 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
76 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
77
78 /* TI-specific rate */
79 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
80
81 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
82 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
83 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
84 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
85 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
86 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
87 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
88 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
89 };
90
91 static const u8 wl18xx_rate_to_idx_5ghz[] = {
92 /* MCS rates are used only with 11n */
93 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
94 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
95 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
96 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
97 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
98 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
99 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
100 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
101 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
102 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
103 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
104 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
105 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
106 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
107 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
108 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
109
110 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
111 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
112 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
113 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
114
115 /* TI-specific rate */
116 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
117
118 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
119 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
120 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
121 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
122 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
123 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
124 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
125 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
126 };
127
128 static const u8 *wl18xx_band_rate_to_idx[] = {
129 [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
130 [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
131 };
132
133 enum wl18xx_hw_rates {
134 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
135 WL18XX_CONF_HW_RXTX_RATE_MCS14,
136 WL18XX_CONF_HW_RXTX_RATE_MCS13,
137 WL18XX_CONF_HW_RXTX_RATE_MCS12,
138 WL18XX_CONF_HW_RXTX_RATE_MCS11,
139 WL18XX_CONF_HW_RXTX_RATE_MCS10,
140 WL18XX_CONF_HW_RXTX_RATE_MCS9,
141 WL18XX_CONF_HW_RXTX_RATE_MCS8,
142 WL18XX_CONF_HW_RXTX_RATE_MCS7,
143 WL18XX_CONF_HW_RXTX_RATE_MCS6,
144 WL18XX_CONF_HW_RXTX_RATE_MCS5,
145 WL18XX_CONF_HW_RXTX_RATE_MCS4,
146 WL18XX_CONF_HW_RXTX_RATE_MCS3,
147 WL18XX_CONF_HW_RXTX_RATE_MCS2,
148 WL18XX_CONF_HW_RXTX_RATE_MCS1,
149 WL18XX_CONF_HW_RXTX_RATE_MCS0,
150 WL18XX_CONF_HW_RXTX_RATE_54,
151 WL18XX_CONF_HW_RXTX_RATE_48,
152 WL18XX_CONF_HW_RXTX_RATE_36,
153 WL18XX_CONF_HW_RXTX_RATE_24,
154 WL18XX_CONF_HW_RXTX_RATE_22,
155 WL18XX_CONF_HW_RXTX_RATE_18,
156 WL18XX_CONF_HW_RXTX_RATE_12,
157 WL18XX_CONF_HW_RXTX_RATE_11,
158 WL18XX_CONF_HW_RXTX_RATE_9,
159 WL18XX_CONF_HW_RXTX_RATE_6,
160 WL18XX_CONF_HW_RXTX_RATE_5_5,
161 WL18XX_CONF_HW_RXTX_RATE_2,
162 WL18XX_CONF_HW_RXTX_RATE_1,
163 WL18XX_CONF_HW_RXTX_RATE_MAX,
164 };
165
166 static struct wlcore_conf wl18xx_conf = {
167 .sg = {
168 .params = {
169 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
170 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
171 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
172 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
173 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
174 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
175 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
176 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
177 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
178 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
179 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
180 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
181 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
182 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
183 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
184 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
185 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
186 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
187 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
188 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
189 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
190 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
191 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
192 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
193 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
194 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
195 /* active scan params */
196 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
197 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
198 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
199 /* passive scan params */
200 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
201 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
202 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
203 /* passive scan in dual antenna params */
204 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
205 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
206 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
207 /* general params */
208 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
209 [CONF_SG_ANTENNA_CONFIGURATION] = 0,
210 [CONF_SG_BEACON_MISS_PERCENT] = 60,
211 [CONF_SG_DHCP_TIME] = 5000,
212 [CONF_SG_RXT] = 1200,
213 [CONF_SG_TXT] = 1000,
214 [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
215 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
216 [CONF_SG_HV3_MAX_SERVED] = 6,
217 [CONF_SG_PS_POLL_TIMEOUT] = 10,
218 [CONF_SG_UPSD_TIMEOUT] = 10,
219 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
220 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
221 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
222 /* AP params */
223 [CONF_AP_BEACON_MISS_TX] = 3,
224 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
225 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
226 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
227 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
228 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
229 /* CTS Diluting params */
230 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
231 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
232 },
233 .state = CONF_SG_PROTECTIVE,
234 },
235 .rx = {
236 .rx_msdu_life_time = 512000,
237 .packet_detection_threshold = 0,
238 .ps_poll_timeout = 15,
239 .upsd_timeout = 15,
240 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
241 .rx_cca_threshold = 0,
242 .irq_blk_threshold = 0xFFFF,
243 .irq_pkt_threshold = 0,
244 .irq_timeout = 600,
245 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
246 },
247 .tx = {
248 .tx_energy_detection = 0,
249 .sta_rc_conf = {
250 .enabled_rates = 0,
251 .short_retry_limit = 10,
252 .long_retry_limit = 10,
253 .aflags = 0,
254 },
255 .ac_conf_count = 4,
256 .ac_conf = {
257 [CONF_TX_AC_BE] = {
258 .ac = CONF_TX_AC_BE,
259 .cw_min = 15,
260 .cw_max = 63,
261 .aifsn = 3,
262 .tx_op_limit = 0,
263 },
264 [CONF_TX_AC_BK] = {
265 .ac = CONF_TX_AC_BK,
266 .cw_min = 15,
267 .cw_max = 63,
268 .aifsn = 7,
269 .tx_op_limit = 0,
270 },
271 [CONF_TX_AC_VI] = {
272 .ac = CONF_TX_AC_VI,
273 .cw_min = 15,
274 .cw_max = 63,
275 .aifsn = CONF_TX_AIFS_PIFS,
276 .tx_op_limit = 3008,
277 },
278 [CONF_TX_AC_VO] = {
279 .ac = CONF_TX_AC_VO,
280 .cw_min = 15,
281 .cw_max = 63,
282 .aifsn = CONF_TX_AIFS_PIFS,
283 .tx_op_limit = 1504,
284 },
285 },
286 .max_tx_retries = 100,
287 .ap_aging_period = 300,
288 .tid_conf_count = 4,
289 .tid_conf = {
290 [CONF_TX_AC_BE] = {
291 .queue_id = CONF_TX_AC_BE,
292 .channel_type = CONF_CHANNEL_TYPE_EDCF,
293 .tsid = CONF_TX_AC_BE,
294 .ps_scheme = CONF_PS_SCHEME_LEGACY,
295 .ack_policy = CONF_ACK_POLICY_LEGACY,
296 .apsd_conf = {0, 0},
297 },
298 [CONF_TX_AC_BK] = {
299 .queue_id = CONF_TX_AC_BK,
300 .channel_type = CONF_CHANNEL_TYPE_EDCF,
301 .tsid = CONF_TX_AC_BK,
302 .ps_scheme = CONF_PS_SCHEME_LEGACY,
303 .ack_policy = CONF_ACK_POLICY_LEGACY,
304 .apsd_conf = {0, 0},
305 },
306 [CONF_TX_AC_VI] = {
307 .queue_id = CONF_TX_AC_VI,
308 .channel_type = CONF_CHANNEL_TYPE_EDCF,
309 .tsid = CONF_TX_AC_VI,
310 .ps_scheme = CONF_PS_SCHEME_LEGACY,
311 .ack_policy = CONF_ACK_POLICY_LEGACY,
312 .apsd_conf = {0, 0},
313 },
314 [CONF_TX_AC_VO] = {
315 .queue_id = CONF_TX_AC_VO,
316 .channel_type = CONF_CHANNEL_TYPE_EDCF,
317 .tsid = CONF_TX_AC_VO,
318 .ps_scheme = CONF_PS_SCHEME_LEGACY,
319 .ack_policy = CONF_ACK_POLICY_LEGACY,
320 .apsd_conf = {0, 0},
321 },
322 },
323 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
324 .tx_compl_timeout = 350,
325 .tx_compl_threshold = 10,
326 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
327 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
328 .tmpl_short_retry_limit = 10,
329 .tmpl_long_retry_limit = 10,
330 .tx_watchdog_timeout = 5000,
331 },
332 .conn = {
333 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
334 .listen_interval = 1,
335 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
336 .suspend_listen_interval = 3,
337 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
338 .bcn_filt_ie_count = 2,
339 .bcn_filt_ie = {
340 [0] = {
341 .ie = WLAN_EID_CHANNEL_SWITCH,
342 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
343 },
344 [1] = {
345 .ie = WLAN_EID_HT_OPERATION,
346 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
347 },
348 },
349 .synch_fail_thold = 10,
350 .bss_lose_timeout = 100,
351 .beacon_rx_timeout = 10000,
352 .broadcast_timeout = 20000,
353 .rx_broadcast_in_ps = 1,
354 .ps_poll_threshold = 10,
355 .bet_enable = CONF_BET_MODE_ENABLE,
356 .bet_max_consecutive = 50,
357 .psm_entry_retries = 8,
358 .psm_exit_retries = 16,
359 .psm_entry_nullfunc_retries = 3,
360 .dynamic_ps_timeout = 40,
361 .forced_ps = false,
362 .keep_alive_interval = 55000,
363 .max_listen_interval = 20,
364 },
365 .itrim = {
366 .enable = false,
367 .timeout = 50000,
368 },
369 .pm_config = {
370 .host_clk_settling_time = 5000,
371 .host_fast_wakeup_support = false
372 },
373 .roam_trigger = {
374 .trigger_pacing = 1,
375 .avg_weight_rssi_beacon = 20,
376 .avg_weight_rssi_data = 10,
377 .avg_weight_snr_beacon = 20,
378 .avg_weight_snr_data = 10,
379 },
380 .scan = {
381 .min_dwell_time_active = 7500,
382 .max_dwell_time_active = 30000,
383 .min_dwell_time_passive = 100000,
384 .max_dwell_time_passive = 100000,
385 .num_probe_reqs = 2,
386 .split_scan_timeout = 50000,
387 },
388 .sched_scan = {
389 /*
390 * Values are in TU/1000 but since sched scan FW command
391 * params are in TUs rounding up may occur.
392 */
393 .base_dwell_time = 7500,
394 .max_dwell_time_delta = 22500,
395 /* based on 250bits per probe @1Mbps */
396 .dwell_time_delta_per_probe = 2000,
397 /* based on 250bits per probe @6Mbps (plus a bit more) */
398 .dwell_time_delta_per_probe_5 = 350,
399 .dwell_time_passive = 100000,
400 .dwell_time_dfs = 150000,
401 .num_probe_reqs = 2,
402 .rssi_threshold = -90,
403 .snr_threshold = 0,
404 },
405 .ht = {
406 .rx_ba_win_size = 10,
407 .tx_ba_win_size = 10,
408 .inactivity_timeout = 10000,
409 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
410 },
411 .mem = {
412 .num_stations = 1,
413 .ssid_profiles = 1,
414 .rx_block_num = 40,
415 .tx_min_block_num = 40,
416 .dynamic_memory = 1,
417 .min_req_tx_blocks = 45,
418 .min_req_rx_blocks = 22,
419 .tx_min = 27,
420 },
421 .fm_coex = {
422 .enable = true,
423 .swallow_period = 5,
424 .n_divider_fref_set_1 = 0xff, /* default */
425 .n_divider_fref_set_2 = 12,
426 .m_divider_fref_set_1 = 148,
427 .m_divider_fref_set_2 = 0xffff, /* default */
428 .coex_pll_stabilization_time = 0xffffffff, /* default */
429 .ldo_stabilization_time = 0xffff, /* default */
430 .fm_disturbed_band_margin = 0xff, /* default */
431 .swallow_clk_diff = 0xff, /* default */
432 },
433 .rx_streaming = {
434 .duration = 150,
435 .queues = 0x1,
436 .interval = 20,
437 .always = 0,
438 },
439 .fwlog = {
440 .mode = WL12XX_FWLOG_ON_DEMAND,
441 .mem_blocks = 2,
442 .severity = 0,
443 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
444 .output = WL12XX_FWLOG_OUTPUT_HOST,
445 .threshold = 0,
446 },
447 .rate = {
448 .rate_retry_score = 32000,
449 .per_add = 8192,
450 .per_th1 = 2048,
451 .per_th2 = 4096,
452 .max_per = 8100,
453 .inverse_curiosity_factor = 5,
454 .tx_fail_low_th = 4,
455 .tx_fail_high_th = 10,
456 .per_alpha_shift = 4,
457 .per_add_shift = 13,
458 .per_beta1_shift = 10,
459 .per_beta2_shift = 8,
460 .rate_check_up = 2,
461 .rate_check_down = 12,
462 .rate_retry_policy = {
463 0x00, 0x00, 0x00, 0x00, 0x00,
464 0x00, 0x00, 0x00, 0x00, 0x00,
465 0x00, 0x00, 0x00,
466 },
467 },
468 .hangover = {
469 .recover_time = 0,
470 .hangover_period = 20,
471 .dynamic_mode = 1,
472 .early_termination_mode = 1,
473 .max_period = 20,
474 .min_period = 1,
475 .increase_delta = 1,
476 .decrease_delta = 2,
477 .quiet_time = 4,
478 .increase_time = 1,
479 .window_size = 16,
480 },
481 };
482
483 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
484 .phy = {
485 .phy_standalone = 0x00,
486 .primary_clock_setting_time = 0x05,
487 .clock_valid_on_wake_up = 0x00,
488 .secondary_clock_setting_time = 0x05,
489 .rdl = 0x01,
490 .auto_detect = 0x00,
491 .dedicated_fem = FEM_NONE,
492 .low_band_component = COMPONENT_2_WAY_SWITCH,
493 .low_band_component_type = 0x05,
494 .high_band_component = COMPONENT_2_WAY_SWITCH,
495 .high_band_component_type = 0x09,
496 .number_of_assembled_ant2_4 = 0x01,
497 .number_of_assembled_ant5 = 0x01,
498 .external_pa_dc2dc = 0x00,
499 .tcxo_ldo_voltage = 0x00,
500 .xtal_itrim_val = 0x04,
501 .srf_state = 0x00,
502 .io_configuration = 0x01,
503 .sdio_configuration = 0x00,
504 .settings = 0x00,
505 .enable_clpc = 0x00,
506 .enable_tx_low_pwr_on_siso_rdl = 0x00,
507 .rx_profile = 0x00,
508 },
509 };
510
511 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
512 [PART_TOP_PRCM_ELP_SOC] = {
513 .mem = { .start = 0x00A02000, .size = 0x00010000 },
514 .reg = { .start = 0x00807000, .size = 0x00005000 },
515 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },
516 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
517 },
518 [PART_DOWN] = {
519 .mem = { .start = 0x00000000, .size = 0x00014000 },
520 .reg = { .start = 0x00810000, .size = 0x0000BFFF },
521 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
522 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
523 },
524 [PART_BOOT] = {
525 .mem = { .start = 0x00700000, .size = 0x0000030c },
526 .reg = { .start = 0x00802000, .size = 0x00014578 },
527 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
528 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
529 },
530 [PART_WORK] = {
531 .mem = { .start = 0x00800000, .size = 0x000050FC },
532 .reg = { .start = 0x00B00404, .size = 0x00001000 },
533 .mem2 = { .start = 0x00C00000, .size = 0x00000400 },
534 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
535 },
536 [PART_PHY_INIT] = {
537 /* TODO: use the phy_conf struct size here */
538 .mem = { .start = 0x80926000, .size = 252 },
539 .reg = { .start = 0x00000000, .size = 0x00000000 },
540 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
541 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
542 },
543 };
544
545 static const int wl18xx_rtable[REG_TABLE_LEN] = {
546 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
547 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
548 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
549 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
550 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
551 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
552 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
553 [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4,
554 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
555 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
556
557 /* data access memory addresses, used with partition translation */
558 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
559 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
560
561 /* raw data access memory addresses */
562 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
563 };
564
565 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
566 [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true },
567 [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true },
568 [CLOCK_CONFIG_16_8_M] = { 7, 100, 0, 0, false },
569 [CLOCK_CONFIG_19_2_M] = { 8, 100, 0, 0, false },
570 [CLOCK_CONFIG_26_M] = { 13, 120, 0, 0, false },
571 [CLOCK_CONFIG_32_736_M] = { 9, 132, 3751, 4, true },
572 [CLOCK_CONFIG_33_6_M] = { 7, 100, 0, 0, false },
573 [CLOCK_CONFIG_38_468_M] = { 8, 100, 0, 0, false },
574 [CLOCK_CONFIG_52_M] = { 13, 120, 0, 0, false },
575 };
576
577 /* TODO: maybe move to a new header file? */
578 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin"
579
580 static int wl18xx_identify_chip(struct wl1271 *wl)
581 {
582 int ret = 0;
583
584 switch (wl->chip.id) {
585 case CHIP_ID_185x_PG10:
586 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)",
587 wl->chip.id);
588 wl->sr_fw_name = WL18XX_FW_NAME;
589 wl->quirks |= WLCORE_QUIRK_NO_ELP |
590 WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
591 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;
592
593 /* TODO: need to blocksize alignment for RX/TX separately? */
594 break;
595 default:
596 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
597 ret = -ENODEV;
598 goto out;
599 }
600
601 out:
602 return ret;
603 }
604
605 static void wl18xx_set_clk(struct wl1271 *wl)
606 {
607 struct wl18xx_priv *priv = wl->priv;
608 u32 clk_freq;
609
610 /* write the translated board type to SCR_PAD2 */
611 wl1271_write32(wl, WL18XX_SCR_PAD2,
612 wl18xx_board_type_to_scrpad2[priv->board_type]);
613
614 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
615
616 /* TODO: PG2: apparently we need to read the clk type */
617
618 clk_freq = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT);
619 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
620 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
621 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
622 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
623
624 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, wl18xx_clk_table[clk_freq].n);
625 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M, wl18xx_clk_table[clk_freq].m);
626
627 if (wl18xx_clk_table[clk_freq].swallow) {
628 /* first the 16 lower bits */
629 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
630 wl18xx_clk_table[clk_freq].q &
631 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
632 /* then the 16 higher bits, masked out */
633 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
634 (wl18xx_clk_table[clk_freq].q >> 16) &
635 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
636
637 /* first the 16 lower bits */
638 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
639 wl18xx_clk_table[clk_freq].p &
640 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
641 /* then the 16 higher bits, masked out */
642 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
643 (wl18xx_clk_table[clk_freq].p >> 16) &
644 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
645 } else {
646 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
647 PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
648 }
649 }
650
651 static void wl18xx_boot_soft_reset(struct wl1271 *wl)
652 {
653 /* disable Rx/Tx */
654 wl1271_write32(wl, WL18XX_ENABLE, 0x0);
655
656 /* disable auto calibration on start*/
657 wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff);
658 }
659
660 static int wl18xx_pre_boot(struct wl1271 *wl)
661 {
662 wl18xx_set_clk(wl);
663
664 /* Continue the ELP wake up sequence */
665 wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
666 udelay(500);
667
668 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
669
670 /* Disable interrupts */
671 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
672
673 wl18xx_boot_soft_reset(wl);
674
675 return 0;
676 }
677
678 static void wl18xx_pre_upload(struct wl1271 *wl)
679 {
680 u32 tmp;
681
682 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
683
684 /* TODO: check if this is all needed */
685 wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
686
687 tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
688
689 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
690
691 tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
692 }
693
694 static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
695 {
696 struct wl18xx_priv *priv = wl->priv;
697 struct wl18xx_conf_phy *phy = &priv->conf.phy;
698 struct wl18xx_mac_and_phy_params params;
699
700 memset(&params, 0, sizeof(params));
701
702 params.phy_standalone = phy->phy_standalone;
703 params.rdl = phy->rdl;
704 params.enable_clpc = phy->enable_clpc;
705 params.enable_tx_low_pwr_on_siso_rdl =
706 phy->enable_tx_low_pwr_on_siso_rdl;
707 params.auto_detect = phy->auto_detect;
708 params.dedicated_fem = phy->dedicated_fem;
709 params.low_band_component = phy->low_band_component;
710 params.low_band_component_type =
711 phy->low_band_component_type;
712 params.high_band_component = phy->high_band_component;
713 params.high_band_component_type =
714 phy->high_band_component_type;
715 params.number_of_assembled_ant2_4 =
716 phy->number_of_assembled_ant2_4;
717 params.number_of_assembled_ant5 =
718 phy->number_of_assembled_ant5;
719 params.external_pa_dc2dc = phy->external_pa_dc2dc;
720 params.tcxo_ldo_voltage = phy->tcxo_ldo_voltage;
721 params.xtal_itrim_val = phy->xtal_itrim_val;
722 params.srf_state = phy->srf_state;
723 params.io_configuration = phy->io_configuration;
724 params.sdio_configuration = phy->sdio_configuration;
725 params.settings = phy->settings;
726 params.rx_profile = phy->rx_profile;
727 params.primary_clock_setting_time =
728 phy->primary_clock_setting_time;
729 params.clock_valid_on_wake_up =
730 phy->clock_valid_on_wake_up;
731 params.secondary_clock_setting_time =
732 phy->secondary_clock_setting_time;
733
734 params.board_type = priv->board_type;
735
736 wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
737 wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&params,
738 sizeof(params), false);
739 }
740
741 static void wl18xx_enable_interrupts(struct wl1271 *wl)
742 {
743 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
744
745 wlcore_enable_interrupts(wl);
746 wlcore_write_reg(wl, REG_INTERRUPT_MASK,
747 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
748 }
749
750 static int wl18xx_boot(struct wl1271 *wl)
751 {
752 int ret;
753
754 ret = wl18xx_pre_boot(wl);
755 if (ret < 0)
756 goto out;
757
758 ret = wlcore_boot_upload_nvs(wl);
759 if (ret < 0)
760 goto out;
761
762 wl18xx_pre_upload(wl);
763
764 ret = wlcore_boot_upload_firmware(wl);
765 if (ret < 0)
766 goto out;
767
768 wl18xx_set_mac_and_phy(wl);
769
770 ret = wlcore_boot_run_firmware(wl);
771 if (ret < 0)
772 goto out;
773
774 wl18xx_enable_interrupts(wl);
775
776 out:
777 return ret;
778 }
779
780 static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
781 void *buf, size_t len)
782 {
783 struct wl18xx_priv *priv = wl->priv;
784
785 memcpy(priv->cmd_buf, buf, len);
786 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
787
788 wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE,
789 false);
790 }
791
792 static void wl18xx_ack_event(struct wl1271 *wl)
793 {
794 wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK);
795 }
796
797 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
798 {
799 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
800 return (len + blk_size - 1) / blk_size + spare_blks;
801 }
802
803 static void
804 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
805 u32 blks, u32 spare_blks)
806 {
807 desc->wl18xx_mem.total_mem_blocks = blks;
808 desc->wl18xx_mem.reserved = 0;
809 }
810
811 static void
812 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
813 struct sk_buff *skb)
814 {
815 desc->length = cpu_to_le16(skb->len);
816
817 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
818 "len: %d life: %d mem: %d", desc->hlid,
819 le16_to_cpu(desc->length),
820 le16_to_cpu(desc->life_time),
821 desc->wl18xx_mem.total_mem_blocks);
822 }
823
824 static enum wl_rx_buf_align
825 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
826 {
827 if (rx_desc & RX_BUF_PADDED_PAYLOAD)
828 return WLCORE_RX_BUF_PADDED;
829
830 return WLCORE_RX_BUF_ALIGNED;
831 }
832
833 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
834 u32 data_len)
835 {
836 struct wl1271_rx_descriptor *desc = rx_data;
837
838 /* invalid packet */
839 if (data_len < sizeof(*desc))
840 return 0;
841
842 return data_len - sizeof(*desc);
843 }
844
845 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
846 {
847 wl18xx_tx_immediate_complete(wl);
848 }
849
850 static int wl18xx_hw_init(struct wl1271 *wl)
851 {
852 int ret;
853 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
854 HOST_IF_CFG_ADD_RX_ALIGNMENT;
855
856 u32 sdio_align_size = 0;
857
858 /* Enable Tx SDIO padding */
859 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
860 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
861 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
862 }
863
864 /* Enable Rx SDIO padding */
865 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
866 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
867 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
868 }
869
870 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
871 sdio_align_size,
872 WL18XX_TX_HW_BLOCK_SPARE,
873 WL18XX_HOST_IF_LEN_SIZE_FIELD);
874 if (ret < 0)
875 return ret;
876
877 ret = wl18xx_acx_set_checksum_state(wl);
878 if (ret != 0)
879 return ret;
880
881 return ret;
882 }
883
884 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
885 struct wl1271_tx_hw_descr *desc,
886 struct sk_buff *skb)
887 {
888 u32 ip_hdr_offset;
889 struct iphdr *ip_hdr;
890
891 if (skb->ip_summed != CHECKSUM_PARTIAL) {
892 desc->wl18xx_checksum_data = 0;
893 return;
894 }
895
896 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
897 if (WARN_ON(ip_hdr_offset >= (1<<7))) {
898 desc->wl18xx_checksum_data = 0;
899 return;
900 }
901
902 desc->wl18xx_checksum_data = ip_hdr_offset << 1;
903
904 /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */
905 ip_hdr = (void *)skb_network_header(skb);
906 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
907 }
908
909 static void wl18xx_set_rx_csum(struct wl1271 *wl,
910 struct wl1271_rx_descriptor *desc,
911 struct sk_buff *skb)
912 {
913 if (desc->status & WL18XX_RX_CHECKSUM_MASK)
914 skb->ip_summed = CHECKSUM_UNNECESSARY;
915 }
916
917 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
918 struct wl12xx_vif *wlvif)
919 {
920 u32 hw_rate_set = wlvif->rate_set;
921
922 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
923 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
924 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
925 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
926
927 /* we don't support MIMO in wide-channel mode */
928 hw_rate_set &= ~CONF_TX_MIMO_RATES;
929 }
930
931 return hw_rate_set;
932 }
933
934 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
935 struct wl12xx_vif *wlvif)
936 {
937 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
938 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
939 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
940 return CONF_TX_RATE_USE_WIDE_CHAN;
941 } else {
942 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
943 return CONF_TX_MIMO_RATES;
944 }
945 }
946
947 static s8 wl18xx_get_pg_ver(struct wl1271 *wl)
948 {
949 u32 fuse;
950
951 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
952
953 fuse = wl1271_read32(wl, WL18XX_REG_FUSE_DATA_1_3);
954 fuse = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
955
956 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
957
958 return (s8)fuse;
959 }
960
961 static void wl18xx_conf_init(struct wl1271 *wl)
962 {
963 struct wl18xx_priv *priv = wl->priv;
964
965 /* apply driver default configuration */
966 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
967
968 /* apply default private configuration */
969 memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
970 }
971
972 static struct wlcore_ops wl18xx_ops = {
973 .identify_chip = wl18xx_identify_chip,
974 .boot = wl18xx_boot,
975 .trigger_cmd = wl18xx_trigger_cmd,
976 .ack_event = wl18xx_ack_event,
977 .calc_tx_blocks = wl18xx_calc_tx_blocks,
978 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
979 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
980 .get_rx_buf_align = wl18xx_get_rx_buf_align,
981 .get_rx_packet_len = wl18xx_get_rx_packet_len,
982 .tx_immediate_compl = wl18xx_tx_immediate_completion,
983 .tx_delayed_compl = NULL,
984 .hw_init = wl18xx_hw_init,
985 .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
986 .get_pg_ver = wl18xx_get_pg_ver,
987 .set_rx_csum = wl18xx_set_rx_csum,
988 .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
989 .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
990 };
991
992 /* HT cap appropriate for wide channels */
993 static struct ieee80211_sta_ht_cap wl18xx_ht_cap = {
994 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
995 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
996 .ht_supported = true,
997 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
998 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
999 .mcs = {
1000 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1001 .rx_highest = cpu_to_le16(150),
1002 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1003 },
1004 };
1005
1006 /* HT cap appropriate for MIMO rates in 20mhz channel */
1007 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap = {
1008 .cap = IEEE80211_HT_CAP_SGI_20,
1009 .ht_supported = true,
1010 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1011 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1012 .mcs = {
1013 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1014 .rx_highest = cpu_to_le16(144),
1015 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1016 },
1017 };
1018
1019 int __devinit wl18xx_probe(struct platform_device *pdev)
1020 {
1021 struct wl1271 *wl;
1022 struct ieee80211_hw *hw;
1023 struct wl18xx_priv *priv;
1024
1025 hw = wlcore_alloc_hw(sizeof(*priv));
1026 if (IS_ERR(hw)) {
1027 wl1271_error("can't allocate hw");
1028 return PTR_ERR(hw);
1029 }
1030
1031 wl = hw->priv;
1032 priv = wl->priv;
1033 wl->ops = &wl18xx_ops;
1034 wl->ptable = wl18xx_ptable;
1035 wl->rtable = wl18xx_rtable;
1036 wl->num_tx_desc = 32;
1037 wl->normal_tx_spare = WL18XX_TX_HW_BLOCK_SPARE;
1038 wl->gem_tx_spare = WL18XX_TX_HW_GEM_BLOCK_SPARE;
1039 wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1040 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1041 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1042 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1043 memcpy(&wl->ht_cap, &wl18xx_ht_cap, sizeof(wl18xx_ht_cap));
1044 if (ht_mode_param && !strcmp(ht_mode_param, "mimo"))
1045 memcpy(&wl->ht_cap, &wl18xx_mimo_ht_cap,
1046 sizeof(wl18xx_mimo_ht_cap));
1047
1048 if (!board_type_param) {
1049 board_type_param = kstrdup("dvp_evb", GFP_KERNEL);
1050 priv->board_type = BOARD_TYPE_DVP_EVB_18XX;
1051 } else {
1052 if (!strcmp(board_type_param, "fpga"))
1053 priv->board_type = BOARD_TYPE_FPGA_18XX;
1054 else if (!strcmp(board_type_param, "hdk"))
1055 priv->board_type = BOARD_TYPE_HDK_18XX;
1056 else if (!strcmp(board_type_param, "dvp_evb"))
1057 priv->board_type = BOARD_TYPE_DVP_EVB_18XX;
1058 else {
1059 wl1271_error("invalid board type '%s'",
1060 board_type_param);
1061 wlcore_free_hw(wl);
1062 return -EINVAL;
1063 }
1064 }
1065
1066 wl18xx_conf_init(wl);
1067
1068 return wlcore_probe(wl, pdev);
1069 }
1070
1071 static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
1072 { "wl18xx", 0 },
1073 { } /* Terminating Entry */
1074 };
1075 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1076
1077 static struct platform_driver wl18xx_driver = {
1078 .probe = wl18xx_probe,
1079 .remove = __devexit_p(wlcore_remove),
1080 .id_table = wl18xx_id_table,
1081 .driver = {
1082 .name = "wl18xx_driver",
1083 .owner = THIS_MODULE,
1084 }
1085 };
1086
1087 static int __init wl18xx_init(void)
1088 {
1089 return platform_driver_register(&wl18xx_driver);
1090 }
1091 module_init(wl18xx_init);
1092
1093 static void __exit wl18xx_exit(void)
1094 {
1095 platform_driver_unregister(&wl18xx_driver);
1096 }
1097 module_exit(wl18xx_exit);
1098
1099 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1100 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or mimo");
1101
1102 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1103 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk or dvp_evb (default)");
1104
1105 MODULE_LICENSE("GPL v2");
1106 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1107 MODULE_FIRMWARE(WL18XX_FW_NAME);
Linux 2.6 libata-dev (mirror)