3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
25 #include <linux/delay.h>
26 #include <linux/types.h>
30 #include "tables_nphy.h"
40 struct nphy_iqcal_params
{
58 void b43_nphy_set_rxantenna(struct b43_wldev
*dev
, int antenna
)
62 static void b43_nphy_op_adjust_txpower(struct b43_wldev
*dev
)
66 static enum b43_txpwr_result
b43_nphy_op_recalc_txpower(struct b43_wldev
*dev
,
69 return B43_TXPWR_RES_DONE
;
72 static void b43_chantab_radio_upload(struct b43_wldev
*dev
,
73 const struct b43_nphy_channeltab_entry
*e
)
75 b43_radio_write16(dev
, B2055_PLL_REF
, e
->radio_pll_ref
);
76 b43_radio_write16(dev
, B2055_RF_PLLMOD0
, e
->radio_rf_pllmod0
);
77 b43_radio_write16(dev
, B2055_RF_PLLMOD1
, e
->radio_rf_pllmod1
);
78 b43_radio_write16(dev
, B2055_VCO_CAPTAIL
, e
->radio_vco_captail
);
79 b43_radio_write16(dev
, B2055_VCO_CAL1
, e
->radio_vco_cal1
);
80 b43_radio_write16(dev
, B2055_VCO_CAL2
, e
->radio_vco_cal2
);
81 b43_radio_write16(dev
, B2055_PLL_LFC1
, e
->radio_pll_lfc1
);
82 b43_radio_write16(dev
, B2055_PLL_LFR1
, e
->radio_pll_lfr1
);
83 b43_radio_write16(dev
, B2055_PLL_LFC2
, e
->radio_pll_lfc2
);
84 b43_radio_write16(dev
, B2055_LGBUF_CENBUF
, e
->radio_lgbuf_cenbuf
);
85 b43_radio_write16(dev
, B2055_LGEN_TUNE1
, e
->radio_lgen_tune1
);
86 b43_radio_write16(dev
, B2055_LGEN_TUNE2
, e
->radio_lgen_tune2
);
87 b43_radio_write16(dev
, B2055_C1_LGBUF_ATUNE
, e
->radio_c1_lgbuf_atune
);
88 b43_radio_write16(dev
, B2055_C1_LGBUF_GTUNE
, e
->radio_c1_lgbuf_gtune
);
89 b43_radio_write16(dev
, B2055_C1_RX_RFR1
, e
->radio_c1_rx_rfr1
);
90 b43_radio_write16(dev
, B2055_C1_TX_PGAPADTN
, e
->radio_c1_tx_pgapadtn
);
91 b43_radio_write16(dev
, B2055_C1_TX_MXBGTRIM
, e
->radio_c1_tx_mxbgtrim
);
92 b43_radio_write16(dev
, B2055_C2_LGBUF_ATUNE
, e
->radio_c2_lgbuf_atune
);
93 b43_radio_write16(dev
, B2055_C2_LGBUF_GTUNE
, e
->radio_c2_lgbuf_gtune
);
94 b43_radio_write16(dev
, B2055_C2_RX_RFR1
, e
->radio_c2_rx_rfr1
);
95 b43_radio_write16(dev
, B2055_C2_TX_PGAPADTN
, e
->radio_c2_tx_pgapadtn
);
96 b43_radio_write16(dev
, B2055_C2_TX_MXBGTRIM
, e
->radio_c2_tx_mxbgtrim
);
99 static void b43_chantab_phy_upload(struct b43_wldev
*dev
,
100 const struct b43_nphy_channeltab_entry
*e
)
102 b43_phy_write(dev
, B43_NPHY_BW1A
, e
->phy_bw1a
);
103 b43_phy_write(dev
, B43_NPHY_BW2
, e
->phy_bw2
);
104 b43_phy_write(dev
, B43_NPHY_BW3
, e
->phy_bw3
);
105 b43_phy_write(dev
, B43_NPHY_BW4
, e
->phy_bw4
);
106 b43_phy_write(dev
, B43_NPHY_BW5
, e
->phy_bw5
);
107 b43_phy_write(dev
, B43_NPHY_BW6
, e
->phy_bw6
);
110 static void b43_nphy_tx_power_fix(struct b43_wldev
*dev
)
115 /* Tune the hardware to a new channel. */
116 static int nphy_channel_switch(struct b43_wldev
*dev
, unsigned int channel
)
118 const struct b43_nphy_channeltab_entry
*tabent
;
120 tabent
= b43_nphy_get_chantabent(dev
, channel
);
124 //FIXME enable/disable band select upper20 in RXCTL
125 if (0 /*FIXME 5Ghz*/)
126 b43_radio_maskset(dev
, B2055_MASTER1
, 0xFF8F, 0x20);
128 b43_radio_maskset(dev
, B2055_MASTER1
, 0xFF8F, 0x50);
129 b43_chantab_radio_upload(dev
, tabent
);
131 b43_radio_write16(dev
, B2055_VCO_CAL10
, 5);
132 b43_radio_write16(dev
, B2055_VCO_CAL10
, 45);
133 b43_radio_write16(dev
, B2055_VCO_CAL10
, 65);
135 if (0 /*FIXME 5Ghz*/)
136 b43_phy_set(dev
, B43_NPHY_BANDCTL
, B43_NPHY_BANDCTL_5GHZ
);
138 b43_phy_mask(dev
, B43_NPHY_BANDCTL
, ~B43_NPHY_BANDCTL_5GHZ
);
139 b43_chantab_phy_upload(dev
, tabent
);
140 b43_nphy_tx_power_fix(dev
);
145 static void b43_radio_init2055_pre(struct b43_wldev
*dev
)
147 b43_phy_mask(dev
, B43_NPHY_RFCTL_CMD
,
148 ~B43_NPHY_RFCTL_CMD_PORFORCE
);
149 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
,
150 B43_NPHY_RFCTL_CMD_CHIP0PU
|
151 B43_NPHY_RFCTL_CMD_OEPORFORCE
);
152 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
,
153 B43_NPHY_RFCTL_CMD_PORFORCE
);
156 static void b43_radio_init2055_post(struct b43_wldev
*dev
)
158 struct ssb_sprom
*sprom
= &(dev
->dev
->bus
->sprom
);
159 struct ssb_boardinfo
*binfo
= &(dev
->dev
->bus
->boardinfo
);
163 b43_radio_mask(dev
, B2055_MASTER1
, 0xFFF3);
165 if ((sprom
->revision
!= 4) ||
166 !(sprom
->boardflags_hi
& B43_BFH_RSSIINV
)) {
167 if ((binfo
->vendor
!= PCI_VENDOR_ID_BROADCOM
) ||
168 (binfo
->type
!= 0x46D) ||
169 (binfo
->rev
< 0x41)) {
170 b43_radio_mask(dev
, B2055_C1_RX_BB_REG
, 0x7F);
171 b43_radio_mask(dev
, B2055_C1_RX_BB_REG
, 0x7F);
175 b43_radio_maskset(dev
, B2055_RRCCAL_NOPTSEL
, 0x3F, 0x2C);
177 b43_radio_write16(dev
, B2055_CAL_MISC
, 0x3C);
179 b43_radio_mask(dev
, B2055_CAL_MISC
, 0xFFBE);
181 b43_radio_set(dev
, B2055_CAL_LPOCTL
, 0x80);
183 b43_radio_set(dev
, B2055_CAL_MISC
, 0x1);
185 b43_radio_set(dev
, B2055_CAL_MISC
, 0x40);
187 for (i
= 0; i
< 100; i
++) {
188 val
= b43_radio_read16(dev
, B2055_CAL_COUT2
);
194 b43_radio_mask(dev
, B2055_CAL_LPOCTL
, 0xFF7F);
196 nphy_channel_switch(dev
, dev
->phy
.channel
);
197 b43_radio_write16(dev
, B2055_C1_RX_BB_LPF
, 0x9);
198 b43_radio_write16(dev
, B2055_C2_RX_BB_LPF
, 0x9);
199 b43_radio_write16(dev
, B2055_C1_RX_BB_MIDACHP
, 0x83);
200 b43_radio_write16(dev
, B2055_C2_RX_BB_MIDACHP
, 0x83);
203 /* Initialize a Broadcom 2055 N-radio */
204 static void b43_radio_init2055(struct b43_wldev
*dev
)
206 b43_radio_init2055_pre(dev
);
207 if (b43_status(dev
) < B43_STAT_INITIALIZED
)
208 b2055_upload_inittab(dev
, 0, 1);
210 b2055_upload_inittab(dev
, 0/*FIXME on 5ghz band*/, 0);
211 b43_radio_init2055_post(dev
);
214 void b43_nphy_radio_turn_on(struct b43_wldev
*dev
)
216 b43_radio_init2055(dev
);
219 void b43_nphy_radio_turn_off(struct b43_wldev
*dev
)
221 b43_phy_mask(dev
, B43_NPHY_RFCTL_CMD
,
222 ~B43_NPHY_RFCTL_CMD_EN
);
226 * Upload the N-PHY tables.
227 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
229 static void b43_nphy_tables_init(struct b43_wldev
*dev
)
231 if (dev
->phy
.rev
< 3)
232 b43_nphy_rev0_1_2_tables_init(dev
);
234 b43_nphy_rev3plus_tables_init(dev
);
237 static void b43_nphy_workarounds(struct b43_wldev
*dev
)
239 struct b43_phy
*phy
= &dev
->phy
;
242 b43_phy_set(dev
, B43_NPHY_IQFLIP
,
243 B43_NPHY_IQFLIP_ADC1
| B43_NPHY_IQFLIP_ADC2
);
244 if (1 /* FIXME band is 2.4GHz */) {
245 b43_phy_set(dev
, B43_NPHY_CLASSCTL
,
246 B43_NPHY_CLASSCTL_CCKEN
);
248 b43_phy_mask(dev
, B43_NPHY_CLASSCTL
,
249 ~B43_NPHY_CLASSCTL_CCKEN
);
251 b43_radio_set(dev
, B2055_C1_TX_RF_SPARE
, 0x8);
252 b43_phy_write(dev
, B43_NPHY_TXFRAMEDELAY
, 8);
254 /* Fixup some tables */
255 b43_ntab_write(dev
, B43_NTAB16(8, 0x00), 0xA);
256 b43_ntab_write(dev
, B43_NTAB16(8, 0x10), 0xA);
257 b43_ntab_write(dev
, B43_NTAB16(8, 0x02), 0xCDAA);
258 b43_ntab_write(dev
, B43_NTAB16(8, 0x12), 0xCDAA);
259 b43_ntab_write(dev
, B43_NTAB16(8, 0x08), 0);
260 b43_ntab_write(dev
, B43_NTAB16(8, 0x18), 0);
261 b43_ntab_write(dev
, B43_NTAB16(8, 0x07), 0x7AAB);
262 b43_ntab_write(dev
, B43_NTAB16(8, 0x17), 0x7AAB);
263 b43_ntab_write(dev
, B43_NTAB16(8, 0x06), 0x800);
264 b43_ntab_write(dev
, B43_NTAB16(8, 0x16), 0x800);
266 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_LO1
, 0x2D8);
267 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP1
, 0x301);
268 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_LO2
, 0x2D8);
269 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP2
, 0x301);
271 //TODO set RF sequence
273 /* Set narrowband clip threshold */
274 b43_phy_write(dev
, B43_NPHY_C1_NBCLIPTHRES
, 66);
275 b43_phy_write(dev
, B43_NPHY_C2_NBCLIPTHRES
, 66);
277 /* Set wideband clip 2 threshold */
278 b43_phy_maskset(dev
, B43_NPHY_C1_CLIPWBTHRES
,
279 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2
,
280 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT
);
281 b43_phy_maskset(dev
, B43_NPHY_C2_CLIPWBTHRES
,
282 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2
,
283 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT
);
285 /* Set Clip 2 detect */
286 b43_phy_set(dev
, B43_NPHY_C1_CGAINI
,
287 B43_NPHY_C1_CGAINI_CL2DETECT
);
288 b43_phy_set(dev
, B43_NPHY_C2_CGAINI
,
289 B43_NPHY_C2_CGAINI_CL2DETECT
);
292 /* Set dwell lengths */
293 b43_phy_write(dev
, B43_NPHY_CLIP1_NBDWELL_LEN
, 43);
294 b43_phy_write(dev
, B43_NPHY_CLIP2_NBDWELL_LEN
, 43);
295 b43_phy_write(dev
, B43_NPHY_W1CLIP1_DWELL_LEN
, 9);
296 b43_phy_write(dev
, B43_NPHY_W1CLIP2_DWELL_LEN
, 9);
298 /* Set gain backoff */
299 b43_phy_maskset(dev
, B43_NPHY_C1_CGAINI
,
300 ~B43_NPHY_C1_CGAINI_GAINBKOFF
,
301 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT
);
302 b43_phy_maskset(dev
, B43_NPHY_C2_CGAINI
,
303 ~B43_NPHY_C2_CGAINI_GAINBKOFF
,
304 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT
);
306 /* Set HPVGA2 index */
307 b43_phy_maskset(dev
, B43_NPHY_C1_INITGAIN
,
308 ~B43_NPHY_C1_INITGAIN_HPVGA2
,
309 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT
);
310 b43_phy_maskset(dev
, B43_NPHY_C2_INITGAIN
,
311 ~B43_NPHY_C2_INITGAIN_HPVGA2
,
312 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT
);
314 //FIXME verify that the specs really mean to use autoinc here.
315 for (i
= 0; i
< 3; i
++)
316 b43_ntab_write(dev
, B43_NTAB16(7, 0x106) + i
, 0x673);
319 /* Set minimum gain value */
320 b43_phy_maskset(dev
, B43_NPHY_C1_MINMAX_GAIN
,
321 ~B43_NPHY_C1_MINGAIN
,
322 23 << B43_NPHY_C1_MINGAIN_SHIFT
);
323 b43_phy_maskset(dev
, B43_NPHY_C2_MINMAX_GAIN
,
324 ~B43_NPHY_C2_MINGAIN
,
325 23 << B43_NPHY_C2_MINGAIN_SHIFT
);
328 b43_phy_mask(dev
, B43_NPHY_SCRAM_SIGCTL
,
329 ~B43_NPHY_SCRAM_SIGCTL_SCM
);
332 /* Set phase track alpha and beta */
333 b43_phy_write(dev
, B43_NPHY_PHASETR_A0
, 0x125);
334 b43_phy_write(dev
, B43_NPHY_PHASETR_A1
, 0x1B3);
335 b43_phy_write(dev
, B43_NPHY_PHASETR_A2
, 0x105);
336 b43_phy_write(dev
, B43_NPHY_PHASETR_B0
, 0x16E);
337 b43_phy_write(dev
, B43_NPHY_PHASETR_B1
, 0xCD);
338 b43_phy_write(dev
, B43_NPHY_PHASETR_B2
, 0x20);
341 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
342 static void b43_nphy_pa_override(struct b43_wldev
*dev
, bool enable
)
344 struct b43_phy_n
*nphy
= dev
->phy
.n
;
345 enum ieee80211_band band
;
349 nphy
->rfctrl_intc1_save
= b43_phy_read(dev
,
350 B43_NPHY_RFCTL_INTC1
);
351 nphy
->rfctrl_intc2_save
= b43_phy_read(dev
,
352 B43_NPHY_RFCTL_INTC2
);
353 band
= b43_current_band(dev
->wl
);
354 if (dev
->phy
.rev
>= 3) {
355 if (band
== IEEE80211_BAND_5GHZ
)
360 if (band
== IEEE80211_BAND_5GHZ
)
365 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, tmp
);
366 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, tmp
);
368 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
,
369 nphy
->rfctrl_intc1_save
);
370 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
,
371 nphy
->rfctrl_intc2_save
);
375 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
376 static void b43_nphy_tx_lp_fbw(struct b43_wldev
*dev
)
378 struct b43_phy_n
*nphy
= dev
->phy
.n
;
380 enum ieee80211_band band
= b43_current_band(dev
->wl
);
381 bool ipa
= (nphy
->ipa2g_on
&& band
== IEEE80211_BAND_2GHZ
) ||
382 (nphy
->ipa5g_on
&& band
== IEEE80211_BAND_5GHZ
);
384 if (dev
->phy
.rev
>= 3) {
387 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B32S2
,
388 (((((tmp
<< 3) | tmp
) << 3) | tmp
) << 3) | tmp
);
392 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B1S2
,
393 (((((tmp
<< 3) | tmp
) << 3) | tmp
) << 3) | tmp
);
397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
398 static void b43_nphy_bmac_clock_fgc(struct b43_wldev
*dev
, bool force
)
402 if (dev
->phy
.type
!= B43_PHYTYPE_N
)
405 tmslow
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
407 tmslow
|= SSB_TMSLOW_FGC
;
409 tmslow
&= ~SSB_TMSLOW_FGC
;
410 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
413 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
414 static void b43_nphy_reset_cca(struct b43_wldev
*dev
)
418 b43_nphy_bmac_clock_fgc(dev
, 1);
419 bbcfg
= b43_phy_read(dev
, B43_NPHY_BBCFG
);
420 b43_phy_write(dev
, B43_NPHY_BBCFG
, bbcfg
| B43_NPHY_BBCFG_RSTCCA
);
422 b43_phy_write(dev
, B43_NPHY_BBCFG
, bbcfg
& ~B43_NPHY_BBCFG_RSTCCA
);
423 b43_nphy_bmac_clock_fgc(dev
, 0);
424 /* TODO: N PHY Force RF Seq with argument 2 */
427 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
428 static void b43_nphy_update_mimo_config(struct b43_wldev
*dev
, s32 preamble
)
430 u16 mimocfg
= b43_phy_read(dev
, B43_NPHY_MIMOCFG
);
432 mimocfg
|= B43_NPHY_MIMOCFG_AUTO
;
434 mimocfg
|= B43_NPHY_MIMOCFG_GFMIX
;
436 mimocfg
&= ~B43_NPHY_MIMOCFG_GFMIX
;
438 b43_phy_write(dev
, B43_NPHY_MIMOCFG
, mimocfg
);
441 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
442 static void b43_nphy_rx_iq_est(struct b43_wldev
*dev
, struct nphy_iq_est
*est
,
443 u16 samps
, u8 time
, bool wait
)
448 b43_phy_write(dev
, B43_NPHY_IQEST_SAMCNT
, samps
);
449 b43_phy_maskset(dev
, B43_NPHY_IQEST_WT
, ~B43_NPHY_IQEST_WT_VAL
, time
);
451 b43_phy_set(dev
, B43_NPHY_IQEST_CMD
, B43_NPHY_IQEST_CMD_MODE
);
453 b43_phy_mask(dev
, B43_NPHY_IQEST_CMD
, ~B43_NPHY_IQEST_CMD_MODE
);
455 b43_phy_set(dev
, B43_NPHY_IQEST_CMD
, B43_NPHY_IQEST_CMD_START
);
457 for (i
= 1000; i
; i
--) {
458 tmp
= b43_phy_read(dev
, B43_NPHY_IQEST_CMD
);
459 if (!(tmp
& B43_NPHY_IQEST_CMD_START
)) {
460 est
->i0_pwr
= (b43_phy_read(dev
, B43_NPHY_IQEST_IPACC_HI0
) << 16) |
461 b43_phy_read(dev
, B43_NPHY_IQEST_IPACC_LO0
);
462 est
->q0_pwr
= (b43_phy_read(dev
, B43_NPHY_IQEST_QPACC_HI0
) << 16) |
463 b43_phy_read(dev
, B43_NPHY_IQEST_QPACC_LO0
);
464 est
->iq0_prod
= (b43_phy_read(dev
, B43_NPHY_IQEST_IQACC_HI0
) << 16) |
465 b43_phy_read(dev
, B43_NPHY_IQEST_IQACC_LO0
);
467 est
->i1_pwr
= (b43_phy_read(dev
, B43_NPHY_IQEST_IPACC_HI1
) << 16) |
468 b43_phy_read(dev
, B43_NPHY_IQEST_IPACC_LO1
);
469 est
->q1_pwr
= (b43_phy_read(dev
, B43_NPHY_IQEST_QPACC_HI1
) << 16) |
470 b43_phy_read(dev
, B43_NPHY_IQEST_QPACC_LO1
);
471 est
->iq1_prod
= (b43_phy_read(dev
, B43_NPHY_IQEST_IQACC_HI1
) << 16) |
472 b43_phy_read(dev
, B43_NPHY_IQEST_IQACC_LO1
);
477 memset(est
, 0, sizeof(*est
));
480 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
481 static void b43_nphy_rx_iq_coeffs(struct b43_wldev
*dev
, bool write
,
482 struct b43_phy_n_iq_comp
*pcomp
)
485 b43_phy_write(dev
, B43_NPHY_C1_RXIQ_COMPA0
, pcomp
->a0
);
486 b43_phy_write(dev
, B43_NPHY_C1_RXIQ_COMPB0
, pcomp
->b0
);
487 b43_phy_write(dev
, B43_NPHY_C2_RXIQ_COMPA1
, pcomp
->a1
);
488 b43_phy_write(dev
, B43_NPHY_C2_RXIQ_COMPB1
, pcomp
->b1
);
490 pcomp
->a0
= b43_phy_read(dev
, B43_NPHY_C1_RXIQ_COMPA0
);
491 pcomp
->b0
= b43_phy_read(dev
, B43_NPHY_C1_RXIQ_COMPB0
);
492 pcomp
->a1
= b43_phy_read(dev
, B43_NPHY_C2_RXIQ_COMPA1
);
493 pcomp
->b1
= b43_phy_read(dev
, B43_NPHY_C2_RXIQ_COMPB1
);
497 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
498 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev
*dev
, u8 core
)
500 u16
*regs
= dev
->phy
.n
->tx_rx_cal_phy_saveregs
;
502 b43_phy_write(dev
, B43_NPHY_RFSEQCA
, regs
[0]);
504 b43_phy_write(dev
, B43_NPHY_AFECTL_C1
, regs
[1]);
505 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, regs
[2]);
507 b43_phy_write(dev
, B43_NPHY_AFECTL_C2
, regs
[1]);
508 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, regs
[2]);
510 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, regs
[3]);
511 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, regs
[4]);
512 b43_phy_write(dev
, B43_NPHY_RFCTL_RSSIO1
, regs
[5]);
513 b43_phy_write(dev
, B43_NPHY_RFCTL_RSSIO2
, regs
[6]);
514 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B1S1
, regs
[7]);
515 b43_phy_write(dev
, B43_NPHY_RFCTL_OVER
, regs
[8]);
516 b43_phy_write(dev
, B43_NPHY_PAPD_EN0
, regs
[9]);
517 b43_phy_write(dev
, B43_NPHY_PAPD_EN1
, regs
[10]);
520 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
521 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev
*dev
, u8 core
)
524 u16
*regs
= dev
->phy
.n
->tx_rx_cal_phy_saveregs
;
526 regs
[0] = b43_phy_read(dev
, B43_NPHY_RFSEQCA
);
528 regs
[1] = b43_phy_read(dev
, B43_NPHY_AFECTL_C1
);
529 regs
[2] = b43_phy_read(dev
, B43_NPHY_AFECTL_OVER1
);
531 regs
[1] = b43_phy_read(dev
, B43_NPHY_AFECTL_C2
);
532 regs
[2] = b43_phy_read(dev
, B43_NPHY_AFECTL_OVER
);
534 regs
[3] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC1
);
535 regs
[4] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC2
);
536 regs
[5] = b43_phy_read(dev
, B43_NPHY_RFCTL_RSSIO1
);
537 regs
[6] = b43_phy_read(dev
, B43_NPHY_RFCTL_RSSIO2
);
538 regs
[7] = b43_phy_read(dev
, B43_NPHY_TXF_40CO_B1S1
);
539 regs
[8] = b43_phy_read(dev
, B43_NPHY_RFCTL_OVER
);
540 regs
[9] = b43_phy_read(dev
, B43_NPHY_PAPD_EN0
);
541 regs
[10] = b43_phy_read(dev
, B43_NPHY_PAPD_EN1
);
543 b43_phy_mask(dev
, B43_NPHY_PAPD_EN0
, ~0x0001);
544 b43_phy_mask(dev
, B43_NPHY_PAPD_EN1
, ~0x0001);
546 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
, (u16
)~B43_NPHY_RFSEQCA_RXDIS
,
547 ((1 - core
) << B43_NPHY_RFSEQCA_RXDIS_SHIFT
));
548 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
, ~B43_NPHY_RFSEQCA_TXEN
,
549 ((1 - core
) << B43_NPHY_RFSEQCA_TXEN_SHIFT
));
550 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
, ~B43_NPHY_RFSEQCA_RXEN
,
551 (core
<< B43_NPHY_RFSEQCA_RXEN_SHIFT
));
552 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
, ~B43_NPHY_RFSEQCA_TXDIS
,
553 (core
<< B43_NPHY_RFSEQCA_TXDIS_SHIFT
));
556 b43_phy_mask(dev
, B43_NPHY_AFECTL_C1
, ~0x0007);
557 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER1
, 0x0007);
559 b43_phy_mask(dev
, B43_NPHY_AFECTL_C2
, ~0x0007);
560 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER
, 0x0007);
563 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */
564 /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */
565 /* TODO: Call N PHY RF Seq with 0 as argument */
575 /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */
576 /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */
579 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
580 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev
*dev
, u8 mask
)
586 int iq_nbits
, qq_nbits
;
590 struct nphy_iq_est est
;
591 struct b43_phy_n_iq_comp old
;
592 struct b43_phy_n_iq_comp
new = { };
598 b43_nphy_rx_iq_coeffs(dev
, false, &old
);
599 b43_nphy_rx_iq_coeffs(dev
, true, &new);
600 b43_nphy_rx_iq_est(dev
, &est
, 0x4000, 32, false);
603 for (i
= 0; i
< 2; i
++) {
604 if (i
== 0 && (mask
& 1)) {
608 } else if (i
== 1 && (mask
& 2)) {
622 iq_nbits
= fls(abs(iq
));
625 arsh
= iq_nbits
- 20;
627 a
= -((iq
<< (30 - iq_nbits
)) + (ii
>> (1 + arsh
)));
630 a
= -((iq
<< (30 - iq_nbits
)) + (ii
<< (-1 - arsh
)));
639 brsh
= qq_nbits
- 11;
641 b
= (qq
<< (31 - qq_nbits
));
644 b
= (qq
<< (31 - qq_nbits
));
651 b
= int_sqrt(b
/ tmp
- a
* a
) - (1 << 10);
653 if (i
== 0 && (mask
& 0x1)) {
654 if (dev
->phy
.rev
>= 3) {
661 } else if (i
== 1 && (mask
& 0x2)) {
662 if (dev
->phy
.rev
>= 3) {
675 b43_nphy_rx_iq_coeffs(dev
, true, &new);
678 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
679 static void b43_nphy_tx_iq_workaround(struct b43_wldev
*dev
)
684 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
, 0x3C50);
685 for (i
= 0; i
< 4; i
++)
686 array
[i
] = b43_phy_read(dev
, B43_NPHY_TABLE_DATALO
);
688 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_NPHY_TXIQW0
, array
[0]);
689 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_NPHY_TXIQW1
, array
[1]);
690 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_NPHY_TXIQW2
, array
[2]);
691 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_NPHY_TXIQW3
, array
[3]);
694 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
695 static void b43_nphy_write_clip_detection(struct b43_wldev
*dev
, u16
*clip_st
)
697 b43_phy_write(dev
, B43_NPHY_C1_CLIP1THRES
, clip_st
[0]);
698 b43_phy_write(dev
, B43_NPHY_C2_CLIP1THRES
, clip_st
[1]);
701 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
702 static void b43_nphy_read_clip_detection(struct b43_wldev
*dev
, u16
*clip_st
)
704 clip_st
[0] = b43_phy_read(dev
, B43_NPHY_C1_CLIP1THRES
);
705 clip_st
[1] = b43_phy_read(dev
, B43_NPHY_C2_CLIP1THRES
);
708 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
709 static u16
b43_nphy_classifier(struct b43_wldev
*dev
, u16 mask
, u16 val
)
713 if (dev
->dev
->id
.revision
== 16)
714 b43_mac_suspend(dev
);
716 tmp
= b43_phy_read(dev
, B43_NPHY_CLASSCTL
);
717 tmp
&= (B43_NPHY_CLASSCTL_CCKEN
| B43_NPHY_CLASSCTL_OFDMEN
|
718 B43_NPHY_CLASSCTL_WAITEDEN
);
721 b43_phy_maskset(dev
, B43_NPHY_CLASSCTL
, 0xFFF8, tmp
);
723 if (dev
->dev
->id
.revision
== 16)
729 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
730 static void b43_nphy_stay_in_carrier_search(struct b43_wldev
*dev
, bool enable
)
732 struct b43_phy
*phy
= &dev
->phy
;
733 struct b43_phy_n
*nphy
= phy
->n
;
736 u16 clip
[] = { 0xFFFF, 0xFFFF };
737 if (nphy
->deaf_count
++ == 0) {
738 nphy
->classifier_state
= b43_nphy_classifier(dev
, 0, 0);
739 b43_nphy_classifier(dev
, 0x7, 0);
740 b43_nphy_read_clip_detection(dev
, nphy
->clip_state
);
741 b43_nphy_write_clip_detection(dev
, clip
);
743 b43_nphy_reset_cca(dev
);
745 if (--nphy
->deaf_count
== 0) {
746 b43_nphy_classifier(dev
, 0x7, nphy
->classifier_state
);
747 b43_nphy_write_clip_detection(dev
, nphy
->clip_state
);
752 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
753 static void b43_nphy_stop_playback(struct b43_wldev
*dev
)
755 struct b43_phy_n
*nphy
= dev
->phy
.n
;
758 if (nphy
->hang_avoid
)
759 b43_nphy_stay_in_carrier_search(dev
, 1);
761 tmp
= b43_phy_read(dev
, B43_NPHY_SAMP_STAT
);
763 b43_phy_set(dev
, B43_NPHY_SAMP_CMD
, B43_NPHY_SAMP_CMD_STOP
);
765 b43_phy_mask(dev
, B43_NPHY_IQLOCAL_CMDGCTL
, (u16
)~0x8000);
767 b43_phy_mask(dev
, B43_NPHY_SAMP_CMD
, ~0x0004);
769 if (nphy
->bb_mult_save
& 0x80000000) {
770 tmp
= nphy
->bb_mult_save
& 0xFFFF;
771 /* TODO: Write an N PHY Table with ID 15, length 1, offset 87,
772 width 16 and data from tmp */
773 nphy
->bb_mult_save
= 0;
776 if (nphy
->hang_avoid
)
777 b43_nphy_stay_in_carrier_search(dev
, 0);
780 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
781 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev
*dev
)
783 struct b43_phy_n
*nphy
= dev
->phy
.n
;
786 u32 cur_real
, cur_imag
, real_part
, imag_part
;
790 if (nphy
->hang_avoid
)
791 b43_nphy_stay_in_carrier_search(dev
, true);
793 /* TODO: Read an N PHY Table with ID 15, length 7, offset 80,
794 width 16, and data pointer buffer */
796 for (i
= 0; i
< 2; i
++) {
797 tmp
= ((buffer
[i
* 2] & 0x3FF) << 10) |
798 (buffer
[i
* 2 + 1] & 0x3FF);
799 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
,
800 (((i
+ 26) << 10) | 320));
801 for (j
= 0; j
< 128; j
++) {
802 b43_phy_write(dev
, B43_NPHY_TABLE_DATAHI
,
803 ((tmp
>> 16) & 0xFFFF));
804 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
,
809 for (i
= 0; i
< 2; i
++) {
811 real_part
= (tmp
>> 8) & 0xFF;
812 imag_part
= (tmp
& 0xFF);
813 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
,
814 (((i
+ 26) << 10) | 448));
816 if (dev
->phy
.rev
>= 3) {
817 cur_real
= real_part
;
818 cur_imag
= imag_part
;
819 tmp
= ((cur_real
& 0xFF) << 8) | (cur_imag
& 0xFF);
822 for (j
= 0; j
< 128; j
++) {
823 if (dev
->phy
.rev
< 3) {
824 cur_real
= (real_part
* loscale
[j
] + 128) >> 8;
825 cur_imag
= (imag_part
* loscale
[j
] + 128) >> 8;
826 tmp
= ((cur_real
& 0xFF) << 8) |
829 b43_phy_write(dev
, B43_NPHY_TABLE_DATAHI
,
830 ((tmp
>> 16) & 0xFFFF));
831 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
,
836 if (dev
->phy
.rev
>= 3) {
837 b43_shm_write16(dev
, B43_SHM_SHARED
,
838 B43_SHM_SH_NPHY_TXPWR_INDX0
, 0xFFFF);
839 b43_shm_write16(dev
, B43_SHM_SHARED
,
840 B43_SHM_SH_NPHY_TXPWR_INDX1
, 0xFFFF);
843 if (nphy
->hang_avoid
)
844 b43_nphy_stay_in_carrier_search(dev
, false);
847 enum b43_nphy_rf_sequence
{
851 B43_RFSEQ_UPDATE_GAINH
,
852 B43_RFSEQ_UPDATE_GAINL
,
853 B43_RFSEQ_UPDATE_GAINU
,
856 static void b43_nphy_force_rf_sequence(struct b43_wldev
*dev
,
857 enum b43_nphy_rf_sequence seq
)
859 static const u16 trigger
[] = {
860 [B43_RFSEQ_RX2TX
] = B43_NPHY_RFSEQTR_RX2TX
,
861 [B43_RFSEQ_TX2RX
] = B43_NPHY_RFSEQTR_TX2RX
,
862 [B43_RFSEQ_RESET2RX
] = B43_NPHY_RFSEQTR_RST2RX
,
863 [B43_RFSEQ_UPDATE_GAINH
] = B43_NPHY_RFSEQTR_UPGH
,
864 [B43_RFSEQ_UPDATE_GAINL
] = B43_NPHY_RFSEQTR_UPGL
,
865 [B43_RFSEQ_UPDATE_GAINU
] = B43_NPHY_RFSEQTR_UPGU
,
869 B43_WARN_ON(seq
>= ARRAY_SIZE(trigger
));
871 b43_phy_set(dev
, B43_NPHY_RFSEQMODE
,
872 B43_NPHY_RFSEQMODE_CAOVER
| B43_NPHY_RFSEQMODE_TROVER
);
873 b43_phy_set(dev
, B43_NPHY_RFSEQTR
, trigger
[seq
]);
874 for (i
= 0; i
< 200; i
++) {
875 if (!(b43_phy_read(dev
, B43_NPHY_RFSEQST
) & trigger
[seq
]))
879 b43err(dev
->wl
, "RF sequence status timeout\n");
881 b43_phy_mask(dev
, B43_NPHY_RFSEQMODE
,
882 ~(B43_NPHY_RFSEQMODE_CAOVER
| B43_NPHY_RFSEQMODE_TROVER
));
885 static void b43_nphy_bphy_init(struct b43_wldev
*dev
)
891 for (i
= 0; i
< 14; i
++) {
892 b43_phy_write(dev
, B43_PHY_N_BMODE(0x88 + i
), val
);
896 for (i
= 0; i
< 16; i
++) {
897 b43_phy_write(dev
, B43_PHY_N_BMODE(0x97 + i
), val
);
900 b43_phy_write(dev
, B43_PHY_N_BMODE(0x38), 0x668);
903 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
904 static void b43_nphy_scale_offset_rssi(struct b43_wldev
*dev
, u16 scale
,
905 s8 offset
, u8 core
, u8 rail
, u8 type
)
908 bool core1or5
= (core
== 1) || (core
== 5);
909 bool core2or5
= (core
== 2) || (core
== 5);
911 offset
= clamp_val(offset
, -32, 31);
912 tmp
= ((scale
& 0x3F) << 8) | (offset
& 0x3F);
914 if (core1or5
&& (rail
== 0) && (type
== 2))
915 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_Z
, tmp
);
916 if (core1or5
&& (rail
== 1) && (type
== 2))
917 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_Z
, tmp
);
918 if (core2or5
&& (rail
== 0) && (type
== 2))
919 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_Z
, tmp
);
920 if (core2or5
&& (rail
== 1) && (type
== 2))
921 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_Z
, tmp
);
922 if (core1or5
&& (rail
== 0) && (type
== 0))
923 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_X
, tmp
);
924 if (core1or5
&& (rail
== 1) && (type
== 0))
925 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_X
, tmp
);
926 if (core2or5
&& (rail
== 0) && (type
== 0))
927 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_X
, tmp
);
928 if (core2or5
&& (rail
== 1) && (type
== 0))
929 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_X
, tmp
);
930 if (core1or5
&& (rail
== 0) && (type
== 1))
931 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_Y
, tmp
);
932 if (core1or5
&& (rail
== 1) && (type
== 1))
933 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_Y
, tmp
);
934 if (core2or5
&& (rail
== 0) && (type
== 1))
935 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_Y
, tmp
);
936 if (core2or5
&& (rail
== 1) && (type
== 1))
937 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_Y
, tmp
);
938 if (core1or5
&& (rail
== 0) && (type
== 6))
939 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_TBD
, tmp
);
940 if (core1or5
&& (rail
== 1) && (type
== 6))
941 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_TBD
, tmp
);
942 if (core2or5
&& (rail
== 0) && (type
== 6))
943 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_TBD
, tmp
);
944 if (core2or5
&& (rail
== 1) && (type
== 6))
945 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_TBD
, tmp
);
946 if (core1or5
&& (rail
== 0) && (type
== 3))
947 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_PWRDET
, tmp
);
948 if (core1or5
&& (rail
== 1) && (type
== 3))
949 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_PWRDET
, tmp
);
950 if (core2or5
&& (rail
== 0) && (type
== 3))
951 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_PWRDET
, tmp
);
952 if (core2or5
&& (rail
== 1) && (type
== 3))
953 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_PWRDET
, tmp
);
954 if (core1or5
&& (type
== 4))
955 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_TSSI
, tmp
);
956 if (core2or5
&& (type
== 4))
957 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_TSSI
, tmp
);
958 if (core1or5
&& (type
== 5))
959 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_TSSI
, tmp
);
960 if (core2or5
&& (type
== 5))
961 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_TSSI
, tmp
);
964 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
965 static void b43_nphy_rssi_select(struct b43_wldev
*dev
, u8 code
, u8 type
)
969 if (dev
->phy
.rev
>= 3) {
981 val
= (val
<< 12) | (val
<< 14);
982 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C1
, 0x0FFF, val
);
983 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C2
, 0x0FFF, val
);
986 b43_phy_maskset(dev
, B43_NPHY_RFCTL_RSSIO1
, 0xFFCF,
988 b43_phy_maskset(dev
, B43_NPHY_RFCTL_RSSIO2
, 0xFFCF,
992 /* TODO use some definitions */
994 b43_phy_maskset(dev
, B43_NPHY_AFECTL_OVER
, 0xCFFF, 0);
996 b43_phy_maskset(dev
, B43_NPHY_RFCTL_CMD
,
998 b43_phy_maskset(dev
, B43_NPHY_RFCTL_OVER
,
1000 b43_phy_maskset(dev
, B43_NPHY_RFCTL_CMD
,
1003 b43_phy_maskset(dev
, B43_NPHY_RFCTL_OVER
,
1007 b43_phy_maskset(dev
, B43_NPHY_AFECTL_OVER
, 0xCFFF,
1010 b43_phy_maskset(dev
, B43_NPHY_RFCTL_CMD
,
1012 b43_phy_maskset(dev
, B43_NPHY_RFCTL_OVER
,
1013 0xEFDC, (code
<< 1 | 0x1021));
1014 b43_phy_maskset(dev
, B43_NPHY_RFCTL_CMD
,
1017 b43_phy_maskset(dev
, B43_NPHY_RFCTL_OVER
,
1024 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1025 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev
*dev
, u8 type
, u8
*buf
)
1028 for (i
= 0; i
< 2; i
++) {
1031 b43_radio_maskset(dev
, B2055_C1_B0NB_RSSIVCM
,
1033 b43_radio_maskset(dev
, B2055_C1_RX_BB_RSSICTL5
,
1036 b43_radio_maskset(dev
, B2055_C2_B0NB_RSSIVCM
,
1038 b43_radio_maskset(dev
, B2055_C2_RX_BB_RSSICTL5
,
1039 0xFC, buf
[2 * i
+ 1]);
1043 b43_radio_maskset(dev
, B2055_C1_RX_BB_RSSICTL5
,
1046 b43_radio_maskset(dev
, B2055_C2_RX_BB_RSSICTL5
,
1047 0xF3, buf
[2 * i
+ 1] << 2);
1052 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1053 static int b43_nphy_poll_rssi(struct b43_wldev
*dev
, u8 type
, s32
*buf
,
1058 u16 save_regs_phy
[9];
1061 if (dev
->phy
.rev
>= 3) {
1062 save_regs_phy
[0] = b43_phy_read(dev
,
1063 B43_NPHY_RFCTL_LUT_TRSW_UP1
);
1064 save_regs_phy
[1] = b43_phy_read(dev
,
1065 B43_NPHY_RFCTL_LUT_TRSW_UP2
);
1066 save_regs_phy
[2] = b43_phy_read(dev
, B43_NPHY_AFECTL_C1
);
1067 save_regs_phy
[3] = b43_phy_read(dev
, B43_NPHY_AFECTL_C2
);
1068 save_regs_phy
[4] = b43_phy_read(dev
, B43_NPHY_AFECTL_OVER1
);
1069 save_regs_phy
[5] = b43_phy_read(dev
, B43_NPHY_AFECTL_OVER
);
1070 save_regs_phy
[6] = b43_phy_read(dev
, B43_NPHY_TXF_40CO_B1S0
);
1071 save_regs_phy
[7] = b43_phy_read(dev
, B43_NPHY_TXF_40CO_B32S1
);
1074 b43_nphy_rssi_select(dev
, 5, type
);
1076 if (dev
->phy
.rev
< 2) {
1077 save_regs_phy
[8] = b43_phy_read(dev
, B43_NPHY_GPIO_SEL
);
1078 b43_phy_write(dev
, B43_NPHY_GPIO_SEL
, 5);
1081 for (i
= 0; i
< 4; i
++)
1084 for (i
= 0; i
< nsamp
; i
++) {
1085 if (dev
->phy
.rev
< 2) {
1086 s
[0] = b43_phy_read(dev
, B43_NPHY_GPIO_LOOUT
);
1087 s
[1] = b43_phy_read(dev
, B43_NPHY_GPIO_HIOUT
);
1089 s
[0] = b43_phy_read(dev
, B43_NPHY_RSSI1
);
1090 s
[1] = b43_phy_read(dev
, B43_NPHY_RSSI2
);
1093 buf
[0] += ((s8
)((s
[0] & 0x3F) << 2)) >> 2;
1094 buf
[1] += ((s8
)(((s
[0] >> 8) & 0x3F) << 2)) >> 2;
1095 buf
[2] += ((s8
)((s
[1] & 0x3F) << 2)) >> 2;
1096 buf
[3] += ((s8
)(((s
[1] >> 8) & 0x3F) << 2)) >> 2;
1098 out
= (buf
[0] & 0xFF) << 24 | (buf
[1] & 0xFF) << 16 |
1099 (buf
[2] & 0xFF) << 8 | (buf
[3] & 0xFF);
1101 if (dev
->phy
.rev
< 2)
1102 b43_phy_write(dev
, B43_NPHY_GPIO_SEL
, save_regs_phy
[8]);
1104 if (dev
->phy
.rev
>= 3) {
1105 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP1
,
1107 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP2
,
1109 b43_phy_write(dev
, B43_NPHY_AFECTL_C1
, save_regs_phy
[2]);
1110 b43_phy_write(dev
, B43_NPHY_AFECTL_C2
, save_regs_phy
[3]);
1111 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, save_regs_phy
[4]);
1112 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, save_regs_phy
[5]);
1113 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B1S0
, save_regs_phy
[6]);
1114 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B32S1
, save_regs_phy
[7]);
1120 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1121 static void b43_nphy_rev2_rssi_cal(struct b43_wldev
*dev
, u8 type
)
1126 u16
class, override
;
1127 u8 regs_save_radio
[2];
1128 u16 regs_save_phy
[2];
1132 u16 clip_off
[2] = { 0xFFFF, 0xFFFF };
1133 s32 results_min
[4] = { };
1134 u8 vcm_final
[4] = { };
1135 s32 results
[4][4] = { };
1136 s32 miniq
[4][2] = { };
1141 } else if (type
< 2) {
1149 class = b43_nphy_classifier(dev
, 0, 0);
1150 b43_nphy_classifier(dev
, 7, 4);
1151 b43_nphy_read_clip_detection(dev
, clip_state
);
1152 b43_nphy_write_clip_detection(dev
, clip_off
);
1154 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
)
1159 regs_save_phy
[0] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC1
);
1160 regs_save_radio
[0] = b43_radio_read16(dev
, B2055_C1_PD_RXTX
);
1161 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, override
);
1162 b43_radio_write16(dev
, B2055_C1_PD_RXTX
, val
);
1164 regs_save_phy
[1] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC2
);
1165 regs_save_radio
[1] = b43_radio_read16(dev
, B2055_C2_PD_RXTX
);
1166 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, override
);
1167 b43_radio_write16(dev
, B2055_C2_PD_RXTX
, val
);
1169 state
[0] = b43_radio_read16(dev
, B2055_C1_PD_RSSIMISC
) & 0x07;
1170 state
[1] = b43_radio_read16(dev
, B2055_C2_PD_RSSIMISC
) & 0x07;
1171 b43_radio_mask(dev
, B2055_C1_PD_RSSIMISC
, 0xF8);
1172 b43_radio_mask(dev
, B2055_C2_PD_RSSIMISC
, 0xF8);
1173 state
[2] = b43_radio_read16(dev
, B2055_C1_SP_RSSI
) & 0x07;
1174 state
[3] = b43_radio_read16(dev
, B2055_C2_SP_RSSI
) & 0x07;
1176 b43_nphy_rssi_select(dev
, 5, type
);
1177 b43_nphy_scale_offset_rssi(dev
, 0, 0, 5, 0, type
);
1178 b43_nphy_scale_offset_rssi(dev
, 0, 0, 5, 1, type
);
1180 for (i
= 0; i
< 4; i
++) {
1182 for (j
= 0; j
< 4; j
++)
1185 b43_nphy_set_rssi_2055_vcm(dev
, type
, tmp
);
1186 b43_nphy_poll_rssi(dev
, type
, results
[i
], 8);
1188 for (j
= 0; j
< 2; j
++)
1189 miniq
[i
][j
] = min(results
[i
][2 * j
],
1190 results
[i
][2 * j
+ 1]);
1193 for (i
= 0; i
< 4; i
++) {
1198 for (j
= 0; j
< 4; j
++) {
1200 curr
= abs(results
[j
][i
]);
1202 curr
= abs(miniq
[j
][i
/ 2] - code
* 8);
1209 if (results
[j
][i
] < minpoll
)
1210 minpoll
= results
[j
][i
];
1212 results_min
[i
] = minpoll
;
1213 vcm_final
[i
] = minvcm
;
1217 b43_nphy_set_rssi_2055_vcm(dev
, type
, vcm_final
);
1219 for (i
= 0; i
< 4; i
++) {
1220 offset
[i
] = (code
* 8) - results
[vcm_final
[i
]][i
];
1223 offset
[i
] = -((abs(offset
[i
]) + 4) / 8);
1225 offset
[i
] = (offset
[i
] + 4) / 8;
1227 if (results_min
[i
] == 248)
1228 offset
[i
] = code
- 32;
1231 b43_nphy_scale_offset_rssi(dev
, 0, offset
[i
], 1, 0,
1234 b43_nphy_scale_offset_rssi(dev
, 0, offset
[i
], 2, 1,
1238 b43_radio_maskset(dev
, B2055_C1_PD_RSSIMISC
, 0xF8, state
[0]);
1239 b43_radio_maskset(dev
, B2055_C1_PD_RSSIMISC
, 0xF8, state
[1]);
1243 b43_nphy_rssi_select(dev
, 1, 2);
1246 b43_nphy_rssi_select(dev
, 1, 0);
1249 b43_nphy_rssi_select(dev
, 1, 1);
1252 b43_nphy_rssi_select(dev
, 1, 1);
1258 b43_nphy_rssi_select(dev
, 2, 2);
1261 b43_nphy_rssi_select(dev
, 2, 0);
1264 b43_nphy_rssi_select(dev
, 2, 1);
1268 b43_nphy_rssi_select(dev
, 0, type
);
1270 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, regs_save_phy
[0]);
1271 b43_radio_write16(dev
, B2055_C1_PD_RXTX
, regs_save_radio
[0]);
1272 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, regs_save_phy
[1]);
1273 b43_radio_write16(dev
, B2055_C2_PD_RXTX
, regs_save_radio
[1]);
1275 b43_nphy_classifier(dev
, 7, class);
1276 b43_nphy_write_clip_detection(dev
, clip_state
);
1279 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1280 static void b43_nphy_rev3_rssi_cal(struct b43_wldev
*dev
)
1287 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1289 static void b43_nphy_rssi_cal(struct b43_wldev
*dev
)
1291 if (dev
->phy
.rev
>= 3) {
1292 b43_nphy_rev3_rssi_cal(dev
);
1294 b43_nphy_rev2_rssi_cal(dev
, 2);
1295 b43_nphy_rev2_rssi_cal(dev
, 0);
1296 b43_nphy_rev2_rssi_cal(dev
, 1);
1301 * Restore RSSI Calibration
1302 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1304 static void b43_nphy_restore_rssi_cal(struct b43_wldev
*dev
)
1306 struct b43_phy_n
*nphy
= dev
->phy
.n
;
1308 u16
*rssical_radio_regs
= NULL
;
1309 u16
*rssical_phy_regs
= NULL
;
1311 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
1312 if (!nphy
->rssical_chanspec_2G
)
1314 rssical_radio_regs
= nphy
->rssical_cache
.rssical_radio_regs_2G
;
1315 rssical_phy_regs
= nphy
->rssical_cache
.rssical_phy_regs_2G
;
1317 if (!nphy
->rssical_chanspec_5G
)
1319 rssical_radio_regs
= nphy
->rssical_cache
.rssical_radio_regs_5G
;
1320 rssical_phy_regs
= nphy
->rssical_cache
.rssical_phy_regs_5G
;
1323 /* TODO use some definitions */
1324 b43_radio_maskset(dev
, 0x602B, 0xE3, rssical_radio_regs
[0]);
1325 b43_radio_maskset(dev
, 0x702B, 0xE3, rssical_radio_regs
[1]);
1327 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_Z
, rssical_phy_regs
[0]);
1328 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_Z
, rssical_phy_regs
[1]);
1329 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_Z
, rssical_phy_regs
[2]);
1330 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_Z
, rssical_phy_regs
[3]);
1332 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_X
, rssical_phy_regs
[4]);
1333 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_X
, rssical_phy_regs
[5]);
1334 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_X
, rssical_phy_regs
[6]);
1335 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_X
, rssical_phy_regs
[7]);
1337 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_Y
, rssical_phy_regs
[8]);
1338 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_Y
, rssical_phy_regs
[9]);
1339 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_Y
, rssical_phy_regs
[10]);
1340 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_Y
, rssical_phy_regs
[11]);
1343 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1344 static const u32
*b43_nphy_get_ipa_gain_table(struct b43_wldev
*dev
)
1346 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
1347 if (dev
->phy
.rev
>= 6) {
1348 /* TODO If the chip is 47162
1349 return txpwrctrl_tx_gain_ipa_rev5 */
1350 return txpwrctrl_tx_gain_ipa_rev6
;
1351 } else if (dev
->phy
.rev
>= 5) {
1352 return txpwrctrl_tx_gain_ipa_rev5
;
1354 return txpwrctrl_tx_gain_ipa
;
1357 return txpwrctrl_tx_gain_ipa_5g
;
1361 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
1362 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev
*dev
)
1364 struct b43_phy_n
*nphy
= dev
->phy
.n
;
1365 u16
*save
= nphy
->tx_rx_cal_radio_saveregs
;
1367 if (dev
->phy
.rev
>= 3) {
1370 save
[0] = b43_radio_read16(dev
, B2055_C1_TX_RF_IQCAL1
);
1371 b43_radio_write16(dev
, B2055_C1_TX_RF_IQCAL1
, 0x29);
1373 save
[1] = b43_radio_read16(dev
, B2055_C1_TX_RF_IQCAL2
);
1374 b43_radio_write16(dev
, B2055_C1_TX_RF_IQCAL2
, 0x54);
1376 save
[2] = b43_radio_read16(dev
, B2055_C2_TX_RF_IQCAL1
);
1377 b43_radio_write16(dev
, B2055_C2_TX_RF_IQCAL1
, 0x29);
1379 save
[3] = b43_radio_read16(dev
, B2055_C2_TX_RF_IQCAL2
);
1380 b43_radio_write16(dev
, B2055_C2_TX_RF_IQCAL2
, 0x54);
1382 save
[3] = b43_radio_read16(dev
, B2055_C1_PWRDET_RXTX
);
1383 save
[4] = b43_radio_read16(dev
, B2055_C2_PWRDET_RXTX
);
1385 if (!(b43_phy_read(dev
, B43_NPHY_BANDCTL
) &
1386 B43_NPHY_BANDCTL_5GHZ
)) {
1387 b43_radio_write16(dev
, B2055_C1_PWRDET_RXTX
, 0x04);
1388 b43_radio_write16(dev
, B2055_C2_PWRDET_RXTX
, 0x04);
1390 b43_radio_write16(dev
, B2055_C1_PWRDET_RXTX
, 0x20);
1391 b43_radio_write16(dev
, B2055_C2_PWRDET_RXTX
, 0x20);
1394 if (dev
->phy
.rev
< 2) {
1395 b43_radio_set(dev
, B2055_C1_TX_BB_MXGM
, 0x20);
1396 b43_radio_set(dev
, B2055_C2_TX_BB_MXGM
, 0x20);
1398 b43_radio_mask(dev
, B2055_C1_TX_BB_MXGM
, ~0x20);
1399 b43_radio_mask(dev
, B2055_C2_TX_BB_MXGM
, ~0x20);
1404 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
1405 static void b43_nphy_iq_cal_gain_params(struct b43_wldev
*dev
, u16 core
,
1406 struct nphy_txgains target
,
1407 struct nphy_iqcal_params
*params
)
1412 if (dev
->phy
.rev
>= 3) {
1413 params
->txgm
= target
.txgm
[core
];
1414 params
->pga
= target
.pga
[core
];
1415 params
->pad
= target
.pad
[core
];
1416 params
->ipa
= target
.ipa
[core
];
1417 params
->cal_gain
= (params
->txgm
<< 12) | (params
->pga
<< 8) |
1418 (params
->pad
<< 4) | (params
->ipa
);
1419 for (j
= 0; j
< 5; j
++)
1420 params
->ncorr
[j
] = 0x79;
1422 gain
= (target
.pad
[core
]) | (target
.pga
[core
] << 4) |
1423 (target
.txgm
[core
] << 8);
1425 indx
= (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) ?
1427 for (i
= 0; i
< 9; i
++)
1428 if (tbl_iqcal_gainparams
[indx
][i
][0] == gain
)
1432 params
->txgm
= tbl_iqcal_gainparams
[indx
][i
][1];
1433 params
->pga
= tbl_iqcal_gainparams
[indx
][i
][2];
1434 params
->pad
= tbl_iqcal_gainparams
[indx
][i
][3];
1435 params
->cal_gain
= (params
->txgm
<< 7) | (params
->pga
<< 4) |
1437 for (j
= 0; j
< 4; j
++)
1438 params
->ncorr
[j
] = tbl_iqcal_gainparams
[indx
][i
][4 + j
];
1442 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
1443 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev
*dev
, u16 core
)
1445 struct b43_phy_n
*nphy
= dev
->phy
.n
;
1449 u16 tmp
= nphy
->txcal_bbmult
;
1454 for (i
= 0; i
< 18; i
++) {
1455 scale
= (ladder_lo
[i
].percent
* tmp
) / 100;
1456 entry
= ((scale
& 0xFF) << 8) | ladder_lo
[i
].g_env
;
1457 /* TODO: Write an N PHY Table with ID 15, length 1,
1458 offset i, width 16, and data entry */
1460 scale
= (ladder_iq
[i
].percent
* tmp
) / 100;
1461 entry
= ((scale
& 0xFF) << 8) | ladder_iq
[i
].g_env
;
1462 /* TODO: Write an N PHY Table with ID 15, length 1,
1463 offset i + 32, width 16, and data entry */
1467 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
1468 static struct nphy_txgains
b43_nphy_get_tx_gains(struct b43_wldev
*dev
)
1470 struct b43_phy_n
*nphy
= dev
->phy
.n
;
1473 struct nphy_txgains target
;
1474 const u32
*table
= NULL
;
1476 if (nphy
->txpwrctrl
== 0) {
1479 if (nphy
->hang_avoid
)
1480 b43_nphy_stay_in_carrier_search(dev
, true);
1481 /* TODO: Read an N PHY Table with ID 7, length 2,
1482 offset 0x110, width 16, and curr_gain */
1483 if (nphy
->hang_avoid
)
1484 b43_nphy_stay_in_carrier_search(dev
, false);
1486 for (i
= 0; i
< 2; ++i
) {
1487 if (dev
->phy
.rev
>= 3) {
1488 target
.ipa
[i
] = curr_gain
[i
] & 0x000F;
1489 target
.pad
[i
] = (curr_gain
[i
] & 0x00F0) >> 4;
1490 target
.pga
[i
] = (curr_gain
[i
] & 0x0F00) >> 8;
1491 target
.txgm
[i
] = (curr_gain
[i
] & 0x7000) >> 12;
1493 target
.ipa
[i
] = curr_gain
[i
] & 0x0003;
1494 target
.pad
[i
] = (curr_gain
[i
] & 0x000C) >> 2;
1495 target
.pga
[i
] = (curr_gain
[i
] & 0x0070) >> 4;
1496 target
.txgm
[i
] = (curr_gain
[i
] & 0x0380) >> 7;
1502 index
[0] = (b43_phy_read(dev
, B43_NPHY_C1_TXPCTL_STAT
) &
1503 B43_NPHY_TXPCTL_STAT_BIDX
) >>
1504 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT
;
1505 index
[1] = (b43_phy_read(dev
, B43_NPHY_C2_TXPCTL_STAT
) &
1506 B43_NPHY_TXPCTL_STAT_BIDX
) >>
1507 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT
;
1509 for (i
= 0; i
< 2; ++i
) {
1510 if (dev
->phy
.rev
>= 3) {
1511 enum ieee80211_band band
=
1512 b43_current_band(dev
->wl
);
1514 if ((nphy
->ipa2g_on
&&
1515 band
== IEEE80211_BAND_2GHZ
) ||
1517 band
== IEEE80211_BAND_5GHZ
)) {
1518 table
= b43_nphy_get_ipa_gain_table(dev
);
1520 if (band
== IEEE80211_BAND_5GHZ
) {
1521 if (dev
->phy
.rev
== 3)
1522 table
= b43_ntab_tx_gain_rev3_5ghz
;
1523 else if (dev
->phy
.rev
== 4)
1524 table
= b43_ntab_tx_gain_rev4_5ghz
;
1526 table
= b43_ntab_tx_gain_rev5plus_5ghz
;
1528 table
= b43_ntab_tx_gain_rev3plus_2ghz
;
1532 target
.ipa
[i
] = (table
[index
[i
]] >> 16) & 0xF;
1533 target
.pad
[i
] = (table
[index
[i
]] >> 20) & 0xF;
1534 target
.pga
[i
] = (table
[index
[i
]] >> 24) & 0xF;
1535 target
.txgm
[i
] = (table
[index
[i
]] >> 28) & 0xF;
1537 table
= b43_ntab_tx_gain_rev0_1_2
;
1539 target
.ipa
[i
] = (table
[index
[i
]] >> 16) & 0x3;
1540 target
.pad
[i
] = (table
[index
[i
]] >> 18) & 0x3;
1541 target
.pga
[i
] = (table
[index
[i
]] >> 20) & 0x7;
1542 target
.txgm
[i
] = (table
[index
[i
]] >> 23) & 0x7;
1550 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
1551 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev
*dev
)
1553 u16
*regs
= dev
->phy
.n
->tx_rx_cal_phy_saveregs
;
1555 if (dev
->phy
.rev
>= 3) {
1556 b43_phy_write(dev
, B43_NPHY_AFECTL_C1
, regs
[0]);
1557 b43_phy_write(dev
, B43_NPHY_AFECTL_C2
, regs
[1]);
1558 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, regs
[2]);
1559 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, regs
[3]);
1560 b43_phy_write(dev
, B43_NPHY_BBCFG
, regs
[4]);
1561 /* TODO: Write an N PHY Table with ID 8, length 1, offset 3,
1562 width 16, and data from regs[5] */
1563 /* TODO: Write an N PHY Table with ID 8, length 1, offset 19,
1564 width 16, and data from regs[6] */
1565 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, regs
[7]);
1566 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, regs
[8]);
1567 b43_phy_write(dev
, B43_NPHY_PAPD_EN0
, regs
[9]);
1568 b43_phy_write(dev
, B43_NPHY_PAPD_EN1
, regs
[10]);
1569 b43_nphy_reset_cca(dev
);
1571 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C1
, 0x0FFF, regs
[0]);
1572 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C2
, 0x0FFF, regs
[1]);
1573 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, regs
[2]);
1574 /* TODO: Write an N PHY Table with ID 8, length 1, offset 2,
1575 width 16, and data from regs[3] */
1576 /* TODO: Write an N PHY Table with ID 8, length 1, offset 18,
1577 width 16, and data from regs[4] */
1578 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, regs
[5]);
1579 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, regs
[6]);
1583 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
1584 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev
*dev
)
1586 u16
*regs
= dev
->phy
.n
->tx_rx_cal_phy_saveregs
;
1589 regs
[0] = b43_phy_read(dev
, B43_NPHY_AFECTL_C1
);
1590 regs
[1] = b43_phy_read(dev
, B43_NPHY_AFECTL_C2
);
1591 if (dev
->phy
.rev
>= 3) {
1592 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C1
, 0xF0FF, 0x0A00);
1593 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C2
, 0xF0FF, 0x0A00);
1595 tmp
= b43_phy_read(dev
, B43_NPHY_AFECTL_OVER1
);
1597 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, tmp
| 0x0600);
1599 tmp
= b43_phy_read(dev
, B43_NPHY_AFECTL_OVER
);
1601 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, tmp
| 0x0600);
1603 regs
[4] = b43_phy_read(dev
, B43_NPHY_BBCFG
);
1604 b43_phy_mask(dev
, B43_NPHY_BBCFG
, ~B43_NPHY_BBCFG_RSTRX
);
1606 /* TODO: Read an N PHY Table with ID 8, length 1, offset 3,
1607 width 16, and data pointing to tmp */
1610 /* TODO: Write an N PHY Table with ID 8, length 1, offset 3,
1611 width 16, and data 0 */
1612 /* TODO: Read an N PHY Table with ID 8, length 1, offset 19,
1613 width 16, and data pointing to tmp */
1616 /* TODO: Write an N PHY Table with ID 8, length 1, offset 19,
1617 width 16, and data 0 */
1618 regs
[7] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC1
);
1619 regs
[8] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC2
);
1621 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 1, 3 */
1622 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 2, 1 */
1623 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 8, 2 */
1625 regs
[9] = b43_phy_read(dev
, B43_NPHY_PAPD_EN0
);
1626 regs
[10] = b43_phy_read(dev
, B43_NPHY_PAPD_EN1
);
1627 b43_phy_mask(dev
, B43_NPHY_PAPD_EN0
, ~0x0001);
1628 b43_phy_mask(dev
, B43_NPHY_PAPD_EN1
, ~0x0001);
1630 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C1
, 0x0FFF, 0xA000);
1631 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C2
, 0x0FFF, 0xA000);
1632 tmp
= b43_phy_read(dev
, B43_NPHY_AFECTL_OVER
);
1634 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, tmp
| 0x3000);
1635 /* TODO: Read an N PHY Table with ID 8, length 1, offset 2,
1636 width 16, and data pointing to tmp */
1639 /* TODO: Write an N PHY Table with ID 8, length 1, offset 2,
1640 width 16, and data pointer tmp */
1641 /* TODO: Read an N PHY Table with ID 8, length 1, offset 18,
1642 width 16, and data pointer tmp */
1645 /* TODO: Write an N PHY Table with ID 8, length 1, offset 18,
1646 width 16, and data pointer tmp */
1647 regs
[5] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC1
);
1648 regs
[6] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC2
);
1649 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
)
1653 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, tmp
);
1654 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, tmp
);
1658 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
1659 static void b43_nphy_restore_cal(struct b43_wldev
*dev
)
1661 struct b43_phy_n
*nphy
= dev
->phy
.n
;
1668 u16
*txcal_radio_regs
= NULL
;
1669 struct b43_phy_n_iq_comp
*rxcal_coeffs
= NULL
;
1671 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
1672 if (nphy
->iqcal_chanspec_2G
== 0)
1674 table
= nphy
->cal_cache
.txcal_coeffs_2G
;
1675 loft
= &nphy
->cal_cache
.txcal_coeffs_2G
[5];
1677 if (nphy
->iqcal_chanspec_5G
== 0)
1679 table
= nphy
->cal_cache
.txcal_coeffs_5G
;
1680 loft
= &nphy
->cal_cache
.txcal_coeffs_5G
[5];
1683 /* TODO: Write an N PHY table with ID 15, length 4, offset 80,
1684 width 16, and data from table */
1686 for (i
= 0; i
< 4; i
++) {
1687 if (dev
->phy
.rev
>= 3)
1693 /* TODO: Write an N PHY table with ID 15, length 4, offset 88,
1694 width 16, and data from coef */
1695 /* TODO: Write an N PHY table with ID 15, length 2, offset 85,
1696 width 16 and data from loft */
1697 /* TODO: Write an N PHY table with ID 15, length 2, offset 93,
1698 width 16 and data from loft */
1700 if (dev
->phy
.rev
< 2)
1701 b43_nphy_tx_iq_workaround(dev
);
1703 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
1704 txcal_radio_regs
= nphy
->cal_cache
.txcal_radio_regs_2G
;
1705 rxcal_coeffs
= &nphy
->cal_cache
.rxcal_coeffs_2G
;
1707 txcal_radio_regs
= nphy
->cal_cache
.txcal_radio_regs_5G
;
1708 rxcal_coeffs
= &nphy
->cal_cache
.rxcal_coeffs_5G
;
1711 /* TODO use some definitions */
1712 if (dev
->phy
.rev
>= 3) {
1713 b43_radio_write(dev
, 0x2021, txcal_radio_regs
[0]);
1714 b43_radio_write(dev
, 0x2022, txcal_radio_regs
[1]);
1715 b43_radio_write(dev
, 0x3021, txcal_radio_regs
[2]);
1716 b43_radio_write(dev
, 0x3022, txcal_radio_regs
[3]);
1717 b43_radio_write(dev
, 0x2023, txcal_radio_regs
[4]);
1718 b43_radio_write(dev
, 0x2024, txcal_radio_regs
[5]);
1719 b43_radio_write(dev
, 0x3023, txcal_radio_regs
[6]);
1720 b43_radio_write(dev
, 0x3024, txcal_radio_regs
[7]);
1722 b43_radio_write(dev
, 0x8B, txcal_radio_regs
[0]);
1723 b43_radio_write(dev
, 0xBA, txcal_radio_regs
[1]);
1724 b43_radio_write(dev
, 0x8D, txcal_radio_regs
[2]);
1725 b43_radio_write(dev
, 0xBC, txcal_radio_regs
[3]);
1727 b43_nphy_rx_iq_coeffs(dev
, true, rxcal_coeffs
);
1730 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
1731 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev
*dev
,
1732 struct nphy_txgains target
,
1733 bool full
, bool mphase
)
1735 struct b43_phy_n
*nphy
= dev
->phy
.n
;
1741 u16 tmp
, core
, type
, count
, max
, numb
, last
, cmd
;
1749 struct nphy_iqcal_params params
[2];
1750 bool updated
[2] = { };
1752 b43_nphy_stay_in_carrier_search(dev
, true);
1754 if (dev
->phy
.rev
>= 4) {
1755 avoid
= nphy
->hang_avoid
;
1756 nphy
->hang_avoid
= 0;
1759 /* TODO: Read an N PHY Table with ID 7, length 2, offset 0x110,
1760 width 16, and data pointer save */
1762 for (i
= 0; i
< 2; i
++) {
1763 b43_nphy_iq_cal_gain_params(dev
, i
, target
, ¶ms
[i
]);
1764 gain
[i
] = params
[i
].cal_gain
;
1766 /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1767 width 16, and data pointer gain */
1769 b43_nphy_tx_cal_radio_setup(dev
);
1770 b43_nphy_tx_cal_phy_setup(dev
);
1772 phy6or5x
= dev
->phy
.rev
>= 6 ||
1773 (dev
->phy
.rev
== 5 && nphy
->ipa2g_on
&&
1774 b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
);
1779 b43_phy_write(dev
, B43_NPHY_IQLOCAL_CMDGCTL
, 0x8AA9);
1781 if (1 /* FIXME: the band width is 20 MHz */)
1786 if (nphy
->mphase_cal_phase_id
> 2)
1787 ;/* TODO: Call N PHY Run Samples with (band width * 8),
1788 0xFFFF, 0, 1, 0 as arguments */
1790 ;/* TODO: Call N PHY TX Tone with freq, 250, 1, 0 as arguments
1791 and save result as error */
1794 if (nphy
->mphase_cal_phase_id
> 2) {
1795 table
= nphy
->mphase_txcal_bestcoeffs
;
1797 if (dev
->phy
.rev
< 3)
1800 if (!full
&& nphy
->txiqlocal_coeffsvalid
) {
1801 table
= nphy
->txiqlocal_bestc
;
1803 if (dev
->phy
.rev
< 3)
1807 if (dev
->phy
.rev
>= 3) {
1808 table
= tbl_tx_iqlo_cal_startcoefs_nphyrev3
;
1809 length
= B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3
;
1811 table
= tbl_tx_iqlo_cal_startcoefs
;
1812 length
= B43_NTAB_TX_IQLO_CAL_STARTCOEFS
;
1817 /* TODO: Write an N PHY Table with ID 15, length from above,
1818 offset 64, width 16, and the data pointer from above */
1821 if (dev
->phy
.rev
>= 3)
1822 max
= B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3
;
1824 max
= B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL
;
1826 if (dev
->phy
.rev
>= 3)
1827 max
= B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3
;
1829 max
= B43_NTAB_TX_IQLO_CAL_CMDS_RECAL
;
1833 count
= nphy
->mphase_txcal_cmdidx
;
1835 (u16
)(count
+ nphy
->mphase_txcal_numcmds
));
1841 for (; count
< numb
; count
++) {
1843 if (dev
->phy
.rev
>= 3)
1844 cmd
= tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3
[count
];
1846 cmd
= tbl_tx_iqlo_cal_cmds_fullcal
[count
];
1848 if (dev
->phy
.rev
>= 3)
1849 cmd
= tbl_tx_iqlo_cal_cmds_recal_nphyrev3
[count
];
1851 cmd
= tbl_tx_iqlo_cal_cmds_recal
[count
];
1854 core
= (cmd
& 0x3000) >> 12;
1855 type
= (cmd
& 0x0F00) >> 8;
1857 if (phy6or5x
&& updated
[core
] == 0) {
1858 b43_nphy_update_tx_cal_ladder(dev
, core
);
1862 tmp
= (params
[core
].ncorr
[type
] << 8) | 0x66;
1863 b43_phy_write(dev
, B43_NPHY_IQLOCAL_CMDNNUM
, tmp
);
1865 if (type
== 1 || type
== 3 || type
== 4) {
1866 /* TODO: Read an N PHY Table with ID 15,
1867 length 1, offset 69 + core,
1868 width 16, and data pointer buffer */
1869 diq_start
= buffer
[0];
1871 /* TODO: Write an N PHY Table with ID 15,
1872 length 1, offset 69 + core, width 16,
1876 b43_phy_write(dev
, B43_NPHY_IQLOCAL_CMD
, cmd
);
1877 for (i
= 0; i
< 2000; i
++) {
1878 tmp
= b43_phy_read(dev
, B43_NPHY_IQLOCAL_CMD
);
1884 /* TODO: Read an N PHY Table with ID 15,
1885 length table_length, offset 96, width 16,
1886 and data pointer buffer */
1887 /* TODO: Write an N PHY Table with ID 15,
1888 length table_length, offset 64, width 16,
1889 and data pointer buffer */
1891 if (type
== 1 || type
== 3 || type
== 4)
1892 buffer
[0] = diq_start
;
1896 nphy
->mphase_txcal_cmdidx
= (numb
>= max
) ? 0 : numb
;
1898 last
= (dev
->phy
.rev
< 3) ? 6 : 7;
1900 if (!mphase
|| nphy
->mphase_cal_phase_id
== last
) {
1901 /* TODO: Write an N PHY Table with ID 15, length 4,
1902 offset 96, width 16, and data pointer buffer */
1903 /* TODO: Read an N PHY Table with ID 15, length 4,
1904 offset 80, width 16, and data pointer buffer */
1905 if (dev
->phy
.rev
< 3) {
1911 /* TODO: Write an N PHY Table with ID 15, length 4,
1912 offset 88, width 16, and data pointer buffer */
1913 /* TODO: Read an N PHY Table with ID 15, length 2,
1914 offset 101, width 16, and data pointer buffer*/
1915 /* TODO: Write an N PHY Table with ID 15, length 2,
1916 offset 85, width 16, and data pointer buffer */
1917 /* TODO: Write an N PHY Table with ID 15, length 2,
1918 offset 93, width 16, and data pointer buffer */
1920 if (dev
->phy
.rev
< 3)
1922 /* TODO: Read an N PHY Table with ID 15, length length,
1923 offset 96, width 16, and data pointer
1924 nphy->txiqlocal_bestc */
1925 nphy
->txiqlocal_coeffsvalid
= true;
1926 /* TODO: Set nphy->txiqlocal_chanspec to
1927 the current channel */
1930 if (dev
->phy
.rev
< 3)
1932 /* TODO: Read an N PHY Table with ID 5, length length,
1933 offset 96, width 16, and data pointer
1934 nphy->mphase_txcal_bestcoeffs */
1937 b43_nphy_stop_playback(dev
);
1938 b43_phy_write(dev
, B43_NPHY_IQLOCAL_CMDGCTL
, 0);
1941 b43_nphy_tx_cal_phy_cleanup(dev
);
1942 /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1943 width 16, and data from save */
1945 if (dev
->phy
.rev
< 2 && (!mphase
|| nphy
->mphase_cal_phase_id
== last
))
1946 b43_nphy_tx_iq_workaround(dev
);
1948 if (dev
->phy
.rev
>= 4)
1949 nphy
->hang_avoid
= avoid
;
1951 b43_nphy_stay_in_carrier_search(dev
, false);
1956 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
1957 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev
*dev
,
1958 struct nphy_txgains target
, u8 type
, bool debug
)
1960 struct b43_phy_n
*nphy
= dev
->phy
.n
;
1965 u16 cur_hpf1
, cur_hpf2
, cur_lna
;
1967 enum ieee80211_band band
;
1971 u16 lna
[3] = { 3, 3, 1 };
1972 u16 hpf1
[3] = { 7, 2, 0 };
1973 u16 hpf2
[3] = { 2, 0, 0 };
1977 struct nphy_iqcal_params cal_params
[2];
1978 struct nphy_iq_est est
;
1980 bool playtone
= true;
1983 b43_nphy_stay_in_carrier_search(dev
, 1);
1985 if (dev
->phy
.rev
< 2)
1986 ;/* TODO: Call N PHY Reapply TX Cal Coeffs */
1987 /* TODO: Read an N PHY Table with ID 7, length 2, offset 0x110,
1988 width 16, and data gain_save */
1989 for (i
= 0; i
< 2; i
++) {
1990 b43_nphy_iq_cal_gain_params(dev
, i
, target
, &cal_params
[i
]);
1991 cal_gain
[i
] = cal_params
[i
].cal_gain
;
1993 /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1994 width 16, and data from cal_gain */
1996 for (i
= 0; i
< 2; i
++) {
1998 rfctl
[0] = B43_NPHY_RFCTL_INTC1
;
1999 rfctl
[1] = B43_NPHY_RFCTL_INTC2
;
2000 afectl_core
= B43_NPHY_AFECTL_C1
;
2002 rfctl
[0] = B43_NPHY_RFCTL_INTC2
;
2003 rfctl
[1] = B43_NPHY_RFCTL_INTC1
;
2004 afectl_core
= B43_NPHY_AFECTL_C2
;
2007 tmp
[1] = b43_phy_read(dev
, B43_NPHY_RFSEQCA
);
2008 tmp
[2] = b43_phy_read(dev
, afectl_core
);
2009 tmp
[3] = b43_phy_read(dev
, B43_NPHY_AFECTL_OVER
);
2010 tmp
[4] = b43_phy_read(dev
, rfctl
[0]);
2011 tmp
[5] = b43_phy_read(dev
, rfctl
[1]);
2013 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
,
2014 (u16
)~B43_NPHY_RFSEQCA_RXDIS
,
2015 ((1 - i
) << B43_NPHY_RFSEQCA_RXDIS_SHIFT
));
2016 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
, ~B43_NPHY_RFSEQCA_TXEN
,
2018 b43_phy_set(dev
, afectl_core
, 0x0006);
2019 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER
, 0x0006);
2021 band
= b43_current_band(dev
->wl
);
2023 if (nphy
->rxcalparams
& 0xFF000000) {
2024 if (band
== IEEE80211_BAND_5GHZ
)
2025 b43_phy_write(dev
, rfctl
[0], 0x140);
2027 b43_phy_write(dev
, rfctl
[0], 0x110);
2029 if (band
== IEEE80211_BAND_5GHZ
)
2030 b43_phy_write(dev
, rfctl
[0], 0x180);
2032 b43_phy_write(dev
, rfctl
[0], 0x120);
2035 if (band
== IEEE80211_BAND_5GHZ
)
2036 b43_phy_write(dev
, rfctl
[1], 0x148);
2038 b43_phy_write(dev
, rfctl
[1], 0x114);
2040 if (nphy
->rxcalparams
& 0x10000) {
2041 b43_radio_maskset(dev
, B2055_C1_GENSPARE2
, 0xFC,
2043 b43_radio_maskset(dev
, B2055_C2_GENSPARE2
, 0xFC,
2047 for (j
= 0; i
< 4; j
++) {
2053 if (power
[1] > 10000) {
2058 if (power
[0] > 10000) {
2068 cur_lna
= lna
[index
];
2069 cur_hpf1
= hpf1
[index
];
2070 cur_hpf2
= hpf2
[index
];
2071 cur_hpf
+= desired
- hweight32(power
[index
]);
2072 cur_hpf
= clamp_val(cur_hpf
, 0, 10);
2079 tmp
[0] = ((cur_hpf2
<< 8) | (cur_hpf1
<< 4) |
2081 /* TODO:Call N PHY RF Ctrl Override with 0x400, tmp[0],
2082 3, 0 as arguments */
2083 /* TODO: Call N PHY Force RF Seq with 2 as argument */
2084 b43_nphy_stop_playback(dev
);
2087 /* TODO: Call N PHY TX Tone with 4000,
2088 (nphy_rxcalparams & 0xffff), 0, 0
2089 as arguments and save result as ret */
2092 /* TODO: Call N PHY Run Samples with 160,
2093 0xFFFF, 0, 0, 0 as arguments */
2098 b43_nphy_rx_iq_est(dev
, &est
, 1024, 32,
2107 power
[i
] = ((real
+ imag
) / 1024) + 1;
2109 b43_nphy_calc_rx_iq_comp(dev
, 1 << i
);
2111 b43_nphy_stop_playback(dev
);
2118 b43_radio_mask(dev
, B2055_C1_GENSPARE2
, 0xFC);
2119 b43_radio_mask(dev
, B2055_C2_GENSPARE2
, 0xFC);
2120 b43_phy_write(dev
, rfctl
[1], tmp
[5]);
2121 b43_phy_write(dev
, rfctl
[0], tmp
[4]);
2122 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, tmp
[3]);
2123 b43_phy_write(dev
, afectl_core
, tmp
[2]);
2124 b43_phy_write(dev
, B43_NPHY_RFSEQCA
, tmp
[1]);
2130 /* TODO: Call N PHY RF Ctrl Override with 0x400, 0, 3, 1 as arguments*/
2131 /* TODO: Call N PHY Force RF Seq with 2 as argument */
2132 /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
2133 width 16, and data from gain_save */
2135 b43_nphy_stay_in_carrier_search(dev
, 0);
2140 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev
*dev
,
2141 struct nphy_txgains target
, u8 type
, bool debug
)
2146 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2147 static int b43_nphy_cal_rx_iq(struct b43_wldev
*dev
,
2148 struct nphy_txgains target
, u8 type
, bool debug
)
2150 if (dev
->phy
.rev
>= 3)
2151 return b43_nphy_rev3_cal_rx_iq(dev
, target
, type
, debug
);
2153 return b43_nphy_rev2_cal_rx_iq(dev
, target
, type
, debug
);
2158 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2160 int b43_phy_initn(struct b43_wldev
*dev
)
2162 struct ssb_bus
*bus
= dev
->dev
->bus
;
2163 struct b43_phy
*phy
= &dev
->phy
;
2164 struct b43_phy_n
*nphy
= phy
->n
;
2166 struct nphy_txgains target
;
2168 enum ieee80211_band tmp2
;
2172 bool do_cal
= false;
2174 if ((dev
->phy
.rev
>= 3) &&
2175 (bus
->sprom
.boardflags_lo
& B43_BFL_EXTLNA
) &&
2176 (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)) {
2177 chipco_set32(&dev
->dev
->bus
->chipco
, SSB_CHIPCO_CHIPCTL
, 0x40);
2179 nphy
->deaf_count
= 0;
2180 b43_nphy_tables_init(dev
);
2181 nphy
->crsminpwr_adjusted
= false;
2182 nphy
->noisevars_adjusted
= false;
2184 /* Clear all overrides */
2185 if (dev
->phy
.rev
>= 3) {
2186 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B1S1
, 0);
2187 b43_phy_write(dev
, B43_NPHY_RFCTL_OVER
, 0);
2188 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B1S0
, 0);
2189 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B32S1
, 0);
2191 b43_phy_write(dev
, B43_NPHY_RFCTL_OVER
, 0);
2193 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, 0);
2194 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, 0);
2195 if (dev
->phy
.rev
< 6) {
2196 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC3
, 0);
2197 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC4
, 0);
2199 b43_phy_mask(dev
, B43_NPHY_RFSEQMODE
,
2200 ~(B43_NPHY_RFSEQMODE_CAOVER
|
2201 B43_NPHY_RFSEQMODE_TROVER
));
2202 if (dev
->phy
.rev
>= 3)
2203 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, 0);
2204 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, 0);
2206 if (dev
->phy
.rev
<= 2) {
2207 tmp
= (dev
->phy
.rev
== 2) ? 0x3B : 0x40;
2208 b43_phy_maskset(dev
, B43_NPHY_BPHY_CTL3
,
2209 ~B43_NPHY_BPHY_CTL3_SCALE
,
2210 tmp
<< B43_NPHY_BPHY_CTL3_SCALE_SHIFT
);
2212 b43_phy_write(dev
, B43_NPHY_AFESEQ_TX2RX_PUD_20M
, 0x20);
2213 b43_phy_write(dev
, B43_NPHY_AFESEQ_TX2RX_PUD_40M
, 0x20);
2215 if (bus
->sprom
.boardflags2_lo
& 0x100 ||
2216 (bus
->boardinfo
.vendor
== PCI_VENDOR_ID_APPLE
&&
2217 bus
->boardinfo
.type
== 0x8B))
2218 b43_phy_write(dev
, B43_NPHY_TXREALFD
, 0xA0);
2220 b43_phy_write(dev
, B43_NPHY_TXREALFD
, 0xB8);
2221 b43_phy_write(dev
, B43_NPHY_MIMO_CRSTXEXT
, 0xC8);
2222 b43_phy_write(dev
, B43_NPHY_PLOAD_CSENSE_EXTLEN
, 0x50);
2223 b43_phy_write(dev
, B43_NPHY_TXRIFS_FRDEL
, 0x30);
2225 b43_nphy_update_mimo_config(dev
, nphy
->preamble_override
);
2226 /* TODO Update TX/RX chain */
2229 b43_phy_write(dev
, B43_NPHY_DUP40_GFBL
, 0xAA8);
2230 b43_phy_write(dev
, B43_NPHY_DUP40_BL
, 0x9A4);
2233 tmp2
= b43_current_band(dev
->wl
);
2234 if ((nphy
->ipa2g_on
&& tmp2
== IEEE80211_BAND_2GHZ
) ||
2235 (nphy
->ipa5g_on
&& tmp2
== IEEE80211_BAND_5GHZ
)) {
2236 b43_phy_set(dev
, B43_NPHY_PAPD_EN0
, 0x1);
2237 b43_phy_maskset(dev
, B43_NPHY_EPS_TABLE_ADJ0
, 0x007F,
2238 nphy
->papd_epsilon_offset
[0] << 7);
2239 b43_phy_set(dev
, B43_NPHY_PAPD_EN1
, 0x1);
2240 b43_phy_maskset(dev
, B43_NPHY_EPS_TABLE_ADJ1
, 0x007F,
2241 nphy
->papd_epsilon_offset
[1] << 7);
2242 /* TODO N PHY IPA Set TX Dig Filters */
2243 } else if (phy
->rev
>= 5) {
2244 /* TODO N PHY Ext PA Set TX Dig Filters */
2247 b43_nphy_workarounds(dev
);
2249 /* Reset CCA, in init code it differs a little from standard way */
2250 b43_nphy_bmac_clock_fgc(dev
, 1);
2251 tmp
= b43_phy_read(dev
, B43_NPHY_BBCFG
);
2252 b43_phy_write(dev
, B43_NPHY_BBCFG
, tmp
| B43_NPHY_BBCFG_RSTCCA
);
2253 b43_phy_write(dev
, B43_NPHY_BBCFG
, tmp
& ~B43_NPHY_BBCFG_RSTCCA
);
2254 b43_nphy_bmac_clock_fgc(dev
, 0);
2256 /* TODO N PHY MAC PHY Clock Set with argument 1 */
2258 b43_nphy_pa_override(dev
, false);
2259 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RX2TX
);
2260 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RESET2RX
);
2261 b43_nphy_pa_override(dev
, true);
2263 b43_nphy_classifier(dev
, 0, 0);
2264 b43_nphy_read_clip_detection(dev
, clip
);
2265 tx_pwr_state
= nphy
->txpwrctrl
;
2266 /* TODO N PHY TX power control with argument 0
2267 (turning off power control) */
2268 /* TODO Fix the TX Power Settings */
2269 /* TODO N PHY TX Power Control Idle TSSI */
2270 /* TODO N PHY TX Power Control Setup */
2272 if (phy
->rev
>= 3) {
2275 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
2276 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
2279 if (nphy
->phyrxchain
!= 3)
2280 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
2281 if (nphy
->mphase_cal_phase_id
> 0)
2282 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
2284 do_rssi_cal
= false;
2285 if (phy
->rev
>= 3) {
2286 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
2287 do_rssi_cal
= (nphy
->rssical_chanspec_2G
== 0);
2289 do_rssi_cal
= (nphy
->rssical_chanspec_5G
== 0);
2292 b43_nphy_rssi_cal(dev
);
2294 b43_nphy_restore_rssi_cal(dev
);
2296 b43_nphy_rssi_cal(dev
);
2299 if (!((nphy
->measure_hold
& 0x6) != 0)) {
2300 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
2301 do_cal
= (nphy
->iqcal_chanspec_2G
== 0);
2303 do_cal
= (nphy
->iqcal_chanspec_5G
== 0);
2309 target
= b43_nphy_get_tx_gains(dev
);
2311 if (nphy
->antsel_type
== 2)
2312 ;/*TODO NPHY Superswitch Init with argument 1*/
2313 if (nphy
->perical
!= 2) {
2314 b43_nphy_rssi_cal(dev
);
2315 if (phy
->rev
>= 3) {
2316 nphy
->cal_orig_pwr_idx
[0] =
2317 nphy
->txpwrindex
[0].index_internal
;
2318 nphy
->cal_orig_pwr_idx
[1] =
2319 nphy
->txpwrindex
[1].index_internal
;
2320 /* TODO N PHY Pre Calibrate TX Gain */
2321 target
= b43_nphy_get_tx_gains(dev
);
2327 if (!b43_nphy_cal_tx_iq_lo(dev
, target
, true, false)) {
2328 if (b43_nphy_cal_rx_iq(dev
, target
, 2, 0) == 0)
2329 ;/* Call N PHY Save Cal */
2330 else if (nphy
->mphase_cal_phase_id
== 0)
2331 ;/* N PHY Periodic Calibration with argument 3 */
2333 b43_nphy_restore_cal(dev
);
2336 b43_nphy_tx_pwr_ctrl_coef_setup(dev
);
2337 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
2338 b43_phy_write(dev
, B43_NPHY_TXMACIF_HOLDOFF
, 0x0015);
2339 b43_phy_write(dev
, B43_NPHY_TXMACDELAY
, 0x0320);
2340 if (phy
->rev
>= 3 && phy
->rev
<= 6)
2341 b43_phy_write(dev
, B43_NPHY_PLOAD_CSENSE_EXTLEN
, 0x0014);
2342 b43_nphy_tx_lp_fbw(dev
);
2343 /* TODO N PHY Spur Workaround */
2345 b43err(dev
->wl
, "IEEE 802.11n devices are not supported, yet.\n");
2349 static int b43_nphy_op_allocate(struct b43_wldev
*dev
)
2351 struct b43_phy_n
*nphy
;
2353 nphy
= kzalloc(sizeof(*nphy
), GFP_KERNEL
);
2361 static void b43_nphy_op_prepare_structs(struct b43_wldev
*dev
)
2363 struct b43_phy
*phy
= &dev
->phy
;
2364 struct b43_phy_n
*nphy
= phy
->n
;
2366 memset(nphy
, 0, sizeof(*nphy
));
2368 //TODO init struct b43_phy_n
2371 static void b43_nphy_op_free(struct b43_wldev
*dev
)
2373 struct b43_phy
*phy
= &dev
->phy
;
2374 struct b43_phy_n
*nphy
= phy
->n
;
2380 static int b43_nphy_op_init(struct b43_wldev
*dev
)
2382 return b43_phy_initn(dev
);
2385 static inline void check_phyreg(struct b43_wldev
*dev
, u16 offset
)
2388 if ((offset
& B43_PHYROUTE
) == B43_PHYROUTE_OFDM_GPHY
) {
2389 /* OFDM registers are onnly available on A/G-PHYs */
2390 b43err(dev
->wl
, "Invalid OFDM PHY access at "
2391 "0x%04X on N-PHY\n", offset
);
2394 if ((offset
& B43_PHYROUTE
) == B43_PHYROUTE_EXT_GPHY
) {
2395 /* Ext-G registers are only available on G-PHYs */
2396 b43err(dev
->wl
, "Invalid EXT-G PHY access at "
2397 "0x%04X on N-PHY\n", offset
);
2400 #endif /* B43_DEBUG */
2403 static u16
b43_nphy_op_read(struct b43_wldev
*dev
, u16 reg
)
2405 check_phyreg(dev
, reg
);
2406 b43_write16(dev
, B43_MMIO_PHY_CONTROL
, reg
);
2407 return b43_read16(dev
, B43_MMIO_PHY_DATA
);
2410 static void b43_nphy_op_write(struct b43_wldev
*dev
, u16 reg
, u16 value
)
2412 check_phyreg(dev
, reg
);
2413 b43_write16(dev
, B43_MMIO_PHY_CONTROL
, reg
);
2414 b43_write16(dev
, B43_MMIO_PHY_DATA
, value
);
2417 static u16
b43_nphy_op_radio_read(struct b43_wldev
*dev
, u16 reg
)
2419 /* Register 1 is a 32-bit register. */
2420 B43_WARN_ON(reg
== 1);
2421 /* N-PHY needs 0x100 for read access */
2424 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, reg
);
2425 return b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
2428 static void b43_nphy_op_radio_write(struct b43_wldev
*dev
, u16 reg
, u16 value
)
2430 /* Register 1 is a 32-bit register. */
2431 B43_WARN_ON(reg
== 1);
2433 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, reg
);
2434 b43_write16(dev
, B43_MMIO_RADIO_DATA_LOW
, value
);
2437 static void b43_nphy_op_software_rfkill(struct b43_wldev
*dev
,
2442 static void b43_nphy_op_switch_analog(struct b43_wldev
*dev
, bool on
)
2444 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
,
2448 static int b43_nphy_op_switch_channel(struct b43_wldev
*dev
,
2449 unsigned int new_channel
)
2451 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
2452 if ((new_channel
< 1) || (new_channel
> 14))
2455 if (new_channel
> 200)
2459 return nphy_channel_switch(dev
, new_channel
);
2462 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev
*dev
)
2464 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
2469 const struct b43_phy_operations b43_phyops_n
= {
2470 .allocate
= b43_nphy_op_allocate
,
2471 .free
= b43_nphy_op_free
,
2472 .prepare_structs
= b43_nphy_op_prepare_structs
,
2473 .init
= b43_nphy_op_init
,
2474 .phy_read
= b43_nphy_op_read
,
2475 .phy_write
= b43_nphy_op_write
,
2476 .radio_read
= b43_nphy_op_radio_read
,
2477 .radio_write
= b43_nphy_op_radio_write
,
2478 .software_rfkill
= b43_nphy_op_software_rfkill
,
2479 .switch_analog
= b43_nphy_op_switch_analog
,
2480 .switch_channel
= b43_nphy_op_switch_channel
,
2481 .get_default_chan
= b43_nphy_op_get_default_chan
,
2482 .recalc_txpower
= b43_nphy_op_recalc_txpower
,
2483 .adjust_txpower
= b43_nphy_op_adjust_txpower
,