2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.14"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66 #define RX_SKB_ALIGN 8
67 #define RX_BUF_WRITE 16
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82 static const u32 default_msg
=
83 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
84 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
87 static int debug
= -1; /* defaults above */
88 module_param(debug
, int, 0);
89 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
91 static int copybreak __read_mostly
= 128;
92 module_param(copybreak
, int, 0);
93 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
95 static int disable_msi
= 0;
96 module_param(disable_msi
, int, 0);
97 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
99 static int idle_timeout
= 0;
100 module_param(idle_timeout
, int, 0);
101 MODULE_PARM_DESC(idle_timeout
, "Watchdog timer for lost interrupts (ms)");
103 static const struct pci_device_id sky2_id_table
[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
133 // { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
137 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
139 /* Avoid conditionals by using array */
140 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
141 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
142 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
144 /* This driver supports yukon2 chipset only */
145 static const char *yukon2_name
[] = {
147 "EC Ultra", /* 0xb4 */
148 "Extreme", /* 0xb5 */
153 /* Access to external PHY */
154 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
158 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
159 gma_write16(hw
, port
, GM_SMI_CTRL
,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
162 for (i
= 0; i
< PHY_RETRIES
; i
++) {
163 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
168 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
172 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
176 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
177 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
179 for (i
= 0; i
< PHY_RETRIES
; i
++) {
180 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
181 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
191 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
195 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
196 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
201 static void sky2_power_on(struct sky2_hw
*hw
)
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw
, B0_POWER_CTRL
,
205 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
207 /* disable Core Clock Division, */
208 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
210 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
211 /* enable bits are inverted */
212 sky2_write8(hw
, B2_Y2_CLK_GATE
,
213 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
214 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
215 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
217 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
219 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
222 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
223 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
224 reg1
&= P_ASPM_CONTROL_MSK
;
225 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
226 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
230 static void sky2_power_aux(struct sky2_hw
*hw
)
232 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
233 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
235 /* enable bits are inverted */
236 sky2_write8(hw
, B2_Y2_CLK_GATE
,
237 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
238 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
239 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
241 /* switch power to VAUX */
242 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
243 sky2_write8(hw
, B0_POWER_CTRL
,
244 (PC_VAUX_ENA
| PC_VCC_ENA
|
245 PC_VAUX_ON
| PC_VCC_OFF
));
248 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
252 /* disable all GMAC IRQ's */
253 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
254 /* disable PHY IRQs */
255 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
257 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
258 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
259 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
260 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
262 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
263 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
264 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
267 /* flow control to advertise bits */
268 static const u16 copper_fc_adv
[] = {
270 [FC_TX
] = PHY_M_AN_ASP
,
271 [FC_RX
] = PHY_M_AN_PC
,
272 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
275 /* flow control to advertise bits when using 1000BaseX */
276 static const u16 fiber_fc_adv
[] = {
277 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
278 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
279 [FC_RX
] = PHY_M_P_SYM_MD_X
,
280 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
283 /* flow control to GMA disable bits */
284 static const u16 gm_fc_disable
[] = {
285 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
286 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
287 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
292 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
294 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
295 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
297 if (sky2
->autoneg
== AUTONEG_ENABLE
298 && !(hw
->chip_id
== CHIP_ID_YUKON_XL
299 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
300 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
301 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
303 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
305 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
307 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
308 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
309 /* set downshift counter to 3x and enable downshift */
310 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
312 /* set master & slave downshift counter to 1x */
313 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
315 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
318 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
319 if (sky2_is_copper(hw
)) {
320 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
321 /* enable automatic crossover */
322 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
324 /* disable energy detect */
325 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
327 /* enable automatic crossover */
328 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
330 /* downshift on PHY 88E1112 and 88E1149 is changed */
331 if (sky2
->autoneg
== AUTONEG_ENABLE
332 && (hw
->chip_id
== CHIP_ID_YUKON_XL
333 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
334 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
335 /* set downshift counter to 3x and enable downshift */
336 ctrl
&= ~PHY_M_PC_DSC_MSK
;
337 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
341 /* workaround for deviation #4.88 (CRC errors) */
342 /* disable Automatic Crossover */
344 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
347 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
349 /* special setup for PHY 88E1112 Fiber */
350 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& !sky2_is_copper(hw
)) {
351 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
353 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
354 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
355 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
356 ctrl
&= ~PHY_M_MAC_MD_MSK
;
357 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
358 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
360 if (hw
->pmd_type
== 'P') {
361 /* select page 1 to access Fiber registers */
362 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
364 /* for SFP-module set SIGDET polarity to low */
365 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
366 ctrl
|= PHY_M_FIB_SIGD_POL
;
367 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
370 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
378 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
379 if (sky2_is_copper(hw
)) {
380 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
381 ct1000
|= PHY_M_1000C_AFD
;
382 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
383 ct1000
|= PHY_M_1000C_AHD
;
384 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
385 adv
|= PHY_M_AN_100_FD
;
386 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
387 adv
|= PHY_M_AN_100_HD
;
388 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
389 adv
|= PHY_M_AN_10_FD
;
390 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
391 adv
|= PHY_M_AN_10_HD
;
393 adv
|= copper_fc_adv
[sky2
->flow_mode
];
394 } else { /* special defines for FIBER (88E1040S only) */
395 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
396 adv
|= PHY_M_AN_1000X_AFD
;
397 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
398 adv
|= PHY_M_AN_1000X_AHD
;
400 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
403 /* Restart Auto-negotiation */
404 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
406 /* forced speed/duplex settings */
407 ct1000
= PHY_M_1000C_MSE
;
409 /* Disable auto update for duplex flow control and speed */
410 reg
|= GM_GPCR_AU_ALL_DIS
;
412 switch (sky2
->speed
) {
414 ctrl
|= PHY_CT_SP1000
;
415 reg
|= GM_GPCR_SPEED_1000
;
418 ctrl
|= PHY_CT_SP100
;
419 reg
|= GM_GPCR_SPEED_100
;
423 if (sky2
->duplex
== DUPLEX_FULL
) {
424 reg
|= GM_GPCR_DUP_FULL
;
425 ctrl
|= PHY_CT_DUP_MD
;
426 } else if (sky2
->speed
< SPEED_1000
)
427 sky2
->flow_mode
= FC_NONE
;
430 reg
|= gm_fc_disable
[sky2
->flow_mode
];
432 /* Forward pause packets to GMAC? */
433 if (sky2
->flow_mode
& FC_RX
)
434 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
436 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
439 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
441 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
442 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
444 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
445 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
447 /* Setup Phy LED's */
448 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
451 switch (hw
->chip_id
) {
452 case CHIP_ID_YUKON_FE
:
453 /* on 88E3082 these bits are at 11..9 (shifted left) */
454 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
456 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
458 /* delete ACT LED control bits */
459 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
460 /* change ACT LED control to blink mode */
461 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
462 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
465 case CHIP_ID_YUKON_XL
:
466 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
468 /* select page 3 to access LED control register */
469 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
471 /* set LED Function Control register */
472 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
473 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
474 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
475 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
476 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
478 /* set Polarity Control register */
479 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
480 (PHY_M_POLC_LS1_P_MIX(4) |
481 PHY_M_POLC_IS0_P_MIX(4) |
482 PHY_M_POLC_LOS_CTRL(2) |
483 PHY_M_POLC_INIT_CTRL(2) |
484 PHY_M_POLC_STA1_CTRL(2) |
485 PHY_M_POLC_STA0_CTRL(2)));
487 /* restore page register */
488 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
491 case CHIP_ID_YUKON_EC_U
:
492 case CHIP_ID_YUKON_EX
:
493 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
495 /* select page 3 to access LED control register */
496 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
498 /* set LED Function Control register */
499 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
500 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
501 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
502 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
503 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
505 /* set Blink Rate in LED Timer Control Register */
506 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
507 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
508 /* restore page register */
509 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
513 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
514 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
515 /* turn off the Rx LED (LED_RX) */
516 ledover
&= ~PHY_M_LED_MO_RX
;
519 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
520 hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
) {
521 /* apply fixes in PHY AFE */
522 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
524 /* increase differential signal amplitude in 10BASE-T */
525 gm_phy_write(hw
, port
, 0x18, 0xaa99);
526 gm_phy_write(hw
, port
, 0x17, 0x2011);
528 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
529 gm_phy_write(hw
, port
, 0x18, 0xa204);
530 gm_phy_write(hw
, port
, 0x17, 0x2002);
532 /* set page register to 0 */
533 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
534 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
535 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
537 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
538 /* turn on 100 Mbps LED (LED_LINK100) */
539 ledover
|= PHY_M_LED_MO_100
;
543 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
547 /* Enable phy interrupt on auto-negotiation complete (or link up) */
548 if (sky2
->autoneg
== AUTONEG_ENABLE
)
549 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
551 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
554 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
557 static const u32 phy_power
[]
558 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
560 /* looks like this XL is back asswards .. */
561 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
564 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
565 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
567 /* Turn off phy power saving */
568 reg1
&= ~phy_power
[port
];
570 reg1
|= phy_power
[port
];
572 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
573 sky2_pci_read32(hw
, PCI_DEV_REG1
);
574 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
578 /* Force a renegotiation */
579 static void sky2_phy_reinit(struct sky2_port
*sky2
)
581 spin_lock_bh(&sky2
->phy_lock
);
582 sky2_phy_init(sky2
->hw
, sky2
->port
);
583 spin_unlock_bh(&sky2
->phy_lock
);
586 /* Put device in state to listen for Wake On Lan */
587 static void sky2_wol_init(struct sky2_port
*sky2
)
589 struct sky2_hw
*hw
= sky2
->hw
;
590 unsigned port
= sky2
->port
;
591 enum flow_control save_mode
;
595 /* Bring hardware out of reset */
596 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
597 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
599 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
600 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
603 * sky2_reset will re-enable on resume
605 save_mode
= sky2
->flow_mode
;
606 ctrl
= sky2
->advertising
;
608 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
609 sky2
->flow_mode
= FC_NONE
;
610 sky2_phy_power(hw
, port
, 1);
611 sky2_phy_reinit(sky2
);
613 sky2
->flow_mode
= save_mode
;
614 sky2
->advertising
= ctrl
;
616 /* Set GMAC to no flow control and auto update for speed/duplex */
617 gma_write16(hw
, port
, GM_GP_CTRL
,
618 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
619 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
621 /* Set WOL address */
622 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
623 sky2
->netdev
->dev_addr
, ETH_ALEN
);
625 /* Turn on appropriate WOL control bits */
626 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
628 if (sky2
->wol
& WAKE_PHY
)
629 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
631 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
633 if (sky2
->wol
& WAKE_MAGIC
)
634 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
636 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
638 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
639 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
641 /* Turn on legacy PCI-Express PME mode */
642 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
643 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
644 reg1
|= PCI_Y2_PME_LEGACY
;
645 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
646 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
649 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
653 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
655 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
658 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
660 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
661 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
663 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
665 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
666 /* WA DEV_472 -- looks like crossed wires on port 2 */
667 /* clear GMAC 1 Control reset */
668 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
670 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
671 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
672 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
673 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
674 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
677 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
679 /* Enable Transmit FIFO Underrun */
680 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
682 spin_lock_bh(&sky2
->phy_lock
);
683 sky2_phy_init(hw
, port
);
684 spin_unlock_bh(&sky2
->phy_lock
);
687 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
688 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
690 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
691 gma_read16(hw
, port
, i
);
692 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
694 /* transmit control */
695 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
697 /* receive control reg: unicast + multicast + no FCS */
698 gma_write16(hw
, port
, GM_RX_CTRL
,
699 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
701 /* transmit flow control */
702 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
704 /* transmit parameter */
705 gma_write16(hw
, port
, GM_TX_PARAM
,
706 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
707 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
708 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
709 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
711 /* serial mode register */
712 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
713 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
715 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
716 reg
|= GM_SMOD_JUMBO_ENA
;
718 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
720 /* virtual address for data */
721 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
723 /* physical address: used for pause frames */
724 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
726 /* ignore counter overflows */
727 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
728 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
729 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
731 /* Configure Rx MAC FIFO */
732 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
733 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
734 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
736 /* Flush Rx MAC FIFO on any flow control or error */
737 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
739 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
740 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
742 /* Configure Tx MAC FIFO */
743 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
744 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
746 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
747 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
748 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
750 /* set Tx GMAC FIFO Almost Empty Threshold */
751 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
752 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
754 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
755 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
756 TX_JUMBO_ENA
| TX_STFW_DIS
);
758 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
759 TX_JUMBO_DIS
| TX_STFW_ENA
);
764 /* Assign Ram Buffer allocation to queue */
765 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
769 /* convert from K bytes to qwords used for hw register */
772 end
= start
+ space
- 1;
774 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
775 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
776 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
777 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
778 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
780 if (q
== Q_R1
|| q
== Q_R2
) {
781 u32 tp
= space
- space
/4;
783 /* On receive queue's set the thresholds
784 * give receiver priority when > 3/4 full
785 * send pause when down to 2K
787 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
788 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
791 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
792 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
794 /* Enable store & forward on Tx queue's because
795 * Tx FIFO is only 1K on Yukon
797 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
800 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
801 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
804 /* Setup Bus Memory Interface */
805 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
807 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
808 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
809 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
810 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
813 /* Setup prefetch unit registers. This is the interface between
814 * hardware and driver list elements
816 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
819 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
820 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
821 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
822 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
823 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
824 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
826 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
829 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
831 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
833 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
838 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
839 struct sky2_tx_le
*le
)
841 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
844 /* Update chip's next pointer */
845 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
847 q
= Y2_QADDR(q
, PREF_UNIT_PUT_IDX
);
849 sky2_write16(hw
, q
, idx
);
854 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
856 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
857 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
862 /* Return high part of DMA address (could be 32 or 64 bit) */
863 static inline u32
high32(dma_addr_t a
)
865 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
868 /* Build description to hardware for one receive segment */
869 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
870 dma_addr_t map
, unsigned len
)
872 struct sky2_rx_le
*le
;
873 u32 hi
= high32(map
);
875 if (sky2
->rx_addr64
!= hi
) {
876 le
= sky2_next_rx(sky2
);
877 le
->addr
= cpu_to_le32(hi
);
878 le
->opcode
= OP_ADDR64
| HW_OWNER
;
879 sky2
->rx_addr64
= high32(map
+ len
);
882 le
= sky2_next_rx(sky2
);
883 le
->addr
= cpu_to_le32((u32
) map
);
884 le
->length
= cpu_to_le16(len
);
885 le
->opcode
= op
| HW_OWNER
;
888 /* Build description to hardware for one possibly fragmented skb */
889 static void sky2_rx_submit(struct sky2_port
*sky2
,
890 const struct rx_ring_info
*re
)
894 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
896 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
897 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
901 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
904 struct sk_buff
*skb
= re
->skb
;
907 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
908 pci_unmap_len_set(re
, data_size
, size
);
910 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
911 re
->frag_addr
[i
] = pci_map_page(pdev
,
912 skb_shinfo(skb
)->frags
[i
].page
,
913 skb_shinfo(skb
)->frags
[i
].page_offset
,
914 skb_shinfo(skb
)->frags
[i
].size
,
918 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
920 struct sk_buff
*skb
= re
->skb
;
923 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
926 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
927 pci_unmap_page(pdev
, re
->frag_addr
[i
],
928 skb_shinfo(skb
)->frags
[i
].size
,
932 /* Tell chip where to start receive checksum.
933 * Actually has two checksums, but set both same to avoid possible byte
936 static void rx_set_checksum(struct sky2_port
*sky2
)
938 struct sky2_rx_le
*le
;
940 le
= sky2_next_rx(sky2
);
941 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
943 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
945 sky2_write32(sky2
->hw
,
946 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
947 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
952 * The RX Stop command will not work for Yukon-2 if the BMU does not
953 * reach the end of packet and since we can't make sure that we have
954 * incoming data, we must reset the BMU while it is not doing a DMA
955 * transfer. Since it is possible that the RX path is still active,
956 * the RX RAM buffer will be stopped first, so any possible incoming
957 * data will not trigger a DMA. After the RAM buffer is stopped, the
958 * BMU is polled until any DMA in progress is ended and only then it
961 static void sky2_rx_stop(struct sky2_port
*sky2
)
963 struct sky2_hw
*hw
= sky2
->hw
;
964 unsigned rxq
= rxqaddr
[sky2
->port
];
967 /* disable the RAM Buffer receive queue */
968 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
970 for (i
= 0; i
< 0xffff; i
++)
971 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
972 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
975 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
978 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
980 /* reset the Rx prefetch unit */
981 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
984 /* Clean out receive buffer area, assumes receiver hardware stopped */
985 static void sky2_rx_clean(struct sky2_port
*sky2
)
989 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
990 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
991 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
994 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1001 /* Basic MII support */
1002 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1004 struct mii_ioctl_data
*data
= if_mii(ifr
);
1005 struct sky2_port
*sky2
= netdev_priv(dev
);
1006 struct sky2_hw
*hw
= sky2
->hw
;
1007 int err
= -EOPNOTSUPP
;
1009 if (!netif_running(dev
))
1010 return -ENODEV
; /* Phy still in reset */
1014 data
->phy_id
= PHY_ADDR_MARV
;
1020 spin_lock_bh(&sky2
->phy_lock
);
1021 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1022 spin_unlock_bh(&sky2
->phy_lock
);
1024 data
->val_out
= val
;
1029 if (!capable(CAP_NET_ADMIN
))
1032 spin_lock_bh(&sky2
->phy_lock
);
1033 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1035 spin_unlock_bh(&sky2
->phy_lock
);
1041 #ifdef SKY2_VLAN_TAG_USED
1042 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1044 struct sky2_port
*sky2
= netdev_priv(dev
);
1045 struct sky2_hw
*hw
= sky2
->hw
;
1046 u16 port
= sky2
->port
;
1048 netif_tx_lock_bh(dev
);
1050 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
1051 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
1054 netif_tx_unlock_bh(dev
);
1057 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
1059 struct sky2_port
*sky2
= netdev_priv(dev
);
1060 struct sky2_hw
*hw
= sky2
->hw
;
1061 u16 port
= sky2
->port
;
1063 netif_tx_lock_bh(dev
);
1065 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
1066 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
1067 vlan_group_set_device(sky2
->vlgrp
, vid
, NULL
);
1069 netif_tx_unlock_bh(dev
);
1074 * Allocate an skb for receiving. If the MTU is large enough
1075 * make the skb non-linear with a fragment list of pages.
1077 * It appears the hardware has a bug in the FIFO logic that
1078 * cause it to hang if the FIFO gets overrun and the receive buffer
1079 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1080 * aligned except if slab debugging is enabled.
1082 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1084 struct sk_buff
*skb
;
1088 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ RX_SKB_ALIGN
);
1092 p
= (unsigned long) skb
->data
;
1093 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
1095 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1096 struct page
*page
= alloc_page(GFP_ATOMIC
);
1100 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1111 * Allocate and setup receiver buffer pool.
1112 * Normal case this ends up creating one list element for skb
1113 * in the receive ring. Worst case if using large MTU and each
1114 * allocation falls on a different 64 bit region, that results
1115 * in 6 list elements per ring entry.
1116 * One element is used for checksum enable/disable, and one
1117 * extra to avoid wrap.
1119 static int sky2_rx_start(struct sky2_port
*sky2
)
1121 struct sky2_hw
*hw
= sky2
->hw
;
1122 struct rx_ring_info
*re
;
1123 unsigned rxq
= rxqaddr
[sky2
->port
];
1124 unsigned i
, size
, space
, thresh
;
1126 sky2
->rx_put
= sky2
->rx_next
= 0;
1129 /* On PCI express lowering the watermark gives better performance */
1130 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1131 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1133 /* These chips have no ram buffer?
1134 * MAC Rx RAM Read is controlled by hardware */
1135 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1136 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1137 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1138 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
1140 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1142 rx_set_checksum(sky2
);
1144 /* Space needed for frame data + headers rounded up */
1145 size
= ALIGN(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8)
1148 /* Stopping point for hardware truncation */
1149 thresh
= (size
- 8) / sizeof(u32
);
1151 /* Account for overhead of skb - to avoid order > 0 allocation */
1152 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1153 + sizeof(struct skb_shared_info
);
1155 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1156 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1158 if (sky2
->rx_nfrags
!= 0) {
1159 /* Compute residue after pages */
1160 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1167 /* Optimize to handle small packets and headers */
1168 if (size
< copybreak
)
1170 if (size
< ETH_HLEN
)
1173 sky2
->rx_data_size
= size
;
1176 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1177 re
= sky2
->rx_ring
+ i
;
1179 re
->skb
= sky2_rx_alloc(sky2
);
1183 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1184 sky2_rx_submit(sky2
, re
);
1188 * The receiver hangs if it receives frames larger than the
1189 * packet buffer. As a workaround, truncate oversize frames, but
1190 * the register is limited to 9 bits, so if you do frames > 2052
1191 * you better get the MTU right!
1194 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1196 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1197 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1200 /* Tell chip about available buffers */
1201 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1204 sky2_rx_clean(sky2
);
1208 /* Bring up network interface. */
1209 static int sky2_up(struct net_device
*dev
)
1211 struct sky2_port
*sky2
= netdev_priv(dev
);
1212 struct sky2_hw
*hw
= sky2
->hw
;
1213 unsigned port
= sky2
->port
;
1215 int cap
, err
= -ENOMEM
;
1216 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1219 * On dual port PCI-X card, there is an problem where status
1220 * can be received out of order due to split transactions
1222 if (otherdev
&& netif_running(otherdev
) &&
1223 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1224 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1227 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1228 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1229 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1235 if (netif_msg_ifup(sky2
))
1236 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1238 /* must be power of 2 */
1239 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1241 sizeof(struct sky2_tx_le
),
1246 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1250 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1252 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1256 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1258 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1263 sky2_phy_power(hw
, port
, 1);
1265 sky2_mac_init(hw
, port
);
1267 /* Register is number of 4K blocks on internal RAM buffer. */
1268 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1269 printk(KERN_INFO PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1275 rxspace
= ramsize
/ 2;
1277 rxspace
= 8 + (2*(ramsize
- 16))/3;
1279 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1280 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1282 /* Make sure SyncQ is disabled */
1283 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1287 sky2_qset(hw
, txqaddr
[port
]);
1289 /* Set almost empty threshold */
1290 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1291 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1292 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1294 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1297 err
= sky2_rx_start(sky2
);
1301 /* Enable interrupts from phy/mac for port */
1302 imask
= sky2_read32(hw
, B0_IMSK
);
1303 imask
|= portirq_msk
[port
];
1304 sky2_write32(hw
, B0_IMSK
, imask
);
1310 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1311 sky2
->rx_le
, sky2
->rx_le_map
);
1315 pci_free_consistent(hw
->pdev
,
1316 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1317 sky2
->tx_le
, sky2
->tx_le_map
);
1320 kfree(sky2
->tx_ring
);
1321 kfree(sky2
->rx_ring
);
1323 sky2
->tx_ring
= NULL
;
1324 sky2
->rx_ring
= NULL
;
1328 /* Modular subtraction in ring */
1329 static inline int tx_dist(unsigned tail
, unsigned head
)
1331 return (head
- tail
) & (TX_RING_SIZE
- 1);
1334 /* Number of list elements available for next tx */
1335 static inline int tx_avail(const struct sky2_port
*sky2
)
1337 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1340 /* Estimate of number of transmit list elements required */
1341 static unsigned tx_le_req(const struct sk_buff
*skb
)
1345 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1346 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1348 if (skb_is_gso(skb
))
1351 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1358 * Put one packet in ring for transmit.
1359 * A single packet can generate multiple list elements, and
1360 * the number of ring elements will probably be less than the number
1361 * of list elements used.
1363 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1365 struct sky2_port
*sky2
= netdev_priv(dev
);
1366 struct sky2_hw
*hw
= sky2
->hw
;
1367 struct sky2_tx_le
*le
= NULL
;
1368 struct tx_ring_info
*re
;
1375 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1376 return NETDEV_TX_BUSY
;
1378 if (unlikely(netif_msg_tx_queued(sky2
)))
1379 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1380 dev
->name
, sky2
->tx_prod
, skb
->len
);
1382 len
= skb_headlen(skb
);
1383 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1384 addr64
= high32(mapping
);
1386 /* Send high bits if changed or crosses boundary */
1387 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1388 le
= get_tx_le(sky2
);
1389 le
->addr
= cpu_to_le32(addr64
);
1390 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1391 sky2
->tx_addr64
= high32(mapping
+ len
);
1394 /* Check for TCP Segmentation Offload */
1395 mss
= skb_shinfo(skb
)->gso_size
;
1397 mss
+= tcp_optlen(skb
); /* TCP options */
1398 mss
+= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
1401 if (mss
!= sky2
->tx_last_mss
) {
1402 le
= get_tx_le(sky2
);
1403 le
->addr
= cpu_to_le32(mss
);
1404 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1405 sky2
->tx_last_mss
= mss
;
1410 #ifdef SKY2_VLAN_TAG_USED
1411 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1412 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1414 le
= get_tx_le(sky2
);
1416 le
->opcode
= OP_VLAN
|HW_OWNER
;
1418 le
->opcode
|= OP_VLAN
;
1419 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1424 /* Handle TCP checksum offload */
1425 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1426 const unsigned offset
= skb_transport_offset(skb
);
1429 tcpsum
= offset
<< 16; /* sum start */
1430 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1432 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1433 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1436 if (tcpsum
!= sky2
->tx_tcpsum
) {
1437 sky2
->tx_tcpsum
= tcpsum
;
1439 le
= get_tx_le(sky2
);
1440 le
->addr
= cpu_to_le32(tcpsum
);
1441 le
->length
= 0; /* initial checksum value */
1442 le
->ctrl
= 1; /* one packet */
1443 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1447 le
= get_tx_le(sky2
);
1448 le
->addr
= cpu_to_le32((u32
) mapping
);
1449 le
->length
= cpu_to_le16(len
);
1451 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1453 re
= tx_le_re(sky2
, le
);
1455 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1456 pci_unmap_len_set(re
, maplen
, len
);
1458 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1459 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1461 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1462 frag
->size
, PCI_DMA_TODEVICE
);
1463 addr64
= high32(mapping
);
1464 if (addr64
!= sky2
->tx_addr64
) {
1465 le
= get_tx_le(sky2
);
1466 le
->addr
= cpu_to_le32(addr64
);
1468 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1469 sky2
->tx_addr64
= addr64
;
1472 le
= get_tx_le(sky2
);
1473 le
->addr
= cpu_to_le32((u32
) mapping
);
1474 le
->length
= cpu_to_le16(frag
->size
);
1476 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1478 re
= tx_le_re(sky2
, le
);
1480 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1481 pci_unmap_len_set(re
, maplen
, frag
->size
);
1486 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1487 netif_stop_queue(dev
);
1489 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1491 dev
->trans_start
= jiffies
;
1492 return NETDEV_TX_OK
;
1496 * Free ring elements from starting at tx_cons until "done"
1498 * NB: the hardware will tell us about partial completion of multi-part
1499 * buffers so make sure not to free skb to early.
1501 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1503 struct net_device
*dev
= sky2
->netdev
;
1504 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1507 BUG_ON(done
>= TX_RING_SIZE
);
1509 for (idx
= sky2
->tx_cons
; idx
!= done
;
1510 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1511 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1512 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1514 switch(le
->opcode
& ~HW_OWNER
) {
1517 pci_unmap_single(pdev
,
1518 pci_unmap_addr(re
, mapaddr
),
1519 pci_unmap_len(re
, maplen
),
1523 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1524 pci_unmap_len(re
, maplen
),
1529 if (le
->ctrl
& EOP
) {
1530 if (unlikely(netif_msg_tx_done(sky2
)))
1531 printk(KERN_DEBUG
"%s: tx done %u\n",
1533 sky2
->net_stats
.tx_packets
++;
1534 sky2
->net_stats
.tx_bytes
+= re
->skb
->len
;
1536 dev_kfree_skb_any(re
->skb
);
1539 le
->opcode
= 0; /* paranoia */
1542 sky2
->tx_cons
= idx
;
1543 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1544 netif_wake_queue(dev
);
1547 /* Cleanup all untransmitted buffers, assume transmitter not running */
1548 static void sky2_tx_clean(struct net_device
*dev
)
1550 struct sky2_port
*sky2
= netdev_priv(dev
);
1552 netif_tx_lock_bh(dev
);
1553 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1554 netif_tx_unlock_bh(dev
);
1557 /* Network shutdown */
1558 static int sky2_down(struct net_device
*dev
)
1560 struct sky2_port
*sky2
= netdev_priv(dev
);
1561 struct sky2_hw
*hw
= sky2
->hw
;
1562 unsigned port
= sky2
->port
;
1566 /* Never really got started! */
1570 if (netif_msg_ifdown(sky2
))
1571 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1573 /* Stop more packets from being queued */
1574 netif_stop_queue(dev
);
1575 netif_carrier_off(dev
);
1577 /* Disable port IRQ */
1578 imask
= sky2_read32(hw
, B0_IMSK
);
1579 imask
&= ~portirq_msk
[port
];
1580 sky2_write32(hw
, B0_IMSK
, imask
);
1583 * Both ports share the NAPI poll on port 0, so if necessary undo the
1584 * the disable that is done in dev_close.
1586 if (sky2
->port
== 0 && hw
->ports
> 1)
1587 netif_poll_enable(dev
);
1589 sky2_gmac_reset(hw
, port
);
1591 /* Stop transmitter */
1592 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1593 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1595 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1596 RB_RST_SET
| RB_DIS_OP_MD
);
1598 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1599 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1600 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1602 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1604 /* Workaround shared GMAC reset */
1605 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1606 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1607 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1609 /* Disable Force Sync bit and Enable Alloc bit */
1610 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1611 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1613 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1614 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1615 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1617 /* Reset the PCI FIFO of the async Tx queue */
1618 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1619 BMU_RST_SET
| BMU_FIFO_RST
);
1621 /* Reset the Tx prefetch units */
1622 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1625 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1629 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1630 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1632 sky2_phy_power(hw
, port
, 0);
1634 /* turn off LED's */
1635 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1637 synchronize_irq(hw
->pdev
->irq
);
1640 sky2_rx_clean(sky2
);
1642 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1643 sky2
->rx_le
, sky2
->rx_le_map
);
1644 kfree(sky2
->rx_ring
);
1646 pci_free_consistent(hw
->pdev
,
1647 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1648 sky2
->tx_le
, sky2
->tx_le_map
);
1649 kfree(sky2
->tx_ring
);
1654 sky2
->rx_ring
= NULL
;
1655 sky2
->tx_ring
= NULL
;
1660 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1662 if (!sky2_is_copper(hw
))
1665 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1666 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1668 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1669 case PHY_M_PS_SPEED_1000
:
1671 case PHY_M_PS_SPEED_100
:
1678 static void sky2_link_up(struct sky2_port
*sky2
)
1680 struct sky2_hw
*hw
= sky2
->hw
;
1681 unsigned port
= sky2
->port
;
1683 static const char *fc_name
[] = {
1691 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1692 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1693 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1695 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1697 netif_carrier_on(sky2
->netdev
);
1698 netif_wake_queue(sky2
->netdev
);
1700 /* Turn on link LED */
1701 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1702 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1704 if (hw
->chip_id
== CHIP_ID_YUKON_XL
1705 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
1706 || hw
->chip_id
== CHIP_ID_YUKON_EX
) {
1707 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1708 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1710 switch(sky2
->speed
) {
1712 led
|= PHY_M_LEDC_INIT_CTRL(7);
1716 led
|= PHY_M_LEDC_STA1_CTRL(7);
1720 led
|= PHY_M_LEDC_STA0_CTRL(7);
1724 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1725 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1726 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1729 if (netif_msg_link(sky2
))
1730 printk(KERN_INFO PFX
1731 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1732 sky2
->netdev
->name
, sky2
->speed
,
1733 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1734 fc_name
[sky2
->flow_status
]);
1737 static void sky2_link_down(struct sky2_port
*sky2
)
1739 struct sky2_hw
*hw
= sky2
->hw
;
1740 unsigned port
= sky2
->port
;
1743 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1745 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1746 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1747 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1749 netif_carrier_off(sky2
->netdev
);
1750 netif_stop_queue(sky2
->netdev
);
1752 /* Turn on link LED */
1753 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1755 if (netif_msg_link(sky2
))
1756 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1758 sky2_phy_init(hw
, port
);
1761 static enum flow_control
sky2_flow(int rx
, int tx
)
1764 return tx
? FC_BOTH
: FC_RX
;
1766 return tx
? FC_TX
: FC_NONE
;
1769 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1771 struct sky2_hw
*hw
= sky2
->hw
;
1772 unsigned port
= sky2
->port
;
1775 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1776 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1777 if (lpa
& PHY_M_AN_RF
) {
1778 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1782 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1783 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1784 sky2
->netdev
->name
);
1788 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1789 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1791 /* Since the pause result bits seem to in different positions on
1792 * different chips. look at registers.
1794 if (!sky2_is_copper(hw
)) {
1795 /* Shift for bits in fiber PHY */
1796 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
1797 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
1799 if (advert
& ADVERTISE_1000XPAUSE
)
1800 advert
|= ADVERTISE_PAUSE_CAP
;
1801 if (advert
& ADVERTISE_1000XPSE_ASYM
)
1802 advert
|= ADVERTISE_PAUSE_ASYM
;
1803 if (lpa
& LPA_1000XPAUSE
)
1804 lpa
|= LPA_PAUSE_CAP
;
1805 if (lpa
& LPA_1000XPAUSE_ASYM
)
1806 lpa
|= LPA_PAUSE_ASYM
;
1809 sky2
->flow_status
= FC_NONE
;
1810 if (advert
& ADVERTISE_PAUSE_CAP
) {
1811 if (lpa
& LPA_PAUSE_CAP
)
1812 sky2
->flow_status
= FC_BOTH
;
1813 else if (advert
& ADVERTISE_PAUSE_ASYM
)
1814 sky2
->flow_status
= FC_RX
;
1815 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
1816 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
1817 sky2
->flow_status
= FC_TX
;
1820 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1821 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
1822 sky2
->flow_status
= FC_NONE
;
1824 if (sky2
->flow_status
& FC_TX
)
1825 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1827 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1832 /* Interrupt from PHY */
1833 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1835 struct net_device
*dev
= hw
->dev
[port
];
1836 struct sky2_port
*sky2
= netdev_priv(dev
);
1837 u16 istatus
, phystat
;
1839 if (!netif_running(dev
))
1842 spin_lock(&sky2
->phy_lock
);
1843 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1844 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1846 if (netif_msg_intr(sky2
))
1847 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1848 sky2
->netdev
->name
, istatus
, phystat
);
1850 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1851 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1856 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1857 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1859 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1861 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1863 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1864 if (phystat
& PHY_M_PS_LINK_UP
)
1867 sky2_link_down(sky2
);
1870 spin_unlock(&sky2
->phy_lock
);
1873 /* Transmit timeout is only called if we are running, carrier is up
1874 * and tx queue is full (stopped).
1876 static void sky2_tx_timeout(struct net_device
*dev
)
1878 struct sky2_port
*sky2
= netdev_priv(dev
);
1879 struct sky2_hw
*hw
= sky2
->hw
;
1881 if (netif_msg_timer(sky2
))
1882 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1884 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1885 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
1886 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
1887 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
1889 /* can't restart safely under softirq */
1890 schedule_work(&hw
->restart_work
);
1893 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1895 struct sky2_port
*sky2
= netdev_priv(dev
);
1896 struct sky2_hw
*hw
= sky2
->hw
;
1897 unsigned port
= sky2
->port
;
1902 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1905 if (new_mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_FE
)
1908 if (!netif_running(dev
)) {
1913 imask
= sky2_read32(hw
, B0_IMSK
);
1914 sky2_write32(hw
, B0_IMSK
, 0);
1916 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1917 netif_stop_queue(dev
);
1918 netif_poll_disable(hw
->dev
[0]);
1920 synchronize_irq(hw
->pdev
->irq
);
1922 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
1923 if (new_mtu
> ETH_DATA_LEN
) {
1924 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1925 TX_JUMBO_ENA
| TX_STFW_DIS
);
1926 dev
->features
&= NETIF_F_TSO
| NETIF_F_SG
| NETIF_F_IP_CSUM
;
1928 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1929 TX_JUMBO_DIS
| TX_STFW_ENA
);
1932 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1933 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1935 sky2_rx_clean(sky2
);
1939 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1940 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1942 if (dev
->mtu
> ETH_DATA_LEN
)
1943 mode
|= GM_SMOD_JUMBO_ENA
;
1945 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
1947 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
1949 err
= sky2_rx_start(sky2
);
1950 sky2_write32(hw
, B0_IMSK
, imask
);
1955 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
1957 netif_poll_enable(hw
->dev
[0]);
1958 netif_wake_queue(dev
);
1964 /* For small just reuse existing skb for next receive */
1965 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
1966 const struct rx_ring_info
*re
,
1969 struct sk_buff
*skb
;
1971 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
1973 skb_reserve(skb
, 2);
1974 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
1975 length
, PCI_DMA_FROMDEVICE
);
1976 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
1977 skb
->ip_summed
= re
->skb
->ip_summed
;
1978 skb
->csum
= re
->skb
->csum
;
1979 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
1980 length
, PCI_DMA_FROMDEVICE
);
1981 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1982 skb_put(skb
, length
);
1987 /* Adjust length of skb with fragments to match received data */
1988 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
1989 unsigned int length
)
1994 /* put header into skb */
1995 size
= min(length
, hdr_space
);
2000 num_frags
= skb_shinfo(skb
)->nr_frags
;
2001 for (i
= 0; i
< num_frags
; i
++) {
2002 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2005 /* don't need this page */
2006 __free_page(frag
->page
);
2007 --skb_shinfo(skb
)->nr_frags
;
2009 size
= min(length
, (unsigned) PAGE_SIZE
);
2012 skb
->data_len
+= size
;
2013 skb
->truesize
+= size
;
2020 /* Normal packet - take skb from ring element and put in a new one */
2021 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2022 struct rx_ring_info
*re
,
2023 unsigned int length
)
2025 struct sk_buff
*skb
, *nskb
;
2026 unsigned hdr_space
= sky2
->rx_data_size
;
2028 pr_debug(PFX
"receive new length=%d\n", length
);
2030 /* Don't be tricky about reusing pages (yet) */
2031 nskb
= sky2_rx_alloc(sky2
);
2032 if (unlikely(!nskb
))
2036 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2038 prefetch(skb
->data
);
2040 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
2042 if (skb_shinfo(skb
)->nr_frags
)
2043 skb_put_frags(skb
, hdr_space
, length
);
2045 skb_put(skb
, length
);
2050 * Receive one packet.
2051 * For larger packets, get new buffer.
2053 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2054 u16 length
, u32 status
)
2056 struct sky2_port
*sky2
= netdev_priv(dev
);
2057 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2058 struct sk_buff
*skb
= NULL
;
2060 if (unlikely(netif_msg_rx_status(sky2
)))
2061 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2062 dev
->name
, sky2
->rx_next
, status
, length
);
2064 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2065 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2067 if (status
& GMR_FS_ANY_ERR
)
2070 if (!(status
& GMR_FS_RX_OK
))
2073 if (length
< copybreak
)
2074 skb
= receive_copy(sky2
, re
, length
);
2076 skb
= receive_new(sky2
, re
, length
);
2078 sky2_rx_submit(sky2
, re
);
2083 ++sky2
->net_stats
.rx_errors
;
2084 if (status
& GMR_FS_RX_FF_OV
) {
2085 sky2
->net_stats
.rx_over_errors
++;
2089 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2090 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2091 dev
->name
, status
, length
);
2093 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2094 sky2
->net_stats
.rx_length_errors
++;
2095 if (status
& GMR_FS_FRAGMENT
)
2096 sky2
->net_stats
.rx_frame_errors
++;
2097 if (status
& GMR_FS_CRC_ERR
)
2098 sky2
->net_stats
.rx_crc_errors
++;
2103 /* Transmit complete */
2104 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2106 struct sky2_port
*sky2
= netdev_priv(dev
);
2108 if (netif_running(dev
)) {
2110 sky2_tx_complete(sky2
, last
);
2111 netif_tx_unlock(dev
);
2115 /* Process status response ring */
2116 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
2118 struct sky2_port
*sky2
;
2120 unsigned buf_write
[2] = { 0, 0 };
2121 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
2125 while (hw
->st_idx
!= hwidx
) {
2126 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2127 struct net_device
*dev
;
2128 struct sk_buff
*skb
;
2132 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2134 BUG_ON(le
->link
>= 2);
2135 dev
= hw
->dev
[le
->link
];
2137 sky2
= netdev_priv(dev
);
2138 length
= le16_to_cpu(le
->length
);
2139 status
= le32_to_cpu(le
->status
);
2141 switch (le
->opcode
& ~HW_OWNER
) {
2143 skb
= sky2_receive(dev
, length
, status
);
2147 skb
->protocol
= eth_type_trans(skb
, dev
);
2148 sky2
->net_stats
.rx_packets
++;
2149 sky2
->net_stats
.rx_bytes
+= skb
->len
;
2150 dev
->last_rx
= jiffies
;
2152 #ifdef SKY2_VLAN_TAG_USED
2153 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2154 vlan_hwaccel_receive_skb(skb
,
2156 be16_to_cpu(sky2
->rx_tag
));
2159 netif_receive_skb(skb
);
2161 /* Update receiver after 16 frames */
2162 if (++buf_write
[le
->link
] == RX_BUF_WRITE
) {
2164 sky2_put_idx(hw
, rxqaddr
[le
->link
], sky2
->rx_put
);
2165 buf_write
[le
->link
] = 0;
2168 /* Stop after net poll weight */
2169 if (++work_done
>= to_do
)
2173 #ifdef SKY2_VLAN_TAG_USED
2175 sky2
->rx_tag
= length
;
2179 sky2
->rx_tag
= length
;
2186 /* Both checksum counters are programmed to start at
2187 * the same offset, so unless there is a problem they
2188 * should match. This failure is an early indication that
2189 * hardware receive checksumming won't work.
2191 if (likely(status
>> 16 == (status
& 0xffff))) {
2192 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2193 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2194 skb
->csum
= status
& 0xffff;
2196 printk(KERN_NOTICE PFX
"%s: hardware receive "
2197 "checksum problem (status = %#x)\n",
2200 sky2_write32(sky2
->hw
,
2201 Q_ADDR(rxqaddr
[le
->link
], Q_CSR
),
2207 /* TX index reports status for both ports */
2208 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2209 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2211 sky2_tx_done(hw
->dev
[1],
2212 ((status
>> 24) & 0xff)
2213 | (u16
)(length
& 0xf) << 8);
2217 if (net_ratelimit())
2218 printk(KERN_WARNING PFX
2219 "unknown status opcode 0x%x\n", le
->opcode
);
2224 /* Fully processed status ring so clear irq */
2225 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2229 sky2
= netdev_priv(hw
->dev
[0]);
2230 sky2_put_idx(hw
, Q_R1
, sky2
->rx_put
);
2234 sky2
= netdev_priv(hw
->dev
[1]);
2235 sky2_put_idx(hw
, Q_R2
, sky2
->rx_put
);
2241 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2243 struct net_device
*dev
= hw
->dev
[port
];
2245 if (net_ratelimit())
2246 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2249 if (status
& Y2_IS_PAR_RD1
) {
2250 if (net_ratelimit())
2251 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2254 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2257 if (status
& Y2_IS_PAR_WR1
) {
2258 if (net_ratelimit())
2259 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2262 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2265 if (status
& Y2_IS_PAR_MAC1
) {
2266 if (net_ratelimit())
2267 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2268 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2271 if (status
& Y2_IS_PAR_RX1
) {
2272 if (net_ratelimit())
2273 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2274 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2277 if (status
& Y2_IS_TCP_TXA1
) {
2278 if (net_ratelimit())
2279 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2281 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2285 static void sky2_hw_intr(struct sky2_hw
*hw
)
2287 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2289 if (status
& Y2_IS_TIST_OV
)
2290 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2292 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2295 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2296 if (net_ratelimit())
2297 dev_err(&hw
->pdev
->dev
, "PCI hardware error (0x%x)\n",
2300 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2301 sky2_pci_write16(hw
, PCI_STATUS
,
2302 pci_err
| PCI_STATUS_ERROR_BITS
);
2303 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2306 if (status
& Y2_IS_PCI_EXP
) {
2307 /* PCI-Express uncorrectable Error occurred */
2310 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2312 if (net_ratelimit())
2313 dev_err(&hw
->pdev
->dev
, "PCI Express error (0x%x)\n",
2316 /* clear the interrupt */
2317 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2318 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2320 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2322 if (pex_err
& PEX_FATAL_ERRORS
) {
2323 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2324 hwmsk
&= ~Y2_IS_PCI_EXP
;
2325 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2329 if (status
& Y2_HWE_L1_MASK
)
2330 sky2_hw_error(hw
, 0, status
);
2332 if (status
& Y2_HWE_L1_MASK
)
2333 sky2_hw_error(hw
, 1, status
);
2336 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2338 struct net_device
*dev
= hw
->dev
[port
];
2339 struct sky2_port
*sky2
= netdev_priv(dev
);
2340 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2342 if (netif_msg_intr(sky2
))
2343 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2346 if (status
& GM_IS_RX_FF_OR
) {
2347 ++sky2
->net_stats
.rx_fifo_errors
;
2348 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2351 if (status
& GM_IS_TX_FF_UR
) {
2352 ++sky2
->net_stats
.tx_fifo_errors
;
2353 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2357 /* This should never happen it is a bug. */
2358 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
,
2359 u16 q
, unsigned ring_size
)
2361 struct net_device
*dev
= hw
->dev
[port
];
2362 struct sky2_port
*sky2
= netdev_priv(dev
);
2364 const u64
*le
= (q
== Q_R1
|| q
== Q_R2
)
2365 ? (u64
*) sky2
->rx_le
: (u64
*) sky2
->tx_le
;
2367 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2368 printk(KERN_ERR PFX
"%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2369 dev
->name
, (unsigned) q
, idx
, (unsigned long long) le
[idx
],
2370 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2372 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2375 /* If idle then force a fake soft NAPI poll once a second
2376 * to work around cases where sharing an edge triggered interrupt.
2378 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2380 if (idle_timeout
> 0)
2381 mod_timer(&hw
->idle_timer
,
2382 jiffies
+ msecs_to_jiffies(idle_timeout
));
2385 static void sky2_idle(unsigned long arg
)
2387 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2388 struct net_device
*dev
= hw
->dev
[0];
2390 if (__netif_rx_schedule_prep(dev
))
2391 __netif_rx_schedule(dev
);
2393 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2396 /* Hardware/software error handling */
2397 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2399 if (net_ratelimit())
2400 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2402 if (status
& Y2_IS_HW_ERR
)
2405 if (status
& Y2_IS_IRQ_MAC1
)
2406 sky2_mac_intr(hw
, 0);
2408 if (status
& Y2_IS_IRQ_MAC2
)
2409 sky2_mac_intr(hw
, 1);
2411 if (status
& Y2_IS_CHK_RX1
)
2412 sky2_le_error(hw
, 0, Q_R1
, RX_LE_SIZE
);
2414 if (status
& Y2_IS_CHK_RX2
)
2415 sky2_le_error(hw
, 1, Q_R2
, RX_LE_SIZE
);
2417 if (status
& Y2_IS_CHK_TXA1
)
2418 sky2_le_error(hw
, 0, Q_XA1
, TX_RING_SIZE
);
2420 if (status
& Y2_IS_CHK_TXA2
)
2421 sky2_le_error(hw
, 1, Q_XA2
, TX_RING_SIZE
);
2424 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2426 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2427 int work_limit
= min(dev0
->quota
, *budget
);
2429 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2431 if (unlikely(status
& Y2_IS_ERROR
))
2432 sky2_err_intr(hw
, status
);
2434 if (status
& Y2_IS_IRQ_PHY1
)
2435 sky2_phy_intr(hw
, 0);
2437 if (status
& Y2_IS_IRQ_PHY2
)
2438 sky2_phy_intr(hw
, 1);
2440 work_done
= sky2_status_intr(hw
, work_limit
);
2441 if (work_done
< work_limit
) {
2442 netif_rx_complete(dev0
);
2444 sky2_read32(hw
, B0_Y2_SP_LISR
);
2447 *budget
-= work_done
;
2448 dev0
->quota
-= work_done
;
2453 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2455 struct sky2_hw
*hw
= dev_id
;
2456 struct net_device
*dev0
= hw
->dev
[0];
2459 /* Reading this mask interrupts as side effect */
2460 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2461 if (status
== 0 || status
== ~0)
2464 prefetch(&hw
->st_le
[hw
->st_idx
]);
2465 if (likely(__netif_rx_schedule_prep(dev0
)))
2466 __netif_rx_schedule(dev0
);
2471 #ifdef CONFIG_NET_POLL_CONTROLLER
2472 static void sky2_netpoll(struct net_device
*dev
)
2474 struct sky2_port
*sky2
= netdev_priv(dev
);
2475 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2477 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2478 __netif_rx_schedule(dev0
);
2482 /* Chip internal frequency for clock calculations */
2483 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2485 switch (hw
->chip_id
) {
2486 case CHIP_ID_YUKON_EC
:
2487 case CHIP_ID_YUKON_EC_U
:
2488 case CHIP_ID_YUKON_EX
:
2489 return 125; /* 125 Mhz */
2490 case CHIP_ID_YUKON_FE
:
2491 return 100; /* 100 Mhz */
2492 default: /* YUKON_XL */
2493 return 156; /* 156 Mhz */
2497 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2499 return sky2_mhz(hw
) * us
;
2502 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2504 return clk
/ sky2_mhz(hw
);
2508 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2512 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2514 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2515 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2516 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2521 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2522 dev_warn(&hw
->pdev
->dev
, "this driver not yet tested on this chip type\n"
2523 "Please report success or failure to <netdev@vger.kernel.org>\n");
2525 /* Make sure and enable all clocks */
2526 if (hw
->chip_id
== CHIP_ID_YUKON_EX
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
2527 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2529 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2531 /* This rev is really old, and requires untested workarounds */
2532 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2533 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2534 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2535 hw
->chip_id
, hw
->chip_rev
);
2539 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2541 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2542 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2543 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2550 static void sky2_reset(struct sky2_hw
*hw
)
2556 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2557 status
= sky2_read16(hw
, HCU_CCSR
);
2558 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2559 HCU_CCSR_UC_STATE_MSK
);
2560 sky2_write16(hw
, HCU_CCSR
, status
);
2562 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2563 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2566 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2567 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2569 /* clear PCI errors, if any */
2570 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2572 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2573 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2576 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2578 /* clear any PEX errors */
2579 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2580 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2585 for (i
= 0; i
< hw
->ports
; i
++) {
2586 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2587 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2590 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2592 /* Clear I2C IRQ noise */
2593 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2595 /* turn off hardware timer (unused) */
2596 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2597 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2599 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2601 /* Turn off descriptor polling */
2602 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2604 /* Turn off receive timestamp */
2605 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2606 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2608 /* enable the Tx Arbiters */
2609 for (i
= 0; i
< hw
->ports
; i
++)
2610 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2612 /* Initialize ram interface */
2613 for (i
= 0; i
< hw
->ports
; i
++) {
2614 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2616 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2617 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2618 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2619 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2620 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2621 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2622 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2623 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2624 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2625 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2626 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2627 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2630 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2632 for (i
= 0; i
< hw
->ports
; i
++)
2633 sky2_gmac_reset(hw
, i
);
2635 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2638 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2639 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2641 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2642 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2644 /* Set the list last index */
2645 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2647 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2648 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2650 /* set Status-FIFO ISR watermark */
2651 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2652 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2654 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2656 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2657 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2658 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2660 /* enable status unit */
2661 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2663 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2664 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2665 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2668 static void sky2_restart(struct work_struct
*work
)
2670 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
2671 struct net_device
*dev
;
2674 dev_dbg(&hw
->pdev
->dev
, "restarting\n");
2676 del_timer_sync(&hw
->idle_timer
);
2679 sky2_write32(hw
, B0_IMSK
, 0);
2680 sky2_read32(hw
, B0_IMSK
);
2682 netif_poll_disable(hw
->dev
[0]);
2684 for (i
= 0; i
< hw
->ports
; i
++) {
2686 if (netif_running(dev
))
2691 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
2692 netif_poll_enable(hw
->dev
[0]);
2694 for (i
= 0; i
< hw
->ports
; i
++) {
2696 if (netif_running(dev
)) {
2699 printk(KERN_INFO PFX
"%s: could not restart %d\n",
2706 sky2_idle_start(hw
);
2711 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
2713 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
2716 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2718 const struct sky2_port
*sky2
= netdev_priv(dev
);
2720 wol
->supported
= sky2_wol_supported(sky2
->hw
);
2721 wol
->wolopts
= sky2
->wol
;
2724 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2726 struct sky2_port
*sky2
= netdev_priv(dev
);
2727 struct sky2_hw
*hw
= sky2
->hw
;
2729 if (wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
2732 sky2
->wol
= wol
->wolopts
;
2734 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
2735 sky2_write32(hw
, B0_CTST
, sky2
->wol
2736 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
2738 if (!netif_running(dev
))
2739 sky2_wol_init(sky2
);
2743 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2745 if (sky2_is_copper(hw
)) {
2746 u32 modes
= SUPPORTED_10baseT_Half
2747 | SUPPORTED_10baseT_Full
2748 | SUPPORTED_100baseT_Half
2749 | SUPPORTED_100baseT_Full
2750 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2752 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2753 modes
|= SUPPORTED_1000baseT_Half
2754 | SUPPORTED_1000baseT_Full
;
2757 return SUPPORTED_1000baseT_Half
2758 | SUPPORTED_1000baseT_Full
2763 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2765 struct sky2_port
*sky2
= netdev_priv(dev
);
2766 struct sky2_hw
*hw
= sky2
->hw
;
2768 ecmd
->transceiver
= XCVR_INTERNAL
;
2769 ecmd
->supported
= sky2_supported_modes(hw
);
2770 ecmd
->phy_address
= PHY_ADDR_MARV
;
2771 if (sky2_is_copper(hw
)) {
2772 ecmd
->supported
= SUPPORTED_10baseT_Half
2773 | SUPPORTED_10baseT_Full
2774 | SUPPORTED_100baseT_Half
2775 | SUPPORTED_100baseT_Full
2776 | SUPPORTED_1000baseT_Half
2777 | SUPPORTED_1000baseT_Full
2778 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2779 ecmd
->port
= PORT_TP
;
2780 ecmd
->speed
= sky2
->speed
;
2782 ecmd
->speed
= SPEED_1000
;
2783 ecmd
->port
= PORT_FIBRE
;
2786 ecmd
->advertising
= sky2
->advertising
;
2787 ecmd
->autoneg
= sky2
->autoneg
;
2788 ecmd
->duplex
= sky2
->duplex
;
2792 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2794 struct sky2_port
*sky2
= netdev_priv(dev
);
2795 const struct sky2_hw
*hw
= sky2
->hw
;
2796 u32 supported
= sky2_supported_modes(hw
);
2798 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2799 ecmd
->advertising
= supported
;
2805 switch (ecmd
->speed
) {
2807 if (ecmd
->duplex
== DUPLEX_FULL
)
2808 setting
= SUPPORTED_1000baseT_Full
;
2809 else if (ecmd
->duplex
== DUPLEX_HALF
)
2810 setting
= SUPPORTED_1000baseT_Half
;
2815 if (ecmd
->duplex
== DUPLEX_FULL
)
2816 setting
= SUPPORTED_100baseT_Full
;
2817 else if (ecmd
->duplex
== DUPLEX_HALF
)
2818 setting
= SUPPORTED_100baseT_Half
;
2824 if (ecmd
->duplex
== DUPLEX_FULL
)
2825 setting
= SUPPORTED_10baseT_Full
;
2826 else if (ecmd
->duplex
== DUPLEX_HALF
)
2827 setting
= SUPPORTED_10baseT_Half
;
2835 if ((setting
& supported
) == 0)
2838 sky2
->speed
= ecmd
->speed
;
2839 sky2
->duplex
= ecmd
->duplex
;
2842 sky2
->autoneg
= ecmd
->autoneg
;
2843 sky2
->advertising
= ecmd
->advertising
;
2845 if (netif_running(dev
))
2846 sky2_phy_reinit(sky2
);
2851 static void sky2_get_drvinfo(struct net_device
*dev
,
2852 struct ethtool_drvinfo
*info
)
2854 struct sky2_port
*sky2
= netdev_priv(dev
);
2856 strcpy(info
->driver
, DRV_NAME
);
2857 strcpy(info
->version
, DRV_VERSION
);
2858 strcpy(info
->fw_version
, "N/A");
2859 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2862 static const struct sky2_stat
{
2863 char name
[ETH_GSTRING_LEN
];
2866 { "tx_bytes", GM_TXO_OK_HI
},
2867 { "rx_bytes", GM_RXO_OK_HI
},
2868 { "tx_broadcast", GM_TXF_BC_OK
},
2869 { "rx_broadcast", GM_RXF_BC_OK
},
2870 { "tx_multicast", GM_TXF_MC_OK
},
2871 { "rx_multicast", GM_RXF_MC_OK
},
2872 { "tx_unicast", GM_TXF_UC_OK
},
2873 { "rx_unicast", GM_RXF_UC_OK
},
2874 { "tx_mac_pause", GM_TXF_MPAUSE
},
2875 { "rx_mac_pause", GM_RXF_MPAUSE
},
2876 { "collisions", GM_TXF_COL
},
2877 { "late_collision",GM_TXF_LAT_COL
},
2878 { "aborted", GM_TXF_ABO_COL
},
2879 { "single_collisions", GM_TXF_SNG_COL
},
2880 { "multi_collisions", GM_TXF_MUL_COL
},
2882 { "rx_short", GM_RXF_SHT
},
2883 { "rx_runt", GM_RXE_FRAG
},
2884 { "rx_64_byte_packets", GM_RXF_64B
},
2885 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2886 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2887 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2888 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2889 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2890 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2891 { "rx_too_long", GM_RXF_LNG_ERR
},
2892 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2893 { "rx_jabber", GM_RXF_JAB_PKT
},
2894 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2896 { "tx_64_byte_packets", GM_TXF_64B
},
2897 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2898 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2899 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2900 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2901 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2902 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2903 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2906 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2908 struct sky2_port
*sky2
= netdev_priv(dev
);
2910 return sky2
->rx_csum
;
2913 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2915 struct sky2_port
*sky2
= netdev_priv(dev
);
2917 sky2
->rx_csum
= data
;
2919 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2920 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2925 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2927 struct sky2_port
*sky2
= netdev_priv(netdev
);
2928 return sky2
->msg_enable
;
2931 static int sky2_nway_reset(struct net_device
*dev
)
2933 struct sky2_port
*sky2
= netdev_priv(dev
);
2935 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
2938 sky2_phy_reinit(sky2
);
2943 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2945 struct sky2_hw
*hw
= sky2
->hw
;
2946 unsigned port
= sky2
->port
;
2949 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2950 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2951 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2952 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2954 for (i
= 2; i
< count
; i
++)
2955 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2958 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2960 struct sky2_port
*sky2
= netdev_priv(netdev
);
2961 sky2
->msg_enable
= value
;
2964 static int sky2_get_stats_count(struct net_device
*dev
)
2966 return ARRAY_SIZE(sky2_stats
);
2969 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2970 struct ethtool_stats
*stats
, u64
* data
)
2972 struct sky2_port
*sky2
= netdev_priv(dev
);
2974 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2977 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2981 switch (stringset
) {
2983 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2984 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2985 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2990 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2992 struct sky2_port
*sky2
= netdev_priv(dev
);
2993 return &sky2
->net_stats
;
2996 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2998 struct sky2_port
*sky2
= netdev_priv(dev
);
2999 struct sky2_hw
*hw
= sky2
->hw
;
3000 unsigned port
= sky2
->port
;
3001 const struct sockaddr
*addr
= p
;
3003 if (!is_valid_ether_addr(addr
->sa_data
))
3004 return -EADDRNOTAVAIL
;
3006 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3007 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3008 dev
->dev_addr
, ETH_ALEN
);
3009 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3010 dev
->dev_addr
, ETH_ALEN
);
3012 /* virtual address for data */
3013 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3015 /* physical address: used for pause frames */
3016 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3021 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3025 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3026 filter
[bit
>> 3] |= 1 << (bit
& 7);
3029 static void sky2_set_multicast(struct net_device
*dev
)
3031 struct sky2_port
*sky2
= netdev_priv(dev
);
3032 struct sky2_hw
*hw
= sky2
->hw
;
3033 unsigned port
= sky2
->port
;
3034 struct dev_mc_list
*list
= dev
->mc_list
;
3038 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3040 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3041 memset(filter
, 0, sizeof(filter
));
3043 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3044 reg
|= GM_RXCR_UCF_ENA
;
3046 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3047 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3048 else if (dev
->flags
& IFF_ALLMULTI
)
3049 memset(filter
, 0xff, sizeof(filter
));
3050 else if (dev
->mc_count
== 0 && !rx_pause
)
3051 reg
&= ~GM_RXCR_MCF_ENA
;
3054 reg
|= GM_RXCR_MCF_ENA
;
3057 sky2_add_filter(filter
, pause_mc_addr
);
3059 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3060 sky2_add_filter(filter
, list
->dmi_addr
);
3063 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3064 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3065 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3066 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3067 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3068 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3069 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3070 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3072 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3075 /* Can have one global because blinking is controlled by
3076 * ethtool and that is always under RTNL mutex
3078 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
3082 switch (hw
->chip_id
) {
3083 case CHIP_ID_YUKON_XL
:
3084 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3085 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3086 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3087 on
? (PHY_M_LEDC_LOS_CTRL(1) |
3088 PHY_M_LEDC_INIT_CTRL(7) |
3089 PHY_M_LEDC_STA1_CTRL(7) |
3090 PHY_M_LEDC_STA0_CTRL(7))
3093 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3097 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
3098 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3099 on
? PHY_M_LED_ALL
: 0);
3103 /* blink LED's for finding board */
3104 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3106 struct sky2_port
*sky2
= netdev_priv(dev
);
3107 struct sky2_hw
*hw
= sky2
->hw
;
3108 unsigned port
= sky2
->port
;
3109 u16 ledctrl
, ledover
= 0;
3114 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
3115 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
3119 /* save initial values */
3120 spin_lock_bh(&sky2
->phy_lock
);
3121 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3122 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3123 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3124 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
3125 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3127 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
3128 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
3132 while (!interrupted
&& ms
> 0) {
3133 sky2_led(hw
, port
, onoff
);
3136 spin_unlock_bh(&sky2
->phy_lock
);
3137 interrupted
= msleep_interruptible(250);
3138 spin_lock_bh(&sky2
->phy_lock
);
3143 /* resume regularly scheduled programming */
3144 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3145 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3146 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3147 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
3148 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3150 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
3151 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
3153 spin_unlock_bh(&sky2
->phy_lock
);
3158 static void sky2_get_pauseparam(struct net_device
*dev
,
3159 struct ethtool_pauseparam
*ecmd
)
3161 struct sky2_port
*sky2
= netdev_priv(dev
);
3163 switch (sky2
->flow_mode
) {
3165 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3168 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3171 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3174 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3177 ecmd
->autoneg
= sky2
->autoneg
;
3180 static int sky2_set_pauseparam(struct net_device
*dev
,
3181 struct ethtool_pauseparam
*ecmd
)
3183 struct sky2_port
*sky2
= netdev_priv(dev
);
3185 sky2
->autoneg
= ecmd
->autoneg
;
3186 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3188 if (netif_running(dev
))
3189 sky2_phy_reinit(sky2
);
3194 static int sky2_get_coalesce(struct net_device
*dev
,
3195 struct ethtool_coalesce
*ecmd
)
3197 struct sky2_port
*sky2
= netdev_priv(dev
);
3198 struct sky2_hw
*hw
= sky2
->hw
;
3200 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3201 ecmd
->tx_coalesce_usecs
= 0;
3203 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3204 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3206 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3208 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3209 ecmd
->rx_coalesce_usecs
= 0;
3211 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3212 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3214 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3216 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3217 ecmd
->rx_coalesce_usecs_irq
= 0;
3219 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3220 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3223 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3228 /* Note: this affect both ports */
3229 static int sky2_set_coalesce(struct net_device
*dev
,
3230 struct ethtool_coalesce
*ecmd
)
3232 struct sky2_port
*sky2
= netdev_priv(dev
);
3233 struct sky2_hw
*hw
= sky2
->hw
;
3234 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3236 if (ecmd
->tx_coalesce_usecs
> tmax
||
3237 ecmd
->rx_coalesce_usecs
> tmax
||
3238 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3241 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3243 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3245 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3248 if (ecmd
->tx_coalesce_usecs
== 0)
3249 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3251 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3252 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3253 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3255 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3257 if (ecmd
->rx_coalesce_usecs
== 0)
3258 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3260 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3261 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3262 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3264 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3266 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3267 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3269 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3270 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3271 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3273 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3277 static void sky2_get_ringparam(struct net_device
*dev
,
3278 struct ethtool_ringparam
*ering
)
3280 struct sky2_port
*sky2
= netdev_priv(dev
);
3282 ering
->rx_max_pending
= RX_MAX_PENDING
;
3283 ering
->rx_mini_max_pending
= 0;
3284 ering
->rx_jumbo_max_pending
= 0;
3285 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3287 ering
->rx_pending
= sky2
->rx_pending
;
3288 ering
->rx_mini_pending
= 0;
3289 ering
->rx_jumbo_pending
= 0;
3290 ering
->tx_pending
= sky2
->tx_pending
;
3293 static int sky2_set_ringparam(struct net_device
*dev
,
3294 struct ethtool_ringparam
*ering
)
3296 struct sky2_port
*sky2
= netdev_priv(dev
);
3299 if (ering
->rx_pending
> RX_MAX_PENDING
||
3300 ering
->rx_pending
< 8 ||
3301 ering
->tx_pending
< MAX_SKB_TX_LE
||
3302 ering
->tx_pending
> TX_RING_SIZE
- 1)
3305 if (netif_running(dev
))
3308 sky2
->rx_pending
= ering
->rx_pending
;
3309 sky2
->tx_pending
= ering
->tx_pending
;
3311 if (netif_running(dev
)) {
3316 sky2_set_multicast(dev
);
3322 static int sky2_get_regs_len(struct net_device
*dev
)
3328 * Returns copy of control register region
3329 * Note: access to the RAM address register set will cause timeouts.
3331 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3334 const struct sky2_port
*sky2
= netdev_priv(dev
);
3335 const void __iomem
*io
= sky2
->hw
->regs
;
3337 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3339 memset(p
, 0, regs
->len
);
3341 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3343 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3345 regs
->len
- B3_RI_WTO_R1
);
3348 /* In order to do Jumbo packets on these chips, need to turn off the
3349 * transmit store/forward. Therefore checksum offload won't work.
3351 static int no_tx_offload(struct net_device
*dev
)
3353 const struct sky2_port
*sky2
= netdev_priv(dev
);
3354 const struct sky2_hw
*hw
= sky2
->hw
;
3356 return dev
->mtu
> ETH_DATA_LEN
&&
3357 (hw
->chip_id
== CHIP_ID_YUKON_EX
3358 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
);
3361 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3363 if (data
&& no_tx_offload(dev
))
3366 return ethtool_op_set_tx_csum(dev
, data
);
3370 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3372 if (data
&& no_tx_offload(dev
))
3375 return ethtool_op_set_tso(dev
, data
);
3378 static const struct ethtool_ops sky2_ethtool_ops
= {
3379 .get_settings
= sky2_get_settings
,
3380 .set_settings
= sky2_set_settings
,
3381 .get_drvinfo
= sky2_get_drvinfo
,
3382 .get_wol
= sky2_get_wol
,
3383 .set_wol
= sky2_set_wol
,
3384 .get_msglevel
= sky2_get_msglevel
,
3385 .set_msglevel
= sky2_set_msglevel
,
3386 .nway_reset
= sky2_nway_reset
,
3387 .get_regs_len
= sky2_get_regs_len
,
3388 .get_regs
= sky2_get_regs
,
3389 .get_link
= ethtool_op_get_link
,
3390 .get_sg
= ethtool_op_get_sg
,
3391 .set_sg
= ethtool_op_set_sg
,
3392 .get_tx_csum
= ethtool_op_get_tx_csum
,
3393 .set_tx_csum
= sky2_set_tx_csum
,
3394 .get_tso
= ethtool_op_get_tso
,
3395 .set_tso
= sky2_set_tso
,
3396 .get_rx_csum
= sky2_get_rx_csum
,
3397 .set_rx_csum
= sky2_set_rx_csum
,
3398 .get_strings
= sky2_get_strings
,
3399 .get_coalesce
= sky2_get_coalesce
,
3400 .set_coalesce
= sky2_set_coalesce
,
3401 .get_ringparam
= sky2_get_ringparam
,
3402 .set_ringparam
= sky2_set_ringparam
,
3403 .get_pauseparam
= sky2_get_pauseparam
,
3404 .set_pauseparam
= sky2_set_pauseparam
,
3405 .phys_id
= sky2_phys_id
,
3406 .get_stats_count
= sky2_get_stats_count
,
3407 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3408 .get_perm_addr
= ethtool_op_get_perm_addr
,
3411 /* Initialize network device */
3412 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3414 int highmem
, int wol
)
3416 struct sky2_port
*sky2
;
3417 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3420 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed");
3424 SET_MODULE_OWNER(dev
);
3425 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3426 dev
->irq
= hw
->pdev
->irq
;
3427 dev
->open
= sky2_up
;
3428 dev
->stop
= sky2_down
;
3429 dev
->do_ioctl
= sky2_ioctl
;
3430 dev
->hard_start_xmit
= sky2_xmit_frame
;
3431 dev
->get_stats
= sky2_get_stats
;
3432 dev
->set_multicast_list
= sky2_set_multicast
;
3433 dev
->set_mac_address
= sky2_set_mac_address
;
3434 dev
->change_mtu
= sky2_change_mtu
;
3435 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3436 dev
->tx_timeout
= sky2_tx_timeout
;
3437 dev
->watchdog_timeo
= TX_WATCHDOG
;
3439 dev
->poll
= sky2_poll
;
3440 dev
->weight
= NAPI_WEIGHT
;
3441 #ifdef CONFIG_NET_POLL_CONTROLLER
3442 /* Network console (only works on port 0)
3443 * because netpoll makes assumptions about NAPI
3446 dev
->poll_controller
= sky2_netpoll
;
3449 sky2
= netdev_priv(dev
);
3452 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3454 /* Auto speed and flow control */
3455 sky2
->autoneg
= AUTONEG_ENABLE
;
3456 sky2
->flow_mode
= FC_BOTH
;
3460 sky2
->advertising
= sky2_supported_modes(hw
);
3464 spin_lock_init(&sky2
->phy_lock
);
3465 sky2
->tx_pending
= TX_DEF_PENDING
;
3466 sky2
->rx_pending
= RX_DEF_PENDING
;
3468 hw
->dev
[port
] = dev
;
3472 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
3474 dev
->features
|= NETIF_F_HIGHDMA
;
3476 #ifdef SKY2_VLAN_TAG_USED
3477 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3478 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3479 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3482 /* read the mac address */
3483 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3484 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3486 /* device is off until link detection */
3487 netif_carrier_off(dev
);
3488 netif_stop_queue(dev
);
3493 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3495 const struct sky2_port
*sky2
= netdev_priv(dev
);
3497 if (netif_msg_probe(sky2
))
3498 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3500 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3501 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3504 /* Handle software interrupt used during MSI test */
3505 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
3507 struct sky2_hw
*hw
= dev_id
;
3508 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3513 if (status
& Y2_IS_IRQ_SW
) {
3515 wake_up(&hw
->msi_wait
);
3516 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3518 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3523 /* Test interrupt path by forcing a a software IRQ */
3524 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3526 struct pci_dev
*pdev
= hw
->pdev
;
3529 init_waitqueue_head (&hw
->msi_wait
);
3531 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3533 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
3535 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
3539 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3540 sky2_read8(hw
, B0_CTST
);
3542 wait_event_timeout(hw
->msi_wait
, hw
->msi
, HZ
/10);
3545 /* MSI test failed, go back to INTx mode */
3546 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
3547 "switching to INTx mode.\n");
3550 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3553 sky2_write32(hw
, B0_IMSK
, 0);
3554 sky2_read32(hw
, B0_IMSK
);
3556 free_irq(pdev
->irq
, hw
);
3561 static int __devinit
pci_wake_enabled(struct pci_dev
*dev
)
3563 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3568 if (pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
))
3570 return value
& PCI_PM_CTRL_PME_ENABLE
;
3573 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3574 const struct pci_device_id
*ent
)
3576 struct net_device
*dev
;
3578 int err
, using_dac
= 0, wol_default
;
3580 err
= pci_enable_device(pdev
);
3582 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
3586 err
= pci_request_regions(pdev
, DRV_NAME
);
3588 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
3589 goto err_out_disable
;
3592 pci_set_master(pdev
);
3594 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3595 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3597 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3599 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
3600 "for consistent allocations\n");
3601 goto err_out_free_regions
;
3604 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3606 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
3607 goto err_out_free_regions
;
3611 wol_default
= pci_wake_enabled(pdev
) ? WAKE_MAGIC
: 0;
3614 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3616 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
3617 goto err_out_free_regions
;
3622 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3624 dev_err(&pdev
->dev
, "cannot map device registers\n");
3625 goto err_out_free_hw
;
3629 /* The sk98lin vendor driver uses hardware byte swapping but
3630 * this driver uses software swapping.
3634 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3635 reg
&= ~PCI_REV_DESC
;
3636 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3640 /* ring for status responses */
3641 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3644 goto err_out_iounmap
;
3646 err
= sky2_init(hw
);
3648 goto err_out_iounmap
;
3650 dev_info(&pdev
->dev
, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3651 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3652 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3653 hw
->chip_id
, hw
->chip_rev
);
3657 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
3660 goto err_out_free_pci
;
3663 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3664 err
= sky2_test_msi(hw
);
3665 if (err
== -EOPNOTSUPP
)
3666 pci_disable_msi(pdev
);
3668 goto err_out_free_netdev
;
3671 err
= register_netdev(dev
);
3673 dev_err(&pdev
->dev
, "cannot register net device\n");
3674 goto err_out_free_netdev
;
3677 err
= request_irq(pdev
->irq
, sky2_intr
, hw
->msi
? 0 : IRQF_SHARED
,
3680 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
3681 goto err_out_unregister
;
3683 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3685 sky2_show_addr(dev
);
3687 if (hw
->ports
> 1) {
3688 struct net_device
*dev1
;
3690 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
3692 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
3693 else if ((err
= register_netdev(dev1
))) {
3694 dev_warn(&pdev
->dev
,
3695 "register of second port failed (%d)\n", err
);
3699 sky2_show_addr(dev1
);
3702 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3703 INIT_WORK(&hw
->restart_work
, sky2_restart
);
3705 sky2_idle_start(hw
);
3707 pci_set_drvdata(pdev
, hw
);
3713 pci_disable_msi(pdev
);
3714 unregister_netdev(dev
);
3715 err_out_free_netdev
:
3718 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3719 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3724 err_out_free_regions
:
3725 pci_release_regions(pdev
);
3727 pci_disable_device(pdev
);
3729 pci_set_drvdata(pdev
, NULL
);
3733 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3735 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3736 struct net_device
*dev0
, *dev1
;
3741 del_timer_sync(&hw
->idle_timer
);
3743 flush_scheduled_work();
3745 sky2_write32(hw
, B0_IMSK
, 0);
3746 synchronize_irq(hw
->pdev
->irq
);
3751 unregister_netdev(dev1
);
3752 unregister_netdev(dev0
);
3756 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3757 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3758 sky2_read8(hw
, B0_CTST
);
3760 free_irq(pdev
->irq
, hw
);
3762 pci_disable_msi(pdev
);
3763 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3764 pci_release_regions(pdev
);
3765 pci_disable_device(pdev
);
3773 pci_set_drvdata(pdev
, NULL
);
3777 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3779 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3785 del_timer_sync(&hw
->idle_timer
);
3786 netif_poll_disable(hw
->dev
[0]);
3788 for (i
= 0; i
< hw
->ports
; i
++) {
3789 struct net_device
*dev
= hw
->dev
[i
];
3790 struct sky2_port
*sky2
= netdev_priv(dev
);
3792 if (netif_running(dev
))
3796 sky2_wol_init(sky2
);
3801 sky2_write32(hw
, B0_IMSK
, 0);
3804 pci_save_state(pdev
);
3805 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
3806 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3811 static int sky2_resume(struct pci_dev
*pdev
)
3813 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3819 err
= pci_set_power_state(pdev
, PCI_D0
);
3823 err
= pci_restore_state(pdev
);
3827 pci_enable_wake(pdev
, PCI_D0
, 0);
3829 /* Re-enable all clocks */
3830 if (hw
->chip_id
== CHIP_ID_YUKON_EX
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
3831 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
3835 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3837 for (i
= 0; i
< hw
->ports
; i
++) {
3838 struct net_device
*dev
= hw
->dev
[i
];
3839 if (netif_running(dev
)) {
3842 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3850 netif_poll_enable(hw
->dev
[0]);
3851 sky2_idle_start(hw
);
3854 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
3855 pci_disable_device(pdev
);
3860 static void sky2_shutdown(struct pci_dev
*pdev
)
3862 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3868 del_timer_sync(&hw
->idle_timer
);
3869 netif_poll_disable(hw
->dev
[0]);
3871 for (i
= 0; i
< hw
->ports
; i
++) {
3872 struct net_device
*dev
= hw
->dev
[i
];
3873 struct sky2_port
*sky2
= netdev_priv(dev
);
3877 sky2_wol_init(sky2
);
3884 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
3885 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
3887 pci_disable_device(pdev
);
3888 pci_set_power_state(pdev
, PCI_D3hot
);
3892 static struct pci_driver sky2_driver
= {
3894 .id_table
= sky2_id_table
,
3895 .probe
= sky2_probe
,
3896 .remove
= __devexit_p(sky2_remove
),
3898 .suspend
= sky2_suspend
,
3899 .resume
= sky2_resume
,
3901 .shutdown
= sky2_shutdown
,
3904 static int __init
sky2_init_module(void)
3906 return pci_register_driver(&sky2_driver
);
3909 static void __exit
sky2_cleanup_module(void)
3911 pci_unregister_driver(&sky2_driver
);
3914 module_init(sky2_init_module
);
3915 module_exit(sky2_cleanup_module
);
3917 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3918 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3919 MODULE_LICENSE("GPL");
3920 MODULE_VERSION(DRV_VERSION
);