arch/arm/mach-ep93xx/clock.c

   1 /*
   2  * arch/arm/mach-ep93xx/clock.c
   3  * Clock control for Cirrus EP93xx chips.
   4  *
   5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or (at
  10  * your option) any later version.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/module.h>
  17 #include <linux/string.h>
  18 #include <asm/div64.h>
  19 #include <asm/hardware.h>
  20 #include <asm/io.h>
  21
  22 struct clk {
  23         char            *name;
  24         unsigned long   rate;
  25         int             users;
  26         u32             enable_reg;
  27         u32             enable_mask;
  28 };
  29
  30 static struct clk clk_pll1 = {
  31         .name           = "pll1",
  32 };
  33 static struct clk clk_f = {
  34         .name           = "fclk",
  35 };
  36 static struct clk clk_h = {
  37         .name           = "hclk",
  38 };
  39 static struct clk clk_p = {
  40         .name           = "pclk",
  41 };
  42 static struct clk clk_pll2 = {
  43         .name           = "pll2",
  44 };
  45 static struct clk clk_usb_host = {
  46         .name           = "usb_host",
  47         .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
  48         .enable_mask    = EP93XX_SYSCON_CLOCK_USH_EN,
  49 };
  50
  51
  52 static struct clk *clocks[] = {
  53         &clk_pll1,
  54         &clk_f,
  55         &clk_h,
  56         &clk_p,
  57         &clk_pll2,
  58         &clk_usb_host,
  59 };
  60
  61 struct clk *clk_get(struct device *dev, const char *id)
  62 {
  63         int i;
  64
  65         for (i = 0; i < ARRAY_SIZE(clocks); i++) {
  66                 if (!strcmp(clocks[i]->name, id))
  67                         return clocks[i];
  68         }
  69
  70         return ERR_PTR(-ENOENT);
  71 }
  72
  73 int clk_enable(struct clk *clk)
  74 {
  75         if (!clk->users++ && clk->enable_reg) {
  76                 u32 value;
  77
  78                 value = __raw_readl(clk->enable_reg);
  79                 __raw_writel(value | clk->enable_mask, clk->enable_reg);
  80         }
  81
  82         return 0;
  83 }
  84
  85 void clk_disable(struct clk *clk)
  86 {
  87         if (!--clk->users && clk->enable_reg) {
  88                 u32 value;
  89
  90                 value = __raw_readl(clk->enable_reg);
  91                 __raw_writel(value & ~clk->enable_mask, clk->enable_reg);
  92         }
  93 }
  94
  95 unsigned long clk_get_rate(struct clk *clk)
  96 {
  97         return clk->rate;
  98 }
  99
 100 void clk_put(struct clk *clk)
 101 {
 102 }
 103
 104
 105
 106 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
 107 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
 108 static char pclk_divisors[] = { 1, 2, 4, 8 };
 109
 110 /*
 111  * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
 112  */
 113 static unsigned long calc_pll_rate(u32 config_word)
 114 {
 115         unsigned long long rate;
 116         int i;
 117
 118         rate = 14745600;
 119         rate *= ((config_word >> 11) & 0x1f) + 1;               /* X1FBD */
 120         rate *= ((config_word >> 5) & 0x3f) + 1;                /* X2FBD */
 121         do_div(rate, (config_word & 0x1f) + 1);                 /* X2IPD */
 122         for (i = 0; i < ((config_word >> 16) & 3); i++)         /* PS */
 123                 rate >>= 1;
 124
 125         return (unsigned long)rate;
 126 }
 127
 128 static int __init ep93xx_clock_init(void)
 129 {
 130         u32 value;
 131
 132         value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
 133         if (!(value & 0x00800000)) {                    /* PLL1 bypassed?  */
 134                 clk_pll1.rate = 14745600;
 135         } else {
 136                 clk_pll1.rate = calc_pll_rate(value);
 137         }
 138         clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
 139         clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
 140         clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
 141
 142         value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
 143         if (!(value & 0x00080000)) {                    /* PLL2 bypassed?  */
 144                 clk_pll2.rate = 14745600;
 145         } else if (value & 0x00040000) {                /* PLL2 enabled?  */
 146                 clk_pll2.rate = calc_pll_rate(value);
 147         } else {
 148                 clk_pll2.rate = 0;
 149         }
 150         clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
 151
 152         printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
 153                 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
 154         printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
 155                 clk_f.rate / 1000000, clk_h.rate / 1000000,
 156                 clk_p.rate / 1000000);
 157
 158         return 0;
 159 }
 160 arch_initcall(ep93xx_clock_init);