arch/x86/kernel/process.c

   1 #include <linux/errno.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mm.h>
   4 #include <linux/smp.h>
   5 #include <linux/prctl.h>
   6 #include <linux/slab.h>
   7 #include <linux/sched.h>
   8 #include <linux/module.h>
   9 #include <linux/pm.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/random.h>
  12 #include <linux/user-return-notifier.h>
  13 #include <linux/dmi.h>
  14 #include <linux/utsname.h>
  15 #include <trace/events/power.h>
  16 #include <linux/hw_breakpoint.h>
  17 #include <asm/system.h>
  18 #include <asm/apic.h>
  19 #include <asm/syscalls.h>
  20 #include <asm/idle.h>
  21 #include <asm/uaccess.h>
  22 #include <asm/i387.h>
  23 #include <asm/ds.h>
  24 #include <asm/debugreg.h>
  25
  26 unsigned long idle_halt;
  27 EXPORT_SYMBOL(idle_halt);
  28 unsigned long idle_nomwait;
  29 EXPORT_SYMBOL(idle_nomwait);
  30
  31 struct kmem_cache *task_xstate_cachep;
  32
  33 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  34 {
  35         *dst = *src;
  36         if (src->thread.xstate) {
  37                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
  38                                                       GFP_KERNEL);
  39                 if (!dst->thread.xstate)
  40                         return -ENOMEM;
  41                 WARN_ON((unsigned long)dst->thread.xstate & 15);
  42                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
  43         }
  44         return 0;
  45 }
  46
  47 void free_thread_xstate(struct task_struct *tsk)
  48 {
  49         if (tsk->thread.xstate) {
  50                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
  51                 tsk->thread.xstate = NULL;
  52         }
  53
  54         WARN(tsk->thread.ds_ctx, "leaking DS context\n");
  55 }
  56
  57 void free_thread_info(struct thread_info *ti)
  58 {
  59         free_thread_xstate(ti->task);
  60         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  61 }
  62
  63 void arch_task_cache_init(void)
  64 {
  65         task_xstate_cachep =
  66                 kmem_cache_create("task_xstate", xstate_size,
  67                                   __alignof__(union thread_xstate),
  68                                   SLAB_PANIC | SLAB_NOTRACK, NULL);
  69 }
  70
  71 /*
  72  * Free current thread data structures etc..
  73  */
  74 void exit_thread(void)
  75 {
  76         struct task_struct *me = current;
  77         struct thread_struct *t = &me->thread;
  78         unsigned long *bp = t->io_bitmap_ptr;
  79
  80         if (bp) {
  81                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
  82
  83                 t->io_bitmap_ptr = NULL;
  84                 clear_thread_flag(TIF_IO_BITMAP);
  85                 /*
  86                  * Careful, clear this in the TSS too:
  87                  */
  88                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
  89                 t->io_bitmap_max = 0;
  90                 put_cpu();
  91                 kfree(bp);
  92         }
  93 }
  94
  95 void show_regs_common(void)
  96 {
  97         const char *board, *product;
  98
  99         board = dmi_get_system_info(DMI_BOARD_NAME);
 100         if (!board)
 101                 board = "";
 102         product = dmi_get_system_info(DMI_PRODUCT_NAME);
 103         if (!product)
 104                 product = "";
 105
 106         printk(KERN_CONT "\n");
 107         printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s/%s\n",
 108                 current->pid, current->comm, print_tainted(),
 109                 init_utsname()->release,
 110                 (int)strcspn(init_utsname()->version, " "),
 111                 init_utsname()->version, board, product);
 112 }
 113
 114 void flush_thread(void)
 115 {
 116         struct task_struct *tsk = current;
 117
 118 #ifdef CONFIG_X86_64
 119         if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
 120                 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
 121                 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
 122                         clear_tsk_thread_flag(tsk, TIF_IA32);
 123                 } else {
 124                         set_tsk_thread_flag(tsk, TIF_IA32);
 125                         current_thread_info()->status |= TS_COMPAT;
 126                 }
 127         }
 128 #endif
 129
 130         flush_ptrace_hw_breakpoint(tsk);
 131         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 132         /*
 133          * Forget coprocessor state..
 134          */
 135         tsk->fpu_counter = 0;
 136         clear_fpu(tsk);
 137         clear_used_math();
 138 }
 139
 140 static void hard_disable_TSC(void)
 141 {
 142         write_cr4(read_cr4() | X86_CR4_TSD);
 143 }
 144
 145 void disable_TSC(void)
 146 {
 147         preempt_disable();
 148         if (!test_and_set_thread_flag(TIF_NOTSC))
 149                 /*
 150                  * Must flip the CPU state synchronously with
 151                  * TIF_NOTSC in the current running context.
 152                  */
 153                 hard_disable_TSC();
 154         preempt_enable();
 155 }
 156
 157 static void hard_enable_TSC(void)
 158 {
 159         write_cr4(read_cr4() & ~X86_CR4_TSD);
 160 }
 161
 162 static void enable_TSC(void)
 163 {
 164         preempt_disable();
 165         if (test_and_clear_thread_flag(TIF_NOTSC))
 166                 /*
 167                  * Must flip the CPU state synchronously with
 168                  * TIF_NOTSC in the current running context.
 169                  */
 170                 hard_enable_TSC();
 171         preempt_enable();
 172 }
 173
 174 int get_tsc_mode(unsigned long adr)
 175 {
 176         unsigned int val;
 177
 178         if (test_thread_flag(TIF_NOTSC))
 179                 val = PR_TSC_SIGSEGV;
 180         else
 181                 val = PR_TSC_ENABLE;
 182
 183         return put_user(val, (unsigned int __user *)adr);
 184 }
 185
 186 int set_tsc_mode(unsigned int val)
 187 {
 188         if (val == PR_TSC_SIGSEGV)
 189                 disable_TSC();
 190         else if (val == PR_TSC_ENABLE)
 191                 enable_TSC();
 192         else
 193                 return -EINVAL;
 194
 195         return 0;
 196 }
 197
 198 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 199                       struct tss_struct *tss)
 200 {
 201         struct thread_struct *prev, *next;
 202
 203         prev = &prev_p->thread;
 204         next = &next_p->thread;
 205
 206         if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
 207             test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
 208                 ds_switch_to(prev_p, next_p);
 209         else if (next->debugctlmsr != prev->debugctlmsr)
 210                 update_debugctlmsr(next->debugctlmsr);
 211
 212         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 213             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 214                 /* prev and next are different */
 215                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 216                         hard_disable_TSC();
 217                 else
 218                         hard_enable_TSC();
 219         }
 220
 221         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 222                 /*
 223                  * Copy the relevant range of the IO bitmap.
 224                  * Normally this is 128 bytes or less:
 225                  */
 226                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 227                        max(prev->io_bitmap_max, next->io_bitmap_max));
 228         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 229                 /*
 230                  * Clear any possible leftover bits:
 231                  */
 232                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 233         }
 234         propagate_user_return_notify(prev_p, next_p);
 235 }
 236
 237 int sys_fork(struct pt_regs *regs)
 238 {
 239         return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
 240 }
 241
 242 /*
 243  * This is trivial, and on the face of it looks like it
 244  * could equally well be done in user mode.
 245  *
 246  * Not so, for quite unobvious reasons - register pressure.
 247  * In user mode vfork() cannot have a stack frame, and if
 248  * done by calling the "clone()" system call directly, you
 249  * do not have enough call-clobbered registers to hold all
 250  * the information you need.
 251  */
 252 int sys_vfork(struct pt_regs *regs)
 253 {
 254         return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
 255                        NULL, NULL);
 256 }
 257
 258 long
 259 sys_clone(unsigned long clone_flags, unsigned long newsp,
 260           void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
 261 {
 262         if (!newsp)
 263                 newsp = regs->sp;
 264         return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
 265 }
 266
 267 /*
 268  * This gets run with %si containing the
 269  * function to call, and %di containing
 270  * the "args".
 271  */
 272 extern void kernel_thread_helper(void);
 273
 274 /*
 275  * Create a kernel thread
 276  */
 277 int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
 278 {
 279         struct pt_regs regs;
 280
 281         memset(&regs, 0, sizeof(regs));
 282
 283         regs.si = (unsigned long) fn;
 284         regs.di = (unsigned long) arg;
 285
 286 #ifdef CONFIG_X86_32
 287         regs.ds = __USER_DS;
 288         regs.es = __USER_DS;
 289         regs.fs = __KERNEL_PERCPU;
 290         regs.gs = __KERNEL_STACK_CANARY;
 291 #endif
 292
 293         regs.orig_ax = -1;
 294         regs.ip = (unsigned long) kernel_thread_helper;
 295         regs.cs = __KERNEL_CS | get_kernel_rpl();
 296         regs.flags = X86_EFLAGS_IF | 0x2;
 297
 298         /* Ok, create the new process.. */
 299         return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 300 }
 301 EXPORT_SYMBOL(kernel_thread);
 302
 303 /*
 304  * sys_execve() executes a new program.
 305  */
 306 long sys_execve(char __user *name, char __user * __user *argv,
 307                 char __user * __user *envp, struct pt_regs *regs)
 308 {
 309         long error;
 310         char *filename;
 311
 312         filename = getname(name);
 313         error = PTR_ERR(filename);
 314         if (IS_ERR(filename))
 315                 return error;
 316         error = do_execve(filename, argv, envp, regs);
 317
 318 #ifdef CONFIG_X86_32
 319         if (error == 0) {
 320                 /* Make sure we don't return using sysenter.. */
 321                 set_thread_flag(TIF_IRET);
 322         }
 323 #endif
 324
 325         putname(filename);
 326         return error;
 327 }
 328
 329 /*
 330  * Idle related variables and functions
 331  */
 332 unsigned long boot_option_idle_override = 0;
 333 EXPORT_SYMBOL(boot_option_idle_override);
 334
 335 /*
 336  * Powermanagement idle function, if any..
 337  */
 338 void (*pm_idle)(void);
 339 EXPORT_SYMBOL(pm_idle);
 340
 341 #ifdef CONFIG_X86_32
 342 /*
 343  * This halt magic was a workaround for ancient floppy DMA
 344  * wreckage. It should be safe to remove.
 345  */
 346 static int hlt_counter;
 347 void disable_hlt(void)
 348 {
 349         hlt_counter++;
 350 }
 351 EXPORT_SYMBOL(disable_hlt);
 352
 353 void enable_hlt(void)
 354 {
 355         hlt_counter--;
 356 }
 357 EXPORT_SYMBOL(enable_hlt);
 358
 359 static inline int hlt_use_halt(void)
 360 {
 361         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
 362 }
 363 #else
 364 static inline int hlt_use_halt(void)
 365 {
 366         return 1;
 367 }
 368 #endif
 369
 370 /*
 371  * We use this if we don't have any better
 372  * idle routine..
 373  */
 374 void default_idle(void)
 375 {
 376         if (hlt_use_halt()) {
 377                 trace_power_start(POWER_CSTATE, 1);
 378                 current_thread_info()->status &= ~TS_POLLING;
 379                 /*
 380                  * TS_POLLING-cleared state must be visible before we
 381                  * test NEED_RESCHED:
 382                  */
 383                 smp_mb();
 384
 385                 if (!need_resched())
 386                         safe_halt();    /* enables interrupts racelessly */
 387                 else
 388                         local_irq_enable();
 389                 current_thread_info()->status |= TS_POLLING;
 390         } else {
 391                 local_irq_enable();
 392                 /* loop is done by the caller */
 393                 cpu_relax();
 394         }
 395 }
 396 #ifdef CONFIG_APM_MODULE
 397 EXPORT_SYMBOL(default_idle);
 398 #endif
 399
 400 void stop_this_cpu(void *dummy)
 401 {
 402         local_irq_disable();
 403         /*
 404          * Remove this CPU:
 405          */
 406         set_cpu_online(smp_processor_id(), false);
 407         disable_local_APIC();
 408
 409         for (;;) {
 410                 if (hlt_works(smp_processor_id()))
 411                         halt();
 412         }
 413 }
 414
 415 static void do_nothing(void *unused)
 416 {
 417 }
 418
 419 /*
 420  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 421  * pm_idle and update to new pm_idle value. Required while changing pm_idle
 422  * handler on SMP systems.
 423  *
 424  * Caller must have changed pm_idle to the new value before the call. Old
 425  * pm_idle value will not be used by any CPU after the return of this function.
 426  */
 427 void cpu_idle_wait(void)
 428 {
 429         smp_mb();
 430         /* kick all the CPUs so that they exit out of pm_idle */
 431         smp_call_function(do_nothing, NULL, 1);
 432 }
 433 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 434
 435 /*
 436  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 437  * which can obviate IPI to trigger checking of need_resched.
 438  * We execute MONITOR against need_resched and enter optimized wait state
 439  * through MWAIT. Whenever someone changes need_resched, we would be woken
 440  * up from MWAIT (without an IPI).
 441  *
 442  * New with Core Duo processors, MWAIT can take some hints based on CPU
 443  * capability.
 444  */
 445 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 446 {
 447         trace_power_start(POWER_CSTATE, (ax>>4)+1);
 448         if (!need_resched()) {
 449                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 450                         clflush((void *)&current_thread_info()->flags);
 451
 452                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 453                 smp_mb();
 454                 if (!need_resched())
 455                         __mwait(ax, cx);
 456         }
 457 }
 458
 459 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 460 static void mwait_idle(void)
 461 {
 462         if (!need_resched()) {
 463                 trace_power_start(POWER_CSTATE, 1);
 464                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 465                         clflush((void *)&current_thread_info()->flags);
 466
 467                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 468                 smp_mb();
 469                 if (!need_resched())
 470                         __sti_mwait(0, 0);
 471                 else
 472                         local_irq_enable();
 473         } else
 474                 local_irq_enable();
 475 }
 476
 477 /*
 478  * On SMP it's slightly faster (but much more power-consuming!)
 479  * to poll the ->work.need_resched flag instead of waiting for the
 480  * cross-CPU IPI to arrive. Use this option with caution.
 481  */
 482 static void poll_idle(void)
 483 {
 484         trace_power_start(POWER_CSTATE, 0);
 485         local_irq_enable();
 486         while (!need_resched())
 487                 cpu_relax();
 488         trace_power_end(0);
 489 }
 490
 491 /*
 492  * mwait selection logic:
 493  *
 494  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 495  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 496  * then depend on a clock divisor and current Pstate of the core. If
 497  * all cores of a processor are in halt state (C1) the processor can
 498  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 499  * happen.
 500  *
 501  * idle=mwait overrides this decision and forces the usage of mwait.
 502  */
 503 static int __cpuinitdata force_mwait;
 504
 505 #define MWAIT_INFO                      0x05
 506 #define MWAIT_ECX_EXTENDED_INFO         0x01
 507 #define MWAIT_EDX_C1                    0xf0
 508
 509 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 510 {
 511         u32 eax, ebx, ecx, edx;
 512
 513         if (force_mwait)
 514                 return 1;
 515
 516         if (c->cpuid_level < MWAIT_INFO)
 517                 return 0;
 518
 519         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 520         /* Check, whether EDX has extended info about MWAIT */
 521         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 522                 return 1;
 523
 524         /*
 525          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 526          * C1  supports MWAIT
 527          */
 528         return (edx & MWAIT_EDX_C1);
 529 }
 530
 531 /*
 532  * Check for AMD CPUs, which have potentially C1E support
 533  */
 534 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 535 {
 536         if (c->x86_vendor != X86_VENDOR_AMD)
 537                 return 0;
 538
 539         if (c->x86 < 0x0F)
 540                 return 0;
 541
 542         /* Family 0x0f models < rev F do not have C1E */
 543         if (c->x86 == 0x0f && c->x86_model < 0x40)
 544                 return 0;
 545
 546         return 1;
 547 }
 548
 549 static cpumask_var_t c1e_mask;
 550 static int c1e_detected;
 551
 552 void c1e_remove_cpu(int cpu)
 553 {
 554         if (c1e_mask != NULL)
 555                 cpumask_clear_cpu(cpu, c1e_mask);
 556 }
 557
 558 /*
 559  * C1E aware idle routine. We check for C1E active in the interrupt
 560  * pending message MSR. If we detect C1E, then we handle it the same
 561  * way as C3 power states (local apic timer and TSC stop)
 562  */
 563 static void c1e_idle(void)
 564 {
 565         if (need_resched())
 566                 return;
 567
 568         if (!c1e_detected) {
 569                 u32 lo, hi;
 570
 571                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 572                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 573                         c1e_detected = 1;
 574                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 575                                 mark_tsc_unstable("TSC halt in AMD C1E");
 576                         printk(KERN_INFO "System has AMD C1E enabled\n");
 577                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
 578                 }
 579         }
 580
 581         if (c1e_detected) {
 582                 int cpu = smp_processor_id();
 583
 584                 if (!cpumask_test_cpu(cpu, c1e_mask)) {
 585                         cpumask_set_cpu(cpu, c1e_mask);
 586                         /*
 587                          * Force broadcast so ACPI can not interfere.
 588                          */
 589                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 590                                            &cpu);
 591                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
 592                                cpu);
 593                 }
 594                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 595
 596                 default_idle();
 597
 598                 /*
 599                  * The switch back from broadcast mode needs to be
 600                  * called with interrupts disabled.
 601                  */
 602                  local_irq_disable();
 603                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 604                  local_irq_enable();
 605         } else
 606                 default_idle();
 607 }
 608
 609 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 610 {
 611 #ifdef CONFIG_SMP
 612         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 613                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
 614                         " performance may degrade.\n");
 615         }
 616 #endif
 617         if (pm_idle)
 618                 return;
 619
 620         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 621                 /*
 622                  * One CPU supports mwait => All CPUs supports mwait
 623                  */
 624                 printk(KERN_INFO "using mwait in idle threads.\n");
 625                 pm_idle = mwait_idle;
 626         } else if (check_c1e_idle(c)) {
 627                 printk(KERN_INFO "using C1E aware idle routine\n");
 628                 pm_idle = c1e_idle;
 629         } else
 630                 pm_idle = default_idle;
 631 }
 632
 633 void __init init_c1e_mask(void)
 634 {
 635         /* If we're using c1e_idle, we need to allocate c1e_mask. */
 636         if (pm_idle == c1e_idle)
 637                 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
 638 }
 639
 640 static int __init idle_setup(char *str)
 641 {
 642         if (!str)
 643                 return -EINVAL;
 644
 645         if (!strcmp(str, "poll")) {
 646                 printk("using polling idle threads.\n");
 647                 pm_idle = poll_idle;
 648         } else if (!strcmp(str, "mwait"))
 649                 force_mwait = 1;
 650         else if (!strcmp(str, "halt")) {
 651                 /*
 652                  * When the boot option of idle=halt is added, halt is
 653                  * forced to be used for CPU idle. In such case CPU C2/C3
 654                  * won't be used again.
 655                  * To continue to load the CPU idle driver, don't touch
 656                  * the boot_option_idle_override.
 657                  */
 658                 pm_idle = default_idle;
 659                 idle_halt = 1;
 660                 return 0;
 661         } else if (!strcmp(str, "nomwait")) {
 662                 /*
 663                  * If the boot option of "idle=nomwait" is added,
 664                  * it means that mwait will be disabled for CPU C2/C3
 665                  * states. In such case it won't touch the variable
 666                  * of boot_option_idle_override.
 667                  */
 668                 idle_nomwait = 1;
 669                 return 0;
 670         } else
 671                 return -1;
 672
 673         boot_option_idle_override = 1;
 674         return 0;
 675 }
 676 early_param("idle", idle_setup);
 677
 678 unsigned long arch_align_stack(unsigned long sp)
 679 {
 680         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 681                 sp -= get_random_int() % 8192;
 682         return sp & ~0xf;
 683 }
 684
 685 unsigned long arch_randomize_brk(struct mm_struct *mm)
 686 {
 687         unsigned long range_end = mm->brk + 0x02000000;
 688         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 689 }
 690