1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/sysdev.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/hpet.h>
8 #include <linux/init.h>
13 #include <asm/fixmap.h>
14 #include <asm/i8253.h>
17 #define HPET_MASK CLOCKSOURCE_MASK(32)
22 #define FSEC_PER_NSEC 1000000L
24 #define HPET_DEV_USED_BIT 2
25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
26 #define HPET_DEV_VALID 0x8
27 #define HPET_DEV_FSB_CAP 0x1000
28 #define HPET_DEV_PERI_CAP 0x2000
30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
33 * HPET address is set in acpi/boot.c, when an ACPI entry exists
35 unsigned long hpet_address
;
36 u8 hpet_blockid
; /* OS timer block num */
38 static unsigned long hpet_num_timers
;
40 static void __iomem
*hpet_virt_address
;
43 struct clock_event_device evt
;
51 inline unsigned int hpet_readl(unsigned int a
)
53 return readl(hpet_virt_address
+ a
);
56 static inline void hpet_writel(unsigned int d
, unsigned int a
)
58 writel(d
, hpet_virt_address
+ a
);
62 #include <asm/pgtable.h>
65 static inline void hpet_set_mapping(void)
67 hpet_virt_address
= ioremap_nocache(hpet_address
, HPET_MMAP_SIZE
);
69 __set_fixmap(VSYSCALL_HPET
, hpet_address
, PAGE_KERNEL_VSYSCALL_NOCACHE
);
73 static inline void hpet_clear_mapping(void)
75 iounmap(hpet_virt_address
);
76 hpet_virt_address
= NULL
;
80 * HPET command line enable / disable
82 static int boot_hpet_disable
;
84 static int hpet_verbose
;
86 static int __init
hpet_setup(char *str
)
89 if (!strncmp("disable", str
, 7))
90 boot_hpet_disable
= 1;
91 if (!strncmp("force", str
, 5))
93 if (!strncmp("verbose", str
, 7))
98 __setup("hpet=", hpet_setup
);
100 static int __init
disable_hpet(char *str
)
102 boot_hpet_disable
= 1;
105 __setup("nohpet", disable_hpet
);
107 static inline int is_hpet_capable(void)
109 return !boot_hpet_disable
&& hpet_address
;
113 * HPET timer interrupt enable / disable
115 static int hpet_legacy_int_enabled
;
118 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
120 int is_hpet_enabled(void)
122 return is_hpet_capable() && hpet_legacy_int_enabled
;
124 EXPORT_SYMBOL_GPL(is_hpet_enabled
);
126 static void _hpet_print_config(const char *function
, int line
)
129 printk(KERN_INFO
"hpet: %s(%d):\n", function
, line
);
130 l
= hpet_readl(HPET_ID
);
131 h
= hpet_readl(HPET_PERIOD
);
132 timers
= ((l
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
) + 1;
133 printk(KERN_INFO
"hpet: ID: 0x%x, PERIOD: 0x%x\n", l
, h
);
134 l
= hpet_readl(HPET_CFG
);
135 h
= hpet_readl(HPET_STATUS
);
136 printk(KERN_INFO
"hpet: CFG: 0x%x, STATUS: 0x%x\n", l
, h
);
137 l
= hpet_readl(HPET_COUNTER
);
138 h
= hpet_readl(HPET_COUNTER
+4);
139 printk(KERN_INFO
"hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l
, h
);
141 for (i
= 0; i
< timers
; i
++) {
142 l
= hpet_readl(HPET_Tn_CFG(i
));
143 h
= hpet_readl(HPET_Tn_CFG(i
)+4);
144 printk(KERN_INFO
"hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
146 l
= hpet_readl(HPET_Tn_CMP(i
));
147 h
= hpet_readl(HPET_Tn_CMP(i
)+4);
148 printk(KERN_INFO
"hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
150 l
= hpet_readl(HPET_Tn_ROUTE(i
));
151 h
= hpet_readl(HPET_Tn_ROUTE(i
)+4);
152 printk(KERN_INFO
"hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
157 #define hpet_print_config() \
160 _hpet_print_config(__FUNCTION__, __LINE__); \
164 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
165 * timer 0 and timer 1 in case of RTC emulation.
169 static void hpet_reserve_msi_timers(struct hpet_data
*hd
);
171 static void hpet_reserve_platform_timers(unsigned int id
)
173 struct hpet __iomem
*hpet
= hpet_virt_address
;
174 struct hpet_timer __iomem
*timer
= &hpet
->hpet_timers
[2];
175 unsigned int nrtimers
, i
;
178 nrtimers
= ((id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
) + 1;
180 memset(&hd
, 0, sizeof(hd
));
181 hd
.hd_phys_address
= hpet_address
;
182 hd
.hd_address
= hpet
;
183 hd
.hd_nirqs
= nrtimers
;
184 hpet_reserve_timer(&hd
, 0);
186 #ifdef CONFIG_HPET_EMULATE_RTC
187 hpet_reserve_timer(&hd
, 1);
191 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
192 * is wrong for i8259!) not the output IRQ. Many BIOS writers
193 * don't bother configuring *any* comparator interrupts.
195 hd
.hd_irq
[0] = HPET_LEGACY_8254
;
196 hd
.hd_irq
[1] = HPET_LEGACY_RTC
;
198 for (i
= 2; i
< nrtimers
; timer
++, i
++) {
199 hd
.hd_irq
[i
] = (readl(&timer
->hpet_config
) &
200 Tn_INT_ROUTE_CNF_MASK
) >> Tn_INT_ROUTE_CNF_SHIFT
;
203 hpet_reserve_msi_timers(&hd
);
209 static void hpet_reserve_platform_timers(unsigned int id
) { }
215 static unsigned long hpet_period
;
217 static void hpet_legacy_set_mode(enum clock_event_mode mode
,
218 struct clock_event_device
*evt
);
219 static int hpet_legacy_next_event(unsigned long delta
,
220 struct clock_event_device
*evt
);
223 * The hpet clock event device
225 static struct clock_event_device hpet_clockevent
= {
227 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
228 .set_mode
= hpet_legacy_set_mode
,
229 .set_next_event
= hpet_legacy_next_event
,
235 static void hpet_stop_counter(void)
237 unsigned long cfg
= hpet_readl(HPET_CFG
);
238 cfg
&= ~HPET_CFG_ENABLE
;
239 hpet_writel(cfg
, HPET_CFG
);
242 static void hpet_reset_counter(void)
244 hpet_writel(0, HPET_COUNTER
);
245 hpet_writel(0, HPET_COUNTER
+ 4);
248 static void hpet_start_counter(void)
250 unsigned int cfg
= hpet_readl(HPET_CFG
);
251 cfg
|= HPET_CFG_ENABLE
;
252 hpet_writel(cfg
, HPET_CFG
);
255 static void hpet_restart_counter(void)
258 hpet_reset_counter();
259 hpet_start_counter();
262 static void hpet_resume_device(void)
267 static void hpet_resume_counter(void)
269 hpet_resume_device();
270 hpet_restart_counter();
273 static void hpet_enable_legacy_int(void)
275 unsigned int cfg
= hpet_readl(HPET_CFG
);
277 cfg
|= HPET_CFG_LEGACY
;
278 hpet_writel(cfg
, HPET_CFG
);
279 hpet_legacy_int_enabled
= 1;
282 static void hpet_legacy_clockevent_register(void)
284 /* Start HPET legacy interrupts */
285 hpet_enable_legacy_int();
288 * The mult factor is defined as (include/linux/clockchips.h)
289 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
290 * hpet_period is in units of femtoseconds (per cycle), so
291 * mult/2^shift = cyc/ns = 10^6/hpet_period
292 * mult = (10^6 * 2^shift)/hpet_period
293 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
295 hpet_clockevent
.mult
= div_sc((unsigned long) FSEC_PER_NSEC
,
296 hpet_period
, hpet_clockevent
.shift
);
297 /* Calculate the min / max delta */
298 hpet_clockevent
.max_delta_ns
= clockevent_delta2ns(0x7FFFFFFF,
300 /* 5 usec minimum reprogramming delta. */
301 hpet_clockevent
.min_delta_ns
= 5000;
304 * Start hpet with the boot cpu mask and make it
305 * global after the IO_APIC has been initialized.
307 hpet_clockevent
.cpumask
= cpumask_of(smp_processor_id());
308 clockevents_register_device(&hpet_clockevent
);
309 global_clock_event
= &hpet_clockevent
;
310 printk(KERN_DEBUG
"hpet clockevent registered\n");
313 static int hpet_setup_msi_irq(unsigned int irq
);
315 static void hpet_set_mode(enum clock_event_mode mode
,
316 struct clock_event_device
*evt
, int timer
)
318 unsigned int cfg
, cmp
, now
;
322 case CLOCK_EVT_MODE_PERIODIC
:
324 delta
= ((uint64_t)(NSEC_PER_SEC
/HZ
)) * evt
->mult
;
325 delta
>>= evt
->shift
;
326 now
= hpet_readl(HPET_COUNTER
);
327 cmp
= now
+ (unsigned int) delta
;
328 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
329 /* Make sure we use edge triggered interrupts */
330 cfg
&= ~HPET_TN_LEVEL
;
331 cfg
|= HPET_TN_ENABLE
| HPET_TN_PERIODIC
|
332 HPET_TN_SETVAL
| HPET_TN_32BIT
;
333 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
334 hpet_writel(cmp
, HPET_Tn_CMP(timer
));
337 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
338 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
339 * bit is automatically cleared after the first write.
340 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
341 * Publication # 24674)
343 hpet_writel((unsigned int) delta
, HPET_Tn_CMP(timer
));
344 hpet_start_counter();
348 case CLOCK_EVT_MODE_ONESHOT
:
349 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
350 cfg
&= ~HPET_TN_PERIODIC
;
351 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
352 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
355 case CLOCK_EVT_MODE_UNUSED
:
356 case CLOCK_EVT_MODE_SHUTDOWN
:
357 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
358 cfg
&= ~HPET_TN_ENABLE
;
359 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
362 case CLOCK_EVT_MODE_RESUME
:
364 hpet_enable_legacy_int();
366 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
367 hpet_setup_msi_irq(hdev
->irq
);
368 disable_irq(hdev
->irq
);
369 irq_set_affinity(hdev
->irq
, cpumask_of(hdev
->cpu
));
370 enable_irq(hdev
->irq
);
377 static int hpet_next_event(unsigned long delta
,
378 struct clock_event_device
*evt
, int timer
)
382 cnt
= hpet_readl(HPET_COUNTER
);
384 hpet_writel(cnt
, HPET_Tn_CMP(timer
));
387 * We need to read back the CMP register on certain HPET
388 * implementations (ATI chipsets) which seem to delay the
389 * transfer of the compare register into the internal compare
390 * logic. With small deltas this might actually be too late as
391 * the counter could already be higher than the compare value
392 * at that point and we would wait for the next hpet interrupt
393 * forever. We found out that reading the CMP register back
394 * forces the transfer so we can rely on the comparison with
395 * the counter register below. If the read back from the
396 * compare register does not match the value we programmed
397 * then we might have a real hardware problem. We can not do
398 * much about it here, but at least alert the user/admin with
399 * a prominent warning.
401 WARN_ONCE(hpet_readl(HPET_Tn_CMP(timer
)) != cnt
,
402 KERN_WARNING
"hpet: compare register read back failed.\n");
404 return (s32
)(hpet_readl(HPET_COUNTER
) - cnt
) >= 0 ? -ETIME
: 0;
407 static void hpet_legacy_set_mode(enum clock_event_mode mode
,
408 struct clock_event_device
*evt
)
410 hpet_set_mode(mode
, evt
, 0);
413 static int hpet_legacy_next_event(unsigned long delta
,
414 struct clock_event_device
*evt
)
416 return hpet_next_event(delta
, evt
, 0);
422 #ifdef CONFIG_PCI_MSI
424 static DEFINE_PER_CPU(struct hpet_dev
*, cpu_hpet_dev
);
425 static struct hpet_dev
*hpet_devs
;
427 void hpet_msi_unmask(unsigned int irq
)
429 struct hpet_dev
*hdev
= get_irq_data(irq
);
433 cfg
= hpet_readl(HPET_Tn_CFG(hdev
->num
));
435 hpet_writel(cfg
, HPET_Tn_CFG(hdev
->num
));
438 void hpet_msi_mask(unsigned int irq
)
441 struct hpet_dev
*hdev
= get_irq_data(irq
);
444 cfg
= hpet_readl(HPET_Tn_CFG(hdev
->num
));
446 hpet_writel(cfg
, HPET_Tn_CFG(hdev
->num
));
449 void hpet_msi_write(unsigned int irq
, struct msi_msg
*msg
)
451 struct hpet_dev
*hdev
= get_irq_data(irq
);
453 hpet_writel(msg
->data
, HPET_Tn_ROUTE(hdev
->num
));
454 hpet_writel(msg
->address_lo
, HPET_Tn_ROUTE(hdev
->num
) + 4);
457 void hpet_msi_read(unsigned int irq
, struct msi_msg
*msg
)
459 struct hpet_dev
*hdev
= get_irq_data(irq
);
461 msg
->data
= hpet_readl(HPET_Tn_ROUTE(hdev
->num
));
462 msg
->address_lo
= hpet_readl(HPET_Tn_ROUTE(hdev
->num
) + 4);
466 static void hpet_msi_set_mode(enum clock_event_mode mode
,
467 struct clock_event_device
*evt
)
469 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
470 hpet_set_mode(mode
, evt
, hdev
->num
);
473 static int hpet_msi_next_event(unsigned long delta
,
474 struct clock_event_device
*evt
)
476 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
477 return hpet_next_event(delta
, evt
, hdev
->num
);
480 static int hpet_setup_msi_irq(unsigned int irq
)
482 if (arch_setup_hpet_msi(irq
, hpet_blockid
)) {
489 static int hpet_assign_irq(struct hpet_dev
*dev
)
497 set_irq_data(irq
, dev
);
499 if (hpet_setup_msi_irq(irq
))
506 static irqreturn_t
hpet_interrupt_handler(int irq
, void *data
)
508 struct hpet_dev
*dev
= (struct hpet_dev
*)data
;
509 struct clock_event_device
*hevt
= &dev
->evt
;
511 if (!hevt
->event_handler
) {
512 printk(KERN_INFO
"Spurious HPET timer interrupt on HPET timer %d\n",
517 hevt
->event_handler(hevt
);
521 static int hpet_setup_irq(struct hpet_dev
*dev
)
524 if (request_irq(dev
->irq
, hpet_interrupt_handler
,
525 IRQF_TIMER
| IRQF_DISABLED
| IRQF_NOBALANCING
,
529 disable_irq(dev
->irq
);
530 irq_set_affinity(dev
->irq
, cpumask_of(dev
->cpu
));
531 enable_irq(dev
->irq
);
533 printk(KERN_DEBUG
"hpet: %s irq %d for MSI\n",
534 dev
->name
, dev
->irq
);
539 /* This should be called in specific @cpu */
540 static void init_one_hpet_msi_clockevent(struct hpet_dev
*hdev
, int cpu
)
542 struct clock_event_device
*evt
= &hdev
->evt
;
545 WARN_ON(cpu
!= smp_processor_id());
546 if (!(hdev
->flags
& HPET_DEV_VALID
))
549 if (hpet_setup_msi_irq(hdev
->irq
))
553 per_cpu(cpu_hpet_dev
, cpu
) = hdev
;
554 evt
->name
= hdev
->name
;
555 hpet_setup_irq(hdev
);
556 evt
->irq
= hdev
->irq
;
559 evt
->features
= CLOCK_EVT_FEAT_ONESHOT
;
560 if (hdev
->flags
& HPET_DEV_PERI_CAP
)
561 evt
->features
|= CLOCK_EVT_FEAT_PERIODIC
;
563 evt
->set_mode
= hpet_msi_set_mode
;
564 evt
->set_next_event
= hpet_msi_next_event
;
568 * The period is a femto seconds value. We need to calculate the
569 * scaled math multiplication factor for nanosecond to hpet tick
572 hpet_freq
= 1000000000000000ULL;
573 do_div(hpet_freq
, hpet_period
);
574 evt
->mult
= div_sc((unsigned long) hpet_freq
,
575 NSEC_PER_SEC
, evt
->shift
);
576 /* Calculate the max delta */
577 evt
->max_delta_ns
= clockevent_delta2ns(0x7FFFFFFF, evt
);
578 /* 5 usec minimum reprogramming delta. */
579 evt
->min_delta_ns
= 5000;
581 evt
->cpumask
= cpumask_of(hdev
->cpu
);
582 clockevents_register_device(evt
);
586 /* Reserve at least one timer for userspace (/dev/hpet) */
587 #define RESERVE_TIMERS 1
589 #define RESERVE_TIMERS 0
592 static void hpet_msi_capability_lookup(unsigned int start_timer
)
595 unsigned int num_timers
;
596 unsigned int num_timers_used
= 0;
599 if (boot_cpu_has(X86_FEATURE_ARAT
))
601 id
= hpet_readl(HPET_ID
);
603 num_timers
= ((id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
);
604 num_timers
++; /* Value read out starts from 0 */
607 hpet_devs
= kzalloc(sizeof(struct hpet_dev
) * num_timers
, GFP_KERNEL
);
611 hpet_num_timers
= num_timers
;
613 for (i
= start_timer
; i
< num_timers
- RESERVE_TIMERS
; i
++) {
614 struct hpet_dev
*hdev
= &hpet_devs
[num_timers_used
];
615 unsigned int cfg
= hpet_readl(HPET_Tn_CFG(i
));
617 /* Only consider HPET timer with MSI support */
618 if (!(cfg
& HPET_TN_FSB_CAP
))
622 if (cfg
& HPET_TN_PERIODIC_CAP
)
623 hdev
->flags
|= HPET_DEV_PERI_CAP
;
626 sprintf(hdev
->name
, "hpet%d", i
);
627 if (hpet_assign_irq(hdev
))
630 hdev
->flags
|= HPET_DEV_FSB_CAP
;
631 hdev
->flags
|= HPET_DEV_VALID
;
633 if (num_timers_used
== num_possible_cpus())
637 printk(KERN_INFO
"HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
638 num_timers
, num_timers_used
);
642 static void hpet_reserve_msi_timers(struct hpet_data
*hd
)
649 for (i
= 0; i
< hpet_num_timers
; i
++) {
650 struct hpet_dev
*hdev
= &hpet_devs
[i
];
652 if (!(hdev
->flags
& HPET_DEV_VALID
))
655 hd
->hd_irq
[hdev
->num
] = hdev
->irq
;
656 hpet_reserve_timer(hd
, hdev
->num
);
661 static struct hpet_dev
*hpet_get_unused_timer(void)
668 for (i
= 0; i
< hpet_num_timers
; i
++) {
669 struct hpet_dev
*hdev
= &hpet_devs
[i
];
671 if (!(hdev
->flags
& HPET_DEV_VALID
))
673 if (test_and_set_bit(HPET_DEV_USED_BIT
,
674 (unsigned long *)&hdev
->flags
))
681 struct hpet_work_struct
{
682 struct delayed_work work
;
683 struct completion complete
;
686 static void hpet_work(struct work_struct
*w
)
688 struct hpet_dev
*hdev
;
689 int cpu
= smp_processor_id();
690 struct hpet_work_struct
*hpet_work
;
692 hpet_work
= container_of(w
, struct hpet_work_struct
, work
.work
);
694 hdev
= hpet_get_unused_timer();
696 init_one_hpet_msi_clockevent(hdev
, cpu
);
698 complete(&hpet_work
->complete
);
701 static int hpet_cpuhp_notify(struct notifier_block
*n
,
702 unsigned long action
, void *hcpu
)
704 unsigned long cpu
= (unsigned long)hcpu
;
705 struct hpet_work_struct work
;
706 struct hpet_dev
*hdev
= per_cpu(cpu_hpet_dev
, cpu
);
708 switch (action
& 0xf) {
710 INIT_DELAYED_WORK_ON_STACK(&work
.work
, hpet_work
);
711 init_completion(&work
.complete
);
712 /* FIXME: add schedule_work_on() */
713 schedule_delayed_work_on(cpu
, &work
.work
, 0);
714 wait_for_completion(&work
.complete
);
715 destroy_timer_on_stack(&work
.work
.timer
);
719 free_irq(hdev
->irq
, hdev
);
720 hdev
->flags
&= ~HPET_DEV_USED
;
721 per_cpu(cpu_hpet_dev
, cpu
) = NULL
;
729 static int hpet_setup_msi_irq(unsigned int irq
)
733 static void hpet_msi_capability_lookup(unsigned int start_timer
)
739 static void hpet_reserve_msi_timers(struct hpet_data
*hd
)
745 static int hpet_cpuhp_notify(struct notifier_block
*n
,
746 unsigned long action
, void *hcpu
)
754 * Clock source related code
756 static cycle_t
read_hpet(struct clocksource
*cs
)
758 return (cycle_t
)hpet_readl(HPET_COUNTER
);
762 static cycle_t __vsyscall_fn
vread_hpet(void)
764 return readl((const void __iomem
*)fix_to_virt(VSYSCALL_HPET
) + 0xf0);
768 static struct clocksource clocksource_hpet
= {
774 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
775 .resume
= hpet_resume_counter
,
781 static int hpet_clocksource_register(void)
786 /* Start the counter */
787 hpet_restart_counter();
789 /* Verify whether hpet counter works */
790 t1
= hpet_readl(HPET_COUNTER
);
794 * We don't know the TSC frequency yet, but waiting for
795 * 200000 TSC cycles is safe:
802 } while ((now
- start
) < 200000UL);
804 if (t1
== hpet_readl(HPET_COUNTER
)) {
806 "HPET counter not counting. HPET disabled\n");
811 * The definition of mult is (include/linux/clocksource.h)
812 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
813 * so we first need to convert hpet_period to ns/cyc units:
814 * mult/2^shift = ns/cyc = hpet_period/10^6
815 * mult = (hpet_period * 2^shift)/10^6
816 * mult = (hpet_period << shift)/FSEC_PER_NSEC
818 clocksource_hpet
.mult
= div_sc(hpet_period
, FSEC_PER_NSEC
, HPET_SHIFT
);
820 clocksource_register(&clocksource_hpet
);
826 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
828 int __init
hpet_enable(void)
833 if (!is_hpet_capable())
839 * Read the period and check for a sane value:
841 hpet_period
= hpet_readl(HPET_PERIOD
);
844 * AMD SB700 based systems with spread spectrum enabled use a
845 * SMM based HPET emulation to provide proper frequency
846 * setting. The SMM code is initialized with the first HPET
847 * register access and takes some time to complete. During
848 * this time the config register reads 0xffffffff. We check
849 * for max. 1000 loops whether the config register reads a non
850 * 0xffffffff value to make sure that HPET is up and running
851 * before we go further. A counting loop is safe, as the HPET
852 * access takes thousands of CPU cycles. On non SB700 based
853 * machines this check is only done once and has no side
856 for (i
= 0; hpet_readl(HPET_CFG
) == 0xFFFFFFFF; i
++) {
859 "HPET config register value = 0xFFFFFFFF. "
865 if (hpet_period
< HPET_MIN_PERIOD
|| hpet_period
> HPET_MAX_PERIOD
)
869 * Read the HPET ID register to retrieve the IRQ routing
870 * information and the number of channels
872 id
= hpet_readl(HPET_ID
);
875 #ifdef CONFIG_HPET_EMULATE_RTC
877 * The legacy routing mode needs at least two channels, tick timer
878 * and the rtc emulation channel.
880 if (!(id
& HPET_ID_NUMBER
))
884 if (hpet_clocksource_register())
887 if (id
& HPET_ID_LEGSUP
) {
888 hpet_legacy_clockevent_register();
894 hpet_clear_mapping();
900 * Needs to be late, as the reserve_timer code calls kalloc !
902 * Not a problem on i386 as hpet_enable is called from late_time_init,
903 * but on x86_64 it is necessary !
905 static __init
int hpet_late_init(void)
909 if (boot_hpet_disable
)
913 if (!force_hpet_address
)
916 hpet_address
= force_hpet_address
;
920 if (!hpet_virt_address
)
923 if (hpet_readl(HPET_ID
) & HPET_ID_LEGSUP
)
924 hpet_msi_capability_lookup(2);
926 hpet_msi_capability_lookup(0);
928 hpet_reserve_platform_timers(hpet_readl(HPET_ID
));
931 if (boot_cpu_has(X86_FEATURE_ARAT
))
934 for_each_online_cpu(cpu
) {
935 hpet_cpuhp_notify(NULL
, CPU_ONLINE
, (void *)(long)cpu
);
938 /* This notifier should be called after workqueue is ready */
939 hotcpu_notifier(hpet_cpuhp_notify
, -20);
943 fs_initcall(hpet_late_init
);
945 void hpet_disable(void)
947 if (is_hpet_capable()) {
948 unsigned int cfg
= hpet_readl(HPET_CFG
);
950 if (hpet_legacy_int_enabled
) {
951 cfg
&= ~HPET_CFG_LEGACY
;
952 hpet_legacy_int_enabled
= 0;
954 cfg
&= ~HPET_CFG_ENABLE
;
955 hpet_writel(cfg
, HPET_CFG
);
959 #ifdef CONFIG_HPET_EMULATE_RTC
961 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
962 * is enabled, we support RTC interrupt functionality in software.
963 * RTC has 3 kinds of interrupts:
964 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
966 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
967 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
968 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
969 * (1) and (2) above are implemented using polling at a frequency of
970 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
971 * overhead. (DEFAULT_RTC_INT_FREQ)
972 * For (3), we use interrupts at 64Hz or user specified periodic
973 * frequency, whichever is higher.
975 #include <linux/mc146818rtc.h>
976 #include <linux/rtc.h>
979 #define DEFAULT_RTC_INT_FREQ 64
980 #define DEFAULT_RTC_SHIFT 6
981 #define RTC_NUM_INTS 1
983 static unsigned long hpet_rtc_flags
;
984 static int hpet_prev_update_sec
;
985 static struct rtc_time hpet_alarm_time
;
986 static unsigned long hpet_pie_count
;
987 static u32 hpet_t1_cmp
;
988 static u32 hpet_default_delta
;
989 static u32 hpet_pie_delta
;
990 static unsigned long hpet_pie_limit
;
992 static rtc_irq_handler irq_handler
;
995 * Check that the hpet counter c1 is ahead of the c2
997 static inline int hpet_cnt_ahead(u32 c1
, u32 c2
)
999 return (s32
)(c2
- c1
) < 0;
1003 * Registers a IRQ handler.
1005 int hpet_register_irq_handler(rtc_irq_handler handler
)
1007 if (!is_hpet_enabled())
1012 irq_handler
= handler
;
1016 EXPORT_SYMBOL_GPL(hpet_register_irq_handler
);
1019 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1022 void hpet_unregister_irq_handler(rtc_irq_handler handler
)
1024 if (!is_hpet_enabled())
1030 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler
);
1033 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1034 * is not supported by all HPET implementations for timer 1.
1036 * hpet_rtc_timer_init() is called when the rtc is initialized.
1038 int hpet_rtc_timer_init(void)
1040 unsigned int cfg
, cnt
, delta
;
1041 unsigned long flags
;
1043 if (!is_hpet_enabled())
1046 if (!hpet_default_delta
) {
1049 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
1050 clc
>>= hpet_clockevent
.shift
+ DEFAULT_RTC_SHIFT
;
1051 hpet_default_delta
= clc
;
1054 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
1055 delta
= hpet_default_delta
;
1057 delta
= hpet_pie_delta
;
1059 local_irq_save(flags
);
1061 cnt
= delta
+ hpet_readl(HPET_COUNTER
);
1062 hpet_writel(cnt
, HPET_T1_CMP
);
1065 cfg
= hpet_readl(HPET_T1_CFG
);
1066 cfg
&= ~HPET_TN_PERIODIC
;
1067 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
1068 hpet_writel(cfg
, HPET_T1_CFG
);
1070 local_irq_restore(flags
);
1074 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init
);
1077 * The functions below are called from rtc driver.
1078 * Return 0 if HPET is not being used.
1079 * Otherwise do the necessary changes and return 1.
1081 int hpet_mask_rtc_irq_bit(unsigned long bit_mask
)
1083 if (!is_hpet_enabled())
1086 hpet_rtc_flags
&= ~bit_mask
;
1089 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit
);
1091 int hpet_set_rtc_irq_bit(unsigned long bit_mask
)
1093 unsigned long oldbits
= hpet_rtc_flags
;
1095 if (!is_hpet_enabled())
1098 hpet_rtc_flags
|= bit_mask
;
1100 if ((bit_mask
& RTC_UIE
) && !(oldbits
& RTC_UIE
))
1101 hpet_prev_update_sec
= -1;
1104 hpet_rtc_timer_init();
1108 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit
);
1110 int hpet_set_alarm_time(unsigned char hrs
, unsigned char min
,
1113 if (!is_hpet_enabled())
1116 hpet_alarm_time
.tm_hour
= hrs
;
1117 hpet_alarm_time
.tm_min
= min
;
1118 hpet_alarm_time
.tm_sec
= sec
;
1122 EXPORT_SYMBOL_GPL(hpet_set_alarm_time
);
1124 int hpet_set_periodic_freq(unsigned long freq
)
1128 if (!is_hpet_enabled())
1131 if (freq
<= DEFAULT_RTC_INT_FREQ
)
1132 hpet_pie_limit
= DEFAULT_RTC_INT_FREQ
/ freq
;
1134 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
1136 clc
>>= hpet_clockevent
.shift
;
1137 hpet_pie_delta
= clc
;
1141 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq
);
1143 int hpet_rtc_dropped_irq(void)
1145 return is_hpet_enabled();
1147 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq
);
1149 static void hpet_rtc_timer_reinit(void)
1151 unsigned int cfg
, delta
;
1154 if (unlikely(!hpet_rtc_flags
)) {
1155 cfg
= hpet_readl(HPET_T1_CFG
);
1156 cfg
&= ~HPET_TN_ENABLE
;
1157 hpet_writel(cfg
, HPET_T1_CFG
);
1161 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
1162 delta
= hpet_default_delta
;
1164 delta
= hpet_pie_delta
;
1167 * Increment the comparator value until we are ahead of the
1171 hpet_t1_cmp
+= delta
;
1172 hpet_writel(hpet_t1_cmp
, HPET_T1_CMP
);
1174 } while (!hpet_cnt_ahead(hpet_t1_cmp
, hpet_readl(HPET_COUNTER
)));
1177 if (hpet_rtc_flags
& RTC_PIE
)
1178 hpet_pie_count
+= lost_ints
;
1179 if (printk_ratelimit())
1180 printk(KERN_WARNING
"hpet1: lost %d rtc interrupts\n",
1185 irqreturn_t
hpet_rtc_interrupt(int irq
, void *dev_id
)
1187 struct rtc_time curr_time
;
1188 unsigned long rtc_int_flag
= 0;
1190 hpet_rtc_timer_reinit();
1191 memset(&curr_time
, 0, sizeof(struct rtc_time
));
1193 if (hpet_rtc_flags
& (RTC_UIE
| RTC_AIE
))
1194 get_rtc_time(&curr_time
);
1196 if (hpet_rtc_flags
& RTC_UIE
&&
1197 curr_time
.tm_sec
!= hpet_prev_update_sec
) {
1198 if (hpet_prev_update_sec
>= 0)
1199 rtc_int_flag
= RTC_UF
;
1200 hpet_prev_update_sec
= curr_time
.tm_sec
;
1203 if (hpet_rtc_flags
& RTC_PIE
&&
1204 ++hpet_pie_count
>= hpet_pie_limit
) {
1205 rtc_int_flag
|= RTC_PF
;
1209 if (hpet_rtc_flags
& RTC_AIE
&&
1210 (curr_time
.tm_sec
== hpet_alarm_time
.tm_sec
) &&
1211 (curr_time
.tm_min
== hpet_alarm_time
.tm_min
) &&
1212 (curr_time
.tm_hour
== hpet_alarm_time
.tm_hour
))
1213 rtc_int_flag
|= RTC_AF
;
1216 rtc_int_flag
|= (RTC_IRQF
| (RTC_NUM_INTS
<< 8));
1218 irq_handler(rtc_int_flag
, dev_id
);
1222 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt
);