arch/sh/drivers/dma/dma-sh.c

   1 /*
   2  * arch/sh/drivers/dma/dma-sh.c
   3  *
   4  * SuperH On-chip DMAC Support
   5  *
   6  * Copyright (C) 2000 Takashi YOSHII
   7  * Copyright (C) 2003, 2004 Paul Mundt
   8  * Copyright (C) 2005 Andriy Skulysh
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/module.h>
  17 #include <asm/dreamcast/dma.h>
  18 #include <asm/dma.h>
  19 #include <asm/io.h>
  20 #include "dma-sh.h"
  21
  22 static int dmte_irq_map[] = {
  23         DMTE0_IRQ,
  24         DMTE1_IRQ,
  25         DMTE2_IRQ,
  26         DMTE3_IRQ,
  27 #if defined(CONFIG_CPU_SUBTYPE_SH7720)  ||      \
  28     defined(CONFIG_CPU_SUBTYPE_SH7751R) ||      \
  29     defined(CONFIG_CPU_SUBTYPE_SH7760)  ||      \
  30     defined(CONFIG_CPU_SUBTYPE_SH7709)  ||      \
  31     defined(CONFIG_CPU_SUBTYPE_SH7780)
  32         DMTE4_IRQ,
  33         DMTE5_IRQ,
  34 #endif
  35 #if defined(CONFIG_CPU_SUBTYPE_SH7751R) ||      \
  36     defined(CONFIG_CPU_SUBTYPE_SH7760)  ||      \
  37     defined(CONFIG_CPU_SUBTYPE_SH7780)
  38         DMTE6_IRQ,
  39         DMTE7_IRQ,
  40 #endif
  41 };
  42
  43 static inline unsigned int get_dmte_irq(unsigned int chan)
  44 {
  45         unsigned int irq = 0;
  46         if (chan < ARRAY_SIZE(dmte_irq_map))
  47                 irq = dmte_irq_map[chan];
  48         return irq;
  49 }
  50
  51 /*
  52  * We determine the correct shift size based off of the CHCR transmit size
  53  * for the given channel. Since we know that it will take:
  54  *
  55  *      info->count >> ts_shift[transmit_size]
  56  *
  57  * iterations to complete the transfer.
  58  */
  59 static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
  60 {
  61         u32 chcr = ctrl_inl(CHCR[chan->chan]);
  62
  63         return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
  64 }
  65
  66 /*
  67  * The transfer end interrupt must read the chcr register to end the
  68  * hardware interrupt active condition.
  69  * Besides that it needs to waken any waiting process, which should handle
  70  * setting up the next transfer.
  71  */
  72 static irqreturn_t dma_tei(int irq, void *dev_id)
  73 {
  74         struct dma_channel *chan = dev_id;
  75         u32 chcr;
  76
  77         chcr = ctrl_inl(CHCR[chan->chan]);
  78
  79         if (!(chcr & CHCR_TE))
  80                 return IRQ_NONE;
  81
  82         chcr &= ~(CHCR_IE | CHCR_DE);
  83         ctrl_outl(chcr, CHCR[chan->chan]);
  84
  85         wake_up(&chan->wait_queue);
  86
  87         return IRQ_HANDLED;
  88 }
  89
  90 static int sh_dmac_request_dma(struct dma_channel *chan)
  91 {
  92         if (unlikely(!chan->flags & DMA_TEI_CAPABLE))
  93                 return 0;
  94
  95         return request_irq(get_dmte_irq(chan->chan), dma_tei,
  96                            IRQF_DISABLED, chan->dev_id, chan);
  97 }
  98
  99 static void sh_dmac_free_dma(struct dma_channel *chan)
 100 {
 101         free_irq(get_dmte_irq(chan->chan), chan);
 102 }
 103
 104 static int
 105 sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
 106 {
 107         if (!chcr)
 108                 chcr = RS_DUAL | CHCR_IE;
 109
 110         if (chcr & CHCR_IE) {
 111                 chcr &= ~CHCR_IE;
 112                 chan->flags |= DMA_TEI_CAPABLE;
 113         } else {
 114                 chan->flags &= ~DMA_TEI_CAPABLE;
 115         }
 116
 117         ctrl_outl(chcr, CHCR[chan->chan]);
 118
 119         chan->flags |= DMA_CONFIGURED;
 120         return 0;
 121 }
 122
 123 static void sh_dmac_enable_dma(struct dma_channel *chan)
 124 {
 125         int irq;
 126         u32 chcr;
 127
 128         chcr = ctrl_inl(CHCR[chan->chan]);
 129         chcr |= CHCR_DE;
 130
 131         if (chan->flags & DMA_TEI_CAPABLE)
 132                 chcr |= CHCR_IE;
 133
 134         ctrl_outl(chcr, CHCR[chan->chan]);
 135
 136         if (chan->flags & DMA_TEI_CAPABLE) {
 137                 irq = get_dmte_irq(chan->chan);
 138                 enable_irq(irq);
 139         }
 140 }
 141
 142 static void sh_dmac_disable_dma(struct dma_channel *chan)
 143 {
 144         int irq;
 145         u32 chcr;
 146
 147         if (chan->flags & DMA_TEI_CAPABLE) {
 148                 irq = get_dmte_irq(chan->chan);
 149                 disable_irq(irq);
 150         }
 151
 152         chcr = ctrl_inl(CHCR[chan->chan]);
 153         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
 154         ctrl_outl(chcr, CHCR[chan->chan]);
 155 }
 156
 157 static int sh_dmac_xfer_dma(struct dma_channel *chan)
 158 {
 159         /*
 160          * If we haven't pre-configured the channel with special flags, use
 161          * the defaults.
 162          */
 163         if (unlikely(!(chan->flags & DMA_CONFIGURED)))
 164                 sh_dmac_configure_channel(chan, 0);
 165
 166         sh_dmac_disable_dma(chan);
 167
 168         /*
 169          * Single-address mode usage note!
 170          *
 171          * It's important that we don't accidentally write any value to SAR/DAR
 172          * (this includes 0) that hasn't been directly specified by the user if
 173          * we're in single-address mode.
 174          *
 175          * In this case, only one address can be defined, anything else will
 176          * result in a DMA address error interrupt (at least on the SH-4),
 177          * which will subsequently halt the transfer.
 178          *
 179          * Channel 2 on the Dreamcast is a special case, as this is used for
 180          * cascading to the PVR2 DMAC. In this case, we still need to write
 181          * SAR and DAR, regardless of value, in order for cascading to work.
 182          */
 183         if (chan->sar || (mach_is_dreamcast() &&
 184                           chan->chan == PVR2_CASCADE_CHAN))
 185                 ctrl_outl(chan->sar, SAR[chan->chan]);
 186         if (chan->dar || (mach_is_dreamcast() &&
 187                           chan->chan == PVR2_CASCADE_CHAN))
 188                 ctrl_outl(chan->dar, DAR[chan->chan]);
 189
 190         ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]);
 191
 192         sh_dmac_enable_dma(chan);
 193
 194         return 0;
 195 }
 196
 197 static int sh_dmac_get_dma_residue(struct dma_channel *chan)
 198 {
 199         if (!(ctrl_inl(CHCR[chan->chan]) & CHCR_DE))
 200                 return 0;
 201
 202         return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
 203 }
 204
 205 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 206     defined(CONFIG_CPU_SUBTYPE_SH7780)
 207 #define dmaor_read_reg()        ctrl_inw(DMAOR)
 208 #define dmaor_write_reg(data)   ctrl_outw(data, DMAOR)
 209 #else
 210 #define dmaor_read_reg()        ctrl_inl(DMAOR)
 211 #define dmaor_write_reg(data)   ctrl_outl(data, DMAOR)
 212 #endif
 213
 214 static inline int dmaor_reset(void)
 215 {
 216         unsigned long dmaor = dmaor_read_reg();
 217
 218         /* Try to clear the error flags first, incase they are set */
 219         dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
 220         dmaor_write_reg(dmaor);
 221
 222         dmaor |= DMAOR_INIT;
 223         dmaor_write_reg(dmaor);
 224
 225         /* See if we got an error again */
 226         if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) {
 227                 printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
 228                 return -EINVAL;
 229         }
 230
 231         return 0;
 232 }
 233
 234 #if defined(CONFIG_CPU_SH4)
 235 static irqreturn_t dma_err(int irq, void *dummy)
 236 {
 237         dmaor_reset();
 238         disable_irq(irq);
 239
 240         return IRQ_HANDLED;
 241 }
 242 #endif
 243
 244 static struct dma_ops sh_dmac_ops = {
 245         .request        = sh_dmac_request_dma,
 246         .free           = sh_dmac_free_dma,
 247         .get_residue    = sh_dmac_get_dma_residue,
 248         .xfer           = sh_dmac_xfer_dma,
 249         .configure      = sh_dmac_configure_channel,
 250 };
 251
 252 static struct dma_info sh_dmac_info = {
 253         .name           = "sh_dmac",
 254         .nr_channels    = CONFIG_NR_ONCHIP_DMA_CHANNELS,
 255         .ops            = &sh_dmac_ops,
 256         .flags          = DMAC_CHANNELS_TEI_CAPABLE,
 257 };
 258
 259 static int __init sh_dmac_init(void)
 260 {
 261         struct dma_info *info = &sh_dmac_info;
 262         int i;
 263
 264 #ifdef CONFIG_CPU_SH4
 265         i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
 266         if (unlikely(i < 0))
 267                 return i;
 268 #endif
 269
 270         /*
 271          * Initialize DMAOR, and clean up any error flags that may have
 272          * been set.
 273          */
 274         i = dmaor_reset();
 275         if (unlikely(i != 0))
 276                 return i;
 277
 278         return register_dmac(info);
 279 }
 280
 281 static void __exit sh_dmac_exit(void)
 282 {
 283 #ifdef CONFIG_CPU_SH4
 284         free_irq(DMAE_IRQ, 0);
 285 #endif
 286         unregister_dmac(&sh_dmac_info);
 287 }
 288
 289 subsys_initcall(sh_dmac_init);
 290 module_exit(sh_dmac_exit);
 291
 292 MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
 293 MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
 294 MODULE_LICENSE("GPL");