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rt2x00: Only initialize the minimum needed fields of PCI TX descriptors.
[linux-2.6/libata-dev.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
blob6c31c5db0ca17a999b21a7943ca046d10ccaef17
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
38
39 /*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
53 {
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65 }
66
67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
69 {
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2500pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91 }
92
93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94 const unsigned int word, u8 *value)
95 {
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2500pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2500pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128 }
129
130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
131 const unsigned int word, const u32 value)
132 {
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149 rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158 }
159
160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161 {
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173 }
174
175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176 {
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188 }
189
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
194 const unsigned int word, u32 *data)
195 {
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197 }
198
199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, u32 data)
201 {
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203 }
204
205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2500pci_read_csr,
209 .write = rt2500pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2500pci_bbp_read,
221 .write = rt2500pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2500pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231 };
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234 #ifdef CONFIG_RT2500PCI_RFKILL
235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236 {
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241 }
242 #else
243 #define rt2500pci_rfkill_poll NULL
244 #endif /* CONFIG_RT2500PCI_RFKILL */
245
246 #ifdef CONFIG_RT2500PCI_LEDS
247 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
249 {
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 u32 reg;
254
255 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
257 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
258 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
259 else if (led->type == LED_TYPE_ACTIVITY)
260 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
261
262 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263 }
264
265 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
266 unsigned long *delay_on,
267 unsigned long *delay_off)
268 {
269 struct rt2x00_led *led =
270 container_of(led_cdev, struct rt2x00_led, led_dev);
271 u32 reg;
272
273 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278 return 0;
279 }
280 #endif /* CONFIG_RT2500PCI_LEDS */
281
282 /*
283 * Configuration handlers.
284 */
285 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
286 const unsigned int filter_flags)
287 {
288 u32 reg;
289
290 /*
291 * Start configuration steps.
292 * Note that the version error will always be dropped
293 * and broadcast frames will always be accepted since
294 * there is no filter for it at this time.
295 */
296 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
297 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
298 !(filter_flags & FIF_FCSFAIL));
299 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
300 !(filter_flags & FIF_PLCPFAIL));
301 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
302 !(filter_flags & FIF_CONTROL));
303 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
304 !(filter_flags & FIF_PROMISC_IN_BSS));
305 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
306 !(filter_flags & FIF_PROMISC_IN_BSS) &&
307 !rt2x00dev->intf_ap_count);
308 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
309 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
310 !(filter_flags & FIF_ALLMULTI));
311 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
312 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
313 }
314
315 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
316 struct rt2x00_intf *intf,
317 struct rt2x00intf_conf *conf,
318 const unsigned int flags)
319 {
320 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
321 unsigned int bcn_preload;
322 u32 reg;
323
324 if (flags & CONFIG_UPDATE_TYPE) {
325 /*
326 * Enable beacon config
327 */
328 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
329 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
330 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
331 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
332 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
333
334 /*
335 * Enable synchronisation.
336 */
337 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
338 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
339 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
340 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
341 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
342 }
343
344 if (flags & CONFIG_UPDATE_MAC)
345 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
346 conf->mac, sizeof(conf->mac));
347
348 if (flags & CONFIG_UPDATE_BSSID)
349 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
350 conf->bssid, sizeof(conf->bssid));
351 }
352
353 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
354 struct rt2x00lib_erp *erp)
355 {
356 int preamble_mask;
357 u32 reg;
358
359 /*
360 * When short preamble is enabled, we should set bit 0x08
361 */
362 preamble_mask = erp->short_preamble << 3;
363
364 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
365 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
366 erp->ack_timeout);
367 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
368 erp->ack_consume_time);
369 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
370
371 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
372 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
373 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
374 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
375 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
376
377 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
378 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
379 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
380 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
381 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
382
383 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
384 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
385 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
386 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
387 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
388
389 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
390 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
391 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
392 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
393 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
394 }
395
396 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
397 const int basic_rate_mask)
398 {
399 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
400 }
401
402 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
403 struct rf_channel *rf, const int txpower)
404 {
405 u8 r70;
406
407 /*
408 * Set TXpower.
409 */
410 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
411
412 /*
413 * Switch on tuning bits.
414 * For RT2523 devices we do not need to update the R1 register.
415 */
416 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
417 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
418 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
419
420 /*
421 * For RT2525 we should first set the channel to half band higher.
422 */
423 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
424 static const u32 vals[] = {
425 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
426 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
427 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
428 0x00080d2e, 0x00080d3a
429 };
430
431 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
432 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
433 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
434 if (rf->rf4)
435 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
436 }
437
438 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
439 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
440 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
441 if (rf->rf4)
442 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
443
444 /*
445 * Channel 14 requires the Japan filter bit to be set.
446 */
447 r70 = 0x46;
448 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
449 rt2500pci_bbp_write(rt2x00dev, 70, r70);
450
451 msleep(1);
452
453 /*
454 * Switch off tuning bits.
455 * For RT2523 devices we do not need to update the R1 register.
456 */
457 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
458 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
459 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
460 }
461
462 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
463 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
464
465 /*
466 * Clear false CRC during channel switch.
467 */
468 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
469 }
470
471 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
472 const int txpower)
473 {
474 u32 rf3;
475
476 rt2x00_rf_read(rt2x00dev, 3, &rf3);
477 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
478 rt2500pci_rf_write(rt2x00dev, 3, rf3);
479 }
480
481 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
482 struct antenna_setup *ant)
483 {
484 u32 reg;
485 u8 r14;
486 u8 r2;
487
488 /*
489 * We should never come here because rt2x00lib is supposed
490 * to catch this and send us the correct antenna explicitely.
491 */
492 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
493 ant->tx == ANTENNA_SW_DIVERSITY);
494
495 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
496 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
497 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
498
499 /*
500 * Configure the TX antenna.
501 */
502 switch (ant->tx) {
503 case ANTENNA_A:
504 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
505 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
506 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
507 break;
508 case ANTENNA_B:
509 default:
510 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
511 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
512 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
513 break;
514 }
515
516 /*
517 * Configure the RX antenna.
518 */
519 switch (ant->rx) {
520 case ANTENNA_A:
521 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
522 break;
523 case ANTENNA_B:
524 default:
525 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
526 break;
527 }
528
529 /*
530 * RT2525E and RT5222 need to flip TX I/Q
531 */
532 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
533 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
534 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
535 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
536 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
537
538 /*
539 * RT2525E does not need RX I/Q Flip.
540 */
541 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
542 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
543 } else {
544 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
545 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
546 }
547
548 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
549 rt2500pci_bbp_write(rt2x00dev, 14, r14);
550 rt2500pci_bbp_write(rt2x00dev, 2, r2);
551 }
552
553 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
554 struct rt2x00lib_conf *libconf)
555 {
556 u32 reg;
557
558 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
559 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
560 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
561
562 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
563 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
564 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
565 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
566
567 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
568 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
569 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
570 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
571
572 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
573 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
574 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
575 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
576
577 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
578 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
579 libconf->conf->beacon_int * 16);
580 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
581 libconf->conf->beacon_int * 16);
582 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
583 }
584
585 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
586 struct rt2x00lib_conf *libconf,
587 const unsigned int flags)
588 {
589 if (flags & CONFIG_UPDATE_PHYMODE)
590 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
591 if (flags & CONFIG_UPDATE_CHANNEL)
592 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
593 libconf->conf->power_level);
594 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
595 rt2500pci_config_txpower(rt2x00dev,
596 libconf->conf->power_level);
597 if (flags & CONFIG_UPDATE_ANTENNA)
598 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
599 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
600 rt2500pci_config_duration(rt2x00dev, libconf);
601 }
602
603 /*
604 * Link tuning
605 */
606 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
607 struct link_qual *qual)
608 {
609 u32 reg;
610
611 /*
612 * Update FCS error count from register.
613 */
614 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
615 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
616
617 /*
618 * Update False CCA count from register.
619 */
620 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
621 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
622 }
623
624 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
625 {
626 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
627 rt2x00dev->link.vgc_level = 0x48;
628 }
629
630 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
631 {
632 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
633 u8 r17;
634
635 /*
636 * To prevent collisions with MAC ASIC on chipsets
637 * up to version C the link tuning should halt after 20
638 * seconds while being associated.
639 */
640 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
641 rt2x00dev->intf_associated &&
642 rt2x00dev->link.count > 20)
643 return;
644
645 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
646
647 /*
648 * Chipset versions C and lower should directly continue
649 * to the dynamic CCA tuning. Chipset version D and higher
650 * should go straight to dynamic CCA tuning when they
651 * are not associated.
652 */
653 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
654 !rt2x00dev->intf_associated)
655 goto dynamic_cca_tune;
656
657 /*
658 * A too low RSSI will cause too much false CCA which will
659 * then corrupt the R17 tuning. To remidy this the tuning should
660 * be stopped (While making sure the R17 value will not exceed limits)
661 */
662 if (rssi < -80 && rt2x00dev->link.count > 20) {
663 if (r17 >= 0x41) {
664 r17 = rt2x00dev->link.vgc_level;
665 rt2500pci_bbp_write(rt2x00dev, 17, r17);
666 }
667 return;
668 }
669
670 /*
671 * Special big-R17 for short distance
672 */
673 if (rssi >= -58) {
674 if (r17 != 0x50)
675 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
676 return;
677 }
678
679 /*
680 * Special mid-R17 for middle distance
681 */
682 if (rssi >= -74) {
683 if (r17 != 0x41)
684 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
685 return;
686 }
687
688 /*
689 * Leave short or middle distance condition, restore r17
690 * to the dynamic tuning range.
691 */
692 if (r17 >= 0x41) {
693 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
694 return;
695 }
696
697 dynamic_cca_tune:
698
699 /*
700 * R17 is inside the dynamic tuning range,
701 * start tuning the link based on the false cca counter.
702 */
703 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
704 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
705 rt2x00dev->link.vgc_level = r17;
706 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
707 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
708 rt2x00dev->link.vgc_level = r17;
709 }
710 }
711
712 /*
713 * Initialization functions.
714 */
715 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
716 struct queue_entry *entry)
717 {
718 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
719 u32 word;
720
721 rt2x00_desc_read(priv_rx->desc, 1, &word);
722 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
723 rt2x00_desc_write(priv_rx->desc, 1, word);
724
725 rt2x00_desc_read(priv_rx->desc, 0, &word);
726 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
727 rt2x00_desc_write(priv_rx->desc, 0, word);
728 }
729
730 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
731 struct queue_entry *entry)
732 {
733 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
734 u32 word;
735
736 rt2x00_desc_read(priv_tx->desc, 0, &word);
737 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
738 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
739 rt2x00_desc_write(priv_tx->desc, 0, word);
740 }
741
742 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
743 {
744 struct queue_entry_priv_pci_rx *priv_rx;
745 struct queue_entry_priv_pci_tx *priv_tx;
746 u32 reg;
747
748 /*
749 * Initialize registers.
750 */
751 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
752 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
753 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
754 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
755 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
756 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
757
758 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
759 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
760 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
761 priv_tx->desc_dma);
762 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
763
764 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
765 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
766 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
767 priv_tx->desc_dma);
768 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
769
770 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
771 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
772 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
773 priv_tx->desc_dma);
774 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
775
776 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
777 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
778 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
779 priv_tx->desc_dma);
780 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
781
782 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
783 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
784 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
785 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
786
787 priv_rx = rt2x00dev->rx->entries[0].priv_data;
788 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
789 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
790 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
791
792 return 0;
793 }
794
795 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
796 {
797 u32 reg;
798
799 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
800 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
801 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
802 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
803
804 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
805 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
806 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
807 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
808 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
809
810 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
811 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
812 rt2x00dev->rx->data_size / 128);
813 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
814
815 /*
816 * Always use CWmin and CWmax set in descriptor.
817 */
818 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
819 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
820 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
821
822 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
823
824 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
825 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
826 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
827 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
828 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
829 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
830 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
831 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
832 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
833 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
834
835 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
836 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
837 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
838 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
839 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
840 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
841
842 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
843 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
844 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
845 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
846 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
847 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
848
849 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
850 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
851 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
852 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
853 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
854 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
855
856 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
857 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
858 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
859 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
860 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
861 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
862 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
863 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
864 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
865 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
866
867 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
868 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
869 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
870 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
871 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
872 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
873 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
874 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
875 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
876
877 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
878
879 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
880 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
881
882 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
883 return -EBUSY;
884
885 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
886 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
887
888 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
889 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
890 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
891
892 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
893 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
894 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
895 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
896 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
897 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
898 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
899 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
900
901 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
902
903 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
904
905 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
906 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
907 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
908 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
909 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
910
911 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
912 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
913 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
914 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
915
916 /*
917 * We must clear the FCS and FIFO error count.
918 * These registers are cleared on read,
919 * so we may pass a useless variable to store the value.
920 */
921 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
922 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
923
924 return 0;
925 }
926
927 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
928 {
929 unsigned int i;
930 u16 eeprom;
931 u8 reg_id;
932 u8 value;
933
934 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
935 rt2500pci_bbp_read(rt2x00dev, 0, &value);
936 if ((value != 0xff) && (value != 0x00))
937 goto continue_csr_init;
938 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
939 udelay(REGISTER_BUSY_DELAY);
940 }
941
942 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
943 return -EACCES;
944
945 continue_csr_init:
946 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
947 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
948 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
949 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
950 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
951 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
952 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
953 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
954 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
955 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
956 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
957 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
958 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
959 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
960 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
961 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
962 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
963 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
964 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
965 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
966 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
967 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
968 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
969 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
970 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
971 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
972 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
973 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
974 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
975 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
976
977 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
978 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
979
980 if (eeprom != 0xffff && eeprom != 0x0000) {
981 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
982 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
983 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
984 }
985 }
986
987 return 0;
988 }
989
990 /*
991 * Device state switch handlers.
992 */
993 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
994 enum dev_state state)
995 {
996 u32 reg;
997
998 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
999 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1000 state == STATE_RADIO_RX_OFF);
1001 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1002 }
1003
1004 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1005 enum dev_state state)
1006 {
1007 int mask = (state == STATE_RADIO_IRQ_OFF);
1008 u32 reg;
1009
1010 /*
1011 * When interrupts are being enabled, the interrupt registers
1012 * should clear the register to assure a clean state.
1013 */
1014 if (state == STATE_RADIO_IRQ_ON) {
1015 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1016 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1017 }
1018
1019 /*
1020 * Only toggle the interrupts bits we are going to use.
1021 * Non-checked interrupt bits are disabled by default.
1022 */
1023 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1024 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1025 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1026 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1027 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1028 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1029 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1030 }
1031
1032 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1033 {
1034 /*
1035 * Initialize all registers.
1036 */
1037 if (rt2500pci_init_queues(rt2x00dev) ||
1038 rt2500pci_init_registers(rt2x00dev) ||
1039 rt2500pci_init_bbp(rt2x00dev)) {
1040 ERROR(rt2x00dev, "Register initialization failed.\n");
1041 return -EIO;
1042 }
1043
1044 /*
1045 * Enable interrupts.
1046 */
1047 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1048
1049 return 0;
1050 }
1051
1052 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1053 {
1054 u32 reg;
1055
1056 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1057
1058 /*
1059 * Disable synchronisation.
1060 */
1061 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1062
1063 /*
1064 * Cancel RX and TX.
1065 */
1066 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1067 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1068 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1069
1070 /*
1071 * Disable interrupts.
1072 */
1073 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1074 }
1075
1076 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1077 enum dev_state state)
1078 {
1079 u32 reg;
1080 unsigned int i;
1081 char put_to_sleep;
1082 char bbp_state;
1083 char rf_state;
1084
1085 put_to_sleep = (state != STATE_AWAKE);
1086
1087 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1088 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1089 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1090 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1091 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1092 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1093
1094 /*
1095 * Device is not guaranteed to be in the requested state yet.
1096 * We must wait until the register indicates that the
1097 * device has entered the correct state.
1098 */
1099 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1100 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1101 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1102 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1103 if (bbp_state == state && rf_state == state)
1104 return 0;
1105 msleep(10);
1106 }
1107
1108 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1109 "current device state: bbp %d and rf %d.\n",
1110 state, bbp_state, rf_state);
1111
1112 return -EBUSY;
1113 }
1114
1115 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1116 enum dev_state state)
1117 {
1118 int retval = 0;
1119
1120 switch (state) {
1121 case STATE_RADIO_ON:
1122 retval = rt2500pci_enable_radio(rt2x00dev);
1123 break;
1124 case STATE_RADIO_OFF:
1125 rt2500pci_disable_radio(rt2x00dev);
1126 break;
1127 case STATE_RADIO_RX_ON:
1128 case STATE_RADIO_RX_ON_LINK:
1129 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1130 break;
1131 case STATE_RADIO_RX_OFF:
1132 case STATE_RADIO_RX_OFF_LINK:
1133 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1134 break;
1135 case STATE_DEEP_SLEEP:
1136 case STATE_SLEEP:
1137 case STATE_STANDBY:
1138 case STATE_AWAKE:
1139 retval = rt2500pci_set_state(rt2x00dev, state);
1140 break;
1141 default:
1142 retval = -ENOTSUPP;
1143 break;
1144 }
1145
1146 return retval;
1147 }
1148
1149 /*
1150 * TX descriptor initialization
1151 */
1152 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1153 struct sk_buff *skb,
1154 struct txentry_desc *txdesc)
1155 {
1156 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1157 struct queue_entry_priv_pci_tx *entry_priv = skbdesc->entry->priv_data;
1158 __le32 *txd = skbdesc->desc;
1159 u32 word;
1160
1161 /*
1162 * Start writing the descriptor words.
1163 */
1164 rt2x00_desc_read(entry_priv->desc, 1, &word);
1165 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
1166 rt2x00_desc_write(entry_priv->desc, 1, word);
1167
1168 rt2x00_desc_read(txd, 2, &word);
1169 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1170 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1171 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1172 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1173 rt2x00_desc_write(txd, 2, word);
1174
1175 rt2x00_desc_read(txd, 3, &word);
1176 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1177 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1178 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1179 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1180 rt2x00_desc_write(txd, 3, word);
1181
1182 rt2x00_desc_read(txd, 10, &word);
1183 rt2x00_set_field32(&word, TXD_W10_RTS,
1184 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1185 rt2x00_desc_write(txd, 10, word);
1186
1187 rt2x00_desc_read(txd, 0, &word);
1188 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1189 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1190 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1191 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1192 rt2x00_set_field32(&word, TXD_W0_ACK,
1193 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1194 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1195 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1196 rt2x00_set_field32(&word, TXD_W0_OFDM,
1197 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1198 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1199 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1200 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1201 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1202 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1203 rt2x00_desc_write(txd, 0, word);
1204 }
1205
1206 /*
1207 * TX data initialization
1208 */
1209 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1210 const enum data_queue_qid queue)
1211 {
1212 u32 reg;
1213
1214 if (queue == QID_BEACON) {
1215 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1216 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1217 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1218 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1219 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1220 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1221 }
1222 return;
1223 }
1224
1225 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1226 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1227 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1228 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1229 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1230 }
1231
1232 /*
1233 * RX control handlers
1234 */
1235 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1236 struct rxdone_entry_desc *rxdesc)
1237 {
1238 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1239 u32 word0;
1240 u32 word2;
1241
1242 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1243 rt2x00_desc_read(priv_rx->desc, 2, &word2);
1244
1245 rxdesc->flags = 0;
1246 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1247 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1248 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1249 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1250
1251 /*
1252 * Obtain the status about this packet.
1253 * When frame was received with an OFDM bitrate,
1254 * the signal is the PLCP value. If it was received with
1255 * a CCK bitrate the signal is the rate in 100kbit/s.
1256 */
1257 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1258 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1259 entry->queue->rt2x00dev->rssi_offset;
1260 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1261
1262 rxdesc->dev_flags = 0;
1263 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1264 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1265 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1266 rxdesc->dev_flags |= RXDONE_MY_BSS;
1267 }
1268
1269 /*
1270 * Interrupt functions.
1271 */
1272 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1273 const enum data_queue_qid queue_idx)
1274 {
1275 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1276 struct queue_entry_priv_pci_tx *priv_tx;
1277 struct queue_entry *entry;
1278 struct txdone_entry_desc txdesc;
1279 u32 word;
1280
1281 while (!rt2x00queue_empty(queue)) {
1282 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1283 priv_tx = entry->priv_data;
1284 rt2x00_desc_read(priv_tx->desc, 0, &word);
1285
1286 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1287 !rt2x00_get_field32(word, TXD_W0_VALID))
1288 break;
1289
1290 /*
1291 * Obtain the status about this packet.
1292 */
1293 txdesc.flags = 0;
1294 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1295 case 0: /* Success */
1296 case 1: /* Success with retry */
1297 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1298 break;
1299 case 2: /* Failure, excessive retries */
1300 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1301 /* Don't break, this is a failed frame! */
1302 default: /* Failure */
1303 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1304 }
1305 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1306
1307 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1308 }
1309 }
1310
1311 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1312 {
1313 struct rt2x00_dev *rt2x00dev = dev_instance;
1314 u32 reg;
1315
1316 /*
1317 * Get the interrupt sources & saved to local variable.
1318 * Write register value back to clear pending interrupts.
1319 */
1320 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1321 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1322
1323 if (!reg)
1324 return IRQ_NONE;
1325
1326 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1327 return IRQ_HANDLED;
1328
1329 /*
1330 * Handle interrupts, walk through all bits
1331 * and run the tasks, the bits are checked in order of
1332 * priority.
1333 */
1334
1335 /*
1336 * 1 - Beacon timer expired interrupt.
1337 */
1338 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1339 rt2x00lib_beacondone(rt2x00dev);
1340
1341 /*
1342 * 2 - Rx ring done interrupt.
1343 */
1344 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1345 rt2x00pci_rxdone(rt2x00dev);
1346
1347 /*
1348 * 3 - Atim ring transmit done interrupt.
1349 */
1350 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1351 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1352
1353 /*
1354 * 4 - Priority ring transmit done interrupt.
1355 */
1356 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1357 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1358
1359 /*
1360 * 5 - Tx ring transmit done interrupt.
1361 */
1362 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1363 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1364
1365 return IRQ_HANDLED;
1366 }
1367
1368 /*
1369 * Device probe functions.
1370 */
1371 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1372 {
1373 struct eeprom_93cx6 eeprom;
1374 u32 reg;
1375 u16 word;
1376 u8 *mac;
1377
1378 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1379
1380 eeprom.data = rt2x00dev;
1381 eeprom.register_read = rt2500pci_eepromregister_read;
1382 eeprom.register_write = rt2500pci_eepromregister_write;
1383 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1384 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1385 eeprom.reg_data_in = 0;
1386 eeprom.reg_data_out = 0;
1387 eeprom.reg_data_clock = 0;
1388 eeprom.reg_chip_select = 0;
1389
1390 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1391 EEPROM_SIZE / sizeof(u16));
1392
1393 /*
1394 * Start validation of the data that has been read.
1395 */
1396 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1397 if (!is_valid_ether_addr(mac)) {
1398 DECLARE_MAC_BUF(macbuf);
1399
1400 random_ether_addr(mac);
1401 EEPROM(rt2x00dev, "MAC: %s\n",
1402 print_mac(macbuf, mac));
1403 }
1404
1405 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1406 if (word == 0xffff) {
1407 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1408 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1409 ANTENNA_SW_DIVERSITY);
1410 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1411 ANTENNA_SW_DIVERSITY);
1412 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1413 LED_MODE_DEFAULT);
1414 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1415 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1416 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1417 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1418 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1419 }
1420
1421 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1422 if (word == 0xffff) {
1423 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1424 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1425 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1426 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1427 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1428 }
1429
1430 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1431 if (word == 0xffff) {
1432 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1433 DEFAULT_RSSI_OFFSET);
1434 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1435 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1436 }
1437
1438 return 0;
1439 }
1440
1441 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1442 {
1443 u32 reg;
1444 u16 value;
1445 u16 eeprom;
1446
1447 /*
1448 * Read EEPROM word for configuration.
1449 */
1450 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1451
1452 /*
1453 * Identify RF chipset.
1454 */
1455 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1456 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1457 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1458
1459 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1460 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1461 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1462 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1463 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1464 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1465 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1466 return -ENODEV;
1467 }
1468
1469 /*
1470 * Identify default antenna configuration.
1471 */
1472 rt2x00dev->default_ant.tx =
1473 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1474 rt2x00dev->default_ant.rx =
1475 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1476
1477 /*
1478 * Store led mode, for correct led behaviour.
1479 */
1480 #ifdef CONFIG_RT2500PCI_LEDS
1481 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1482
1483 rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1484 rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1485 rt2x00dev->led_radio.led_dev.brightness_set =
1486 rt2500pci_brightness_set;
1487 rt2x00dev->led_radio.led_dev.blink_set =
1488 rt2500pci_blink_set;
1489 rt2x00dev->led_radio.flags = LED_INITIALIZED;
1490
1491 if (value == LED_MODE_TXRX_ACTIVITY) {
1492 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1493 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1494 rt2x00dev->led_qual.led_dev.brightness_set =
1495 rt2500pci_brightness_set;
1496 rt2x00dev->led_qual.led_dev.blink_set =
1497 rt2500pci_blink_set;
1498 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1499 }
1500 #endif /* CONFIG_RT2500PCI_LEDS */
1501
1502 /*
1503 * Detect if this device has an hardware controlled radio.
1504 */
1505 #ifdef CONFIG_RT2500PCI_RFKILL
1506 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1507 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1508 #endif /* CONFIG_RT2500PCI_RFKILL */
1509
1510 /*
1511 * Check if the BBP tuning should be enabled.
1512 */
1513 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1514
1515 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1516 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1517
1518 /*
1519 * Read the RSSI <-> dBm offset information.
1520 */
1521 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1522 rt2x00dev->rssi_offset =
1523 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1524
1525 return 0;
1526 }
1527
1528 /*
1529 * RF value list for RF2522
1530 * Supports: 2.4 GHz
1531 */
1532 static const struct rf_channel rf_vals_bg_2522[] = {
1533 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1534 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1535 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1536 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1537 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1538 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1539 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1540 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1541 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1542 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1543 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1544 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1545 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1546 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1547 };
1548
1549 /*
1550 * RF value list for RF2523
1551 * Supports: 2.4 GHz
1552 */
1553 static const struct rf_channel rf_vals_bg_2523[] = {
1554 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1555 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1556 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1557 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1558 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1559 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1560 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1561 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1562 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1563 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1564 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1565 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1566 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1567 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1568 };
1569
1570 /*
1571 * RF value list for RF2524
1572 * Supports: 2.4 GHz
1573 */
1574 static const struct rf_channel rf_vals_bg_2524[] = {
1575 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1576 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1577 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1578 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1579 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1580 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1581 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1582 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1583 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1584 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1585 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1586 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1587 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1588 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1589 };
1590
1591 /*
1592 * RF value list for RF2525
1593 * Supports: 2.4 GHz
1594 */
1595 static const struct rf_channel rf_vals_bg_2525[] = {
1596 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1597 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1598 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1599 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1600 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1601 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1602 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1603 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1604 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1605 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1606 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1607 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1608 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1609 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1610 };
1611
1612 /*
1613 * RF value list for RF2525e
1614 * Supports: 2.4 GHz
1615 */
1616 static const struct rf_channel rf_vals_bg_2525e[] = {
1617 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1618 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1619 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1620 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1621 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1622 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1623 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1624 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1625 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1626 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1627 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1628 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1629 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1630 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1631 };
1632
1633 /*
1634 * RF value list for RF5222
1635 * Supports: 2.4 GHz & 5.2 GHz
1636 */
1637 static const struct rf_channel rf_vals_5222[] = {
1638 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1639 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1640 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1641 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1642 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1643 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1644 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1645 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1646 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1647 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1648 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1649 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1650 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1651 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1652
1653 /* 802.11 UNI / HyperLan 2 */
1654 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1655 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1656 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1657 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1658 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1659 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1660 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1661 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1662
1663 /* 802.11 HyperLan 2 */
1664 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1665 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1666 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1667 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1668 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1669 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1670 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1671 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1672 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1673 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1674
1675 /* 802.11 UNII */
1676 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1677 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1678 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1679 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1680 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1681 };
1682
1683 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1684 {
1685 struct hw_mode_spec *spec = &rt2x00dev->spec;
1686 u8 *txpower;
1687 unsigned int i;
1688
1689 /*
1690 * Initialize all hw fields.
1691 */
1692 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1693 IEEE80211_HW_SIGNAL_DBM;
1694
1695 rt2x00dev->hw->extra_tx_headroom = 0;
1696
1697 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1698 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1699 rt2x00_eeprom_addr(rt2x00dev,
1700 EEPROM_MAC_ADDR_0));
1701
1702 /*
1703 * Convert tx_power array in eeprom.
1704 */
1705 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1706 for (i = 0; i < 14; i++)
1707 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1708
1709 /*
1710 * Initialize hw_mode information.
1711 */
1712 spec->supported_bands = SUPPORT_BAND_2GHZ;
1713 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1714 spec->tx_power_a = NULL;
1715 spec->tx_power_bg = txpower;
1716 spec->tx_power_default = DEFAULT_TXPOWER;
1717
1718 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1719 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1720 spec->channels = rf_vals_bg_2522;
1721 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1722 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1723 spec->channels = rf_vals_bg_2523;
1724 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1725 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1726 spec->channels = rf_vals_bg_2524;
1727 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1728 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1729 spec->channels = rf_vals_bg_2525;
1730 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1731 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1732 spec->channels = rf_vals_bg_2525e;
1733 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1734 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1735 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1736 spec->channels = rf_vals_5222;
1737 }
1738 }
1739
1740 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1741 {
1742 int retval;
1743
1744 /*
1745 * Allocate eeprom data.
1746 */
1747 retval = rt2500pci_validate_eeprom(rt2x00dev);
1748 if (retval)
1749 return retval;
1750
1751 retval = rt2500pci_init_eeprom(rt2x00dev);
1752 if (retval)
1753 return retval;
1754
1755 /*
1756 * Initialize hw specifications.
1757 */
1758 rt2500pci_probe_hw_mode(rt2x00dev);
1759
1760 /*
1761 * This device requires the atim queue
1762 */
1763 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1764
1765 /*
1766 * Set the rssi offset.
1767 */
1768 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1769
1770 return 0;
1771 }
1772
1773 /*
1774 * IEEE80211 stack callback functions.
1775 */
1776 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1777 u32 short_retry, u32 long_retry)
1778 {
1779 struct rt2x00_dev *rt2x00dev = hw->priv;
1780 u32 reg;
1781
1782 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1783 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1784 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1785 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1786
1787 return 0;
1788 }
1789
1790 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1791 {
1792 struct rt2x00_dev *rt2x00dev = hw->priv;
1793 u64 tsf;
1794 u32 reg;
1795
1796 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1797 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1798 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1799 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1800
1801 return tsf;
1802 }
1803
1804 static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1805 struct ieee80211_tx_control *control)
1806 {
1807 struct rt2x00_dev *rt2x00dev = hw->priv;
1808 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1809 struct queue_entry_priv_pci_tx *priv_tx;
1810 struct skb_frame_desc *skbdesc;
1811 u32 reg;
1812
1813 if (unlikely(!intf->beacon))
1814 return -ENOBUFS;
1815
1816 priv_tx = intf->beacon->priv_data;
1817
1818 /*
1819 * Fill in skb descriptor
1820 */
1821 skbdesc = get_skb_frame_desc(skb);
1822 memset(skbdesc, 0, sizeof(*skbdesc));
1823 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1824 skbdesc->data = skb->data;
1825 skbdesc->data_len = skb->len;
1826 skbdesc->desc = priv_tx->desc;
1827 skbdesc->desc_len = intf->beacon->queue->desc_size;
1828 skbdesc->entry = intf->beacon;
1829
1830 /*
1831 * Disable beaconing while we are reloading the beacon data,
1832 * otherwise we might be sending out invalid data.
1833 */
1834 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1835 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1836 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1837 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1838 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1839
1840 /*
1841 * Enable beacon generation.
1842 * Write entire beacon with descriptor to register,
1843 * and kick the beacon generator.
1844 */
1845 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1846 memcpy(priv_tx->data, skb->data, skb->len);
1847 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
1848
1849 return 0;
1850 }
1851
1852 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1853 {
1854 struct rt2x00_dev *rt2x00dev = hw->priv;
1855 u32 reg;
1856
1857 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1858 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1859 }
1860
1861 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1862 .tx = rt2x00mac_tx,
1863 .start = rt2x00mac_start,
1864 .stop = rt2x00mac_stop,
1865 .add_interface = rt2x00mac_add_interface,
1866 .remove_interface = rt2x00mac_remove_interface,
1867 .config = rt2x00mac_config,
1868 .config_interface = rt2x00mac_config_interface,
1869 .configure_filter = rt2x00mac_configure_filter,
1870 .get_stats = rt2x00mac_get_stats,
1871 .set_retry_limit = rt2500pci_set_retry_limit,
1872 .bss_info_changed = rt2x00mac_bss_info_changed,
1873 .conf_tx = rt2x00mac_conf_tx,
1874 .get_tx_stats = rt2x00mac_get_tx_stats,
1875 .get_tsf = rt2500pci_get_tsf,
1876 .beacon_update = rt2500pci_beacon_update,
1877 .tx_last_beacon = rt2500pci_tx_last_beacon,
1878 };
1879
1880 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1881 .irq_handler = rt2500pci_interrupt,
1882 .probe_hw = rt2500pci_probe_hw,
1883 .initialize = rt2x00pci_initialize,
1884 .uninitialize = rt2x00pci_uninitialize,
1885 .init_rxentry = rt2500pci_init_rxentry,
1886 .init_txentry = rt2500pci_init_txentry,
1887 .set_device_state = rt2500pci_set_device_state,
1888 .rfkill_poll = rt2500pci_rfkill_poll,
1889 .link_stats = rt2500pci_link_stats,
1890 .reset_tuner = rt2500pci_reset_tuner,
1891 .link_tuner = rt2500pci_link_tuner,
1892 .write_tx_desc = rt2500pci_write_tx_desc,
1893 .write_tx_data = rt2x00pci_write_tx_data,
1894 .kick_tx_queue = rt2500pci_kick_tx_queue,
1895 .fill_rxdone = rt2500pci_fill_rxdone,
1896 .config_filter = rt2500pci_config_filter,
1897 .config_intf = rt2500pci_config_intf,
1898 .config_erp = rt2500pci_config_erp,
1899 .config = rt2500pci_config,
1900 };
1901
1902 static const struct data_queue_desc rt2500pci_queue_rx = {
1903 .entry_num = RX_ENTRIES,
1904 .data_size = DATA_FRAME_SIZE,
1905 .desc_size = RXD_DESC_SIZE,
1906 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1907 };
1908
1909 static const struct data_queue_desc rt2500pci_queue_tx = {
1910 .entry_num = TX_ENTRIES,
1911 .data_size = DATA_FRAME_SIZE,
1912 .desc_size = TXD_DESC_SIZE,
1913 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1914 };
1915
1916 static const struct data_queue_desc rt2500pci_queue_bcn = {
1917 .entry_num = BEACON_ENTRIES,
1918 .data_size = MGMT_FRAME_SIZE,
1919 .desc_size = TXD_DESC_SIZE,
1920 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1921 };
1922
1923 static const struct data_queue_desc rt2500pci_queue_atim = {
1924 .entry_num = ATIM_ENTRIES,
1925 .data_size = DATA_FRAME_SIZE,
1926 .desc_size = TXD_DESC_SIZE,
1927 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1928 };
1929
1930 static const struct rt2x00_ops rt2500pci_ops = {
1931 .name = KBUILD_MODNAME,
1932 .max_sta_intf = 1,
1933 .max_ap_intf = 1,
1934 .eeprom_size = EEPROM_SIZE,
1935 .rf_size = RF_SIZE,
1936 .tx_queues = NUM_TX_QUEUES,
1937 .rx = &rt2500pci_queue_rx,
1938 .tx = &rt2500pci_queue_tx,
1939 .bcn = &rt2500pci_queue_bcn,
1940 .atim = &rt2500pci_queue_atim,
1941 .lib = &rt2500pci_rt2x00_ops,
1942 .hw = &rt2500pci_mac80211_ops,
1943 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1944 .debugfs = &rt2500pci_rt2x00debug,
1945 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1946 };
1947
1948 /*
1949 * RT2500pci module information.
1950 */
1951 static struct pci_device_id rt2500pci_device_table[] = {
1952 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1953 { 0, }
1954 };
1955
1956 MODULE_AUTHOR(DRV_PROJECT);
1957 MODULE_VERSION(DRV_VERSION);
1958 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1959 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1960 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1961 MODULE_LICENSE("GPL");
1962
1963 static struct pci_driver rt2500pci_driver = {
1964 .name = KBUILD_MODNAME,
1965 .id_table = rt2500pci_device_table,
1966 .probe = rt2x00pci_probe,
1967 .remove = __devexit_p(rt2x00pci_remove),
1968 .suspend = rt2x00pci_suspend,
1969 .resume = rt2x00pci_resume,
1970 };
1971
1972 static int __init rt2500pci_init(void)
1973 {
1974 return pci_register_driver(&rt2500pci_driver);
1975 }
1976
1977 static void __exit rt2500pci_exit(void)
1978 {
1979 pci_unregister_driver(&rt2500pci_driver);
1980 }
1981
1982 module_init(rt2500pci_init);
1983 module_exit(rt2500pci_exit);
Linux 2.6 libata-dev (mirror)