arch/arm/mach-s5p64x0/irq-eint.c

   1 /* arch/arm/mach-s5p64x0/irq-eint.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd
   4  *              http://www.samsung.com/
   5  *
   6  * Based on linux/arch/arm/mach-s3c64xx/irq-eint.c
   7  *
   8  * S5P64X0 - Interrupt handling for External Interrupts.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/gpio.h>
  17 #include <linux/irq.h>
  18 #include <linux/io.h>
  19
  20 #include <plat/regs-irqtype.h>
  21 #include <plat/gpio-cfg.h>
  22
  23 #include <mach/regs-gpio.h>
  24 #include <mach/regs-clock.h>
  25
  26 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
  27
  28 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
  29 {
  30         int offs = eint_offset(data->irq);
  31         int shift;
  32         u32 ctrl, mask;
  33         u32 newvalue = 0;
  34
  35         if (offs > 15)
  36                 return -EINVAL;
  37
  38         switch (type) {
  39         case IRQ_TYPE_NONE:
  40                 printk(KERN_WARNING "No edge setting!\n");
  41                 break;
  42         case IRQ_TYPE_EDGE_RISING:
  43                 newvalue = S3C2410_EXTINT_RISEEDGE;
  44                 break;
  45         case IRQ_TYPE_EDGE_FALLING:
  46                 newvalue = S3C2410_EXTINT_FALLEDGE;
  47                 break;
  48         case IRQ_TYPE_EDGE_BOTH:
  49                 newvalue = S3C2410_EXTINT_BOTHEDGE;
  50                 break;
  51         case IRQ_TYPE_LEVEL_LOW:
  52                 newvalue = S3C2410_EXTINT_LOWLEV;
  53                 break;
  54         case IRQ_TYPE_LEVEL_HIGH:
  55                 newvalue = S3C2410_EXTINT_HILEV;
  56                 break;
  57         default:
  58                 printk(KERN_ERR "No such irq type %d", type);
  59                 return -EINVAL;
  60         }
  61
  62         shift = (offs / 2) * 4;
  63         mask = 0x7 << shift;
  64
  65         ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
  66         ctrl |= newvalue << shift;
  67         __raw_writel(ctrl, S5P64X0_EINT0CON0);
  68
  69         /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
  70         if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000))
  71                 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
  72         else
  73                 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
  74
  75         return 0;
  76 }
  77
  78 /*
  79  * s5p64x0_irq_demux_eint
  80  *
  81  * This function demuxes the IRQ from the group0 external interrupts,
  82  * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
  83  * the specific handlers s5p64x0_irq_demux_eintX_Y.
  84  */
  85 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
  86 {
  87         u32 status = __raw_readl(S5P64X0_EINT0PEND);
  88         u32 mask = __raw_readl(S5P64X0_EINT0MASK);
  89         unsigned int irq;
  90
  91         status &= ~mask;
  92         status >>= start;
  93         status &= (1 << (end - start + 1)) - 1;
  94
  95         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
  96                 if (status & 1)
  97                         generic_handle_irq(irq);
  98                 status >>= 1;
  99         }
 100 }
 101
 102 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 103 {
 104         s5p64x0_irq_demux_eint(0, 3);
 105 }
 106
 107 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 108 {
 109         s5p64x0_irq_demux_eint(4, 11);
 110 }
 111
 112 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
 113                                         struct irq_desc *desc)
 114 {
 115         s5p64x0_irq_demux_eint(12, 15);
 116 }
 117
 118 static int s5p64x0_alloc_gc(void)
 119 {
 120         struct irq_chip_generic *gc;
 121         struct irq_chip_type *ct;
 122
 123         gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
 124                                     S5P_VA_GPIO, handle_level_irq);
 125         if (!gc) {
 126                 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
 127                         "external interrupts failed\n", __func__);
 128                 return -EINVAL;
 129         }
 130
 131         ct = gc->chip_types;
 132         ct->chip.irq_ack = irq_gc_ack_set_bit;
 133         ct->chip.irq_mask = irq_gc_mask_set_bit;
 134         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 135         ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
 136         ct->regs.ack = EINT0PEND_OFFSET;
 137         ct->regs.mask = EINT0MASK_OFFSET;
 138         irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
 139                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 140         return 0;
 141 }
 142
 143 static int __init s5p64x0_init_irq_eint(void)
 144 {
 145         int ret = s5p64x0_alloc_gc();
 146         irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
 147         irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
 148         irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
 149
 150         return ret;
 151 }
 152 arch_initcall(s5p64x0_init_irq_eint);