2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
32 #include "nouveau_drm.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_dma.h"
35 #include "nouveau_mm.h"
36 #include "nouveau_vm.h"
38 #include <linux/log2.h>
39 #include <linux/slab.h>
42 nouveau_bo_del_ttm(struct ttm_buffer_object
*bo
)
44 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
45 struct drm_device
*dev
= dev_priv
->dev
;
46 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
48 if (unlikely(nvbo
->gem
))
49 DRM_ERROR("bo %p still attached to GEM object\n", bo
);
51 nv10_mem_put_tile_region(dev
, nvbo
->tile
, NULL
);
52 nouveau_vm_put(&nvbo
->vma
);
57 nouveau_bo_fixup_align(struct drm_device
*dev
,
58 uint32_t tile_mode
, uint32_t tile_flags
,
59 int *align
, int *size
)
61 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
63 if (dev_priv
->card_type
< NV_50
) {
65 if (dev_priv
->chipset
>= 0x40) {
67 *size
= roundup(*size
, 64 * tile_mode
);
69 } else if (dev_priv
->chipset
>= 0x30) {
71 *size
= roundup(*size
, 64 * tile_mode
);
73 } else if (dev_priv
->chipset
>= 0x20) {
75 *size
= roundup(*size
, 64 * tile_mode
);
77 } else if (dev_priv
->chipset
>= 0x10) {
79 *size
= roundup(*size
, 32 * tile_mode
);
84 /* ALIGN works only on powers of two. */
85 *size
= roundup(*size
, PAGE_SIZE
);
86 if (dev_priv
->card_type
== NV_50
) {
87 *size
= roundup(*size
, 65536);
88 *align
= max(65536, *align
);
93 nouveau_bo_new(struct drm_device
*dev
, struct nouveau_channel
*chan
,
94 int size
, int align
, uint32_t flags
, uint32_t tile_mode
,
95 uint32_t tile_flags
, bool no_vm
, bool mappable
,
96 struct nouveau_bo
**pnvbo
)
98 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
99 struct nouveau_bo
*nvbo
;
102 nvbo
= kzalloc(sizeof(struct nouveau_bo
), GFP_KERNEL
);
105 INIT_LIST_HEAD(&nvbo
->head
);
106 INIT_LIST_HEAD(&nvbo
->entry
);
107 nvbo
->mappable
= mappable
;
109 nvbo
->tile_mode
= tile_mode
;
110 nvbo
->tile_flags
= tile_flags
;
111 nvbo
->bo
.bdev
= &dev_priv
->ttm
.bdev
;
113 nouveau_bo_fixup_align(dev
, tile_mode
, nouveau_bo_tile_layout(nvbo
),
115 align
>>= PAGE_SHIFT
;
117 if (!nvbo
->no_vm
&& dev_priv
->chan_vm
) {
118 ret
= nouveau_vm_get(dev_priv
->chan_vm
, size
, 16,
119 NV_MEM_ACCESS_RW
, &nvbo
->vma
);
126 nouveau_bo_placement_set(nvbo
, flags
, 0);
128 nvbo
->channel
= chan
;
129 ret
= ttm_bo_init(&dev_priv
->ttm
.bdev
, &nvbo
->bo
, size
,
130 ttm_bo_type_device
, &nvbo
->placement
, align
, 0,
131 false, NULL
, size
, nouveau_bo_del_ttm
);
133 /* ttm will call nouveau_bo_del_ttm if it fails.. */
136 nvbo
->channel
= NULL
;
138 if (nvbo
->vma
.node
) {
139 if (nvbo
->bo
.mem
.mem_type
== TTM_PL_VRAM
)
140 nvbo
->bo
.offset
= nvbo
->vma
.offset
;
148 set_placement_list(uint32_t *pl
, unsigned *n
, uint32_t type
, uint32_t flags
)
152 if (type
& TTM_PL_FLAG_VRAM
)
153 pl
[(*n
)++] = TTM_PL_FLAG_VRAM
| flags
;
154 if (type
& TTM_PL_FLAG_TT
)
155 pl
[(*n
)++] = TTM_PL_FLAG_TT
| flags
;
156 if (type
& TTM_PL_FLAG_SYSTEM
)
157 pl
[(*n
)++] = TTM_PL_FLAG_SYSTEM
| flags
;
161 set_placement_range(struct nouveau_bo
*nvbo
, uint32_t type
)
163 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
165 if (dev_priv
->card_type
== NV_10
&&
166 nvbo
->tile_mode
&& (type
& TTM_PL_FLAG_VRAM
)) {
168 * Make sure that the color and depth buffers are handled
169 * by independent memory controller units. Up to a 9x
170 * speed up when alpha-blending and depth-test are enabled
173 int vram_pages
= dev_priv
->vram_size
>> PAGE_SHIFT
;
175 if (nvbo
->tile_flags
& NOUVEAU_GEM_TILE_ZETA
) {
176 nvbo
->placement
.fpfn
= vram_pages
/ 2;
177 nvbo
->placement
.lpfn
= ~0;
179 nvbo
->placement
.fpfn
= 0;
180 nvbo
->placement
.lpfn
= vram_pages
/ 2;
186 nouveau_bo_placement_set(struct nouveau_bo
*nvbo
, uint32_t type
, uint32_t busy
)
188 struct ttm_placement
*pl
= &nvbo
->placement
;
189 uint32_t flags
= TTM_PL_MASK_CACHING
|
190 (nvbo
->pin_refcnt
? TTM_PL_FLAG_NO_EVICT
: 0);
192 pl
->placement
= nvbo
->placements
;
193 set_placement_list(nvbo
->placements
, &pl
->num_placement
,
196 pl
->busy_placement
= nvbo
->busy_placements
;
197 set_placement_list(nvbo
->busy_placements
, &pl
->num_busy_placement
,
200 set_placement_range(nvbo
, type
);
204 nouveau_bo_pin(struct nouveau_bo
*nvbo
, uint32_t memtype
)
206 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
207 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
210 if (nvbo
->pin_refcnt
&& !(memtype
& (1 << bo
->mem
.mem_type
))) {
211 NV_ERROR(nouveau_bdev(bo
->bdev
)->dev
,
212 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo
,
213 1 << bo
->mem
.mem_type
, memtype
);
217 if (nvbo
->pin_refcnt
++)
220 ret
= ttm_bo_reserve(bo
, false, false, false, 0);
224 nouveau_bo_placement_set(nvbo
, memtype
, 0);
226 ret
= nouveau_bo_validate(nvbo
, false, false, false);
228 switch (bo
->mem
.mem_type
) {
230 dev_priv
->fb_aper_free
-= bo
->mem
.size
;
233 dev_priv
->gart_info
.aper_free
-= bo
->mem
.size
;
239 ttm_bo_unreserve(bo
);
247 nouveau_bo_unpin(struct nouveau_bo
*nvbo
)
249 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
250 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
253 if (--nvbo
->pin_refcnt
)
256 ret
= ttm_bo_reserve(bo
, false, false, false, 0);
260 nouveau_bo_placement_set(nvbo
, bo
->mem
.placement
, 0);
262 ret
= nouveau_bo_validate(nvbo
, false, false, false);
264 switch (bo
->mem
.mem_type
) {
266 dev_priv
->fb_aper_free
+= bo
->mem
.size
;
269 dev_priv
->gart_info
.aper_free
+= bo
->mem
.size
;
276 ttm_bo_unreserve(bo
);
281 nouveau_bo_map(struct nouveau_bo
*nvbo
)
285 ret
= ttm_bo_reserve(&nvbo
->bo
, false, false, false, 0);
289 ret
= ttm_bo_kmap(&nvbo
->bo
, 0, nvbo
->bo
.mem
.num_pages
, &nvbo
->kmap
);
290 ttm_bo_unreserve(&nvbo
->bo
);
295 nouveau_bo_unmap(struct nouveau_bo
*nvbo
)
298 ttm_bo_kunmap(&nvbo
->kmap
);
302 nouveau_bo_validate(struct nouveau_bo
*nvbo
, bool interruptible
,
303 bool no_wait_reserve
, bool no_wait_gpu
)
307 ret
= ttm_bo_validate(&nvbo
->bo
, &nvbo
->placement
, interruptible
,
308 no_wait_reserve
, no_wait_gpu
);
312 if (nvbo
->vma
.node
) {
313 if (nvbo
->bo
.mem
.mem_type
== TTM_PL_VRAM
)
314 nvbo
->bo
.offset
= nvbo
->vma
.offset
;
321 nouveau_bo_rd16(struct nouveau_bo
*nvbo
, unsigned index
)
324 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
327 return ioread16_native((void __force __iomem
*)mem
);
333 nouveau_bo_wr16(struct nouveau_bo
*nvbo
, unsigned index
, u16 val
)
336 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
339 iowrite16_native(val
, (void __force __iomem
*)mem
);
345 nouveau_bo_rd32(struct nouveau_bo
*nvbo
, unsigned index
)
348 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
351 return ioread32_native((void __force __iomem
*)mem
);
357 nouveau_bo_wr32(struct nouveau_bo
*nvbo
, unsigned index
, u32 val
)
360 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
363 iowrite32_native(val
, (void __force __iomem
*)mem
);
368 static struct ttm_backend
*
369 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device
*bdev
)
371 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
372 struct drm_device
*dev
= dev_priv
->dev
;
374 switch (dev_priv
->gart_info
.type
) {
376 case NOUVEAU_GART_AGP
:
377 return ttm_agp_backend_init(bdev
, dev
->agp
->bridge
);
379 case NOUVEAU_GART_SGDMA
:
380 return nouveau_sgdma_init_ttm(dev
);
382 NV_ERROR(dev
, "Unknown GART type %d\n",
383 dev_priv
->gart_info
.type
);
391 nouveau_bo_invalidate_caches(struct ttm_bo_device
*bdev
, uint32_t flags
)
393 /* We'll do this from user space. */
398 nouveau_bo_init_mem_type(struct ttm_bo_device
*bdev
, uint32_t type
,
399 struct ttm_mem_type_manager
*man
)
401 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
402 struct drm_device
*dev
= dev_priv
->dev
;
406 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
407 man
->available_caching
= TTM_PL_MASK_CACHING
;
408 man
->default_caching
= TTM_PL_FLAG_CACHED
;
411 if (dev_priv
->card_type
== NV_50
) {
412 man
->func
= &nouveau_vram_manager
;
413 man
->io_reserve_fastpath
= false;
414 man
->use_io_reserve_lru
= true;
416 man
->func
= &ttm_bo_manager_func
;
418 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
|
419 TTM_MEMTYPE_FLAG_MAPPABLE
;
420 man
->available_caching
= TTM_PL_FLAG_UNCACHED
|
422 man
->default_caching
= TTM_PL_FLAG_WC
;
426 man
->func
= &ttm_bo_manager_func
;
427 switch (dev_priv
->gart_info
.type
) {
428 case NOUVEAU_GART_AGP
:
429 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
430 man
->available_caching
= TTM_PL_FLAG_UNCACHED
|
432 man
->default_caching
= TTM_PL_FLAG_WC
;
434 case NOUVEAU_GART_SGDMA
:
435 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
|
436 TTM_MEMTYPE_FLAG_CMA
;
437 man
->available_caching
= TTM_PL_MASK_CACHING
;
438 man
->default_caching
= TTM_PL_FLAG_CACHED
;
441 NV_ERROR(dev
, "Unknown GART type: %d\n",
442 dev_priv
->gart_info
.type
);
445 man
->gpu_offset
= dev_priv
->vm_gart_base
;
448 NV_ERROR(dev
, "Unsupported memory type %u\n", (unsigned)type
);
455 nouveau_bo_evict_flags(struct ttm_buffer_object
*bo
, struct ttm_placement
*pl
)
457 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
459 switch (bo
->mem
.mem_type
) {
461 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_TT
,
465 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_SYSTEM
, 0);
469 *pl
= nvbo
->placement
;
473 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
474 * TTM_PL_{VRAM,TT} directly.
478 nouveau_bo_move_accel_cleanup(struct nouveau_channel
*chan
,
479 struct nouveau_bo
*nvbo
, bool evict
,
480 bool no_wait_reserve
, bool no_wait_gpu
,
481 struct ttm_mem_reg
*new_mem
)
483 struct nouveau_fence
*fence
= NULL
;
486 ret
= nouveau_fence_new(chan
, &fence
, true);
490 ret
= ttm_bo_move_accel_cleanup(&nvbo
->bo
, fence
, NULL
, evict
,
491 no_wait_reserve
, no_wait_gpu
, new_mem
);
492 nouveau_fence_unref(&fence
);
496 static inline uint32_t
497 nouveau_bo_mem_ctxdma(struct ttm_buffer_object
*bo
,
498 struct nouveau_channel
*chan
, struct ttm_mem_reg
*mem
)
500 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
503 if (mem
->mem_type
== TTM_PL_TT
)
508 if (mem
->mem_type
== TTM_PL_TT
)
509 return chan
->gart_handle
;
510 return chan
->vram_handle
;
514 nv50_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
515 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
517 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
518 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
519 u64 length
= (new_mem
->num_pages
<< PAGE_SHIFT
);
520 u64 src_offset
, dst_offset
;
523 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
524 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
526 if (old_mem
->mem_type
== TTM_PL_VRAM
)
527 src_offset
= nvbo
->vma
.offset
;
529 src_offset
+= dev_priv
->vm_gart_base
;
531 if (new_mem
->mem_type
== TTM_PL_VRAM
)
532 dst_offset
= nvbo
->vma
.offset
;
534 dst_offset
+= dev_priv
->vm_gart_base
;
537 ret
= RING_SPACE(chan
, 3);
541 BEGIN_RING(chan
, NvSubM2MF
, 0x0184, 2);
542 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, old_mem
));
543 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, new_mem
));
546 u32 amount
, stride
, height
;
548 amount
= min(length
, (u64
)(4 * 1024 * 1024));
550 height
= amount
/ stride
;
552 if (new_mem
->mem_type
== TTM_PL_VRAM
&&
553 nouveau_bo_tile_layout(nvbo
)) {
554 ret
= RING_SPACE(chan
, 8);
558 BEGIN_RING(chan
, NvSubM2MF
, 0x0200, 7);
561 OUT_RING (chan
, stride
);
562 OUT_RING (chan
, height
);
567 ret
= RING_SPACE(chan
, 2);
571 BEGIN_RING(chan
, NvSubM2MF
, 0x0200, 1);
574 if (old_mem
->mem_type
== TTM_PL_VRAM
&&
575 nouveau_bo_tile_layout(nvbo
)) {
576 ret
= RING_SPACE(chan
, 8);
580 BEGIN_RING(chan
, NvSubM2MF
, 0x021c, 7);
583 OUT_RING (chan
, stride
);
584 OUT_RING (chan
, height
);
589 ret
= RING_SPACE(chan
, 2);
593 BEGIN_RING(chan
, NvSubM2MF
, 0x021c, 1);
597 ret
= RING_SPACE(chan
, 14);
601 BEGIN_RING(chan
, NvSubM2MF
, 0x0238, 2);
602 OUT_RING (chan
, upper_32_bits(src_offset
));
603 OUT_RING (chan
, upper_32_bits(dst_offset
));
604 BEGIN_RING(chan
, NvSubM2MF
, 0x030c, 8);
605 OUT_RING (chan
, lower_32_bits(src_offset
));
606 OUT_RING (chan
, lower_32_bits(dst_offset
));
607 OUT_RING (chan
, stride
);
608 OUT_RING (chan
, stride
);
609 OUT_RING (chan
, stride
);
610 OUT_RING (chan
, height
);
611 OUT_RING (chan
, 0x00000101);
612 OUT_RING (chan
, 0x00000000);
613 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
617 src_offset
+= amount
;
618 dst_offset
+= amount
;
625 nv04_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
626 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
628 u32 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
629 u32 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
630 u32 page_count
= new_mem
->num_pages
;
633 ret
= RING_SPACE(chan
, 3);
637 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE
, 2);
638 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, old_mem
));
639 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, new_mem
));
641 page_count
= new_mem
->num_pages
;
643 int line_count
= (page_count
> 2047) ? 2047 : page_count
;
645 ret
= RING_SPACE(chan
, 11);
649 BEGIN_RING(chan
, NvSubM2MF
,
650 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN
, 8);
651 OUT_RING (chan
, src_offset
);
652 OUT_RING (chan
, dst_offset
);
653 OUT_RING (chan
, PAGE_SIZE
); /* src_pitch */
654 OUT_RING (chan
, PAGE_SIZE
); /* dst_pitch */
655 OUT_RING (chan
, PAGE_SIZE
); /* line_length */
656 OUT_RING (chan
, line_count
);
657 OUT_RING (chan
, 0x00000101);
658 OUT_RING (chan
, 0x00000000);
659 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
662 page_count
-= line_count
;
663 src_offset
+= (PAGE_SIZE
* line_count
);
664 dst_offset
+= (PAGE_SIZE
* line_count
);
671 nouveau_bo_move_m2mf(struct ttm_buffer_object
*bo
, int evict
, bool intr
,
672 bool no_wait_reserve
, bool no_wait_gpu
,
673 struct ttm_mem_reg
*new_mem
)
675 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
676 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
677 struct nouveau_channel
*chan
;
680 chan
= nvbo
->channel
;
681 if (!chan
|| nvbo
->no_vm
) {
682 chan
= dev_priv
->channel
;
683 mutex_lock_nested(&chan
->mutex
, NOUVEAU_KCHANNEL_MUTEX
);
686 if (dev_priv
->card_type
< NV_50
)
687 ret
= nv04_bo_move_m2mf(chan
, bo
, &bo
->mem
, new_mem
);
689 ret
= nv50_bo_move_m2mf(chan
, bo
, &bo
->mem
, new_mem
);
691 ret
= nouveau_bo_move_accel_cleanup(chan
, nvbo
, evict
,
693 no_wait_gpu
, new_mem
);
696 if (chan
== dev_priv
->channel
)
697 mutex_unlock(&chan
->mutex
);
702 nouveau_bo_move_flipd(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
703 bool no_wait_reserve
, bool no_wait_gpu
,
704 struct ttm_mem_reg
*new_mem
)
706 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
707 struct ttm_placement placement
;
708 struct ttm_mem_reg tmp_mem
;
711 placement
.fpfn
= placement
.lpfn
= 0;
712 placement
.num_placement
= placement
.num_busy_placement
= 1;
713 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
716 tmp_mem
.mm_node
= NULL
;
717 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_reserve
, no_wait_gpu
);
721 ret
= ttm_tt_bind(bo
->ttm
, &tmp_mem
);
725 ret
= nouveau_bo_move_m2mf(bo
, true, intr
, no_wait_reserve
, no_wait_gpu
, &tmp_mem
);
729 ret
= ttm_bo_move_ttm(bo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
731 ttm_bo_mem_put(bo
, &tmp_mem
);
736 nouveau_bo_move_flips(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
737 bool no_wait_reserve
, bool no_wait_gpu
,
738 struct ttm_mem_reg
*new_mem
)
740 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
741 struct ttm_placement placement
;
742 struct ttm_mem_reg tmp_mem
;
745 placement
.fpfn
= placement
.lpfn
= 0;
746 placement
.num_placement
= placement
.num_busy_placement
= 1;
747 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
750 tmp_mem
.mm_node
= NULL
;
751 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_reserve
, no_wait_gpu
);
755 ret
= ttm_bo_move_ttm(bo
, evict
, no_wait_reserve
, no_wait_gpu
, &tmp_mem
);
759 ret
= nouveau_bo_move_m2mf(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
764 ttm_bo_mem_put(bo
, &tmp_mem
);
769 nouveau_bo_vm_bind(struct ttm_buffer_object
*bo
, struct ttm_mem_reg
*new_mem
,
770 struct nouveau_tile_reg
**new_tile
)
772 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
773 struct drm_device
*dev
= dev_priv
->dev
;
774 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
777 if (nvbo
->no_vm
|| new_mem
->mem_type
!= TTM_PL_VRAM
) {
783 offset
= new_mem
->start
<< PAGE_SHIFT
;
785 if (dev_priv
->chan_vm
) {
786 nouveau_vm_map(&nvbo
->vma
, new_mem
->mm_node
);
787 } else if (dev_priv
->card_type
>= NV_10
) {
788 *new_tile
= nv10_mem_set_tiling(dev
, offset
, new_mem
->size
,
797 nouveau_bo_vm_cleanup(struct ttm_buffer_object
*bo
,
798 struct nouveau_tile_reg
*new_tile
,
799 struct nouveau_tile_reg
**old_tile
)
801 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
802 struct drm_device
*dev
= dev_priv
->dev
;
804 if (dev_priv
->card_type
>= NV_10
&&
805 dev_priv
->card_type
< NV_50
) {
806 nv10_mem_put_tile_region(dev
, *old_tile
, bo
->sync_obj
);
807 *old_tile
= new_tile
;
812 nouveau_bo_move(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
813 bool no_wait_reserve
, bool no_wait_gpu
,
814 struct ttm_mem_reg
*new_mem
)
816 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
817 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
818 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
819 struct nouveau_tile_reg
*new_tile
= NULL
;
822 ret
= nouveau_bo_vm_bind(bo
, new_mem
, &new_tile
);
827 if (old_mem
->mem_type
== TTM_PL_SYSTEM
&& !bo
->ttm
) {
828 BUG_ON(bo
->mem
.mm_node
!= NULL
);
830 new_mem
->mm_node
= NULL
;
834 /* Software copy if the card isn't up and running yet. */
835 if (!dev_priv
->channel
) {
836 ret
= ttm_bo_move_memcpy(bo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
840 /* Hardware assisted copy. */
841 if (new_mem
->mem_type
== TTM_PL_SYSTEM
)
842 ret
= nouveau_bo_move_flipd(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
843 else if (old_mem
->mem_type
== TTM_PL_SYSTEM
)
844 ret
= nouveau_bo_move_flips(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
846 ret
= nouveau_bo_move_m2mf(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
851 /* Fallback to software copy. */
852 ret
= ttm_bo_move_memcpy(bo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
856 nouveau_bo_vm_cleanup(bo
, NULL
, &new_tile
);
858 nouveau_bo_vm_cleanup(bo
, new_tile
, &nvbo
->tile
);
864 nouveau_bo_verify_access(struct ttm_buffer_object
*bo
, struct file
*filp
)
870 nouveau_ttm_io_mem_reserve(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
872 struct ttm_mem_type_manager
*man
= &bdev
->man
[mem
->mem_type
];
873 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
874 struct drm_device
*dev
= dev_priv
->dev
;
877 mem
->bus
.addr
= NULL
;
879 mem
->bus
.size
= mem
->num_pages
<< PAGE_SHIFT
;
881 mem
->bus
.is_iomem
= false;
882 if (!(man
->flags
& TTM_MEMTYPE_FLAG_MAPPABLE
))
884 switch (mem
->mem_type
) {
890 if (dev_priv
->gart_info
.type
== NOUVEAU_GART_AGP
) {
891 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
892 mem
->bus
.base
= dev_priv
->gart_info
.aper_base
;
893 mem
->bus
.is_iomem
= true;
899 struct nouveau_vram
*vram
= mem
->mm_node
;
901 if (!dev_priv
->bar1_vm
) {
902 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
903 mem
->bus
.base
= pci_resource_start(dev
->pdev
, 1);
904 mem
->bus
.is_iomem
= true;
908 ret
= nouveau_vm_get(dev_priv
->bar1_vm
, mem
->bus
.size
, 12,
909 NV_MEM_ACCESS_RW
, &vram
->bar_vma
);
913 nouveau_vm_map(&vram
->bar_vma
, vram
);
915 nouveau_vm_put(&vram
->bar_vma
);
919 mem
->bus
.offset
= vram
->bar_vma
.offset
;
920 mem
->bus
.offset
-= 0x0020000000ULL
;
921 mem
->bus
.base
= pci_resource_start(dev
->pdev
, 1);
922 mem
->bus
.is_iomem
= true;
932 nouveau_ttm_io_mem_free(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
934 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
935 struct nouveau_vram
*vram
= mem
->mm_node
;
937 if (!dev_priv
->bar1_vm
|| mem
->mem_type
!= TTM_PL_VRAM
)
940 if (!vram
->bar_vma
.node
)
943 nouveau_vm_unmap(&vram
->bar_vma
);
944 nouveau_vm_put(&vram
->bar_vma
);
948 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object
*bo
)
950 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
951 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
953 /* as long as the bo isn't in vram, and isn't tiled, we've got
954 * nothing to do here.
956 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
) {
957 if (dev_priv
->card_type
< NV_50
||
958 !nouveau_bo_tile_layout(nvbo
))
962 /* make sure bo is in mappable vram */
963 if (bo
->mem
.start
+ bo
->mem
.num_pages
< dev_priv
->fb_mappable_pages
)
967 nvbo
->placement
.fpfn
= 0;
968 nvbo
->placement
.lpfn
= dev_priv
->fb_mappable_pages
;
969 nouveau_bo_placement_set(nvbo
, TTM_PL_VRAM
, 0);
970 return nouveau_bo_validate(nvbo
, false, true, false);
974 nouveau_bo_fence(struct nouveau_bo
*nvbo
, struct nouveau_fence
*fence
)
976 struct nouveau_fence
*old_fence
;
979 nouveau_fence_ref(fence
);
981 spin_lock(&nvbo
->bo
.bdev
->fence_lock
);
982 old_fence
= nvbo
->bo
.sync_obj
;
983 nvbo
->bo
.sync_obj
= fence
;
984 spin_unlock(&nvbo
->bo
.bdev
->fence_lock
);
986 nouveau_fence_unref(&old_fence
);
989 struct ttm_bo_driver nouveau_bo_driver
= {
990 .create_ttm_backend_entry
= nouveau_bo_create_ttm_backend_entry
,
991 .invalidate_caches
= nouveau_bo_invalidate_caches
,
992 .init_mem_type
= nouveau_bo_init_mem_type
,
993 .evict_flags
= nouveau_bo_evict_flags
,
994 .move
= nouveau_bo_move
,
995 .verify_access
= nouveau_bo_verify_access
,
996 .sync_obj_signaled
= __nouveau_fence_signalled
,
997 .sync_obj_wait
= __nouveau_fence_wait
,
998 .sync_obj_flush
= __nouveau_fence_flush
,
999 .sync_obj_unref
= __nouveau_fence_unref
,
1000 .sync_obj_ref
= __nouveau_fence_ref
,
1001 .fault_reserve_notify
= &nouveau_ttm_fault_reserve_notify
,
1002 .io_mem_reserve
= &nouveau_ttm_io_mem_reserve
,
1003 .io_mem_free
= &nouveau_ttm_io_mem_free
,