arch/sh/kernel/cpu/sh4a/clock-sh7724.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
   3  *
   4  * SH7724 clock framework support
   5  *
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <asm/clkdev.h>
  26 #include <asm/clock.h>
  27 #include <asm/hwblk.h>
  28 #include <cpu/sh7724.h>
  29
  30 /* SH7724 registers */
  31 #define FRQCRA          0xa4150000
  32 #define FRQCRB          0xa4150004
  33 #define VCLKCR          0xa4150048
  34 #define FCLKACR         0xa4150008
  35 #define FCLKBCR         0xa415000c
  36 #define IRDACLKCR       0xa4150018
  37 #define PLLCR           0xa4150024
  38 #define SPUCLKCR        0xa415003c
  39 #define FLLFRQ          0xa4150050
  40 #define LSTATS          0xa4150060
  41
  42 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
  43 static struct clk r_clk = {
  44         .rate           = 32768,
  45 };
  46
  47 /*
  48  * Default rate for the root input clock, reset this with clk_set_rate()
  49  * from the platform code.
  50  */
  51 static struct clk extal_clk = {
  52         .rate           = 33333333,
  53 };
  54
  55 /* The fll multiplies the 32khz r_clk, may be used instead of extal */
  56 static unsigned long fll_recalc(struct clk *clk)
  57 {
  58         unsigned long mult = 0;
  59         unsigned long div = 1;
  60
  61         if (__raw_readl(PLLCR) & 0x1000)
  62                 mult = __raw_readl(FLLFRQ) & 0x3ff;
  63
  64         if (__raw_readl(FLLFRQ) & 0x4000)
  65                 div = 2;
  66
  67         return (clk->parent->rate * mult) / div;
  68 }
  69
  70 static struct clk_ops fll_clk_ops = {
  71         .recalc         = fll_recalc,
  72 };
  73
  74 static struct clk fll_clk = {
  75         .ops            = &fll_clk_ops,
  76         .parent         = &r_clk,
  77         .flags          = CLK_ENABLE_ON_INIT,
  78 };
  79
  80 static unsigned long pll_recalc(struct clk *clk)
  81 {
  82         unsigned long mult = 1;
  83
  84         if (__raw_readl(PLLCR) & 0x4000)
  85                 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
  86
  87         return clk->parent->rate * mult;
  88 }
  89
  90 static struct clk_ops pll_clk_ops = {
  91         .recalc         = pll_recalc,
  92 };
  93
  94 static struct clk pll_clk = {
  95         .ops            = &pll_clk_ops,
  96         .flags          = CLK_ENABLE_ON_INIT,
  97 };
  98
  99 /* A fixed divide-by-3 block use by the div6 clocks */
 100 static unsigned long div3_recalc(struct clk *clk)
 101 {
 102         return clk->parent->rate / 3;
 103 }
 104
 105 static struct clk_ops div3_clk_ops = {
 106         .recalc         = div3_recalc,
 107 };
 108
 109 static struct clk div3_clk = {
 110         .ops            = &div3_clk_ops,
 111         .parent         = &pll_clk,
 112 };
 113
 114 /* External input clock (pin name: FSIMCKA/FSIMCKB ) */
 115 struct clk sh7724_fsimcka_clk = {
 116 };
 117
 118 struct clk sh7724_fsimckb_clk = {
 119 };
 120
 121 static struct clk *main_clks[] = {
 122         &r_clk,
 123         &extal_clk,
 124         &fll_clk,
 125         &pll_clk,
 126         &div3_clk,
 127         &sh7724_fsimcka_clk,
 128         &sh7724_fsimckb_clk,
 129 };
 130
 131 static void div4_kick(struct clk *clk)
 132 {
 133         unsigned long value;
 134
 135         /* set KICK bit in FRQCRA to update hardware setting */
 136         value = __raw_readl(FRQCRA);
 137         value |= (1 << 31);
 138         __raw_writel(value, FRQCRA);
 139 }
 140
 141 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
 142
 143 static struct clk_div_mult_table div4_div_mult_table = {
 144         .divisors = divisors,
 145         .nr_divisors = ARRAY_SIZE(divisors),
 146 };
 147
 148 static struct clk_div4_table div4_table = {
 149         .div_mult_table = &div4_div_mult_table,
 150         .kick = div4_kick,
 151 };
 152
 153 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
 154
 155 #define DIV4(_reg, _bit, _mask, _flags) \
 156   SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 157
 158 struct clk div4_clks[DIV4_NR] = {
 159         [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
 160         [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
 161         [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
 162         [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
 163         [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
 164 };
 165
 166 enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
 167
 168 static struct clk div6_clks[DIV6_NR] = {
 169         [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
 170         [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
 171         [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
 172 };
 173
 174 enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
 175
 176 /* Indices are important - they are the actual src selecting values */
 177 static struct clk *fclkacr_parent[] = {
 178         [0] = &div3_clk,
 179         [1] = NULL,
 180         [2] = &sh7724_fsimcka_clk,
 181         [3] = NULL,
 182 };
 183
 184 static struct clk *fclkbcr_parent[] = {
 185         [0] = &div3_clk,
 186         [1] = NULL,
 187         [2] = &sh7724_fsimckb_clk,
 188         [3] = NULL,
 189 };
 190
 191 static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
 192         [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
 193                                       fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
 194         [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
 195                                       fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
 196 };
 197
 198 static struct clk mstp_clks[HWBLK_NR] = {
 199         SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 200         SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 201         SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 202         SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
 203         SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 204         SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
 205         SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 206         SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
 207         SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
 208         SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
 209         SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
 210         SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
 211         SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
 212         SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
 213         SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
 214         SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
 215         SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
 216         SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
 217         SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
 218         SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
 219         SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
 220         SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
 221         SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
 222         SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
 223         SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
 224
 225         SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
 226         SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
 227         SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0),
 228         SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0),
 229
 230         SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0),
 231         SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0),
 232         SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0),
 233         SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
 234         SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
 235         SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
 236         SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0),
 237         SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0),
 238         SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
 239         SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
 240         SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
 241         SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0),
 242         SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0),
 243         SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0),
 244         SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0),
 245         SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0),
 246         SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
 247         SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
 248         SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0),
 249         SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0),
 250         SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0),
 251         SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
 252         SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
 253 };
 254
 255 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 256
 257 static struct clk_lookup lookups[] = {
 258         /* main clocks */
 259         CLKDEV_CON_ID("rclk", &r_clk),
 260         CLKDEV_CON_ID("extal", &extal_clk),
 261         CLKDEV_CON_ID("fll_clk", &fll_clk),
 262         CLKDEV_CON_ID("pll_clk", &pll_clk),
 263         CLKDEV_CON_ID("div3_clk", &div3_clk),
 264
 265         /* DIV4 clocks */
 266         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 267         CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
 268         CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
 269         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 270         CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
 271
 272         /* DIV6 clocks */
 273         CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
 274         CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
 275         CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
 276         CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
 277         CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
 278
 279         /* MSTP clocks */
 280         CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
 281         CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
 282         CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
 283         CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
 284         CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
 285         CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
 286         CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
 287         CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
 288         CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
 289         CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
 290         CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
 291         CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
 292         {
 293                 /* TMU0 */
 294                 .dev_id         = "sh_tmu.0",
 295                 .con_id         = "tmu_fck",
 296                 .clk            = &mstp_clks[HWBLK_TMU0],
 297         }, {
 298                 /* TMU1 */
 299                 .dev_id         = "sh_tmu.1",
 300                 .con_id         = "tmu_fck",
 301                 .clk            = &mstp_clks[HWBLK_TMU0],
 302         }, {
 303                 /* TMU2 */
 304                 .dev_id         = "sh_tmu.2",
 305                 .con_id         = "tmu_fck",
 306                 .clk            = &mstp_clks[HWBLK_TMU0],
 307         }, {
 308                 /* TMU3 */
 309                 .dev_id         = "sh_tmu.3",
 310                 .con_id         = "tmu_fck",
 311                 .clk            = &mstp_clks[HWBLK_TMU1],
 312         },
 313         CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
 314         CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
 315         CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
 316         {
 317                 /* TMU4 */
 318                 .dev_id         = "sh_tmu.4",
 319                 .con_id         = "tmu_fck",
 320                 .clk            = &mstp_clks[HWBLK_TMU1],
 321         }, {
 322                 /* TMU5 */
 323                 .dev_id         = "sh_tmu.5",
 324                 .con_id         = "tmu_fck",
 325                 .clk            = &mstp_clks[HWBLK_TMU1],
 326         }, {
 327                 /* SCIF0 */
 328                 .dev_id         = "sh-sci.0",
 329                 .con_id         = "sci_fck",
 330                 .clk            = &mstp_clks[HWBLK_SCIF0],
 331         }, {
 332                 /* SCIF1 */
 333                 .dev_id         = "sh-sci.1",
 334                 .con_id         = "sci_fck",
 335                 .clk            = &mstp_clks[HWBLK_SCIF1],
 336         }, {
 337                 /* SCIF2 */
 338                 .dev_id         = "sh-sci.2",
 339                 .con_id         = "sci_fck",
 340                 .clk            = &mstp_clks[HWBLK_SCIF2],
 341         }, {
 342                 /* SCIF3 */
 343                 .dev_id         = "sh-sci.3",
 344                 .con_id         = "sci_fck",
 345                 .clk            = &mstp_clks[HWBLK_SCIF3],
 346         }, {
 347                 /* SCIF4 */
 348                 .dev_id         = "sh-sci.4",
 349                 .con_id         = "sci_fck",
 350                 .clk            = &mstp_clks[HWBLK_SCIF4],
 351         }, {
 352                 /* SCIF5 */
 353                 .dev_id         = "sh-sci.5",
 354                 .con_id         = "sci_fck",
 355                 .clk            = &mstp_clks[HWBLK_SCIF5],
 356         },
 357         CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
 358         CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
 359         CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
 360         CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
 361         CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC0]),
 362         CLKDEV_CON_ID("i2c1", &mstp_clks[HWBLK_IIC1]),
 363         CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]),
 364         CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]),
 365         CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
 366         CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
 367         CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
 368         CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
 369         CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
 370         CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
 371         CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
 372         CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
 373         CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
 374         CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
 375         CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]),
 376         CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
 377         CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
 378         CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
 379         CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
 380         CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
 381         CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
 382         CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]),
 383         CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
 384         CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
 385         CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
 386 };
 387
 388 int __init arch_clk_init(void)
 389 {
 390         int k, ret = 0;
 391
 392         /* autodetect extal or fll configuration */
 393         if (__raw_readl(PLLCR) & 0x1000)
 394                 pll_clk.parent = &fll_clk;
 395         else
 396                 pll_clk.parent = &extal_clk;
 397
 398         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 399                 ret = clk_register(main_clks[k]);
 400
 401         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 402
 403         if (!ret)
 404                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 405
 406         if (!ret)
 407                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 408
 409         if (!ret)
 410                 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
 411
 412         if (!ret)
 413                 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
 414
 415         return ret;
 416 }