include/asm-i386/processor.h

   1 /*
   2  * include/asm-i386/processor.h
   3  *
   4  * Copyright (C) 1994 Linus Torvalds
   5  */
   6
   7 #ifndef __ASM_I386_PROCESSOR_H
   8 #define __ASM_I386_PROCESSOR_H
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/page.h>
  14 #include <asm/types.h>
  15 #include <asm/sigcontext.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/msr.h>
  18 #include <asm/system.h>
  19 #include <linux/cache.h>
  20 #include <linux/threads.h>
  21 #include <asm/percpu.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/init.h>
  24 #include <asm/processor-flags.h>
  25
  26 /* flag for disabling the tsc */
  27 extern int tsc_disable;
  28
  29 struct desc_struct {
  30         unsigned long a,b;
  31 };
  32
  33 #define desc_empty(desc) \
  34                 (!((desc)->a | (desc)->b))
  35
  36 #define desc_equal(desc1, desc2) \
  37                 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
  38 /*
  39  * Default implementation of macro that returns current
  40  * instruction pointer ("program counter").
  41  */
  42 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
  43
  44 /*
  45  *  CPU type and hardware bug flags. Kept separately for each CPU.
  46  *  Members of this structure are referenced in head.S, so think twice
  47  *  before touching them. [mj]
  48  */
  49
  50 struct cpuinfo_x86 {
  51         __u8    x86;            /* CPU family */
  52         __u8    x86_vendor;     /* CPU vendor */
  53         __u8    x86_model;
  54         __u8    x86_mask;
  55         char    wp_works_ok;    /* It doesn't on 386's */
  56         char    hlt_works_ok;   /* Problems on some 486Dx4's and old 386's */
  57         char    hard_math;
  58         char    rfu;
  59         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  60         unsigned long   x86_capability[NCAPINTS];
  61         char    x86_vendor_id[16];
  62         char    x86_model_id[64];
  63         int     x86_cache_size;  /* in KB - valid for CPUS which support this
  64                                     call  */
  65         int     x86_cache_alignment;    /* In bytes */
  66         char    fdiv_bug;
  67         char    f00f_bug;
  68         char    coma_bug;
  69         char    pad0;
  70         int     x86_power;
  71         unsigned long loops_per_jiffy;
  72 #ifdef CONFIG_SMP
  73         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
  74 #endif
  75         unsigned char x86_max_cores;    /* cpuid returned max cores value */
  76         unsigned char apicid;
  77         unsigned short x86_clflush_size;
  78 #ifdef CONFIG_SMP
  79         unsigned char booted_cores;     /* number of cores as seen by OS */
  80         __u8 phys_proc_id;              /* Physical processor id. */
  81         __u8 cpu_core_id;               /* Core id */
  82 #endif
  83 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
  84
  85 #define X86_VENDOR_INTEL 0
  86 #define X86_VENDOR_CYRIX 1
  87 #define X86_VENDOR_AMD 2
  88 #define X86_VENDOR_UMC 3
  89 #define X86_VENDOR_NEXGEN 4
  90 #define X86_VENDOR_CENTAUR 5
  91 #define X86_VENDOR_RISE 6
  92 #define X86_VENDOR_TRANSMETA 7
  93 #define X86_VENDOR_NSC 8
  94 #define X86_VENDOR_NUM 9
  95 #define X86_VENDOR_UNKNOWN 0xff
  96
  97 /*
  98  * capabilities of CPUs
  99  */
 100
 101 extern struct cpuinfo_x86 boot_cpu_data;
 102 extern struct cpuinfo_x86 new_cpu_data;
 103 extern struct tss_struct doublefault_tss;
 104 DECLARE_PER_CPU(struct tss_struct, init_tss);
 105
 106 #ifdef CONFIG_SMP
 107 extern struct cpuinfo_x86 cpu_data[];
 108 #define current_cpu_data cpu_data[smp_processor_id()]
 109 #else
 110 #define cpu_data (&boot_cpu_data)
 111 #define current_cpu_data boot_cpu_data
 112 #endif
 113
 114 extern  int cpu_llc_id[NR_CPUS];
 115 extern char ignore_fpu_irq;
 116
 117 void __init cpu_detect(struct cpuinfo_x86 *c);
 118
 119 extern void identify_boot_cpu(void);
 120 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 121 extern void print_cpu_info(struct cpuinfo_x86 *);
 122 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 123 extern unsigned short num_cache_leaves;
 124
 125 #ifdef CONFIG_X86_HT
 126 extern void detect_ht(struct cpuinfo_x86 *c);
 127 #else
 128 static inline void detect_ht(struct cpuinfo_x86 *c) {}
 129 #endif
 130
 131 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 132                                          unsigned int *ecx, unsigned int *edx)
 133 {
 134         /* ecx is often an input as well as an output. */
 135         __asm__("cpuid"
 136                 : "=a" (*eax),
 137                   "=b" (*ebx),
 138                   "=c" (*ecx),
 139                   "=d" (*edx)
 140                 : "0" (*eax), "2" (*ecx));
 141 }
 142
 143 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
 144
 145 /*
 146  * Save the cr4 feature set we're using (ie
 147  * Pentium 4MB enable and PPro Global page
 148  * enable), so that any CPU's that boot up
 149  * after us can get the correct flags.
 150  */
 151 extern unsigned long mmu_cr4_features;
 152
 153 static inline void set_in_cr4 (unsigned long mask)
 154 {
 155         unsigned cr4;
 156         mmu_cr4_features |= mask;
 157         cr4 = read_cr4();
 158         cr4 |= mask;
 159         write_cr4(cr4);
 160 }
 161
 162 static inline void clear_in_cr4 (unsigned long mask)
 163 {
 164         unsigned cr4;
 165         mmu_cr4_features &= ~mask;
 166         cr4 = read_cr4();
 167         cr4 &= ~mask;
 168         write_cr4(cr4);
 169 }
 170
 171 /*
 172  *      NSC/Cyrix CPU indexed register access macros
 173  */
 174
 175 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
 176
 177 #define setCx86(reg, data) do { \
 178         outb((reg), 0x22); \
 179         outb((data), 0x23); \
 180 } while (0)
 181
 182 /* Stop speculative execution */
 183 static inline void sync_core(void)
 184 {
 185         int tmp;
 186         asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
 187 }
 188
 189 static inline void __monitor(const void *eax, unsigned long ecx,
 190                 unsigned long edx)
 191 {
 192         /* "monitor %eax,%ecx,%edx;" */
 193         asm volatile(
 194                 ".byte 0x0f,0x01,0xc8;"
 195                 : :"a" (eax), "c" (ecx), "d"(edx));
 196 }
 197
 198 static inline void __mwait(unsigned long eax, unsigned long ecx)
 199 {
 200         /* "mwait %eax,%ecx;" */
 201         asm volatile(
 202                 ".byte 0x0f,0x01,0xc9;"
 203                 : :"a" (eax), "c" (ecx));
 204 }
 205
 206 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 207
 208 /* from system description table in BIOS.  Mostly for MCA use, but
 209 others may find it useful. */
 210 extern unsigned int machine_id;
 211 extern unsigned int machine_submodel_id;
 212 extern unsigned int BIOS_revision;
 213 extern unsigned int mca_pentium_flag;
 214
 215 /* Boot loader type from the setup header */
 216 extern int bootloader_type;
 217
 218 /*
 219  * User space process size: 3GB (default).
 220  */
 221 #define TASK_SIZE       (PAGE_OFFSET)
 222
 223 /* This decides where the kernel will search for a free chunk of vm
 224  * space during mmap's.
 225  */
 226 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 227
 228 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 229
 230 /*
 231  * Size of io_bitmap.
 232  */
 233 #define IO_BITMAP_BITS  65536
 234 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 235 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 236 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
 237 #define INVALID_IO_BITMAP_OFFSET 0x8000
 238 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
 239
 240 struct i387_fsave_struct {
 241         long    cwd;
 242         long    swd;
 243         long    twd;
 244         long    fip;
 245         long    fcs;
 246         long    foo;
 247         long    fos;
 248         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 249         long    status;         /* software status information */
 250 };
 251
 252 struct i387_fxsave_struct {
 253         unsigned short  cwd;
 254         unsigned short  swd;
 255         unsigned short  twd;
 256         unsigned short  fop;
 257         long    fip;
 258         long    fcs;
 259         long    foo;
 260         long    fos;
 261         long    mxcsr;
 262         long    mxcsr_mask;
 263         long    st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 264         long    xmm_space[32];  /* 8*16 bytes for each XMM-reg = 128 bytes */
 265         long    padding[56];
 266 } __attribute__ ((aligned (16)));
 267
 268 struct i387_soft_struct {
 269         long    cwd;
 270         long    swd;
 271         long    twd;
 272         long    fip;
 273         long    fcs;
 274         long    foo;
 275         long    fos;
 276         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 277         unsigned char   ftop, changed, lookahead, no_update, rm, alimit;
 278         struct info     *info;
 279         unsigned long   entry_eip;
 280 };
 281
 282 union i387_union {
 283         struct i387_fsave_struct        fsave;
 284         struct i387_fxsave_struct       fxsave;
 285         struct i387_soft_struct soft;
 286 };
 287
 288 typedef struct {
 289         unsigned long seg;
 290 } mm_segment_t;
 291
 292 struct thread_struct;
 293
 294 struct tss_struct {
 295         unsigned short  back_link,__blh;
 296         unsigned long   esp0;
 297         unsigned short  ss0,__ss0h;
 298         unsigned long   esp1;
 299         unsigned short  ss1,__ss1h;     /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
 300         unsigned long   esp2;
 301         unsigned short  ss2,__ss2h;
 302         unsigned long   __cr3;
 303         unsigned long   eip;
 304         unsigned long   eflags;
 305         unsigned long   eax,ecx,edx,ebx;
 306         unsigned long   esp;
 307         unsigned long   ebp;
 308         unsigned long   esi;
 309         unsigned long   edi;
 310         unsigned short  es, __esh;
 311         unsigned short  cs, __csh;
 312         unsigned short  ss, __ssh;
 313         unsigned short  ds, __dsh;
 314         unsigned short  fs, __fsh;
 315         unsigned short  gs, __gsh;
 316         unsigned short  ldt, __ldth;
 317         unsigned short  trace, io_bitmap_base;
 318         /*
 319          * The extra 1 is there because the CPU will access an
 320          * additional byte beyond the end of the IO permission
 321          * bitmap. The extra byte must be all 1 bits, and must
 322          * be within the limit.
 323          */
 324         unsigned long   io_bitmap[IO_BITMAP_LONGS + 1];
 325         /*
 326          * Cache the current maximum and the last task that used the bitmap:
 327          */
 328         unsigned long io_bitmap_max;
 329         struct thread_struct *io_bitmap_owner;
 330         /*
 331          * pads the TSS to be cacheline-aligned (size is 0x100)
 332          */
 333         unsigned long __cacheline_filler[35];
 334         /*
 335          * .. and then another 0x100 bytes for emergency kernel stack
 336          */
 337         unsigned long stack[64];
 338 } __attribute__((packed));
 339
 340 #define ARCH_MIN_TASKALIGN      16
 341
 342 struct thread_struct {
 343 /* cached TLS descriptors. */
 344         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 345         unsigned long   esp0;
 346         unsigned long   sysenter_cs;
 347         unsigned long   eip;
 348         unsigned long   esp;
 349         unsigned long   fs;
 350         unsigned long   gs;
 351 /* Hardware debugging registers */
 352         unsigned long   debugreg[8];  /* %%db0-7 debug registers */
 353 /* fault info */
 354         unsigned long   cr2, trap_no, error_code;
 355 /* floating point info */
 356         union i387_union        i387;
 357 /* virtual 86 mode info */
 358         struct vm86_struct __user * vm86_info;
 359         unsigned long           screen_bitmap;
 360         unsigned long           v86flags, v86mask, saved_esp0;
 361         unsigned int            saved_fs, saved_gs;
 362 /* IO permissions */
 363         unsigned long   *io_bitmap_ptr;
 364         unsigned long   iopl;
 365 /* max allowed port in the bitmap, in bytes: */
 366         unsigned long   io_bitmap_max;
 367 };
 368
 369 #define INIT_THREAD  {                                                  \
 370         .esp0 = sizeof(init_stack) + (long)&init_stack,                 \
 371         .vm86_info = NULL,                                              \
 372         .sysenter_cs = __KERNEL_CS,                                     \
 373         .io_bitmap_ptr = NULL,                                          \
 374         .fs = __KERNEL_PDA,                                             \
 375 }
 376
 377 /*
 378  * Note that the .io_bitmap member must be extra-big. This is because
 379  * the CPU will access an additional byte beyond the end of the IO
 380  * permission bitmap. The extra byte must be all 1 bits, and must
 381  * be within the limit.
 382  */
 383 #define INIT_TSS  {                                                     \
 384         .esp0           = sizeof(init_stack) + (long)&init_stack,       \
 385         .ss0            = __KERNEL_DS,                                  \
 386         .ss1            = __KERNEL_CS,                                  \
 387         .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,                     \
 388         .io_bitmap      = { [ 0 ... IO_BITMAP_LONGS] = ~0 },            \
 389 }
 390
 391 #define start_thread(regs, new_eip, new_esp) do {               \
 392         __asm__("movl %0,%%gs": :"r" (0));                      \
 393         regs->xfs = 0;                                          \
 394         set_fs(USER_DS);                                        \
 395         regs->xds = __USER_DS;                                  \
 396         regs->xes = __USER_DS;                                  \
 397         regs->xss = __USER_DS;                                  \
 398         regs->xcs = __USER_CS;                                  \
 399         regs->eip = new_eip;                                    \
 400         regs->esp = new_esp;                                    \
 401 } while (0)
 402
 403 /* Forward declaration, a strange C thing */
 404 struct task_struct;
 405 struct mm_struct;
 406
 407 /* Free all resources held by a thread. */
 408 extern void release_thread(struct task_struct *);
 409
 410 /* Prepare to copy thread state - unlazy all lazy status */
 411 extern void prepare_to_copy(struct task_struct *tsk);
 412
 413 /*
 414  * create a kernel thread without removing it from tasklists
 415  */
 416 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 417
 418 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 419 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
 420
 421 unsigned long get_wchan(struct task_struct *p);
 422
 423 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 424 #define KSTK_TOP(info)                                                 \
 425 ({                                                                     \
 426        unsigned long *__ptr = (unsigned long *)(info);                 \
 427        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 428 })
 429
 430 /*
 431  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 432  * This is necessary to guarantee that the entire "struct pt_regs"
 433  * is accessable even if the CPU haven't stored the SS/ESP registers
 434  * on the stack (interrupt gate does not save these registers
 435  * when switching to the same priv ring).
 436  * Therefore beware: accessing the xss/esp fields of the
 437  * "struct pt_regs" is possible, but they may contain the
 438  * completely wrong values.
 439  */
 440 #define task_pt_regs(task)                                             \
 441 ({                                                                     \
 442        struct pt_regs *__regs__;                                       \
 443        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 444        __regs__ - 1;                                                   \
 445 })
 446
 447 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
 448 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
 449
 450
 451 struct microcode_header {
 452         unsigned int hdrver;
 453         unsigned int rev;
 454         unsigned int date;
 455         unsigned int sig;
 456         unsigned int cksum;
 457         unsigned int ldrver;
 458         unsigned int pf;
 459         unsigned int datasize;
 460         unsigned int totalsize;
 461         unsigned int reserved[3];
 462 };
 463
 464 struct microcode {
 465         struct microcode_header hdr;
 466         unsigned int bits[0];
 467 };
 468
 469 typedef struct microcode microcode_t;
 470 typedef struct microcode_header microcode_header_t;
 471
 472 /* microcode format is extended from prescott processors */
 473 struct extended_signature {
 474         unsigned int sig;
 475         unsigned int pf;
 476         unsigned int cksum;
 477 };
 478
 479 struct extended_sigtable {
 480         unsigned int count;
 481         unsigned int cksum;
 482         unsigned int reserved[3];
 483         struct extended_signature sigs[0];
 484 };
 485
 486 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 487 static inline void rep_nop(void)
 488 {
 489         __asm__ __volatile__("rep;nop": : :"memory");
 490 }
 491
 492 #define cpu_relax()     rep_nop()
 493
 494 static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread)
 495 {
 496         tss->esp0 = thread->esp0;
 497         /* This can only happen when SEP is enabled, no need to test "SEP"arately */
 498         if (unlikely(tss->ss1 != thread->sysenter_cs)) {
 499                 tss->ss1 = thread->sysenter_cs;
 500                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 501         }
 502 }
 503
 504
 505 static inline unsigned long native_get_debugreg(int regno)
 506 {
 507         unsigned long val = 0;  /* Damn you, gcc! */
 508
 509         switch (regno) {
 510         case 0:
 511                 asm("movl %%db0, %0" :"=r" (val)); break;
 512         case 1:
 513                 asm("movl %%db1, %0" :"=r" (val)); break;
 514         case 2:
 515                 asm("movl %%db2, %0" :"=r" (val)); break;
 516         case 3:
 517                 asm("movl %%db3, %0" :"=r" (val)); break;
 518         case 6:
 519                 asm("movl %%db6, %0" :"=r" (val)); break;
 520         case 7:
 521                 asm("movl %%db7, %0" :"=r" (val)); break;
 522         default:
 523                 BUG();
 524         }
 525         return val;
 526 }
 527
 528 static inline void native_set_debugreg(int regno, unsigned long value)
 529 {
 530         switch (regno) {
 531         case 0:
 532                 asm("movl %0,%%db0"     : /* no output */ :"r" (value));
 533                 break;
 534         case 1:
 535                 asm("movl %0,%%db1"     : /* no output */ :"r" (value));
 536                 break;
 537         case 2:
 538                 asm("movl %0,%%db2"     : /* no output */ :"r" (value));
 539                 break;
 540         case 3:
 541                 asm("movl %0,%%db3"     : /* no output */ :"r" (value));
 542                 break;
 543         case 6:
 544                 asm("movl %0,%%db6"     : /* no output */ :"r" (value));
 545                 break;
 546         case 7:
 547                 asm("movl %0,%%db7"     : /* no output */ :"r" (value));
 548                 break;
 549         default:
 550                 BUG();
 551         }
 552 }
 553
 554 /*
 555  * Set IOPL bits in EFLAGS from given mask
 556  */
 557 static inline void native_set_iopl_mask(unsigned mask)
 558 {
 559         unsigned int reg;
 560         __asm__ __volatile__ ("pushfl;"
 561                               "popl %0;"
 562                               "andl %1, %0;"
 563                               "orl %2, %0;"
 564                               "pushl %0;"
 565                               "popfl"
 566                                 : "=&r" (reg)
 567                                 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 568 }
 569
 570 #ifdef CONFIG_PARAVIRT
 571 #include <asm/paravirt.h>
 572 #else
 573 #define paravirt_enabled() 0
 574 #define __cpuid native_cpuid
 575
 576 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
 577 {
 578         native_load_esp0(tss, thread);
 579 }
 580
 581 /*
 582  * These special macros can be used to get or set a debugging register
 583  */
 584 #define get_debugreg(var, register)                             \
 585         (var) = native_get_debugreg(register)
 586 #define set_debugreg(value, register)                           \
 587         native_set_debugreg(register, value)
 588
 589 #define set_iopl_mask native_set_iopl_mask
 590 #endif /* CONFIG_PARAVIRT */
 591
 592 /*
 593  * Generic CPUID function
 594  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 595  * resulting in stale register contents being returned.
 596  */
 597 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
 598 {
 599         *eax = op;
 600         *ecx = 0;
 601         __cpuid(eax, ebx, ecx, edx);
 602 }
 603
 604 /* Some CPUID calls want 'count' to be placed in ecx */
 605 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
 606                                int *edx)
 607 {
 608         *eax = op;
 609         *ecx = count;
 610         __cpuid(eax, ebx, ecx, edx);
 611 }
 612
 613 /*
 614  * CPUID functions returning a single datum
 615  */
 616 static inline unsigned int cpuid_eax(unsigned int op)
 617 {
 618         unsigned int eax, ebx, ecx, edx;
 619
 620         cpuid(op, &eax, &ebx, &ecx, &edx);
 621         return eax;
 622 }
 623 static inline unsigned int cpuid_ebx(unsigned int op)
 624 {
 625         unsigned int eax, ebx, ecx, edx;
 626
 627         cpuid(op, &eax, &ebx, &ecx, &edx);
 628         return ebx;
 629 }
 630 static inline unsigned int cpuid_ecx(unsigned int op)
 631 {
 632         unsigned int eax, ebx, ecx, edx;
 633
 634         cpuid(op, &eax, &ebx, &ecx, &edx);
 635         return ecx;
 636 }
 637 static inline unsigned int cpuid_edx(unsigned int op)
 638 {
 639         unsigned int eax, ebx, ecx, edx;
 640
 641         cpuid(op, &eax, &ebx, &ecx, &edx);
 642         return edx;
 643 }
 644
 645 /* generic versions from gas */
 646 #define GENERIC_NOP1    ".byte 0x90\n"
 647 #define GENERIC_NOP2            ".byte 0x89,0xf6\n"
 648 #define GENERIC_NOP3        ".byte 0x8d,0x76,0x00\n"
 649 #define GENERIC_NOP4        ".byte 0x8d,0x74,0x26,0x00\n"
 650 #define GENERIC_NOP5        GENERIC_NOP1 GENERIC_NOP4
 651 #define GENERIC_NOP6    ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
 652 #define GENERIC_NOP7    ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
 653 #define GENERIC_NOP8    GENERIC_NOP1 GENERIC_NOP7
 654
 655 /* Opteron nops */
 656 #define K8_NOP1 GENERIC_NOP1
 657 #define K8_NOP2 ".byte 0x66,0x90\n"
 658 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
 659 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
 660 #define K8_NOP5 K8_NOP3 K8_NOP2
 661 #define K8_NOP6 K8_NOP3 K8_NOP3
 662 #define K8_NOP7 K8_NOP4 K8_NOP3
 663 #define K8_NOP8 K8_NOP4 K8_NOP4
 664
 665 /* K7 nops */
 666 /* uses eax dependencies (arbitary choice) */
 667 #define K7_NOP1  GENERIC_NOP1
 668 #define K7_NOP2 ".byte 0x8b,0xc0\n"
 669 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
 670 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
 671 #define K7_NOP5 K7_NOP4 ASM_NOP1
 672 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
 673 #define K7_NOP7        ".byte 0x8D,0x04,0x05,0,0,0,0\n"
 674 #define K7_NOP8        K7_NOP7 ASM_NOP1
 675
 676 #ifdef CONFIG_MK8
 677 #define ASM_NOP1 K8_NOP1
 678 #define ASM_NOP2 K8_NOP2
 679 #define ASM_NOP3 K8_NOP3
 680 #define ASM_NOP4 K8_NOP4
 681 #define ASM_NOP5 K8_NOP5
 682 #define ASM_NOP6 K8_NOP6
 683 #define ASM_NOP7 K8_NOP7
 684 #define ASM_NOP8 K8_NOP8
 685 #elif defined(CONFIG_MK7)
 686 #define ASM_NOP1 K7_NOP1
 687 #define ASM_NOP2 K7_NOP2
 688 #define ASM_NOP3 K7_NOP3
 689 #define ASM_NOP4 K7_NOP4
 690 #define ASM_NOP5 K7_NOP5
 691 #define ASM_NOP6 K7_NOP6
 692 #define ASM_NOP7 K7_NOP7
 693 #define ASM_NOP8 K7_NOP8
 694 #else
 695 #define ASM_NOP1 GENERIC_NOP1
 696 #define ASM_NOP2 GENERIC_NOP2
 697 #define ASM_NOP3 GENERIC_NOP3
 698 #define ASM_NOP4 GENERIC_NOP4
 699 #define ASM_NOP5 GENERIC_NOP5
 700 #define ASM_NOP6 GENERIC_NOP6
 701 #define ASM_NOP7 GENERIC_NOP7
 702 #define ASM_NOP8 GENERIC_NOP8
 703 #endif
 704
 705 #define ASM_NOP_MAX 8
 706
 707 /* Prefetch instructions for Pentium III and AMD Athlon */
 708 /* It's not worth to care about 3dnow! prefetches for the K6
 709    because they are microcoded there and very slow.
 710    However we don't do prefetches for pre XP Athlons currently
 711    That should be fixed. */
 712 #define ARCH_HAS_PREFETCH
 713 static inline void prefetch(const void *x)
 714 {
 715         alternative_input(ASM_NOP4,
 716                           "prefetchnta (%1)",
 717                           X86_FEATURE_XMM,
 718                           "r" (x));
 719 }
 720
 721 #define ARCH_HAS_PREFETCH
 722 #define ARCH_HAS_PREFETCHW
 723 #define ARCH_HAS_SPINLOCK_PREFETCH
 724
 725 /* 3dnow! prefetch to get an exclusive cache line. Useful for
 726    spinlocks to avoid one state transition in the cache coherency protocol. */
 727 static inline void prefetchw(const void *x)
 728 {
 729         alternative_input(ASM_NOP4,
 730                           "prefetchw (%1)",
 731                           X86_FEATURE_3DNOW,
 732                           "r" (x));
 733 }
 734 #define spin_lock_prefetch(x)   prefetchw(x)
 735
 736 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 737
 738 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 739
 740 extern unsigned long boot_option_idle_override;
 741 extern void enable_sep_cpu(void);
 742 extern int sysenter_setup(void);
 743
 744 extern void cpu_set_gdt(int);
 745 extern void cpu_init(void);
 746
 747 extern int force_mwait;
 748
 749 #endif /* __ASM_I386_PROCESSOR_H */