arch/cris/arch-v32/kernel/irq.c

   1 /*
   2  * Copyright (C) 2003, Axis Communications AB.
   3  */
   4
   5 #include <asm/irq.h>
   6 #include <linux/irq.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/smp.h>
   9 #include <linux/kernel.h>
  10 #include <linux/errno.h>
  11 #include <linux/init.h>
  12 #include <linux/profile.h>
  13 #include <linux/proc_fs.h>
  14 #include <linux/seq_file.h>
  15 #include <linux/threads.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/kernel_stat.h>
  18 #include <asm/arch/hwregs/reg_map.h>
  19 #include <asm/arch/hwregs/reg_rdwr.h>
  20 #include <asm/arch/hwregs/intr_vect.h>
  21 #include <asm/arch/hwregs/intr_vect_defs.h>
  22
  23 #define CPU_FIXED -1
  24
  25 /* IRQ masks (refer to comment for crisv32_do_multiple) */
  26 #define TIMER_MASK (1 << (TIMER_INTR_VECT - FIRST_IRQ))
  27 #ifdef CONFIG_ETRAX_KGDB
  28 #if defined(CONFIG_ETRAX_KGDB_PORT0)
  29 #define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
  30 #elif defined(CONFIG_ETRAX_KGDB_PORT1)
  31 #define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
  32 #elif defined(CONFIG_ETRAX_KGB_PORT2)
  33 #define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
  34 #elif defined(CONFIG_ETRAX_KGDB_PORT3)
  35 #define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
  36 #endif
  37 #endif
  38
  39 DEFINE_SPINLOCK(irq_lock);
  40
  41 struct cris_irq_allocation
  42 {
  43   int cpu; /* The CPU to which the IRQ is currently allocated. */
  44   cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */
  45 };
  46
  47 struct cris_irq_allocation irq_allocations[NR_IRQS] =
  48   {[0 ... NR_IRQS - 1] = {0, CPU_MASK_ALL}};
  49
  50 static unsigned long irq_regs[NR_CPUS] =
  51 {
  52   regi_irq,
  53 #ifdef CONFIG_SMP
  54   regi_irq2,
  55 #endif
  56 };
  57
  58 unsigned long cpu_irq_counters[NR_CPUS];
  59 unsigned long irq_counters[NR_REAL_IRQS];
  60
  61 /* From irq.c. */
  62 extern void weird_irq(void);
  63
  64 /* From entry.S. */
  65 extern void system_call(void);
  66 extern void nmi_interrupt(void);
  67 extern void multiple_interrupt(void);
  68 extern void gdb_handle_exception(void);
  69 extern void i_mmu_refill(void);
  70 extern void i_mmu_invalid(void);
  71 extern void i_mmu_access(void);
  72 extern void i_mmu_execute(void);
  73 extern void d_mmu_refill(void);
  74 extern void d_mmu_invalid(void);
  75 extern void d_mmu_access(void);
  76 extern void d_mmu_write(void);
  77
  78 /* From kgdb.c. */
  79 extern void kgdb_init(void);
  80 extern void breakpoint(void);
  81
  82 /*
  83  * Build the IRQ handler stubs using macros from irq.h. First argument is the
  84  * IRQ number, the second argument is the corresponding bit in
  85  * intr_rw_vect_mask found in asm/arch/hwregs/intr_vect_defs.h.
  86  */
  87 BUILD_IRQ(0x31, (1 << 0))       /* memarb */
  88 BUILD_IRQ(0x32, (1 << 1))       /* gen_io */
  89 BUILD_IRQ(0x33, (1 << 2))       /* iop0 */
  90 BUILD_IRQ(0x34, (1 << 3))       /* iop1 */
  91 BUILD_IRQ(0x35, (1 << 4))       /* iop2 */
  92 BUILD_IRQ(0x36, (1 << 5))       /* iop3 */
  93 BUILD_IRQ(0x37, (1 << 6))       /* dma0 */
  94 BUILD_IRQ(0x38, (1 << 7))       /* dma1 */
  95 BUILD_IRQ(0x39, (1 << 8))       /* dma2 */
  96 BUILD_IRQ(0x3a, (1 << 9))       /* dma3 */
  97 BUILD_IRQ(0x3b, (1 << 10))      /* dma4 */
  98 BUILD_IRQ(0x3c, (1 << 11))      /* dma5 */
  99 BUILD_IRQ(0x3d, (1 << 12))      /* dma6 */
 100 BUILD_IRQ(0x3e, (1 << 13))      /* dma7 */
 101 BUILD_IRQ(0x3f, (1 << 14))      /* dma8 */
 102 BUILD_IRQ(0x40, (1 << 15))      /* dma9 */
 103 BUILD_IRQ(0x41, (1 << 16))      /* ata */
 104 BUILD_IRQ(0x42, (1 << 17))      /* sser0 */
 105 BUILD_IRQ(0x43, (1 << 18))      /* sser1 */
 106 BUILD_IRQ(0x44, (1 << 19))      /* ser0 */
 107 BUILD_IRQ(0x45, (1 << 20))      /* ser1 */
 108 BUILD_IRQ(0x46, (1 << 21))      /* ser2 */
 109 BUILD_IRQ(0x47, (1 << 22))      /* ser3 */
 110 BUILD_IRQ(0x48, (1 << 23))
 111 BUILD_IRQ(0x49, (1 << 24))      /* eth0 */
 112 BUILD_IRQ(0x4a, (1 << 25))      /* eth1 */
 113 BUILD_TIMER_IRQ(0x4b, (1 << 26))/* timer */
 114 BUILD_IRQ(0x4c, (1 << 27))      /* bif_arb */
 115 BUILD_IRQ(0x4d, (1 << 28))      /* bif_dma */
 116 BUILD_IRQ(0x4e, (1 << 29))      /* ext */
 117 BUILD_IRQ(0x4f, (1 << 29))      /* ipi */
 118
 119 /* Pointers to the low-level handlers. */
 120 static void (*interrupt[NR_IRQS])(void) = {
 121         IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,
 122         IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,
 123         IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,
 124         IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt,
 125         IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt,
 126         IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt,
 127         IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt,
 128         IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,
 129         IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,
 130         IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,
 131         IRQ0x4f_interrupt
 132 };
 133
 134 void
 135 block_irq(int irq, int cpu)
 136 {
 137         int intr_mask;
 138         unsigned long flags;
 139
 140         spin_lock_irqsave(&irq_lock, flags);
 141         intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
 142
 143         /* Remember; 1 let through, 0 block. */
 144         intr_mask &= ~(1 << (irq - FIRST_IRQ));
 145
 146         REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask);
 147         spin_unlock_irqrestore(&irq_lock, flags);
 148 }
 149
 150 void
 151 unblock_irq(int irq, int cpu)
 152 {
 153         int intr_mask;
 154         unsigned long flags;
 155
 156         spin_lock_irqsave(&irq_lock, flags);
 157         intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
 158
 159         /* Remember; 1 let through, 0 block. */
 160         intr_mask |= (1 << (irq - FIRST_IRQ));
 161
 162         REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask);
 163         spin_unlock_irqrestore(&irq_lock, flags);
 164 }
 165
 166 /* Find out which CPU the irq should be allocated to. */
 167 static int irq_cpu(int irq)
 168 {
 169         int cpu;
 170         unsigned long flags;
 171
 172         spin_lock_irqsave(&irq_lock, flags);
 173         cpu = irq_allocations[irq - FIRST_IRQ].cpu;
 174
 175         /* Fixed interrupts stay on the local CPU. */
 176         if (cpu == CPU_FIXED)
 177         {
 178                 spin_unlock_irqrestore(&irq_lock, flags);
 179                 return smp_processor_id();
 180         }
 181
 182
 183         /* Let the interrupt stay if possible */
 184         if (cpu_isset(cpu, irq_allocations[irq - FIRST_IRQ].mask))
 185                 goto out;
 186
 187         /* IRQ must be moved to another CPU. */
 188         cpu = first_cpu(irq_allocations[irq - FIRST_IRQ].mask);
 189         irq_allocations[irq - FIRST_IRQ].cpu = cpu;
 190 out:
 191         spin_unlock_irqrestore(&irq_lock, flags);
 192         return cpu;
 193 }
 194
 195 void
 196 mask_irq(int irq)
 197 {
 198         int cpu;
 199
 200         for (cpu = 0; cpu < NR_CPUS; cpu++)
 201                 block_irq(irq, cpu);
 202 }
 203
 204 void
 205 unmask_irq(int irq)
 206 {
 207         unblock_irq(irq, irq_cpu(irq));
 208 }
 209
 210
 211 static unsigned int startup_crisv32_irq(unsigned int irq)
 212 {
 213         unmask_irq(irq);
 214         return 0;
 215 }
 216
 217 static void shutdown_crisv32_irq(unsigned int irq)
 218 {
 219         mask_irq(irq);
 220 }
 221
 222 static void enable_crisv32_irq(unsigned int irq)
 223 {
 224         unmask_irq(irq);
 225 }
 226
 227 static void disable_crisv32_irq(unsigned int irq)
 228 {
 229         mask_irq(irq);
 230 }
 231
 232 static void ack_crisv32_irq(unsigned int irq)
 233 {
 234 }
 235
 236 static void end_crisv32_irq(unsigned int irq)
 237 {
 238 }
 239
 240 void set_affinity_crisv32_irq(unsigned int irq, cpumask_t dest)
 241 {
 242         unsigned long flags;
 243         spin_lock_irqsave(&irq_lock, flags);
 244         irq_allocations[irq - FIRST_IRQ].mask = dest;
 245         spin_unlock_irqrestore(&irq_lock, flags);
 246 }
 247
 248 static struct hw_interrupt_type crisv32_irq_type = {
 249         .typename =    "CRISv32",
 250         .startup =     startup_crisv32_irq,
 251         .shutdown =    shutdown_crisv32_irq,
 252         .enable =      enable_crisv32_irq,
 253         .disable =     disable_crisv32_irq,
 254         .ack =         ack_crisv32_irq,
 255         .end =         end_crisv32_irq,
 256         .set_affinity = set_affinity_crisv32_irq
 257 };
 258
 259 void
 260 set_exception_vector(int n, irqvectptr addr)
 261 {
 262         etrax_irv->v[n] = (irqvectptr) addr;
 263 }
 264
 265 extern void do_IRQ(int irq, struct pt_regs * regs);
 266
 267 void
 268 crisv32_do_IRQ(int irq, int block, struct pt_regs* regs)
 269 {
 270         /* Interrupts that may not be moved to another CPU and
 271          * are IRQF_DISABLED may skip blocking. This is currently
 272          * only valid for the timer IRQ and the IPI and is used
 273          * for the timer interrupt to avoid watchdog starvation.
 274          */
 275         if (!block) {
 276                 do_IRQ(irq, regs);
 277                 return;
 278         }
 279
 280         block_irq(irq, smp_processor_id());
 281         do_IRQ(irq, regs);
 282
 283         unblock_irq(irq, irq_cpu(irq));
 284 }
 285
 286 /* If multiple interrupts occur simultaneously we get a multiple
 287  * interrupt from the CPU and software has to sort out which
 288  * interrupts that happened. There are two special cases here:
 289  *
 290  * 1. Timer interrupts may never be blocked because of the
 291  *    watchdog (refer to comment in include/asr/arch/irq.h)
 292  * 2. GDB serial port IRQs are unhandled here and will be handled
 293  *    as a single IRQ when it strikes again because the GDB
 294  *    stubb wants to save the registers in its own fashion.
 295  */
 296 void
 297 crisv32_do_multiple(struct pt_regs* regs)
 298 {
 299         int cpu;
 300         int mask;
 301         int masked;
 302         int bit;
 303
 304         cpu = smp_processor_id();
 305
 306         /* An extra irq_enter here to prevent softIRQs to run after
 307          * each do_IRQ. This will decrease the interrupt latency.
 308          */
 309         irq_enter();
 310
 311         /* Get which IRQs that happened. */
 312         masked = REG_RD_INT(intr_vect, irq_regs[cpu], r_masked_vect);
 313
 314         /* Calculate new IRQ mask with these IRQs disabled. */
 315         mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
 316         mask &= ~masked;
 317
 318         /* Timer IRQ is never masked */
 319         if (masked & TIMER_MASK)
 320                 mask |= TIMER_MASK;
 321
 322         /* Block all the IRQs */
 323         REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask);
 324
 325         /* Check for timer IRQ and handle it special. */
 326         if (masked & TIMER_MASK) {
 327                 masked &= ~TIMER_MASK;
 328                 do_IRQ(TIMER_INTR_VECT, regs);
 329         }
 330
 331 #ifdef IGNORE_MASK
 332         /* Remove IRQs that can't be handled as multiple. */
 333         masked &= ~IGNORE_MASK;
 334 #endif
 335
 336         /* Handle the rest of the IRQs. */
 337         for (bit = 0; bit < 32; bit++)
 338         {
 339                 if (masked & (1 << bit))
 340                         do_IRQ(bit + FIRST_IRQ, regs);
 341         }
 342
 343         /* Unblock all the IRQs. */
 344         mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
 345         mask |= masked;
 346         REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask);
 347
 348         /* This irq_exit() will trigger the soft IRQs. */
 349         irq_exit();
 350 }
 351
 352 /*
 353  * This is called by start_kernel. It fixes the IRQ masks and setup the
 354  * interrupt vector table to point to bad_interrupt pointers.
 355  */
 356 void __init
 357 init_IRQ(void)
 358 {
 359         int i;
 360         int j;
 361         reg_intr_vect_rw_mask vect_mask = {0};
 362
 363         /* Clear all interrupts masks. */
 364         REG_WR(intr_vect, regi_irq, rw_mask, vect_mask);
 365
 366         for (i = 0; i < 256; i++)
 367                 etrax_irv->v[i] = weird_irq;
 368
 369         /* Point all IRQs to bad handlers. */
 370         for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
 371                 irq_desc[j].chip = &crisv32_irq_type;
 372                 set_exception_vector(i, interrupt[j]);
 373         }
 374
 375         /* Mark Timer and IPI IRQs as CPU local */
 376         irq_allocations[TIMER_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
 377         irq_desc[TIMER_INTR_VECT].status |= IRQ_PER_CPU;
 378         irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
 379         irq_desc[IPI_INTR_VECT].status |= IRQ_PER_CPU;
 380
 381         set_exception_vector(0x00, nmi_interrupt);
 382         set_exception_vector(0x30, multiple_interrupt);
 383
 384         /* Set up handler for various MMU bus faults. */
 385         set_exception_vector(0x04, i_mmu_refill);
 386         set_exception_vector(0x05, i_mmu_invalid);
 387         set_exception_vector(0x06, i_mmu_access);
 388         set_exception_vector(0x07, i_mmu_execute);
 389         set_exception_vector(0x08, d_mmu_refill);
 390         set_exception_vector(0x09, d_mmu_invalid);
 391         set_exception_vector(0x0a, d_mmu_access);
 392         set_exception_vector(0x0b, d_mmu_write);
 393
 394         /* The system-call trap is reached by "break 13". */
 395         set_exception_vector(0x1d, system_call);
 396
 397         /* Exception handlers for debugging, both user-mode and kernel-mode. */
 398
 399         /* Break 8. */
 400         set_exception_vector(0x18, gdb_handle_exception);
 401         /* Hardware single step. */
 402         set_exception_vector(0x3, gdb_handle_exception);
 403         /* Hardware breakpoint. */
 404         set_exception_vector(0xc, gdb_handle_exception);
 405
 406 #ifdef CONFIG_ETRAX_KGDB
 407         kgdb_init();
 408         /* Everything is set up; now trap the kernel. */
 409         breakpoint();
 410 #endif
 411 }
 412