4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
15 * 3. Handle MMC errors better
19 #include <linux/dma-mapping.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/card.h>
22 #include <linux/mmc/core.h>
23 #include <linux/mmc/mmc.h>
24 #include <linux/mmc/sdio.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/mmc/sh_mmcif.h>
30 #define DRIVER_NAME "sh_mmcif"
31 #define DRIVER_VERSION "2010-04-28"
34 #define CMD_MASK 0x3f000000
35 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
36 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
37 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
38 #define CMD_SET_RBSY (1 << 21) /* R1b */
39 #define CMD_SET_CCSEN (1 << 20)
40 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
41 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
42 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
43 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
44 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
45 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
46 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
47 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
48 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
49 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
50 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
51 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
52 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
53 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
54 #define CMD_SET_CCSH (1 << 5)
55 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
56 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
57 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
60 #define CMD_CTRL_BREAK (1 << 0)
63 #define BLOCK_SIZE_MASK 0x0000ffff
66 #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
67 #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
68 #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
69 #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
70 #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
71 (1 << 9) | (1 << 8)) /* resp busy timeout */
72 #define SRWDTO_29 ((1 << 7) | (1 << 6) | \
73 (1 << 5) | (1 << 4)) /* read/write timeout */
74 #define SCCSTO_29 ((1 << 3) | (1 << 2) | \
75 (1 << 1) | (1 << 0)) /* ccs timeout */
78 #define BUF_ACC_DMAWEN (1 << 25)
79 #define BUF_ACC_DMAREN (1 << 24)
80 #define BUF_ACC_BUSW_32 (0 << 17)
81 #define BUF_ACC_BUSW_16 (1 << 17)
82 #define BUF_ACC_ATYP (1 << 16)
85 #define INT_CCSDE (1 << 29)
86 #define INT_CMD12DRE (1 << 26)
87 #define INT_CMD12RBE (1 << 25)
88 #define INT_CMD12CRE (1 << 24)
89 #define INT_DTRANE (1 << 23)
90 #define INT_BUFRE (1 << 22)
91 #define INT_BUFWEN (1 << 21)
92 #define INT_BUFREN (1 << 20)
93 #define INT_CCSRCV (1 << 19)
94 #define INT_RBSYE (1 << 17)
95 #define INT_CRSPE (1 << 16)
96 #define INT_CMDVIO (1 << 15)
97 #define INT_BUFVIO (1 << 14)
98 #define INT_WDATERR (1 << 11)
99 #define INT_RDATERR (1 << 10)
100 #define INT_RIDXERR (1 << 9)
101 #define INT_RSPERR (1 << 8)
102 #define INT_CCSTO (1 << 5)
103 #define INT_CRCSTO (1 << 4)
104 #define INT_WDATTO (1 << 3)
105 #define INT_RDATTO (1 << 2)
106 #define INT_RBSYTO (1 << 1)
107 #define INT_RSPTO (1 << 0)
108 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
109 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
110 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
111 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
114 #define MASK_ALL 0x00000000
115 #define MASK_MCCSDE (1 << 29)
116 #define MASK_MCMD12DRE (1 << 26)
117 #define MASK_MCMD12RBE (1 << 25)
118 #define MASK_MCMD12CRE (1 << 24)
119 #define MASK_MDTRANE (1 << 23)
120 #define MASK_MBUFRE (1 << 22)
121 #define MASK_MBUFWEN (1 << 21)
122 #define MASK_MBUFREN (1 << 20)
123 #define MASK_MCCSRCV (1 << 19)
124 #define MASK_MRBSYE (1 << 17)
125 #define MASK_MCRSPE (1 << 16)
126 #define MASK_MCMDVIO (1 << 15)
127 #define MASK_MBUFVIO (1 << 14)
128 #define MASK_MWDATERR (1 << 11)
129 #define MASK_MRDATERR (1 << 10)
130 #define MASK_MRIDXERR (1 << 9)
131 #define MASK_MRSPERR (1 << 8)
132 #define MASK_MCCSTO (1 << 5)
133 #define MASK_MCRCSTO (1 << 4)
134 #define MASK_MWDATTO (1 << 3)
135 #define MASK_MRDATTO (1 << 2)
136 #define MASK_MRBSYTO (1 << 1)
137 #define MASK_MRSPTO (1 << 0)
140 #define STS1_CMDSEQ (1 << 31)
143 #define STS2_CRCSTE (1 << 31)
144 #define STS2_CRC16E (1 << 30)
145 #define STS2_AC12CRCE (1 << 29)
146 #define STS2_RSPCRC7E (1 << 28)
147 #define STS2_CRCSTEBE (1 << 27)
148 #define STS2_RDATEBE (1 << 26)
149 #define STS2_AC12REBE (1 << 25)
150 #define STS2_RSPEBE (1 << 24)
151 #define STS2_AC12IDXE (1 << 23)
152 #define STS2_RSPIDXE (1 << 22)
153 #define STS2_CCSTO (1 << 15)
154 #define STS2_RDATTO (1 << 14)
155 #define STS2_DATBSYTO (1 << 13)
156 #define STS2_CRCSTTO (1 << 12)
157 #define STS2_AC12BSYTO (1 << 11)
158 #define STS2_RSPBSYTO (1 << 10)
159 #define STS2_AC12RSPTO (1 << 9)
160 #define STS2_RSPTO (1 << 8)
161 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
162 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
163 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
164 STS2_DATBSYTO | STS2_CRCSTTO | \
165 STS2_AC12BSYTO | STS2_RSPBSYTO | \
166 STS2_AC12RSPTO | STS2_RSPTO)
169 #define SOFT_RST_ON (1 << 31)
170 #define SOFT_RST_OFF (0 << 31)
172 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
173 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */
174 #define CLKDEV_INIT 400000 /* 400 KHz */
176 struct sh_mmcif_host
{
177 struct mmc_host
*mmc
;
178 struct mmc_data
*data
;
179 struct mmc_command
*cmd
;
180 struct platform_device
*pd
;
188 wait_queue_head_t intr_wait
;
192 static inline void sh_mmcif_bitset(struct sh_mmcif_host
*host
,
193 unsigned int reg
, u32 val
)
195 writel(val
| readl(host
->addr
+ reg
), host
->addr
+ reg
);
198 static inline void sh_mmcif_bitclr(struct sh_mmcif_host
*host
,
199 unsigned int reg
, u32 val
)
201 writel(~val
& readl(host
->addr
+ reg
), host
->addr
+ reg
);
205 static void sh_mmcif_clock_control(struct sh_mmcif_host
*host
, unsigned int clk
)
207 struct sh_mmcif_plat_data
*p
= host
->pd
->dev
.platform_data
;
209 sh_mmcif_bitclr(host
, MMCIF_CE_CLK_CTRL
, CLK_ENABLE
);
210 sh_mmcif_bitclr(host
, MMCIF_CE_CLK_CTRL
, CLK_CLEAR
);
214 if (p
->sup_pclk
&& clk
== host
->clk
)
215 sh_mmcif_bitset(host
, MMCIF_CE_CLK_CTRL
, CLK_SUP_PCLK
);
217 sh_mmcif_bitset(host
, MMCIF_CE_CLK_CTRL
, CLK_CLEAR
&
218 (ilog2(__rounddown_pow_of_two(host
->clk
/ clk
)) << 16));
220 sh_mmcif_bitset(host
, MMCIF_CE_CLK_CTRL
, CLK_ENABLE
);
223 static void sh_mmcif_sync_reset(struct sh_mmcif_host
*host
)
227 tmp
= 0x010f0000 & sh_mmcif_readl(host
->addr
, MMCIF_CE_CLK_CTRL
);
229 sh_mmcif_writel(host
->addr
, MMCIF_CE_VERSION
, SOFT_RST_ON
);
230 sh_mmcif_writel(host
->addr
, MMCIF_CE_VERSION
, SOFT_RST_OFF
);
231 sh_mmcif_bitset(host
, MMCIF_CE_CLK_CTRL
, tmp
|
232 SRSPTO_256
| SRBSYTO_29
| SRWDTO_29
| SCCSTO_29
);
234 sh_mmcif_bitset(host
, MMCIF_CE_BUF_ACC
, BUF_ACC_ATYP
);
237 static int sh_mmcif_error_manage(struct sh_mmcif_host
*host
)
240 int ret
, timeout
= 10000000;
245 state1
= sh_mmcif_readl(host
->addr
, MMCIF_CE_HOST_STS1
);
246 state2
= sh_mmcif_readl(host
->addr
, MMCIF_CE_HOST_STS2
);
247 pr_debug("%s: ERR HOST_STS1 = %08x\n", DRIVER_NAME
, state1
);
248 pr_debug("%s: ERR HOST_STS2 = %08x\n", DRIVER_NAME
, state2
);
250 if (state1
& STS1_CMDSEQ
) {
251 sh_mmcif_bitset(host
, MMCIF_CE_CMD_CTRL
, CMD_CTRL_BREAK
);
252 sh_mmcif_bitset(host
, MMCIF_CE_CMD_CTRL
, ~CMD_CTRL_BREAK
);
256 pr_err(DRIVER_NAME
": Forceed end of " \
257 "command sequence timeout err\n");
260 if (!(sh_mmcif_readl(host
->addr
, MMCIF_CE_HOST_STS1
)
265 sh_mmcif_sync_reset(host
);
266 pr_debug(DRIVER_NAME
": Forced end of command sequence\n");
270 if (state2
& STS2_CRC_ERR
) {
271 pr_debug(DRIVER_NAME
": Happened CRC error\n");
273 } else if (state2
& STS2_TIMEOUT_ERR
) {
274 pr_debug(DRIVER_NAME
": Happened Timeout error\n");
277 pr_debug(DRIVER_NAME
": Happened End/Index error\n");
283 static int sh_mmcif_single_read(struct sh_mmcif_host
*host
,
284 struct mmc_request
*mrq
)
286 struct mmc_data
*data
= mrq
->data
;
288 u32 blocksize
, i
, *p
= sg_virt(data
->sg
);
292 /* buf read enable */
293 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFREN
);
294 time
= wait_event_interruptible_timeout(host
->intr_wait
,
295 host
->wait_int
== 1 ||
296 host
->sd_error
== 1, host
->timeout
);
297 if (host
->wait_int
!= 1 && (time
== 0 || host
->sd_error
!= 0))
298 return sh_mmcif_error_manage(host
);
301 blocksize
= (BLOCK_SIZE_MASK
&
302 sh_mmcif_readl(host
->addr
, MMCIF_CE_BLOCK_SET
)) + 3;
303 for (i
= 0; i
< blocksize
/ 4; i
++)
304 *p
++ = sh_mmcif_readl(host
->addr
, MMCIF_CE_DATA
);
306 /* buffer read end */
307 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFRE
);
308 time
= wait_event_interruptible_timeout(host
->intr_wait
,
309 host
->wait_int
== 1 ||
310 host
->sd_error
== 1, host
->timeout
);
311 if (host
->wait_int
!= 1 && (time
== 0 || host
->sd_error
!= 0))
312 return sh_mmcif_error_manage(host
);
318 static int sh_mmcif_multi_read(struct sh_mmcif_host
*host
,
319 struct mmc_request
*mrq
)
321 struct mmc_data
*data
= mrq
->data
;
323 u32 blocksize
, i
, j
, sec
, *p
;
325 blocksize
= BLOCK_SIZE_MASK
& sh_mmcif_readl(host
->addr
,
327 for (j
= 0; j
< data
->sg_len
; j
++) {
328 p
= sg_virt(data
->sg
);
330 for (sec
= 0; sec
< data
->sg
->length
/ blocksize
; sec
++) {
331 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFREN
);
332 /* buf read enable */
333 time
= wait_event_interruptible_timeout(host
->intr_wait
,
334 host
->wait_int
== 1 ||
335 host
->sd_error
== 1, host
->timeout
);
337 if (host
->wait_int
!= 1 &&
338 (time
== 0 || host
->sd_error
!= 0))
339 return sh_mmcif_error_manage(host
);
342 for (i
= 0; i
< blocksize
/ 4; i
++)
343 *p
++ = sh_mmcif_readl(host
->addr
,
346 if (j
< data
->sg_len
- 1)
352 static int sh_mmcif_single_write(struct sh_mmcif_host
*host
,
353 struct mmc_request
*mrq
)
355 struct mmc_data
*data
= mrq
->data
;
357 u32 blocksize
, i
, *p
= sg_virt(data
->sg
);
360 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFWEN
);
362 /* buf write enable */
363 time
= wait_event_interruptible_timeout(host
->intr_wait
,
364 host
->wait_int
== 1 ||
365 host
->sd_error
== 1, host
->timeout
);
366 if (host
->wait_int
!= 1 && (time
== 0 || host
->sd_error
!= 0))
367 return sh_mmcif_error_manage(host
);
370 blocksize
= (BLOCK_SIZE_MASK
&
371 sh_mmcif_readl(host
->addr
, MMCIF_CE_BLOCK_SET
)) + 3;
372 for (i
= 0; i
< blocksize
/ 4; i
++)
373 sh_mmcif_writel(host
->addr
, MMCIF_CE_DATA
, *p
++);
375 /* buffer write end */
376 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MDTRANE
);
378 time
= wait_event_interruptible_timeout(host
->intr_wait
,
379 host
->wait_int
== 1 ||
380 host
->sd_error
== 1, host
->timeout
);
381 if (host
->wait_int
!= 1 && (time
== 0 || host
->sd_error
!= 0))
382 return sh_mmcif_error_manage(host
);
388 static int sh_mmcif_multi_write(struct sh_mmcif_host
*host
,
389 struct mmc_request
*mrq
)
391 struct mmc_data
*data
= mrq
->data
;
393 u32 i
, sec
, j
, blocksize
, *p
;
395 blocksize
= BLOCK_SIZE_MASK
& sh_mmcif_readl(host
->addr
,
398 for (j
= 0; j
< data
->sg_len
; j
++) {
399 p
= sg_virt(data
->sg
);
401 for (sec
= 0; sec
< data
->sg
->length
/ blocksize
; sec
++) {
402 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFWEN
);
403 /* buf write enable*/
404 time
= wait_event_interruptible_timeout(host
->intr_wait
,
405 host
->wait_int
== 1 ||
406 host
->sd_error
== 1, host
->timeout
);
408 if (host
->wait_int
!= 1 &&
409 (time
== 0 || host
->sd_error
!= 0))
410 return sh_mmcif_error_manage(host
);
413 for (i
= 0; i
< blocksize
/ 4; i
++)
414 sh_mmcif_writel(host
->addr
,
415 MMCIF_CE_DATA
, *p
++);
417 if (j
< data
->sg_len
- 1)
423 static void sh_mmcif_get_response(struct sh_mmcif_host
*host
,
424 struct mmc_command
*cmd
)
426 if (cmd
->flags
& MMC_RSP_136
) {
427 cmd
->resp
[0] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP3
);
428 cmd
->resp
[1] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP2
);
429 cmd
->resp
[2] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP1
);
430 cmd
->resp
[3] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP0
);
432 cmd
->resp
[0] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP0
);
435 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host
*host
,
436 struct mmc_command
*cmd
)
438 cmd
->resp
[0] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP_CMD12
);
441 static u32
sh_mmcif_set_cmd(struct sh_mmcif_host
*host
,
442 struct mmc_request
*mrq
, struct mmc_command
*cmd
, u32 opc
)
446 /* Response Type check */
447 switch (mmc_resp_type(cmd
)) {
449 tmp
|= CMD_SET_RTYP_NO
;
454 tmp
|= CMD_SET_RTYP_6B
;
457 tmp
|= CMD_SET_RTYP_17B
;
460 pr_err(DRIVER_NAME
": Not support type response.\n");
466 case MMC_STOP_TRANSMISSION
:
467 case MMC_SET_WRITE_PROT
:
468 case MMC_CLR_WRITE_PROT
:
477 switch (host
->bus_width
) {
478 case MMC_BUS_WIDTH_1
:
479 tmp
|= CMD_SET_DATW_1
;
481 case MMC_BUS_WIDTH_4
:
482 tmp
|= CMD_SET_DATW_4
;
484 case MMC_BUS_WIDTH_8
:
485 tmp
|= CMD_SET_DATW_8
;
488 pr_err(DRIVER_NAME
": Not support bus width.\n");
493 if (opc
== MMC_WRITE_BLOCK
|| opc
== MMC_WRITE_MULTIPLE_BLOCK
)
496 if (opc
== MMC_READ_MULTIPLE_BLOCK
|| opc
== MMC_WRITE_MULTIPLE_BLOCK
) {
497 tmp
|= CMD_SET_CMLTE
| CMD_SET_CMD12EN
;
498 sh_mmcif_bitset(host
, MMCIF_CE_BLOCK_SET
,
499 mrq
->data
->blocks
<< 16);
501 /* RIDXC[1:0] check bits */
502 if (opc
== MMC_SEND_OP_COND
|| opc
== MMC_ALL_SEND_CID
||
503 opc
== MMC_SEND_CSD
|| opc
== MMC_SEND_CID
)
504 tmp
|= CMD_SET_RIDXC_BITS
;
505 /* RCRC7C[1:0] check bits */
506 if (opc
== MMC_SEND_OP_COND
)
507 tmp
|= CMD_SET_CRC7C_BITS
;
508 /* RCRC7C[1:0] internal CRC7 */
509 if (opc
== MMC_ALL_SEND_CID
||
510 opc
== MMC_SEND_CSD
|| opc
== MMC_SEND_CID
)
511 tmp
|= CMD_SET_CRC7C_INTERNAL
;
513 return opc
= ((opc
<< 24) | tmp
);
516 static u32
sh_mmcif_data_trans(struct sh_mmcif_host
*host
,
517 struct mmc_request
*mrq
, u32 opc
)
522 case MMC_READ_MULTIPLE_BLOCK
:
523 ret
= sh_mmcif_multi_read(host
, mrq
);
525 case MMC_WRITE_MULTIPLE_BLOCK
:
526 ret
= sh_mmcif_multi_write(host
, mrq
);
528 case MMC_WRITE_BLOCK
:
529 ret
= sh_mmcif_single_write(host
, mrq
);
531 case MMC_READ_SINGLE_BLOCK
:
532 case MMC_SEND_EXT_CSD
:
533 ret
= sh_mmcif_single_read(host
, mrq
);
536 pr_err(DRIVER_NAME
": NOT SUPPORT CMD = d'%08d\n", opc
);
543 static void sh_mmcif_start_cmd(struct sh_mmcif_host
*host
,
544 struct mmc_request
*mrq
, struct mmc_command
*cmd
)
547 int ret
= 0, mask
= 0;
548 u32 opc
= cmd
->opcode
;
553 /* respons busy check */
555 case MMC_STOP_TRANSMISSION
:
556 case MMC_SET_WRITE_PROT
:
557 case MMC_CLR_WRITE_PROT
:
566 mask
|= MASK_MCMDVIO
| MASK_MBUFVIO
| MASK_MWDATERR
|
567 MASK_MRDATERR
| MASK_MRIDXERR
| MASK_MRSPERR
|
568 MASK_MCCSTO
| MASK_MCRCSTO
| MASK_MWDATTO
|
569 MASK_MRDATTO
| MASK_MRBSYTO
| MASK_MRSPTO
;
572 sh_mmcif_writel(host
->addr
, MMCIF_CE_BLOCK_SET
, 0);
573 sh_mmcif_writel(host
->addr
, MMCIF_CE_BLOCK_SET
,
576 opc
= sh_mmcif_set_cmd(host
, mrq
, cmd
, opc
);
578 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, 0xD80430C0);
579 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT_MASK
, mask
);
581 sh_mmcif_writel(host
->addr
, MMCIF_CE_ARG
, cmd
->arg
);
584 sh_mmcif_writel(host
->addr
, MMCIF_CE_CMD_SET
, opc
);
586 time
= wait_event_interruptible_timeout(host
->intr_wait
,
587 host
->wait_int
== 1 || host
->sd_error
== 1, host
->timeout
);
588 if (host
->wait_int
!= 1 && time
== 0) {
589 cmd
->error
= sh_mmcif_error_manage(host
);
592 if (host
->sd_error
) {
593 switch (cmd
->opcode
) {
594 case MMC_ALL_SEND_CID
:
595 case MMC_SELECT_CARD
:
597 cmd
->error
= -ETIMEDOUT
;
600 pr_debug("%s: Cmd(d'%d) err\n",
601 DRIVER_NAME
, cmd
->opcode
);
602 cmd
->error
= sh_mmcif_error_manage(host
);
609 if (!(cmd
->flags
& MMC_RSP_PRESENT
)) {
614 if (host
->wait_int
== 1) {
615 sh_mmcif_get_response(host
, cmd
);
619 ret
= sh_mmcif_data_trans(host
, mrq
, cmd
->opcode
);
621 mrq
->data
->bytes_xfered
= 0;
623 mrq
->data
->bytes_xfered
=
624 mrq
->data
->blocks
* mrq
->data
->blksz
;
629 static void sh_mmcif_stop_cmd(struct sh_mmcif_host
*host
,
630 struct mmc_request
*mrq
, struct mmc_command
*cmd
)
634 if (mrq
->cmd
->opcode
== MMC_READ_MULTIPLE_BLOCK
)
635 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MCMD12DRE
);
636 else if (mrq
->cmd
->opcode
== MMC_WRITE_MULTIPLE_BLOCK
)
637 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MCMD12RBE
);
639 pr_err(DRIVER_NAME
": not support stop cmd\n");
640 cmd
->error
= sh_mmcif_error_manage(host
);
644 time
= wait_event_interruptible_timeout(host
->intr_wait
,
645 host
->wait_int
== 1 ||
646 host
->sd_error
== 1, host
->timeout
);
647 if (host
->wait_int
!= 1 && (time
== 0 || host
->sd_error
!= 0)) {
648 cmd
->error
= sh_mmcif_error_manage(host
);
651 sh_mmcif_get_cmd12response(host
, cmd
);
656 static void sh_mmcif_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
658 struct sh_mmcif_host
*host
= mmc_priv(mmc
);
660 switch (mrq
->cmd
->opcode
) {
661 /* MMCIF does not support SD/SDIO command */
662 case SD_IO_SEND_OP_COND
:
664 mrq
->cmd
->error
= -ETIMEDOUT
;
665 mmc_request_done(mmc
, mrq
);
667 case MMC_SEND_EXT_CSD
: /* = SD_SEND_IF_COND (8) */
669 /* send_if_cond cmd (not support) */
670 mrq
->cmd
->error
= -ETIMEDOUT
;
671 mmc_request_done(mmc
, mrq
);
678 host
->data
= mrq
->data
;
679 sh_mmcif_start_cmd(host
, mrq
, mrq
->cmd
);
682 if (mrq
->cmd
->error
!= 0) {
683 mmc_request_done(mmc
, mrq
);
687 sh_mmcif_stop_cmd(host
, mrq
, mrq
->stop
);
688 mmc_request_done(mmc
, mrq
);
691 static void sh_mmcif_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
693 struct sh_mmcif_host
*host
= mmc_priv(mmc
);
694 struct sh_mmcif_plat_data
*p
= host
->pd
->dev
.platform_data
;
696 if (ios
->power_mode
== MMC_POWER_OFF
) {
698 sh_mmcif_clock_control(host
, 0);
700 p
->down_pwr(host
->pd
);
702 } else if (ios
->power_mode
== MMC_POWER_UP
) {
704 p
->set_pwr(host
->pd
, ios
->power_mode
);
708 sh_mmcif_clock_control(host
, ios
->clock
);
710 host
->bus_width
= ios
->bus_width
;
713 static struct mmc_host_ops sh_mmcif_ops
= {
714 .request
= sh_mmcif_request
,
715 .set_ios
= sh_mmcif_set_ios
,
718 static void sh_mmcif_detect(struct mmc_host
*mmc
)
720 mmc_detect_change(mmc
, 0);
723 static irqreturn_t
sh_mmcif_intr(int irq
, void *dev_id
)
725 struct sh_mmcif_host
*host
= dev_id
;
729 state
= sh_mmcif_readl(host
->addr
, MMCIF_CE_INT
);
731 if (state
& INT_RBSYE
) {
732 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
,
733 ~(INT_RBSYE
| INT_CRSPE
));
734 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MRBSYE
);
735 } else if (state
& INT_CRSPE
) {
736 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~INT_CRSPE
);
737 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MCRSPE
);
738 } else if (state
& INT_BUFREN
) {
739 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~INT_BUFREN
);
740 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MBUFREN
);
741 } else if (state
& INT_BUFWEN
) {
742 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~INT_BUFWEN
);
743 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MBUFWEN
);
744 } else if (state
& INT_CMD12DRE
) {
745 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
,
746 ~(INT_CMD12DRE
| INT_CMD12RBE
|
747 INT_CMD12CRE
| INT_BUFRE
));
748 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MCMD12DRE
);
749 } else if (state
& INT_BUFRE
) {
750 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~INT_BUFRE
);
751 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MBUFRE
);
752 } else if (state
& INT_DTRANE
) {
753 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~INT_DTRANE
);
754 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MDTRANE
);
755 } else if (state
& INT_CMD12RBE
) {
756 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
,
757 ~(INT_CMD12RBE
| INT_CMD12CRE
));
758 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MCMD12RBE
);
759 } else if (state
& INT_ERR_STS
) {
761 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~state
);
762 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, state
);
765 pr_debug("%s: Not support int\n", DRIVER_NAME
);
766 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~state
);
767 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, state
);
772 pr_debug("%s: int err state = %08x\n", DRIVER_NAME
, state
);
775 wake_up(&host
->intr_wait
);
780 static int __devinit
sh_mmcif_probe(struct platform_device
*pdev
)
783 struct mmc_host
*mmc
;
784 struct sh_mmcif_host
*host
= NULL
;
785 struct sh_mmcif_plat_data
*pd
= NULL
;
786 struct resource
*res
;
790 irq
[0] = platform_get_irq(pdev
, 0);
791 irq
[1] = platform_get_irq(pdev
, 1);
792 if (irq
[0] < 0 || irq
[1] < 0) {
793 pr_err(DRIVER_NAME
": Get irq error\n");
796 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
798 dev_err(&pdev
->dev
, "platform_get_resource error.\n");
801 reg
= ioremap(res
->start
, resource_size(res
));
803 dev_err(&pdev
->dev
, "ioremap error.\n");
806 pd
= (struct sh_mmcif_plat_data
*)(pdev
->dev
.platform_data
);
808 dev_err(&pdev
->dev
, "sh_mmcif plat data error.\n");
812 mmc
= mmc_alloc_host(sizeof(struct sh_mmcif_host
), &pdev
->dev
);
817 host
= mmc_priv(mmc
);
820 host
->timeout
= 1000;
822 snprintf(clk_name
, sizeof(clk_name
), "mmc%d", pdev
->id
);
823 host
->hclk
= clk_get(&pdev
->dev
, clk_name
);
824 if (IS_ERR(host
->hclk
)) {
825 dev_err(&pdev
->dev
, "cannot get clock \"%s\"\n", clk_name
);
826 ret
= PTR_ERR(host
->hclk
);
829 clk_enable(host
->hclk
);
830 host
->clk
= clk_get_rate(host
->hclk
);
833 init_waitqueue_head(&host
->intr_wait
);
835 mmc
->ops
= &sh_mmcif_ops
;
836 mmc
->f_max
= host
->clk
;
837 /* close to 400KHz */
838 if (mmc
->f_max
< 51200000)
839 mmc
->f_min
= mmc
->f_max
/ 128;
840 else if (mmc
->f_max
< 102400000)
841 mmc
->f_min
= mmc
->f_max
/ 256;
843 mmc
->f_min
= mmc
->f_max
/ 512;
845 mmc
->ocr_avail
= pd
->ocr
;
846 mmc
->caps
= MMC_CAP_MMC_HIGHSPEED
;
848 mmc
->caps
|= pd
->caps
;
849 mmc
->max_phys_segs
= 128;
850 mmc
->max_hw_segs
= 128;
851 mmc
->max_blk_size
= 512;
852 mmc
->max_blk_count
= 65535;
853 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
854 mmc
->max_seg_size
= mmc
->max_req_size
;
856 sh_mmcif_sync_reset(host
);
857 platform_set_drvdata(pdev
, host
);
860 ret
= request_irq(irq
[0], sh_mmcif_intr
, 0, "sh_mmc:error", host
);
862 pr_err(DRIVER_NAME
": request_irq error (sh_mmc:error)\n");
865 ret
= request_irq(irq
[1], sh_mmcif_intr
, 0, "sh_mmc:int", host
);
867 free_irq(irq
[0], host
);
868 pr_err(DRIVER_NAME
": request_irq error (sh_mmc:int)\n");
872 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT_MASK
, MASK_ALL
);
873 sh_mmcif_detect(host
->mmc
);
875 pr_info("%s: driver version %s\n", DRIVER_NAME
, DRIVER_VERSION
);
876 pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME
,
877 sh_mmcif_readl(host
->addr
, MMCIF_CE_VERSION
) & 0x0000ffff);
881 clk_disable(host
->hclk
);
890 static int __devexit
sh_mmcif_remove(struct platform_device
*pdev
)
892 struct sh_mmcif_host
*host
= platform_get_drvdata(pdev
);
895 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT_MASK
, MASK_ALL
);
897 irq
[0] = platform_get_irq(pdev
, 0);
898 irq
[1] = platform_get_irq(pdev
, 1);
903 platform_set_drvdata(pdev
, NULL
);
904 mmc_remove_host(host
->mmc
);
906 free_irq(irq
[0], host
);
907 free_irq(irq
[1], host
);
909 clk_disable(host
->hclk
);
910 mmc_free_host(host
->mmc
);
915 static struct platform_driver sh_mmcif_driver
= {
916 .probe
= sh_mmcif_probe
,
917 .remove
= sh_mmcif_remove
,
923 static int __init
sh_mmcif_init(void)
925 return platform_driver_register(&sh_mmcif_driver
);
928 static void __exit
sh_mmcif_exit(void)
930 platform_driver_unregister(&sh_mmcif_driver
);
933 module_init(sh_mmcif_init
);
934 module_exit(sh_mmcif_exit
);
937 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
938 MODULE_LICENSE("GPL");
939 MODULE_ALIAS(DRIVER_NAME
);
940 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");