drivers/staging/benet/doorbells.h

   1 /*
   2  * Copyright (C) 2005 - 2008 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17 /*
  18  * Autogenerated by srcgen version: 0127
  19  */
  20 #ifndef __doorbells_amap_h__
  21 #define __doorbells_amap_h__
  22
  23 /* The TX/RDMA send queue doorbell. */
  24 struct BE_SQ_DB_AMAP {
  25         u8 cid[11];             /* DWORD 0 */
  26         u8 rsvd0[5];    /* DWORD 0 */
  27         u8 numPosted[14];       /* DWORD 0 */
  28         u8 rsvd1[2];    /* DWORD 0 */
  29 } __packed;
  30 struct SQ_DB_AMAP {
  31         u32 dw[1];
  32 };
  33
  34 /* The receive queue doorbell. */
  35 struct BE_RQ_DB_AMAP {
  36         u8 rq[10];              /* DWORD 0 */
  37         u8 rsvd0[13];   /* DWORD 0 */
  38         u8 Invalidate;  /* DWORD 0 */
  39         u8 numPosted[8];        /* DWORD 0 */
  40 } __packed;
  41 struct RQ_DB_AMAP {
  42         u32 dw[1];
  43 };
  44
  45 /*
  46  * The CQ/EQ doorbell. Software MUST set reserved fields in this
  47  * descriptor to zero, otherwise (CEV) hardware will not execute the
  48  * doorbell (flagging a bad_db_qid error instead).
  49  */
  50 struct BE_CQ_DB_AMAP {
  51         u8 qid[10];             /* DWORD 0 */
  52         u8 rsvd0[4];    /* DWORD 0 */
  53         u8 rearm;               /* DWORD 0 */
  54         u8 event;               /* DWORD 0 */
  55         u8 num_popped[13];      /* DWORD 0 */
  56         u8 rsvd1[3];    /* DWORD 0 */
  57 } __packed;
  58 struct CQ_DB_AMAP {
  59         u32 dw[1];
  60 };
  61
  62 struct BE_TPM_RQ_DB_AMAP {
  63         u8 qid[10];             /* DWORD 0 */
  64         u8 rsvd0[6];    /* DWORD 0 */
  65         u8 numPosted[11];       /* DWORD 0 */
  66         u8 mss_cnt[5];  /* DWORD 0 */
  67 } __packed;
  68 struct TPM_RQ_DB_AMAP {
  69         u32 dw[1];
  70 };
  71
  72 /*
  73  * Post WRB Queue Doorbell Register used by the host Storage stack
  74  * to notify the controller of a posted Work Request Block
  75  */
  76 struct BE_WRB_POST_DB_AMAP {
  77         u8 wrb_cid[10]; /* DWORD 0 */
  78         u8 rsvd0[6];    /* DWORD 0 */
  79         u8 wrb_index[8];        /* DWORD 0 */
  80         u8 numberPosted[8];     /* DWORD 0 */
  81 } __packed;
  82 struct WRB_POST_DB_AMAP {
  83         u32 dw[1];
  84 };
  85
  86 /*
  87  * Update Default PDU Queue Doorbell Register used to communicate
  88  * to the controller that the driver has stopped processing the queue
  89  * and where in the queue it stopped, this is
  90  * a CQ Entry Type. Used by storage driver.
  91  */
  92 struct BE_DEFAULT_PDU_DB_AMAP {
  93         u8 qid[10];             /* DWORD 0 */
  94         u8 rsvd0[4];    /* DWORD 0 */
  95         u8 rearm;               /* DWORD 0 */
  96         u8 event;               /* DWORD 0 */
  97         u8 cqproc[14];  /* DWORD 0 */
  98         u8 rsvd1[2];    /* DWORD 0 */
  99 } __packed;
 100 struct DEFAULT_PDU_DB_AMAP {
 101         u32 dw[1];
 102 };
 103
 104 /* Management Command and Controller default fragment ring */
 105 struct BE_MCC_DB_AMAP {
 106         u8 rid[11];             /* DWORD 0 */
 107         u8 rsvd0[5];    /* DWORD 0 */
 108         u8 numPosted[14];       /* DWORD 0 */
 109         u8 rsvd1[2];    /* DWORD 0 */
 110 } __packed;
 111 struct MCC_DB_AMAP {
 112         u32 dw[1];
 113 };
 114
 115 /*
 116  * Used for bootstrapping the Host interface. This register is
 117  * used for driver communication with the MPU when no MCC Rings exist.
 118  * The software must write this register twice to post any MCC
 119  * command. First, it writes the register with hi=1 and the upper bits of
 120  * the  physical address for the MCC_MAILBOX structure.  Software must poll
 121  * the ready bit until this is acknowledged.  Then, sotware writes the
 122  * register with hi=0 with the lower bits in the address.  It must
 123  * poll the ready bit until the MCC command is complete.  Upon completion,
 124  * the MCC_MAILBOX will contain a valid completion queue  entry.
 125  */
 126 struct BE_MPU_MAILBOX_DB_AMAP {
 127         u8 ready;               /* DWORD 0 */
 128         u8 hi;          /* DWORD 0 */
 129         u8 address[30]; /* DWORD 0 */
 130 } __packed;
 131 struct MPU_MAILBOX_DB_AMAP {
 132         u32 dw[1];
 133 };
 134
 135 /*
 136  *  This is the protection domain doorbell register map. Note that
 137  *  while this map shows doorbells for all Blade Engine supported
 138  *  protocols, not all of these may be valid in a given function or
 139  *  protection domain. It is the responsibility of the application
 140  *  accessing the doorbells to know which are valid. Each doorbell
 141  *  occupies 32 bytes of space, but unless otherwise specified,
 142  *  only the first 4 bytes should be written.  There are 32 instances
 143  *  of these doorbells for the host and 31 virtual machines respectively.
 144  *  The host and VMs will only map the doorbell pages belonging to its
 145  *  protection domain. It will not be able to touch the doorbells for
 146  *  another VM. The doorbells are the only registers directly accessible
 147  *  by a virtual machine. Similarly, there are 511 additional
 148  *  doorbells for RDMA protection domains. PD 0 for RDMA shares
 149  *  the same physical protection domain doorbell page as ETH/iSCSI.
 150  *
 151  */
 152 struct BE_PROTECTION_DOMAIN_DBMAP_AMAP {
 153         u8 rsvd0[512];  /* DWORD 0 */
 154         struct BE_SQ_DB_AMAP rdma_sq_db;
 155         u8 rsvd1[7][32];        /* DWORD 17 */
 156         struct BE_WRB_POST_DB_AMAP iscsi_wrb_post_db;
 157         u8 rsvd2[7][32];        /* DWORD 25 */
 158         struct BE_SQ_DB_AMAP etx_sq_db;
 159         u8 rsvd3[7][32];        /* DWORD 33 */
 160         struct BE_RQ_DB_AMAP rdma_rq_db;
 161         u8 rsvd4[7][32];        /* DWORD 41 */
 162         struct BE_DEFAULT_PDU_DB_AMAP iscsi_default_pdu_db;
 163         u8 rsvd5[7][32];        /* DWORD 49 */
 164         struct BE_TPM_RQ_DB_AMAP tpm_rq_db;
 165         u8 rsvd6[7][32];        /* DWORD 57 */
 166         struct BE_RQ_DB_AMAP erx_rq_db;
 167         u8 rsvd7[7][32];        /* DWORD 65 */
 168         struct BE_CQ_DB_AMAP cq_db;
 169         u8 rsvd8[7][32];        /* DWORD 73 */
 170         struct BE_MCC_DB_AMAP mpu_mcc_db;
 171         u8 rsvd9[7][32];        /* DWORD 81 */
 172         struct BE_MPU_MAILBOX_DB_AMAP mcc_bootstrap_db;
 173         u8 rsvd10[935][32];     /* DWORD 89 */
 174 } __packed;
 175 struct PROTECTION_DOMAIN_DBMAP_AMAP {
 176         u32 dw[1024];
 177 };
 178
 179 #endif /* __doorbells_amap_h__ */