2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
36 #define wrmsrl(msr, val) \
38 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39 (unsigned long)(val)); \
40 native_write_msr((msr), (u32)((u64)(val)), \
41 (u32)((u64)(val) >> 32)); \
46 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
49 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
51 unsigned long offset
, addr
= (unsigned long)from
;
52 int type
= in_nmi() ? KM_NMI
: KM_IRQ0
;
53 unsigned long size
, len
= 0;
59 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
63 offset
= addr
& (PAGE_SIZE
- 1);
64 size
= min(PAGE_SIZE
- offset
, n
- len
);
66 map
= kmap_atomic(page
, type
);
67 memcpy(to
, map
+offset
, size
);
68 kunmap_atomic(map
, type
);
80 struct event_constraint
{
82 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
91 int nb_id
; /* NorthBridge id */
92 int refcnt
; /* reference count */
93 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
94 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
97 #define MAX_LBR_ENTRIES 16
99 struct cpu_hw_events
{
101 * Generic x86 PMC bits
103 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
104 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
109 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
110 u64 tags
[X86_PMC_IDX_MAX
];
111 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
114 * Intel DebugStore bits
116 struct debug_store
*ds
;
124 struct perf_branch_stack lbr_stack
;
125 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
130 struct amd_nb
*amd_nb
;
133 #define __EVENT_CONSTRAINT(c, n, m, w) {\
134 { .idxmsk64 = (n) }, \
140 #define EVENT_CONSTRAINT(c, n, m) \
141 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
144 * Constraint on the Event code.
146 #define INTEL_EVENT_CONSTRAINT(c, n) \
147 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
150 * Constraint on the Event code + UMask + fixed-mask
152 * filter mask to validate fixed counter events.
153 * the following filters disqualify for fixed counters:
157 * The other filters are supported by fixed counters.
158 * The any-thread option is supported starting with v3.
160 #define FIXED_EVENT_CONSTRAINT(c, n) \
161 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
164 * Constraint on the Event code + UMask
166 #define PEBS_EVENT_CONSTRAINT(c, n) \
167 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
169 #define EVENT_CONSTRAINT_END \
170 EVENT_CONSTRAINT(0, 0, 0)
172 #define for_each_event_constraint(e, c) \
173 for ((e) = (c); (e)->cmask; (e)++)
175 union perf_capabilities
{
179 u64 pebs_arch_reg
: 1;
187 * struct x86_pmu - generic x86 pmu
191 * Generic x86 PMC bits
195 int (*handle_irq
)(struct pt_regs
*);
196 void (*disable_all
)(void);
197 void (*enable_all
)(int added
);
198 void (*enable
)(struct perf_event
*);
199 void (*disable
)(struct perf_event
*);
200 int (*hw_config
)(struct perf_event
*event
);
201 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
204 u64 (*event_map
)(int);
207 int num_counters_fixed
;
212 struct event_constraint
*
213 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
214 struct perf_event
*event
);
216 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
217 struct perf_event
*event
);
218 struct event_constraint
*event_constraints
;
219 void (*quirks
)(void);
221 int (*cpu_prepare
)(int cpu
);
222 void (*cpu_starting
)(int cpu
);
223 void (*cpu_dying
)(int cpu
);
224 void (*cpu_dead
)(int cpu
);
227 * Intel Arch Perfmon v2+
230 union perf_capabilities intel_cap
;
233 * Intel DebugStore bits
236 int pebs_record_size
;
237 void (*drain_pebs
)(struct pt_regs
*regs
);
238 struct event_constraint
*pebs_constraints
;
243 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
244 int lbr_nr
; /* hardware stack size */
247 static struct x86_pmu x86_pmu __read_mostly
;
249 static DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
253 static int x86_perf_event_set_period(struct perf_event
*event
);
256 * Generalized hw caching related hw_event table, filled
257 * in on a per model basis. A value of 0 means
258 * 'not supported', -1 means 'hw_event makes no sense on
259 * this CPU', any other value means the raw hw_event
263 #define C(x) PERF_COUNT_HW_CACHE_##x
265 static u64 __read_mostly hw_cache_event_ids
266 [PERF_COUNT_HW_CACHE_MAX
]
267 [PERF_COUNT_HW_CACHE_OP_MAX
]
268 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
271 * Propagate event elapsed time into the generic event.
272 * Can only be executed on the CPU where the event is active.
273 * Returns the delta events processed.
276 x86_perf_event_update(struct perf_event
*event
)
278 struct hw_perf_event
*hwc
= &event
->hw
;
279 int shift
= 64 - x86_pmu
.cntval_bits
;
280 u64 prev_raw_count
, new_raw_count
;
284 if (idx
== X86_PMC_IDX_FIXED_BTS
)
288 * Careful: an NMI might modify the previous event value.
290 * Our tactic to handle this is to first atomically read and
291 * exchange a new raw count - then add that new-prev delta
292 * count to the generic event atomically:
295 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
296 rdmsrl(hwc
->event_base
+ idx
, new_raw_count
);
298 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
299 new_raw_count
) != prev_raw_count
)
303 * Now we have the new raw value and have updated the prev
304 * timestamp already. We can now calculate the elapsed delta
305 * (event-)time and add that to the generic event.
307 * Careful, not all hw sign-extends above the physical width
310 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
313 atomic64_add(delta
, &event
->count
);
314 atomic64_sub(delta
, &hwc
->period_left
);
316 return new_raw_count
;
319 static atomic_t active_events
;
320 static DEFINE_MUTEX(pmc_reserve_mutex
);
322 #ifdef CONFIG_X86_LOCAL_APIC
324 static bool reserve_pmc_hardware(void)
328 if (nmi_watchdog
== NMI_LOCAL_APIC
)
329 disable_lapic_nmi_watchdog();
331 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
332 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
336 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
337 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
344 for (i
--; i
>= 0; i
--)
345 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
347 i
= x86_pmu
.num_counters
;
350 for (i
--; i
>= 0; i
--)
351 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
353 if (nmi_watchdog
== NMI_LOCAL_APIC
)
354 enable_lapic_nmi_watchdog();
359 static void release_pmc_hardware(void)
363 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
364 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
365 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
368 if (nmi_watchdog
== NMI_LOCAL_APIC
)
369 enable_lapic_nmi_watchdog();
374 static bool reserve_pmc_hardware(void) { return true; }
375 static void release_pmc_hardware(void) {}
379 static int reserve_ds_buffers(void);
380 static void release_ds_buffers(void);
382 static void hw_perf_event_destroy(struct perf_event
*event
)
384 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
385 release_pmc_hardware();
386 release_ds_buffers();
387 mutex_unlock(&pmc_reserve_mutex
);
391 static inline int x86_pmu_initialized(void)
393 return x86_pmu
.handle_irq
!= NULL
;
397 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event_attr
*attr
)
399 unsigned int cache_type
, cache_op
, cache_result
;
402 config
= attr
->config
;
404 cache_type
= (config
>> 0) & 0xff;
405 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
408 cache_op
= (config
>> 8) & 0xff;
409 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
412 cache_result
= (config
>> 16) & 0xff;
413 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
416 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
429 static int x86_setup_perfctr(struct perf_event
*event
);
431 static int x86_pmu_hw_config(struct perf_event
*event
)
435 * (keep 'enabled' bit clear for now)
437 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
440 * Count user and OS events unless requested not to
442 if (!event
->attr
.exclude_user
)
443 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
444 if (!event
->attr
.exclude_kernel
)
445 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
447 if (event
->attr
.type
== PERF_TYPE_RAW
)
448 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
454 * Setup the hardware configuration for a given attr_type
456 static int __hw_perf_event_init(struct perf_event
*event
)
460 if (!x86_pmu_initialized())
464 if (!atomic_inc_not_zero(&active_events
)) {
465 mutex_lock(&pmc_reserve_mutex
);
466 if (atomic_read(&active_events
) == 0) {
467 if (!reserve_pmc_hardware())
470 err
= reserve_ds_buffers();
472 release_pmc_hardware();
476 atomic_inc(&active_events
);
477 mutex_unlock(&pmc_reserve_mutex
);
482 event
->destroy
= hw_perf_event_destroy
;
485 event
->hw
.last_cpu
= -1;
486 event
->hw
.last_tag
= ~0ULL;
488 /* Processor specifics */
489 err
= x86_pmu
.hw_config(event
);
493 return x86_setup_perfctr(event
);
496 static int x86_setup_perfctr(struct perf_event
*event
)
498 struct perf_event_attr
*attr
= &event
->attr
;
499 struct hw_perf_event
*hwc
= &event
->hw
;
502 if (!hwc
->sample_period
) {
503 hwc
->sample_period
= x86_pmu
.max_period
;
504 hwc
->last_period
= hwc
->sample_period
;
505 atomic64_set(&hwc
->period_left
, hwc
->sample_period
);
508 * If we have a PMU initialized but no APIC
509 * interrupts, we cannot sample hardware
510 * events (user-space has to fall back and
511 * sample via a hrtimer based software event):
517 if (attr
->type
== PERF_TYPE_RAW
)
520 if (attr
->type
== PERF_TYPE_HW_CACHE
)
521 return set_ext_hw_attr(hwc
, attr
);
523 if (attr
->config
>= x86_pmu
.max_events
)
529 config
= x86_pmu
.event_map(attr
->config
);
540 if ((attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
) &&
541 (hwc
->sample_period
== 1)) {
542 /* BTS is not supported by this architecture. */
546 /* BTS is currently only allowed for user-mode. */
547 if (!attr
->exclude_kernel
)
551 hwc
->config
|= config
;
556 static void x86_pmu_disable_all(void)
558 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
561 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
564 if (!test_bit(idx
, cpuc
->active_mask
))
566 rdmsrl(x86_pmu
.eventsel
+ idx
, val
);
567 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
569 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
570 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
574 void hw_perf_disable(void)
576 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
578 if (!x86_pmu_initialized())
588 x86_pmu
.disable_all();
591 static void x86_pmu_enable_all(int added
)
593 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
596 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
597 struct perf_event
*event
= cpuc
->events
[idx
];
600 if (!test_bit(idx
, cpuc
->active_mask
))
603 val
= event
->hw
.config
;
604 val
|= ARCH_PERFMON_EVENTSEL_ENABLE
;
605 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
609 static const struct pmu pmu
;
611 static inline int is_x86_event(struct perf_event
*event
)
613 return event
->pmu
== &pmu
;
616 static int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
618 struct event_constraint
*c
, *constraints
[X86_PMC_IDX_MAX
];
619 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
620 int i
, j
, w
, wmax
, num
= 0;
621 struct hw_perf_event
*hwc
;
623 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
625 for (i
= 0; i
< n
; i
++) {
626 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
631 * fastpath, try to reuse previous register
633 for (i
= 0; i
< n
; i
++) {
634 hwc
= &cpuc
->event_list
[i
]->hw
;
641 /* constraint still honored */
642 if (!test_bit(hwc
->idx
, c
->idxmsk
))
645 /* not already used */
646 if (test_bit(hwc
->idx
, used_mask
))
649 __set_bit(hwc
->idx
, used_mask
);
651 assign
[i
] = hwc
->idx
;
660 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
663 * weight = number of possible counters
665 * 1 = most constrained, only works on one counter
666 * wmax = least constrained, works on any counter
668 * assign events to counters starting with most
669 * constrained events.
671 wmax
= x86_pmu
.num_counters
;
674 * when fixed event counters are present,
675 * wmax is incremented by 1 to account
676 * for one more choice
678 if (x86_pmu
.num_counters_fixed
)
681 for (w
= 1, num
= n
; num
&& w
<= wmax
; w
++) {
683 for (i
= 0; num
&& i
< n
; i
++) {
685 hwc
= &cpuc
->event_list
[i
]->hw
;
690 for_each_set_bit(j
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
691 if (!test_bit(j
, used_mask
))
695 if (j
== X86_PMC_IDX_MAX
)
698 __set_bit(j
, used_mask
);
707 * scheduling failed or is just a simulation,
708 * free resources if necessary
710 if (!assign
|| num
) {
711 for (i
= 0; i
< n
; i
++) {
712 if (x86_pmu
.put_event_constraints
)
713 x86_pmu
.put_event_constraints(cpuc
, cpuc
->event_list
[i
]);
716 return num
? -ENOSPC
: 0;
720 * dogrp: true if must collect siblings events (group)
721 * returns total number of events and error code
723 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
725 struct perf_event
*event
;
728 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
730 /* current number of events already accepted */
733 if (is_x86_event(leader
)) {
736 cpuc
->event_list
[n
] = leader
;
742 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
743 if (!is_x86_event(event
) ||
744 event
->state
<= PERF_EVENT_STATE_OFF
)
750 cpuc
->event_list
[n
] = event
;
756 static inline void x86_assign_hw_event(struct perf_event
*event
,
757 struct cpu_hw_events
*cpuc
, int i
)
759 struct hw_perf_event
*hwc
= &event
->hw
;
761 hwc
->idx
= cpuc
->assign
[i
];
762 hwc
->last_cpu
= smp_processor_id();
763 hwc
->last_tag
= ++cpuc
->tags
[i
];
765 if (hwc
->idx
== X86_PMC_IDX_FIXED_BTS
) {
766 hwc
->config_base
= 0;
768 } else if (hwc
->idx
>= X86_PMC_IDX_FIXED
) {
769 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
771 * We set it so that event_base + idx in wrmsr/rdmsr maps to
772 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
775 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
777 hwc
->config_base
= x86_pmu
.eventsel
;
778 hwc
->event_base
= x86_pmu
.perfctr
;
782 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
783 struct cpu_hw_events
*cpuc
,
786 return hwc
->idx
== cpuc
->assign
[i
] &&
787 hwc
->last_cpu
== smp_processor_id() &&
788 hwc
->last_tag
== cpuc
->tags
[i
];
791 static int x86_pmu_start(struct perf_event
*event
);
792 static void x86_pmu_stop(struct perf_event
*event
);
794 void hw_perf_enable(void)
796 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
797 struct perf_event
*event
;
798 struct hw_perf_event
*hwc
;
799 int i
, added
= cpuc
->n_added
;
801 if (!x86_pmu_initialized())
808 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
810 * apply assignment obtained either from
811 * hw_perf_group_sched_in() or x86_pmu_enable()
813 * step1: save events moving to new counters
814 * step2: reprogram moved events into new counters
816 for (i
= 0; i
< n_running
; i
++) {
817 event
= cpuc
->event_list
[i
];
821 * we can avoid reprogramming counter if:
822 * - assigned same counter as last time
823 * - running on same CPU as last time
824 * - no other event has used the counter since
826 if (hwc
->idx
== -1 ||
827 match_prev_assignment(hwc
, cpuc
, i
))
833 for (i
= 0; i
< cpuc
->n_events
; i
++) {
834 event
= cpuc
->event_list
[i
];
837 if (!match_prev_assignment(hwc
, cpuc
, i
))
838 x86_assign_hw_event(event
, cpuc
, i
);
839 else if (i
< n_running
)
842 x86_pmu_start(event
);
845 perf_events_lapic_init();
851 x86_pmu
.enable_all(added
);
854 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
)
856 wrmsrl(hwc
->config_base
+ hwc
->idx
,
857 hwc
->config
| ARCH_PERFMON_EVENTSEL_ENABLE
);
860 static inline void x86_pmu_disable_event(struct perf_event
*event
)
862 struct hw_perf_event
*hwc
= &event
->hw
;
864 wrmsrl(hwc
->config_base
+ hwc
->idx
, hwc
->config
);
867 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
870 * Set the next IRQ period, based on the hwc->period_left value.
871 * To be called with the event disabled in hw:
874 x86_perf_event_set_period(struct perf_event
*event
)
876 struct hw_perf_event
*hwc
= &event
->hw
;
877 s64 left
= atomic64_read(&hwc
->period_left
);
878 s64 period
= hwc
->sample_period
;
879 int ret
= 0, idx
= hwc
->idx
;
881 if (idx
== X86_PMC_IDX_FIXED_BTS
)
885 * If we are way outside a reasonable range then just skip forward:
887 if (unlikely(left
<= -period
)) {
889 atomic64_set(&hwc
->period_left
, left
);
890 hwc
->last_period
= period
;
894 if (unlikely(left
<= 0)) {
896 atomic64_set(&hwc
->period_left
, left
);
897 hwc
->last_period
= period
;
901 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
903 if (unlikely(left
< 2))
906 if (left
> x86_pmu
.max_period
)
907 left
= x86_pmu
.max_period
;
909 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
912 * The hw event starts counting from this event offset,
913 * mark it to be able to extra future deltas:
915 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
917 wrmsrl(hwc
->event_base
+ idx
,
918 (u64
)(-left
) & x86_pmu
.cntval_mask
);
920 perf_event_update_userpage(event
);
925 static void x86_pmu_enable_event(struct perf_event
*event
)
927 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
929 __x86_pmu_enable_event(&event
->hw
);
933 * activate a single event
935 * The event is added to the group of enabled events
936 * but only if it can be scehduled with existing events.
938 * Called with PMU disabled. If successful and return value 1,
939 * then guaranteed to call perf_enable() and hw_perf_enable()
941 static int x86_pmu_enable(struct perf_event
*event
)
943 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
944 struct hw_perf_event
*hwc
;
945 int assign
[X86_PMC_IDX_MAX
];
951 n
= collect_events(cpuc
, event
, false);
955 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
959 * copy new assignment, now we know it is possible
960 * will be used by hw_perf_enable()
962 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
965 cpuc
->n_added
+= n
- n0
;
970 static int x86_pmu_start(struct perf_event
*event
)
972 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
973 int idx
= event
->hw
.idx
;
978 x86_perf_event_set_period(event
);
979 cpuc
->events
[idx
] = event
;
980 __set_bit(idx
, cpuc
->active_mask
);
981 x86_pmu
.enable(event
);
982 perf_event_update_userpage(event
);
987 static void x86_pmu_unthrottle(struct perf_event
*event
)
989 int ret
= x86_pmu_start(event
);
993 void perf_event_print_debug(void)
995 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
997 struct cpu_hw_events
*cpuc
;
1001 if (!x86_pmu
.num_counters
)
1004 local_irq_save(flags
);
1006 cpu
= smp_processor_id();
1007 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1009 if (x86_pmu
.version
>= 2) {
1010 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1011 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1012 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1013 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1014 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1017 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1018 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1019 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1020 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1021 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1023 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1025 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1026 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
1027 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
1029 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1031 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1032 cpu
, idx
, pmc_ctrl
);
1033 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1034 cpu
, idx
, pmc_count
);
1035 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1036 cpu
, idx
, prev_left
);
1038 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1039 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1041 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1042 cpu
, idx
, pmc_count
);
1044 local_irq_restore(flags
);
1047 static void x86_pmu_stop(struct perf_event
*event
)
1049 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1050 struct hw_perf_event
*hwc
= &event
->hw
;
1053 if (!__test_and_clear_bit(idx
, cpuc
->active_mask
))
1056 x86_pmu
.disable(event
);
1059 * Drain the remaining delta count out of a event
1060 * that we are disabling:
1062 x86_perf_event_update(event
);
1064 cpuc
->events
[idx
] = NULL
;
1067 static void x86_pmu_disable(struct perf_event
*event
)
1069 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1072 x86_pmu_stop(event
);
1074 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1075 if (event
== cpuc
->event_list
[i
]) {
1077 if (x86_pmu
.put_event_constraints
)
1078 x86_pmu
.put_event_constraints(cpuc
, event
);
1080 while (++i
< cpuc
->n_events
)
1081 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1087 perf_event_update_userpage(event
);
1090 static int x86_pmu_handle_irq(struct pt_regs
*regs
)
1092 struct perf_sample_data data
;
1093 struct cpu_hw_events
*cpuc
;
1094 struct perf_event
*event
;
1095 struct hw_perf_event
*hwc
;
1096 int idx
, handled
= 0;
1099 perf_sample_data_init(&data
, 0);
1101 cpuc
= &__get_cpu_var(cpu_hw_events
);
1103 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1104 if (!test_bit(idx
, cpuc
->active_mask
))
1107 event
= cpuc
->events
[idx
];
1110 val
= x86_perf_event_update(event
);
1111 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1118 data
.period
= event
->hw
.last_period
;
1120 if (!x86_perf_event_set_period(event
))
1123 if (perf_event_overflow(event
, 1, &data
, regs
))
1124 x86_pmu_stop(event
);
1128 inc_irq_stat(apic_perf_irqs
);
1133 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
1137 inc_irq_stat(apic_pending_irqs
);
1138 perf_event_do_pending();
1142 void set_perf_event_pending(void)
1144 #ifdef CONFIG_X86_LOCAL_APIC
1145 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1148 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
1152 void perf_events_lapic_init(void)
1154 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1158 * Always use NMI for PMU
1160 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1163 static int __kprobes
1164 perf_event_nmi_handler(struct notifier_block
*self
,
1165 unsigned long cmd
, void *__args
)
1167 struct die_args
*args
= __args
;
1168 struct pt_regs
*regs
;
1170 if (!atomic_read(&active_events
))
1184 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1186 * Can't rely on the handled return value to say it was our NMI, two
1187 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1189 * If the first NMI handles both, the latter will be empty and daze
1192 x86_pmu
.handle_irq(regs
);
1197 static __read_mostly
struct notifier_block perf_event_nmi_notifier
= {
1198 .notifier_call
= perf_event_nmi_handler
,
1203 static struct event_constraint unconstrained
;
1204 static struct event_constraint emptyconstraint
;
1206 static struct event_constraint
*
1207 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
)
1209 struct event_constraint
*c
;
1211 if (x86_pmu
.event_constraints
) {
1212 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1213 if ((event
->hw
.config
& c
->cmask
) == c
->code
)
1218 return &unconstrained
;
1221 static int x86_event_sched_in(struct perf_event
*event
,
1222 struct perf_cpu_context
*cpuctx
)
1226 event
->state
= PERF_EVENT_STATE_ACTIVE
;
1227 event
->oncpu
= smp_processor_id();
1228 event
->tstamp_running
+= event
->ctx
->time
- event
->tstamp_stopped
;
1230 if (!is_x86_event(event
))
1231 ret
= event
->pmu
->enable(event
);
1233 if (!ret
&& !is_software_event(event
))
1234 cpuctx
->active_oncpu
++;
1236 if (!ret
&& event
->attr
.exclusive
)
1237 cpuctx
->exclusive
= 1;
1242 static void x86_event_sched_out(struct perf_event
*event
,
1243 struct perf_cpu_context
*cpuctx
)
1245 event
->state
= PERF_EVENT_STATE_INACTIVE
;
1248 if (!is_x86_event(event
))
1249 event
->pmu
->disable(event
);
1251 event
->tstamp_running
-= event
->ctx
->time
- event
->tstamp_stopped
;
1253 if (!is_software_event(event
))
1254 cpuctx
->active_oncpu
--;
1256 if (event
->attr
.exclusive
|| !cpuctx
->active_oncpu
)
1257 cpuctx
->exclusive
= 0;
1261 * Called to enable a whole group of events.
1262 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1263 * Assumes the caller has disabled interrupts and has
1264 * frozen the PMU with hw_perf_save_disable.
1266 * called with PMU disabled. If successful and return value 1,
1267 * then guaranteed to call perf_enable() and hw_perf_enable()
1269 int hw_perf_group_sched_in(struct perf_event
*leader
,
1270 struct perf_cpu_context
*cpuctx
,
1271 struct perf_event_context
*ctx
)
1273 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1274 struct perf_event
*sub
;
1275 int assign
[X86_PMC_IDX_MAX
];
1278 if (!x86_pmu_initialized())
1281 /* n0 = total number of events */
1282 n0
= collect_events(cpuc
, leader
, true);
1286 ret
= x86_pmu
.schedule_events(cpuc
, n0
, assign
);
1290 ret
= x86_event_sched_in(leader
, cpuctx
);
1295 list_for_each_entry(sub
, &leader
->sibling_list
, group_entry
) {
1296 if (sub
->state
> PERF_EVENT_STATE_OFF
) {
1297 ret
= x86_event_sched_in(sub
, cpuctx
);
1304 * copy new assignment, now we know it is possible
1305 * will be used by hw_perf_enable()
1307 memcpy(cpuc
->assign
, assign
, n0
*sizeof(int));
1309 cpuc
->n_events
= n0
;
1310 cpuc
->n_added
+= n1
;
1311 ctx
->nr_active
+= n1
;
1314 * 1 means successful and events are active
1315 * This is not quite true because we defer
1316 * actual activation until hw_perf_enable() but
1317 * this way we* ensure caller won't try to enable
1322 x86_event_sched_out(leader
, cpuctx
);
1324 list_for_each_entry(sub
, &leader
->sibling_list
, group_entry
) {
1325 if (sub
->state
== PERF_EVENT_STATE_ACTIVE
) {
1326 x86_event_sched_out(sub
, cpuctx
);
1334 #include "perf_event_amd.c"
1335 #include "perf_event_p6.c"
1336 #include "perf_event_p4.c"
1337 #include "perf_event_intel_lbr.c"
1338 #include "perf_event_intel_ds.c"
1339 #include "perf_event_intel.c"
1341 static int __cpuinit
1342 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1344 unsigned int cpu
= (long)hcpu
;
1345 int ret
= NOTIFY_OK
;
1347 switch (action
& ~CPU_TASKS_FROZEN
) {
1348 case CPU_UP_PREPARE
:
1349 if (x86_pmu
.cpu_prepare
)
1350 ret
= x86_pmu
.cpu_prepare(cpu
);
1354 if (x86_pmu
.cpu_starting
)
1355 x86_pmu
.cpu_starting(cpu
);
1359 if (x86_pmu
.cpu_dying
)
1360 x86_pmu
.cpu_dying(cpu
);
1363 case CPU_UP_CANCELED
:
1365 if (x86_pmu
.cpu_dead
)
1366 x86_pmu
.cpu_dead(cpu
);
1376 static void __init
pmu_check_apic(void)
1382 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1383 pr_info("no hardware sampling interrupt available.\n");
1386 void __init
init_hw_perf_events(void)
1388 struct event_constraint
*c
;
1391 pr_info("Performance Events: ");
1393 switch (boot_cpu_data
.x86_vendor
) {
1394 case X86_VENDOR_INTEL
:
1395 err
= intel_pmu_init();
1397 case X86_VENDOR_AMD
:
1398 err
= amd_pmu_init();
1404 pr_cont("no PMU driver, software events only.\n");
1410 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1415 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
1416 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
1417 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
1418 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
1420 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1421 perf_max_events
= x86_pmu
.num_counters
;
1423 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
1424 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
1425 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
1426 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
1429 x86_pmu
.intel_ctrl
|=
1430 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1432 perf_events_lapic_init();
1433 register_die_notifier(&perf_event_nmi_notifier
);
1435 unconstrained
= (struct event_constraint
)
1436 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1437 0, x86_pmu
.num_counters
);
1439 if (x86_pmu
.event_constraints
) {
1440 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1441 if (c
->cmask
!= X86_RAW_EVENT_MASK
)
1444 c
->idxmsk64
|= (1ULL << x86_pmu
.num_counters
) - 1;
1445 c
->weight
+= x86_pmu
.num_counters
;
1449 pr_info("... version: %d\n", x86_pmu
.version
);
1450 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1451 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1452 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1453 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1454 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1455 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1457 perf_cpu_notifier(x86_pmu_notifier
);
1460 static inline void x86_pmu_read(struct perf_event
*event
)
1462 x86_perf_event_update(event
);
1465 static const struct pmu pmu
= {
1466 .enable
= x86_pmu_enable
,
1467 .disable
= x86_pmu_disable
,
1468 .start
= x86_pmu_start
,
1469 .stop
= x86_pmu_stop
,
1470 .read
= x86_pmu_read
,
1471 .unthrottle
= x86_pmu_unthrottle
,
1475 * validate that we can schedule this event
1477 static int validate_event(struct perf_event
*event
)
1479 struct cpu_hw_events
*fake_cpuc
;
1480 struct event_constraint
*c
;
1483 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1487 c
= x86_pmu
.get_event_constraints(fake_cpuc
, event
);
1489 if (!c
|| !c
->weight
)
1492 if (x86_pmu
.put_event_constraints
)
1493 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1501 * validate a single event group
1503 * validation include:
1504 * - check events are compatible which each other
1505 * - events do not compete for the same counter
1506 * - number of events <= number of counters
1508 * validation ensures the group can be loaded onto the
1509 * PMU if it was the only group available.
1511 static int validate_group(struct perf_event
*event
)
1513 struct perf_event
*leader
= event
->group_leader
;
1514 struct cpu_hw_events
*fake_cpuc
;
1518 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1523 * the event is not yet connected with its
1524 * siblings therefore we must first collect
1525 * existing siblings, then add the new event
1526 * before we can simulate the scheduling
1529 n
= collect_events(fake_cpuc
, leader
, true);
1533 fake_cpuc
->n_events
= n
;
1534 n
= collect_events(fake_cpuc
, event
, false);
1538 fake_cpuc
->n_events
= n
;
1540 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1548 const struct pmu
*hw_perf_event_init(struct perf_event
*event
)
1550 const struct pmu
*tmp
;
1553 err
= __hw_perf_event_init(event
);
1556 * we temporarily connect event to its pmu
1557 * such that validate_group() can classify
1558 * it as an x86 event using is_x86_event()
1563 if (event
->group_leader
!= event
)
1564 err
= validate_group(event
);
1566 err
= validate_event(event
);
1572 event
->destroy(event
);
1573 return ERR_PTR(err
);
1584 void callchain_store(struct perf_callchain_entry
*entry
, u64 ip
)
1586 if (entry
->nr
< PERF_MAX_STACK_DEPTH
)
1587 entry
->ip
[entry
->nr
++] = ip
;
1590 static DEFINE_PER_CPU(struct perf_callchain_entry
, pmc_irq_entry
);
1591 static DEFINE_PER_CPU(struct perf_callchain_entry
, pmc_nmi_entry
);
1595 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1597 /* Ignore warnings */
1600 static void backtrace_warning(void *data
, char *msg
)
1602 /* Ignore warnings */
1605 static int backtrace_stack(void *data
, char *name
)
1610 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1612 struct perf_callchain_entry
*entry
= data
;
1614 callchain_store(entry
, addr
);
1617 static const struct stacktrace_ops backtrace_ops
= {
1618 .warning
= backtrace_warning
,
1619 .warning_symbol
= backtrace_warning_symbol
,
1620 .stack
= backtrace_stack
,
1621 .address
= backtrace_address
,
1622 .walk_stack
= print_context_stack_bp
,
1625 #include "../dumpstack.h"
1628 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1630 callchain_store(entry
, PERF_CONTEXT_KERNEL
);
1631 callchain_store(entry
, regs
->ip
);
1633 dump_trace(NULL
, regs
, NULL
, regs
->bp
, &backtrace_ops
, entry
);
1636 #ifdef CONFIG_COMPAT
1638 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1640 /* 32-bit process in 64-bit kernel. */
1641 struct stack_frame_ia32 frame
;
1642 const void __user
*fp
;
1644 if (!test_thread_flag(TIF_IA32
))
1647 fp
= compat_ptr(regs
->bp
);
1648 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1649 unsigned long bytes
;
1650 frame
.next_frame
= 0;
1651 frame
.return_address
= 0;
1653 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1654 if (bytes
!= sizeof(frame
))
1657 if (fp
< compat_ptr(regs
->sp
))
1660 callchain_store(entry
, frame
.return_address
);
1661 fp
= compat_ptr(frame
.next_frame
);
1667 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1674 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1676 struct stack_frame frame
;
1677 const void __user
*fp
;
1679 if (!user_mode(regs
))
1680 regs
= task_pt_regs(current
);
1682 fp
= (void __user
*)regs
->bp
;
1684 callchain_store(entry
, PERF_CONTEXT_USER
);
1685 callchain_store(entry
, regs
->ip
);
1687 if (perf_callchain_user32(regs
, entry
))
1690 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1691 unsigned long bytes
;
1692 frame
.next_frame
= NULL
;
1693 frame
.return_address
= 0;
1695 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1696 if (bytes
!= sizeof(frame
))
1699 if ((unsigned long)fp
< regs
->sp
)
1702 callchain_store(entry
, frame
.return_address
);
1703 fp
= frame
.next_frame
;
1708 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1715 is_user
= user_mode(regs
);
1717 if (is_user
&& current
->state
!= TASK_RUNNING
)
1721 perf_callchain_kernel(regs
, entry
);
1724 perf_callchain_user(regs
, entry
);
1727 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1729 struct perf_callchain_entry
*entry
;
1731 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1732 /* TODO: We don't support guest os callchain now */
1737 entry
= &__get_cpu_var(pmc_nmi_entry
);
1739 entry
= &__get_cpu_var(pmc_irq_entry
);
1743 perf_do_callchain(regs
, entry
);
1748 void perf_arch_fetch_caller_regs(struct pt_regs
*regs
, unsigned long ip
, int skip
)
1752 * perf_arch_fetch_caller_regs adds another call, we need to increment
1755 regs
->bp
= rewind_frame_pointer(skip
+ 1);
1756 regs
->cs
= __KERNEL_CS
;
1757 local_save_flags(regs
->flags
);
1760 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
1764 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
1765 ip
= perf_guest_cbs
->get_guest_ip();
1767 ip
= instruction_pointer(regs
);
1772 unsigned long perf_misc_flags(struct pt_regs
*regs
)
1776 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1777 if (perf_guest_cbs
->is_user_mode())
1778 misc
|= PERF_RECORD_MISC_GUEST_USER
;
1780 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
1782 if (user_mode(regs
))
1783 misc
|= PERF_RECORD_MISC_USER
;
1785 misc
|= PERF_RECORD_MISC_KERNEL
;
1788 if (regs
->flags
& PERF_EFLAGS_EXACT
)
1789 misc
|= PERF_RECORD_MISC_EXACT
;