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KVM: SVM: clean up nested_svm_exit_handled_msr
[linux-2.6/libata-dev.git] / arch / x86 / kvm / svm.c
blobe85d79142ffcbb397e81211413e9fe9c032d70ee
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "irq.h"
19 #include "mmu.h"
20 #include "kvm_cache_regs.h"
21 #include "x86.h"
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29
30 #include <asm/desc.h>
31
32 #include <asm/virtext.h>
33 #include "trace.h"
34
35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
36
37 MODULE_AUTHOR("Qumranet");
38 MODULE_LICENSE("GPL");
39
40 #define IOPM_ALLOC_ORDER 2
41 #define MSRPM_ALLOC_ORDER 1
42
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
45
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_FEATURE_SVML (1 << 2)
49
50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
51
52 /* Turn on to get debugging output*/
53 /* #define NESTED_DEBUG */
54
55 #ifdef NESTED_DEBUG
56 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
57 #else
58 #define nsvm_printk(fmt, args...) do {} while(0)
59 #endif
60
61 static const u32 host_save_user_msrs[] = {
62 #ifdef CONFIG_X86_64
63 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
64 MSR_FS_BASE,
65 #endif
66 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
67 };
68
69 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
70
71 struct kvm_vcpu;
72
73 struct nested_state {
74 struct vmcb *hsave;
75 u64 hsave_msr;
76 u64 vmcb;
77
78 /* These are the merged vectors */
79 u32 *msrpm;
80
81 /* gpa pointers to the real vectors */
82 u64 vmcb_msrpm;
83
84 /* cache for intercepts of the guest */
85 u16 intercept_cr_read;
86 u16 intercept_cr_write;
87 u16 intercept_dr_read;
88 u16 intercept_dr_write;
89 u32 intercept_exceptions;
90 u64 intercept;
91
92 };
93
94 struct vcpu_svm {
95 struct kvm_vcpu vcpu;
96 struct vmcb *vmcb;
97 unsigned long vmcb_pa;
98 struct svm_cpu_data *svm_data;
99 uint64_t asid_generation;
100 uint64_t sysenter_esp;
101 uint64_t sysenter_eip;
102
103 u64 next_rip;
104
105 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
106 u64 host_gs_base;
107
108 u32 *msrpm;
109
110 struct nested_state nested;
111 };
112
113 /* enable NPT for AMD64 and X86 with PAE */
114 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
115 static bool npt_enabled = true;
116 #else
117 static bool npt_enabled = false;
118 #endif
119 static int npt = 1;
120
121 module_param(npt, int, S_IRUGO);
122
123 static int nested = 0;
124 module_param(nested, int, S_IRUGO);
125
126 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
127 static void svm_complete_interrupts(struct vcpu_svm *svm);
128
129 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
130 static int nested_svm_vmexit(struct vcpu_svm *svm);
131 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
132 void *arg2, void *opaque);
133 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
134 bool has_error_code, u32 error_code);
135
136 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
137 {
138 return container_of(vcpu, struct vcpu_svm, vcpu);
139 }
140
141 static inline bool is_nested(struct vcpu_svm *svm)
142 {
143 return svm->nested.vmcb;
144 }
145
146 static inline void enable_gif(struct vcpu_svm *svm)
147 {
148 svm->vcpu.arch.hflags |= HF_GIF_MASK;
149 }
150
151 static inline void disable_gif(struct vcpu_svm *svm)
152 {
153 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
154 }
155
156 static inline bool gif_set(struct vcpu_svm *svm)
157 {
158 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
159 }
160
161 static unsigned long iopm_base;
162
163 struct kvm_ldttss_desc {
164 u16 limit0;
165 u16 base0;
166 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
167 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
168 u32 base3;
169 u32 zero1;
170 } __attribute__((packed));
171
172 struct svm_cpu_data {
173 int cpu;
174
175 u64 asid_generation;
176 u32 max_asid;
177 u32 next_asid;
178 struct kvm_ldttss_desc *tss_desc;
179
180 struct page *save_area;
181 };
182
183 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
184 static uint32_t svm_features;
185
186 struct svm_init_data {
187 int cpu;
188 int r;
189 };
190
191 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
192
193 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
194 #define MSRS_RANGE_SIZE 2048
195 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
196
197 #define MAX_INST_SIZE 15
198
199 static inline u32 svm_has(u32 feat)
200 {
201 return svm_features & feat;
202 }
203
204 static inline void clgi(void)
205 {
206 asm volatile (__ex(SVM_CLGI));
207 }
208
209 static inline void stgi(void)
210 {
211 asm volatile (__ex(SVM_STGI));
212 }
213
214 static inline void invlpga(unsigned long addr, u32 asid)
215 {
216 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
217 }
218
219 static inline void force_new_asid(struct kvm_vcpu *vcpu)
220 {
221 to_svm(vcpu)->asid_generation--;
222 }
223
224 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
225 {
226 force_new_asid(vcpu);
227 }
228
229 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
230 {
231 if (!npt_enabled && !(efer & EFER_LMA))
232 efer &= ~EFER_LME;
233
234 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
235 vcpu->arch.shadow_efer = efer;
236 }
237
238 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
239 bool has_error_code, u32 error_code)
240 {
241 struct vcpu_svm *svm = to_svm(vcpu);
242
243 /* If we are within a nested VM we'd better #VMEXIT and let the
244 guest handle the exception */
245 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
246 return;
247
248 svm->vmcb->control.event_inj = nr
249 | SVM_EVTINJ_VALID
250 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
251 | SVM_EVTINJ_TYPE_EXEPT;
252 svm->vmcb->control.event_inj_err = error_code;
253 }
254
255 static int is_external_interrupt(u32 info)
256 {
257 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
258 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
259 }
260
261 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
262 {
263 struct vcpu_svm *svm = to_svm(vcpu);
264 u32 ret = 0;
265
266 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
267 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
268 return ret & mask;
269 }
270
271 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
272 {
273 struct vcpu_svm *svm = to_svm(vcpu);
274
275 if (mask == 0)
276 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
277 else
278 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
279
280 }
281
282 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
283 {
284 struct vcpu_svm *svm = to_svm(vcpu);
285
286 if (!svm->next_rip) {
287 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
288 EMULATE_DONE)
289 printk(KERN_DEBUG "%s: NOP\n", __func__);
290 return;
291 }
292 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
293 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
294 __func__, kvm_rip_read(vcpu), svm->next_rip);
295
296 kvm_rip_write(vcpu, svm->next_rip);
297 svm_set_interrupt_shadow(vcpu, 0);
298 }
299
300 static int has_svm(void)
301 {
302 const char *msg;
303
304 if (!cpu_has_svm(&msg)) {
305 printk(KERN_INFO "has_svm: %s\n", msg);
306 return 0;
307 }
308
309 return 1;
310 }
311
312 static void svm_hardware_disable(void *garbage)
313 {
314 cpu_svm_disable();
315 }
316
317 static void svm_hardware_enable(void *garbage)
318 {
319
320 struct svm_cpu_data *svm_data;
321 uint64_t efer;
322 struct descriptor_table gdt_descr;
323 struct desc_struct *gdt;
324 int me = raw_smp_processor_id();
325
326 if (!has_svm()) {
327 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
328 return;
329 }
330 svm_data = per_cpu(svm_data, me);
331
332 if (!svm_data) {
333 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
334 me);
335 return;
336 }
337
338 svm_data->asid_generation = 1;
339 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
340 svm_data->next_asid = svm_data->max_asid + 1;
341
342 kvm_get_gdt(&gdt_descr);
343 gdt = (struct desc_struct *)gdt_descr.base;
344 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
345
346 rdmsrl(MSR_EFER, efer);
347 wrmsrl(MSR_EFER, efer | EFER_SVME);
348
349 wrmsrl(MSR_VM_HSAVE_PA,
350 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
351 }
352
353 static void svm_cpu_uninit(int cpu)
354 {
355 struct svm_cpu_data *svm_data
356 = per_cpu(svm_data, raw_smp_processor_id());
357
358 if (!svm_data)
359 return;
360
361 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
362 __free_page(svm_data->save_area);
363 kfree(svm_data);
364 }
365
366 static int svm_cpu_init(int cpu)
367 {
368 struct svm_cpu_data *svm_data;
369 int r;
370
371 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
372 if (!svm_data)
373 return -ENOMEM;
374 svm_data->cpu = cpu;
375 svm_data->save_area = alloc_page(GFP_KERNEL);
376 r = -ENOMEM;
377 if (!svm_data->save_area)
378 goto err_1;
379
380 per_cpu(svm_data, cpu) = svm_data;
381
382 return 0;
383
384 err_1:
385 kfree(svm_data);
386 return r;
387
388 }
389
390 static void set_msr_interception(u32 *msrpm, unsigned msr,
391 int read, int write)
392 {
393 int i;
394
395 for (i = 0; i < NUM_MSR_MAPS; i++) {
396 if (msr >= msrpm_ranges[i] &&
397 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
398 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
399 msrpm_ranges[i]) * 2;
400
401 u32 *base = msrpm + (msr_offset / 32);
402 u32 msr_shift = msr_offset % 32;
403 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
404 *base = (*base & ~(0x3 << msr_shift)) |
405 (mask << msr_shift);
406 return;
407 }
408 }
409 BUG();
410 }
411
412 static void svm_vcpu_init_msrpm(u32 *msrpm)
413 {
414 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
415
416 #ifdef CONFIG_X86_64
417 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
418 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
419 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
420 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
421 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
422 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
423 #endif
424 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
425 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
426 }
427
428 static void svm_enable_lbrv(struct vcpu_svm *svm)
429 {
430 u32 *msrpm = svm->msrpm;
431
432 svm->vmcb->control.lbr_ctl = 1;
433 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
434 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
435 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
436 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
437 }
438
439 static void svm_disable_lbrv(struct vcpu_svm *svm)
440 {
441 u32 *msrpm = svm->msrpm;
442
443 svm->vmcb->control.lbr_ctl = 0;
444 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
445 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
446 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
447 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
448 }
449
450 static __init int svm_hardware_setup(void)
451 {
452 int cpu;
453 struct page *iopm_pages;
454 void *iopm_va;
455 int r;
456
457 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
458
459 if (!iopm_pages)
460 return -ENOMEM;
461
462 iopm_va = page_address(iopm_pages);
463 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
464 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
465
466 if (boot_cpu_has(X86_FEATURE_NX))
467 kvm_enable_efer_bits(EFER_NX);
468
469 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
470 kvm_enable_efer_bits(EFER_FFXSR);
471
472 if (nested) {
473 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
474 kvm_enable_efer_bits(EFER_SVME);
475 }
476
477 for_each_online_cpu(cpu) {
478 r = svm_cpu_init(cpu);
479 if (r)
480 goto err;
481 }
482
483 svm_features = cpuid_edx(SVM_CPUID_FUNC);
484
485 if (!svm_has(SVM_FEATURE_NPT))
486 npt_enabled = false;
487
488 if (npt_enabled && !npt) {
489 printk(KERN_INFO "kvm: Nested Paging disabled\n");
490 npt_enabled = false;
491 }
492
493 if (npt_enabled) {
494 printk(KERN_INFO "kvm: Nested Paging enabled\n");
495 kvm_enable_tdp();
496 } else
497 kvm_disable_tdp();
498
499 return 0;
500
501 err:
502 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
503 iopm_base = 0;
504 return r;
505 }
506
507 static __exit void svm_hardware_unsetup(void)
508 {
509 int cpu;
510
511 for_each_online_cpu(cpu)
512 svm_cpu_uninit(cpu);
513
514 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
515 iopm_base = 0;
516 }
517
518 static void init_seg(struct vmcb_seg *seg)
519 {
520 seg->selector = 0;
521 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
522 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
523 seg->limit = 0xffff;
524 seg->base = 0;
525 }
526
527 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
528 {
529 seg->selector = 0;
530 seg->attrib = SVM_SELECTOR_P_MASK | type;
531 seg->limit = 0xffff;
532 seg->base = 0;
533 }
534
535 static void init_vmcb(struct vcpu_svm *svm)
536 {
537 struct vmcb_control_area *control = &svm->vmcb->control;
538 struct vmcb_save_area *save = &svm->vmcb->save;
539
540 control->intercept_cr_read = INTERCEPT_CR0_MASK |
541 INTERCEPT_CR3_MASK |
542 INTERCEPT_CR4_MASK;
543
544 control->intercept_cr_write = INTERCEPT_CR0_MASK |
545 INTERCEPT_CR3_MASK |
546 INTERCEPT_CR4_MASK |
547 INTERCEPT_CR8_MASK;
548
549 control->intercept_dr_read = INTERCEPT_DR0_MASK |
550 INTERCEPT_DR1_MASK |
551 INTERCEPT_DR2_MASK |
552 INTERCEPT_DR3_MASK;
553
554 control->intercept_dr_write = INTERCEPT_DR0_MASK |
555 INTERCEPT_DR1_MASK |
556 INTERCEPT_DR2_MASK |
557 INTERCEPT_DR3_MASK |
558 INTERCEPT_DR5_MASK |
559 INTERCEPT_DR7_MASK;
560
561 control->intercept_exceptions = (1 << PF_VECTOR) |
562 (1 << UD_VECTOR) |
563 (1 << MC_VECTOR);
564
565
566 control->intercept = (1ULL << INTERCEPT_INTR) |
567 (1ULL << INTERCEPT_NMI) |
568 (1ULL << INTERCEPT_SMI) |
569 (1ULL << INTERCEPT_CPUID) |
570 (1ULL << INTERCEPT_INVD) |
571 (1ULL << INTERCEPT_HLT) |
572 (1ULL << INTERCEPT_INVLPG) |
573 (1ULL << INTERCEPT_INVLPGA) |
574 (1ULL << INTERCEPT_IOIO_PROT) |
575 (1ULL << INTERCEPT_MSR_PROT) |
576 (1ULL << INTERCEPT_TASK_SWITCH) |
577 (1ULL << INTERCEPT_SHUTDOWN) |
578 (1ULL << INTERCEPT_VMRUN) |
579 (1ULL << INTERCEPT_VMMCALL) |
580 (1ULL << INTERCEPT_VMLOAD) |
581 (1ULL << INTERCEPT_VMSAVE) |
582 (1ULL << INTERCEPT_STGI) |
583 (1ULL << INTERCEPT_CLGI) |
584 (1ULL << INTERCEPT_SKINIT) |
585 (1ULL << INTERCEPT_WBINVD) |
586 (1ULL << INTERCEPT_MONITOR) |
587 (1ULL << INTERCEPT_MWAIT);
588
589 control->iopm_base_pa = iopm_base;
590 control->msrpm_base_pa = __pa(svm->msrpm);
591 control->tsc_offset = 0;
592 control->int_ctl = V_INTR_MASKING_MASK;
593
594 init_seg(&save->es);
595 init_seg(&save->ss);
596 init_seg(&save->ds);
597 init_seg(&save->fs);
598 init_seg(&save->gs);
599
600 save->cs.selector = 0xf000;
601 /* Executable/Readable Code Segment */
602 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
603 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
604 save->cs.limit = 0xffff;
605 /*
606 * cs.base should really be 0xffff0000, but vmx can't handle that, so
607 * be consistent with it.
608 *
609 * Replace when we have real mode working for vmx.
610 */
611 save->cs.base = 0xf0000;
612
613 save->gdtr.limit = 0xffff;
614 save->idtr.limit = 0xffff;
615
616 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
617 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
618
619 save->efer = EFER_SVME;
620 save->dr6 = 0xffff0ff0;
621 save->dr7 = 0x400;
622 save->rflags = 2;
623 save->rip = 0x0000fff0;
624 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
625
626 /*
627 * cr0 val on cpu init should be 0x60000010, we enable cpu
628 * cache by default. the orderly way is to enable cache in bios.
629 */
630 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
631 save->cr4 = X86_CR4_PAE;
632 /* rdx = ?? */
633
634 if (npt_enabled) {
635 /* Setup VMCB for Nested Paging */
636 control->nested_ctl = 1;
637 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
638 (1ULL << INTERCEPT_INVLPG));
639 control->intercept_exceptions &= ~(1 << PF_VECTOR);
640 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
641 INTERCEPT_CR3_MASK);
642 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
643 INTERCEPT_CR3_MASK);
644 save->g_pat = 0x0007040600070406ULL;
645 /* enable caching because the QEMU Bios doesn't enable it */
646 save->cr0 = X86_CR0_ET;
647 save->cr3 = 0;
648 save->cr4 = 0;
649 }
650 force_new_asid(&svm->vcpu);
651
652 svm->nested.vmcb = 0;
653 svm->vcpu.arch.hflags = 0;
654
655 enable_gif(svm);
656 }
657
658 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
659 {
660 struct vcpu_svm *svm = to_svm(vcpu);
661
662 init_vmcb(svm);
663
664 if (!kvm_vcpu_is_bsp(vcpu)) {
665 kvm_rip_write(vcpu, 0);
666 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
667 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
668 }
669 vcpu->arch.regs_avail = ~0;
670 vcpu->arch.regs_dirty = ~0;
671
672 return 0;
673 }
674
675 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
676 {
677 struct vcpu_svm *svm;
678 struct page *page;
679 struct page *msrpm_pages;
680 struct page *hsave_page;
681 struct page *nested_msrpm_pages;
682 int err;
683
684 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
685 if (!svm) {
686 err = -ENOMEM;
687 goto out;
688 }
689
690 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
691 if (err)
692 goto free_svm;
693
694 page = alloc_page(GFP_KERNEL);
695 if (!page) {
696 err = -ENOMEM;
697 goto uninit;
698 }
699
700 err = -ENOMEM;
701 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
702 if (!msrpm_pages)
703 goto uninit;
704
705 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
706 if (!nested_msrpm_pages)
707 goto uninit;
708
709 svm->msrpm = page_address(msrpm_pages);
710 svm_vcpu_init_msrpm(svm->msrpm);
711
712 hsave_page = alloc_page(GFP_KERNEL);
713 if (!hsave_page)
714 goto uninit;
715 svm->nested.hsave = page_address(hsave_page);
716
717 svm->nested.msrpm = page_address(nested_msrpm_pages);
718
719 svm->vmcb = page_address(page);
720 clear_page(svm->vmcb);
721 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
722 svm->asid_generation = 0;
723 init_vmcb(svm);
724
725 fx_init(&svm->vcpu);
726 svm->vcpu.fpu_active = 1;
727 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
728 if (kvm_vcpu_is_bsp(&svm->vcpu))
729 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
730
731 return &svm->vcpu;
732
733 uninit:
734 kvm_vcpu_uninit(&svm->vcpu);
735 free_svm:
736 kmem_cache_free(kvm_vcpu_cache, svm);
737 out:
738 return ERR_PTR(err);
739 }
740
741 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
742 {
743 struct vcpu_svm *svm = to_svm(vcpu);
744
745 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
746 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
747 __free_page(virt_to_page(svm->nested.hsave));
748 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
749 kvm_vcpu_uninit(vcpu);
750 kmem_cache_free(kvm_vcpu_cache, svm);
751 }
752
753 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
754 {
755 struct vcpu_svm *svm = to_svm(vcpu);
756 int i;
757
758 if (unlikely(cpu != vcpu->cpu)) {
759 u64 tsc_this, delta;
760
761 /*
762 * Make sure that the guest sees a monotonically
763 * increasing TSC.
764 */
765 rdtscll(tsc_this);
766 delta = vcpu->arch.host_tsc - tsc_this;
767 svm->vmcb->control.tsc_offset += delta;
768 vcpu->cpu = cpu;
769 kvm_migrate_timers(vcpu);
770 svm->asid_generation = 0;
771 }
772
773 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
774 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
775 }
776
777 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
778 {
779 struct vcpu_svm *svm = to_svm(vcpu);
780 int i;
781
782 ++vcpu->stat.host_state_reload;
783 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
784 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
785
786 rdtscll(vcpu->arch.host_tsc);
787 }
788
789 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
790 {
791 return to_svm(vcpu)->vmcb->save.rflags;
792 }
793
794 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
795 {
796 to_svm(vcpu)->vmcb->save.rflags = rflags;
797 }
798
799 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
800 {
801 switch (reg) {
802 case VCPU_EXREG_PDPTR:
803 BUG_ON(!npt_enabled);
804 load_pdptrs(vcpu, vcpu->arch.cr3);
805 break;
806 default:
807 BUG();
808 }
809 }
810
811 static void svm_set_vintr(struct vcpu_svm *svm)
812 {
813 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
814 }
815
816 static void svm_clear_vintr(struct vcpu_svm *svm)
817 {
818 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
819 }
820
821 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
822 {
823 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
824
825 switch (seg) {
826 case VCPU_SREG_CS: return &save->cs;
827 case VCPU_SREG_DS: return &save->ds;
828 case VCPU_SREG_ES: return &save->es;
829 case VCPU_SREG_FS: return &save->fs;
830 case VCPU_SREG_GS: return &save->gs;
831 case VCPU_SREG_SS: return &save->ss;
832 case VCPU_SREG_TR: return &save->tr;
833 case VCPU_SREG_LDTR: return &save->ldtr;
834 }
835 BUG();
836 return NULL;
837 }
838
839 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
840 {
841 struct vmcb_seg *s = svm_seg(vcpu, seg);
842
843 return s->base;
844 }
845
846 static void svm_get_segment(struct kvm_vcpu *vcpu,
847 struct kvm_segment *var, int seg)
848 {
849 struct vmcb_seg *s = svm_seg(vcpu, seg);
850
851 var->base = s->base;
852 var->limit = s->limit;
853 var->selector = s->selector;
854 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
855 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
856 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
857 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
858 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
859 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
860 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
861 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
862
863 /* AMD's VMCB does not have an explicit unusable field, so emulate it
864 * for cross vendor migration purposes by "not present"
865 */
866 var->unusable = !var->present || (var->type == 0);
867
868 switch (seg) {
869 case VCPU_SREG_CS:
870 /*
871 * SVM always stores 0 for the 'G' bit in the CS selector in
872 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
873 * Intel's VMENTRY has a check on the 'G' bit.
874 */
875 var->g = s->limit > 0xfffff;
876 break;
877 case VCPU_SREG_TR:
878 /*
879 * Work around a bug where the busy flag in the tr selector
880 * isn't exposed
881 */
882 var->type |= 0x2;
883 break;
884 case VCPU_SREG_DS:
885 case VCPU_SREG_ES:
886 case VCPU_SREG_FS:
887 case VCPU_SREG_GS:
888 /*
889 * The accessed bit must always be set in the segment
890 * descriptor cache, although it can be cleared in the
891 * descriptor, the cached bit always remains at 1. Since
892 * Intel has a check on this, set it here to support
893 * cross-vendor migration.
894 */
895 if (!var->unusable)
896 var->type |= 0x1;
897 break;
898 case VCPU_SREG_SS:
899 /* On AMD CPUs sometimes the DB bit in the segment
900 * descriptor is left as 1, although the whole segment has
901 * been made unusable. Clear it here to pass an Intel VMX
902 * entry check when cross vendor migrating.
903 */
904 if (var->unusable)
905 var->db = 0;
906 break;
907 }
908 }
909
910 static int svm_get_cpl(struct kvm_vcpu *vcpu)
911 {
912 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
913
914 return save->cpl;
915 }
916
917 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
918 {
919 struct vcpu_svm *svm = to_svm(vcpu);
920
921 dt->limit = svm->vmcb->save.idtr.limit;
922 dt->base = svm->vmcb->save.idtr.base;
923 }
924
925 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
926 {
927 struct vcpu_svm *svm = to_svm(vcpu);
928
929 svm->vmcb->save.idtr.limit = dt->limit;
930 svm->vmcb->save.idtr.base = dt->base ;
931 }
932
933 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
934 {
935 struct vcpu_svm *svm = to_svm(vcpu);
936
937 dt->limit = svm->vmcb->save.gdtr.limit;
938 dt->base = svm->vmcb->save.gdtr.base;
939 }
940
941 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
942 {
943 struct vcpu_svm *svm = to_svm(vcpu);
944
945 svm->vmcb->save.gdtr.limit = dt->limit;
946 svm->vmcb->save.gdtr.base = dt->base ;
947 }
948
949 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
950 {
951 }
952
953 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
954 {
955 struct vcpu_svm *svm = to_svm(vcpu);
956
957 #ifdef CONFIG_X86_64
958 if (vcpu->arch.shadow_efer & EFER_LME) {
959 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
960 vcpu->arch.shadow_efer |= EFER_LMA;
961 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
962 }
963
964 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
965 vcpu->arch.shadow_efer &= ~EFER_LMA;
966 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
967 }
968 }
969 #endif
970 if (npt_enabled)
971 goto set;
972
973 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
974 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
975 vcpu->fpu_active = 1;
976 }
977
978 vcpu->arch.cr0 = cr0;
979 cr0 |= X86_CR0_PG | X86_CR0_WP;
980 if (!vcpu->fpu_active) {
981 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
982 cr0 |= X86_CR0_TS;
983 }
984 set:
985 /*
986 * re-enable caching here because the QEMU bios
987 * does not do it - this results in some delay at
988 * reboot
989 */
990 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
991 svm->vmcb->save.cr0 = cr0;
992 }
993
994 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
995 {
996 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
997 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
998
999 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1000 force_new_asid(vcpu);
1001
1002 vcpu->arch.cr4 = cr4;
1003 if (!npt_enabled)
1004 cr4 |= X86_CR4_PAE;
1005 cr4 |= host_cr4_mce;
1006 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1007 }
1008
1009 static void svm_set_segment(struct kvm_vcpu *vcpu,
1010 struct kvm_segment *var, int seg)
1011 {
1012 struct vcpu_svm *svm = to_svm(vcpu);
1013 struct vmcb_seg *s = svm_seg(vcpu, seg);
1014
1015 s->base = var->base;
1016 s->limit = var->limit;
1017 s->selector = var->selector;
1018 if (var->unusable)
1019 s->attrib = 0;
1020 else {
1021 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1022 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1023 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1024 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1025 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1026 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1027 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1028 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1029 }
1030 if (seg == VCPU_SREG_CS)
1031 svm->vmcb->save.cpl
1032 = (svm->vmcb->save.cs.attrib
1033 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1034
1035 }
1036
1037 static void update_db_intercept(struct kvm_vcpu *vcpu)
1038 {
1039 struct vcpu_svm *svm = to_svm(vcpu);
1040
1041 svm->vmcb->control.intercept_exceptions &=
1042 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1043
1044 if (vcpu->arch.singlestep)
1045 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1046
1047 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1048 if (vcpu->guest_debug &
1049 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1050 svm->vmcb->control.intercept_exceptions |=
1051 1 << DB_VECTOR;
1052 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1053 svm->vmcb->control.intercept_exceptions |=
1054 1 << BP_VECTOR;
1055 } else
1056 vcpu->guest_debug = 0;
1057 }
1058
1059 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1060 {
1061 int old_debug = vcpu->guest_debug;
1062 struct vcpu_svm *svm = to_svm(vcpu);
1063
1064 vcpu->guest_debug = dbg->control;
1065
1066 update_db_intercept(vcpu);
1067
1068 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1069 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1070 else
1071 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1072
1073 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1074 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1075 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1076 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1077
1078 return 0;
1079 }
1080
1081 static void load_host_msrs(struct kvm_vcpu *vcpu)
1082 {
1083 #ifdef CONFIG_X86_64
1084 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1085 #endif
1086 }
1087
1088 static void save_host_msrs(struct kvm_vcpu *vcpu)
1089 {
1090 #ifdef CONFIG_X86_64
1091 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1092 #endif
1093 }
1094
1095 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1096 {
1097 if (svm_data->next_asid > svm_data->max_asid) {
1098 ++svm_data->asid_generation;
1099 svm_data->next_asid = 1;
1100 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1101 }
1102
1103 svm->asid_generation = svm_data->asid_generation;
1104 svm->vmcb->control.asid = svm_data->next_asid++;
1105 }
1106
1107 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1108 {
1109 struct vcpu_svm *svm = to_svm(vcpu);
1110 unsigned long val;
1111
1112 switch (dr) {
1113 case 0 ... 3:
1114 val = vcpu->arch.db[dr];
1115 break;
1116 case 6:
1117 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1118 val = vcpu->arch.dr6;
1119 else
1120 val = svm->vmcb->save.dr6;
1121 break;
1122 case 7:
1123 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1124 val = vcpu->arch.dr7;
1125 else
1126 val = svm->vmcb->save.dr7;
1127 break;
1128 default:
1129 val = 0;
1130 }
1131
1132 return val;
1133 }
1134
1135 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1136 int *exception)
1137 {
1138 struct vcpu_svm *svm = to_svm(vcpu);
1139
1140 *exception = 0;
1141
1142 switch (dr) {
1143 case 0 ... 3:
1144 vcpu->arch.db[dr] = value;
1145 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1146 vcpu->arch.eff_db[dr] = value;
1147 return;
1148 case 4 ... 5:
1149 if (vcpu->arch.cr4 & X86_CR4_DE)
1150 *exception = UD_VECTOR;
1151 return;
1152 case 6:
1153 if (value & 0xffffffff00000000ULL) {
1154 *exception = GP_VECTOR;
1155 return;
1156 }
1157 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1158 return;
1159 case 7:
1160 if (value & 0xffffffff00000000ULL) {
1161 *exception = GP_VECTOR;
1162 return;
1163 }
1164 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1165 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1166 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1167 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1168 }
1169 return;
1170 default:
1171 /* FIXME: Possible case? */
1172 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1173 __func__, dr);
1174 *exception = UD_VECTOR;
1175 return;
1176 }
1177 }
1178
1179 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1180 {
1181 u64 fault_address;
1182 u32 error_code;
1183
1184 fault_address = svm->vmcb->control.exit_info_2;
1185 error_code = svm->vmcb->control.exit_info_1;
1186
1187 trace_kvm_page_fault(fault_address, error_code);
1188 /*
1189 * FIXME: Tis shouldn't be necessary here, but there is a flush
1190 * missing in the MMU code. Until we find this bug, flush the
1191 * complete TLB here on an NPF
1192 */
1193 if (npt_enabled)
1194 svm_flush_tlb(&svm->vcpu);
1195 else {
1196 if (kvm_event_needs_reinjection(&svm->vcpu))
1197 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1198 }
1199 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1200 }
1201
1202 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1203 {
1204 if (!(svm->vcpu.guest_debug &
1205 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1206 !svm->vcpu.arch.singlestep) {
1207 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1208 return 1;
1209 }
1210
1211 if (svm->vcpu.arch.singlestep) {
1212 svm->vcpu.arch.singlestep = false;
1213 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1214 svm->vmcb->save.rflags &=
1215 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1216 update_db_intercept(&svm->vcpu);
1217 }
1218
1219 if (svm->vcpu.guest_debug &
1220 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1221 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1222 kvm_run->debug.arch.pc =
1223 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1224 kvm_run->debug.arch.exception = DB_VECTOR;
1225 return 0;
1226 }
1227
1228 return 1;
1229 }
1230
1231 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1232 {
1233 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1234 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1235 kvm_run->debug.arch.exception = BP_VECTOR;
1236 return 0;
1237 }
1238
1239 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1240 {
1241 int er;
1242
1243 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1244 if (er != EMULATE_DONE)
1245 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1246 return 1;
1247 }
1248
1249 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1250 {
1251 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1252 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1253 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1254 svm->vcpu.fpu_active = 1;
1255
1256 return 1;
1257 }
1258
1259 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1260 {
1261 /*
1262 * On an #MC intercept the MCE handler is not called automatically in
1263 * the host. So do it by hand here.
1264 */
1265 asm volatile (
1266 "int $0x12\n");
1267 /* not sure if we ever come back to this point */
1268
1269 return 1;
1270 }
1271
1272 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1273 {
1274 /*
1275 * VMCB is undefined after a SHUTDOWN intercept
1276 * so reinitialize it.
1277 */
1278 clear_page(svm->vmcb);
1279 init_vmcb(svm);
1280
1281 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1282 return 0;
1283 }
1284
1285 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1286 {
1287 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1288 int size, in, string;
1289 unsigned port;
1290
1291 ++svm->vcpu.stat.io_exits;
1292
1293 svm->next_rip = svm->vmcb->control.exit_info_2;
1294
1295 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1296
1297 if (string) {
1298 if (emulate_instruction(&svm->vcpu,
1299 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1300 return 0;
1301 return 1;
1302 }
1303
1304 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1305 port = io_info >> 16;
1306 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1307
1308 skip_emulated_instruction(&svm->vcpu);
1309 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1310 }
1311
1312 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1313 {
1314 return 1;
1315 }
1316
1317 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1318 {
1319 ++svm->vcpu.stat.irq_exits;
1320 return 1;
1321 }
1322
1323 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1324 {
1325 return 1;
1326 }
1327
1328 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1329 {
1330 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1331 skip_emulated_instruction(&svm->vcpu);
1332 return kvm_emulate_halt(&svm->vcpu);
1333 }
1334
1335 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1336 {
1337 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1338 skip_emulated_instruction(&svm->vcpu);
1339 kvm_emulate_hypercall(&svm->vcpu);
1340 return 1;
1341 }
1342
1343 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1344 {
1345 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1346 || !is_paging(&svm->vcpu)) {
1347 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1348 return 1;
1349 }
1350
1351 if (svm->vmcb->save.cpl) {
1352 kvm_inject_gp(&svm->vcpu, 0);
1353 return 1;
1354 }
1355
1356 return 0;
1357 }
1358
1359 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1360 bool has_error_code, u32 error_code)
1361 {
1362 if (!is_nested(svm))
1363 return 0;
1364
1365 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1366 svm->vmcb->control.exit_code_hi = 0;
1367 svm->vmcb->control.exit_info_1 = error_code;
1368 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1369
1370 return nested_svm_exit_handled(svm, false);
1371 }
1372
1373 static inline int nested_svm_intr(struct vcpu_svm *svm)
1374 {
1375 if (is_nested(svm)) {
1376 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1377 return 0;
1378
1379 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1380 return 0;
1381
1382 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1383
1384 if (nested_svm_exit_handled(svm, false)) {
1385 nsvm_printk("VMexit -> INTR\n");
1386 return 1;
1387 }
1388 }
1389
1390 return 0;
1391 }
1392
1393 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1394 {
1395 struct page *page;
1396
1397 down_read(&current->mm->mmap_sem);
1398 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1399 up_read(&current->mm->mmap_sem);
1400
1401 if (is_error_page(page))
1402 goto error;
1403
1404 return kmap_atomic(page, idx);
1405
1406 error:
1407 kvm_release_page_clean(page);
1408 kvm_inject_gp(&svm->vcpu, 0);
1409
1410 return NULL;
1411 }
1412
1413 static void nested_svm_unmap(void *addr, enum km_type idx)
1414 {
1415 struct page *page;
1416
1417 if (!addr)
1418 return;
1419
1420 page = kmap_atomic_to_page(addr);
1421
1422 kunmap_atomic(addr, idx);
1423 kvm_release_page_dirty(page);
1424 }
1425
1426 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1427 {
1428 struct page *page;
1429
1430 down_read(&current->mm->mmap_sem);
1431 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1432 up_read(&current->mm->mmap_sem);
1433
1434 if (is_error_page(page)) {
1435 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1436 __func__, gpa);
1437 kvm_release_page_clean(page);
1438 kvm_inject_gp(&svm->vcpu, 0);
1439 return NULL;
1440 }
1441 return page;
1442 }
1443
1444 static int nested_svm_do(struct vcpu_svm *svm,
1445 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1446 int (*handler)(struct vcpu_svm *svm,
1447 void *arg1,
1448 void *arg2,
1449 void *opaque))
1450 {
1451 struct page *arg1_page;
1452 struct page *arg2_page = NULL;
1453 void *arg1;
1454 void *arg2 = NULL;
1455 int retval;
1456
1457 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1458 if(arg1_page == NULL)
1459 return 1;
1460
1461 if (arg2_gpa) {
1462 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1463 if(arg2_page == NULL) {
1464 kvm_release_page_clean(arg1_page);
1465 return 1;
1466 }
1467 }
1468
1469 arg1 = kmap_atomic(arg1_page, KM_USER0);
1470 if (arg2_gpa)
1471 arg2 = kmap_atomic(arg2_page, KM_USER1);
1472
1473 retval = handler(svm, arg1, arg2, opaque);
1474
1475 kunmap_atomic(arg1, KM_USER0);
1476 if (arg2_gpa)
1477 kunmap_atomic(arg2, KM_USER1);
1478
1479 kvm_release_page_dirty(arg1_page);
1480 if (arg2_gpa)
1481 kvm_release_page_dirty(arg2_page);
1482
1483 return retval;
1484 }
1485
1486 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1487 {
1488 u32 param = svm->vmcb->control.exit_info_1 & 1;
1489 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1490 bool ret = false;
1491 u32 t0, t1;
1492 u8 *msrpm;
1493
1494 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1495 return false;
1496
1497 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1498
1499 if (!msrpm)
1500 goto out;
1501
1502 switch (msr) {
1503 case 0 ... 0x1fff:
1504 t0 = (msr * 2) % 8;
1505 t1 = msr / 8;
1506 break;
1507 case 0xc0000000 ... 0xc0001fff:
1508 t0 = (8192 + msr - 0xc0000000) * 2;
1509 t1 = (t0 / 8);
1510 t0 %= 8;
1511 break;
1512 case 0xc0010000 ... 0xc0011fff:
1513 t0 = (16384 + msr - 0xc0010000) * 2;
1514 t1 = (t0 / 8);
1515 t0 %= 8;
1516 break;
1517 default:
1518 ret = true;
1519 goto out;
1520 }
1521
1522 ret = msrpm[t1] & ((1 << param) << t0);
1523
1524 out:
1525 nested_svm_unmap(msrpm, KM_USER0);
1526
1527 return ret;
1528 }
1529
1530 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1531 {
1532 u32 exit_code = svm->vmcb->control.exit_code;
1533 bool vmexit = false;
1534
1535 if (kvm_override) {
1536 switch (exit_code) {
1537 case SVM_EXIT_INTR:
1538 case SVM_EXIT_NMI:
1539 return 0;
1540 /* For now we are always handling NPFs when using them */
1541 case SVM_EXIT_NPF:
1542 if (npt_enabled)
1543 return 0;
1544 break;
1545 /* When we're shadowing, trap PFs */
1546 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1547 if (!npt_enabled)
1548 return 0;
1549 break;
1550 default:
1551 break;
1552 }
1553 }
1554
1555 switch (exit_code) {
1556 case SVM_EXIT_MSR:
1557 vmexit = nested_svm_exit_handled_msr(svm);
1558 break;
1559 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1560 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1561 if (svm->nested.intercept_cr_read & cr_bits)
1562 vmexit = true;
1563 break;
1564 }
1565 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1566 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1567 if (svm->nested.intercept_cr_write & cr_bits)
1568 vmexit = true;
1569 break;
1570 }
1571 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1572 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1573 if (svm->nested.intercept_dr_read & dr_bits)
1574 vmexit = true;
1575 break;
1576 }
1577 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1578 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1579 if (svm->nested.intercept_dr_write & dr_bits)
1580 vmexit = true;
1581 break;
1582 }
1583 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1584 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1585 if (svm->nested.intercept_exceptions & excp_bits)
1586 vmexit = true;
1587 break;
1588 }
1589 default: {
1590 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1591 nsvm_printk("exit code: 0x%x\n", exit_code);
1592 if (svm->nested.intercept & exit_bits)
1593 vmexit = true;
1594 }
1595 }
1596
1597 if (vmexit) {
1598 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1599 nested_svm_vmexit(svm);
1600 }
1601
1602 return vmexit;
1603 }
1604
1605 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1606 {
1607 struct vmcb_control_area *dst = &dst_vmcb->control;
1608 struct vmcb_control_area *from = &from_vmcb->control;
1609
1610 dst->intercept_cr_read = from->intercept_cr_read;
1611 dst->intercept_cr_write = from->intercept_cr_write;
1612 dst->intercept_dr_read = from->intercept_dr_read;
1613 dst->intercept_dr_write = from->intercept_dr_write;
1614 dst->intercept_exceptions = from->intercept_exceptions;
1615 dst->intercept = from->intercept;
1616 dst->iopm_base_pa = from->iopm_base_pa;
1617 dst->msrpm_base_pa = from->msrpm_base_pa;
1618 dst->tsc_offset = from->tsc_offset;
1619 dst->asid = from->asid;
1620 dst->tlb_ctl = from->tlb_ctl;
1621 dst->int_ctl = from->int_ctl;
1622 dst->int_vector = from->int_vector;
1623 dst->int_state = from->int_state;
1624 dst->exit_code = from->exit_code;
1625 dst->exit_code_hi = from->exit_code_hi;
1626 dst->exit_info_1 = from->exit_info_1;
1627 dst->exit_info_2 = from->exit_info_2;
1628 dst->exit_int_info = from->exit_int_info;
1629 dst->exit_int_info_err = from->exit_int_info_err;
1630 dst->nested_ctl = from->nested_ctl;
1631 dst->event_inj = from->event_inj;
1632 dst->event_inj_err = from->event_inj_err;
1633 dst->nested_cr3 = from->nested_cr3;
1634 dst->lbr_ctl = from->lbr_ctl;
1635 }
1636
1637 static int nested_svm_vmexit(struct vcpu_svm *svm)
1638 {
1639 struct vmcb *nested_vmcb;
1640 struct vmcb *hsave = svm->nested.hsave;
1641 struct vmcb *vmcb = svm->vmcb;
1642
1643 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1644 if (!nested_vmcb)
1645 return 1;
1646
1647 /* Give the current vmcb to the guest */
1648 disable_gif(svm);
1649
1650 nested_vmcb->save.es = vmcb->save.es;
1651 nested_vmcb->save.cs = vmcb->save.cs;
1652 nested_vmcb->save.ss = vmcb->save.ss;
1653 nested_vmcb->save.ds = vmcb->save.ds;
1654 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1655 nested_vmcb->save.idtr = vmcb->save.idtr;
1656 if (npt_enabled)
1657 nested_vmcb->save.cr3 = vmcb->save.cr3;
1658 nested_vmcb->save.cr2 = vmcb->save.cr2;
1659 nested_vmcb->save.rflags = vmcb->save.rflags;
1660 nested_vmcb->save.rip = vmcb->save.rip;
1661 nested_vmcb->save.rsp = vmcb->save.rsp;
1662 nested_vmcb->save.rax = vmcb->save.rax;
1663 nested_vmcb->save.dr7 = vmcb->save.dr7;
1664 nested_vmcb->save.dr6 = vmcb->save.dr6;
1665 nested_vmcb->save.cpl = vmcb->save.cpl;
1666
1667 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1668 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1669 nested_vmcb->control.int_state = vmcb->control.int_state;
1670 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1671 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1672 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1673 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1674 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1675 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1676 nested_vmcb->control.tlb_ctl = 0;
1677 nested_vmcb->control.event_inj = 0;
1678 nested_vmcb->control.event_inj_err = 0;
1679
1680 /* We always set V_INTR_MASKING and remember the old value in hflags */
1681 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1682 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1683
1684 /* Restore the original control entries */
1685 copy_vmcb_control_area(vmcb, hsave);
1686
1687 /* Kill any pending exceptions */
1688 if (svm->vcpu.arch.exception.pending == true)
1689 nsvm_printk("WARNING: Pending Exception\n");
1690
1691 kvm_clear_exception_queue(&svm->vcpu);
1692 kvm_clear_interrupt_queue(&svm->vcpu);
1693
1694 /* Restore selected save entries */
1695 svm->vmcb->save.es = hsave->save.es;
1696 svm->vmcb->save.cs = hsave->save.cs;
1697 svm->vmcb->save.ss = hsave->save.ss;
1698 svm->vmcb->save.ds = hsave->save.ds;
1699 svm->vmcb->save.gdtr = hsave->save.gdtr;
1700 svm->vmcb->save.idtr = hsave->save.idtr;
1701 svm->vmcb->save.rflags = hsave->save.rflags;
1702 svm_set_efer(&svm->vcpu, hsave->save.efer);
1703 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1704 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1705 if (npt_enabled) {
1706 svm->vmcb->save.cr3 = hsave->save.cr3;
1707 svm->vcpu.arch.cr3 = hsave->save.cr3;
1708 } else {
1709 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1710 }
1711 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1712 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1713 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1714 svm->vmcb->save.dr7 = 0;
1715 svm->vmcb->save.cpl = 0;
1716 svm->vmcb->control.exit_int_info = 0;
1717
1718 /* Exit nested SVM mode */
1719 svm->nested.vmcb = 0;
1720
1721 nested_svm_unmap(nested_vmcb, KM_USER0);
1722
1723 kvm_mmu_reset_context(&svm->vcpu);
1724 kvm_mmu_load(&svm->vcpu);
1725
1726 return 0;
1727 }
1728
1729 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1730 void *arg2, void *opaque)
1731 {
1732 int i;
1733 u32 *nested_msrpm = (u32*)arg1;
1734 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1735 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1736 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1737
1738 return 0;
1739 }
1740
1741 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1742 void *arg2, void *opaque)
1743 {
1744 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1745 struct vmcb *hsave = svm->nested.hsave;
1746 struct vmcb *vmcb = svm->vmcb;
1747
1748 /* nested_vmcb is our indicator if nested SVM is activated */
1749 svm->nested.vmcb = svm->vmcb->save.rax;
1750
1751 /* Clear internal status */
1752 kvm_clear_exception_queue(&svm->vcpu);
1753 kvm_clear_interrupt_queue(&svm->vcpu);
1754
1755 /* Save the old vmcb, so we don't need to pick what we save, but
1756 can restore everything when a VMEXIT occurs */
1757 hsave->save.es = vmcb->save.es;
1758 hsave->save.cs = vmcb->save.cs;
1759 hsave->save.ss = vmcb->save.ss;
1760 hsave->save.ds = vmcb->save.ds;
1761 hsave->save.gdtr = vmcb->save.gdtr;
1762 hsave->save.idtr = vmcb->save.idtr;
1763 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1764 hsave->save.cr0 = svm->vcpu.arch.cr0;
1765 hsave->save.cr4 = svm->vcpu.arch.cr4;
1766 hsave->save.rflags = vmcb->save.rflags;
1767 hsave->save.rip = svm->next_rip;
1768 hsave->save.rsp = vmcb->save.rsp;
1769 hsave->save.rax = vmcb->save.rax;
1770 if (npt_enabled)
1771 hsave->save.cr3 = vmcb->save.cr3;
1772 else
1773 hsave->save.cr3 = svm->vcpu.arch.cr3;
1774
1775 copy_vmcb_control_area(hsave, vmcb);
1776
1777 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1778 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1779 else
1780 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1781
1782 /* Load the nested guest state */
1783 svm->vmcb->save.es = nested_vmcb->save.es;
1784 svm->vmcb->save.cs = nested_vmcb->save.cs;
1785 svm->vmcb->save.ss = nested_vmcb->save.ss;
1786 svm->vmcb->save.ds = nested_vmcb->save.ds;
1787 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1788 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1789 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1790 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1791 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1792 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1793 if (npt_enabled) {
1794 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1795 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1796 } else {
1797 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1798 kvm_mmu_reset_context(&svm->vcpu);
1799 }
1800 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1801 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1802 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1803 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1804 /* In case we don't even reach vcpu_run, the fields are not updated */
1805 svm->vmcb->save.rax = nested_vmcb->save.rax;
1806 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1807 svm->vmcb->save.rip = nested_vmcb->save.rip;
1808 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1809 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1810 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1811
1812 /* We don't want a nested guest to be more powerful than the guest,
1813 so all intercepts are ORed */
1814 svm->vmcb->control.intercept_cr_read |=
1815 nested_vmcb->control.intercept_cr_read;
1816 svm->vmcb->control.intercept_cr_write |=
1817 nested_vmcb->control.intercept_cr_write;
1818 svm->vmcb->control.intercept_dr_read |=
1819 nested_vmcb->control.intercept_dr_read;
1820 svm->vmcb->control.intercept_dr_write |=
1821 nested_vmcb->control.intercept_dr_write;
1822 svm->vmcb->control.intercept_exceptions |=
1823 nested_vmcb->control.intercept_exceptions;
1824
1825 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1826
1827 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1828
1829 /* cache intercepts */
1830 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1831 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1832 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1833 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1834 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1835 svm->nested.intercept = nested_vmcb->control.intercept;
1836
1837 force_new_asid(&svm->vcpu);
1838 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1839 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1840 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1841 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1842 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1843 nested_vmcb->control.int_ctl);
1844 }
1845 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1846 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1847 else
1848 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1849
1850 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1851 nested_vmcb->control.exit_int_info,
1852 nested_vmcb->control.int_state);
1853
1854 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1855 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1856 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1857 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1858 nsvm_printk("Injecting Event: 0x%x\n",
1859 nested_vmcb->control.event_inj);
1860 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1861 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1862
1863 enable_gif(svm);
1864
1865 return 0;
1866 }
1867
1868 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1869 {
1870 to_vmcb->save.fs = from_vmcb->save.fs;
1871 to_vmcb->save.gs = from_vmcb->save.gs;
1872 to_vmcb->save.tr = from_vmcb->save.tr;
1873 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1874 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1875 to_vmcb->save.star = from_vmcb->save.star;
1876 to_vmcb->save.lstar = from_vmcb->save.lstar;
1877 to_vmcb->save.cstar = from_vmcb->save.cstar;
1878 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1879 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1880 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1881 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1882
1883 return 1;
1884 }
1885
1886 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1887 void *arg2, void *opaque)
1888 {
1889 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1890 }
1891
1892 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1893 void *arg2, void *opaque)
1894 {
1895 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1896 }
1897
1898 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1899 {
1900 if (nested_svm_check_permissions(svm))
1901 return 1;
1902
1903 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1904 skip_emulated_instruction(&svm->vcpu);
1905
1906 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1907
1908 return 1;
1909 }
1910
1911 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1912 {
1913 if (nested_svm_check_permissions(svm))
1914 return 1;
1915
1916 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1917 skip_emulated_instruction(&svm->vcpu);
1918
1919 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1920
1921 return 1;
1922 }
1923
1924 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1925 {
1926 nsvm_printk("VMrun\n");
1927 if (nested_svm_check_permissions(svm))
1928 return 1;
1929
1930 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1931 skip_emulated_instruction(&svm->vcpu);
1932
1933 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1934 NULL, nested_svm_vmrun))
1935 return 1;
1936
1937 if (nested_svm_do(svm, svm->nested.vmcb_msrpm, 0,
1938 NULL, nested_svm_vmrun_msrpm))
1939 return 1;
1940
1941 return 1;
1942 }
1943
1944 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1945 {
1946 if (nested_svm_check_permissions(svm))
1947 return 1;
1948
1949 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1950 skip_emulated_instruction(&svm->vcpu);
1951
1952 enable_gif(svm);
1953
1954 return 1;
1955 }
1956
1957 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1958 {
1959 if (nested_svm_check_permissions(svm))
1960 return 1;
1961
1962 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1963 skip_emulated_instruction(&svm->vcpu);
1964
1965 disable_gif(svm);
1966
1967 /* After a CLGI no interrupts should come */
1968 svm_clear_vintr(svm);
1969 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1970
1971 return 1;
1972 }
1973
1974 static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1975 {
1976 struct kvm_vcpu *vcpu = &svm->vcpu;
1977 nsvm_printk("INVLPGA\n");
1978
1979 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1980 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1981
1982 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1983 skip_emulated_instruction(&svm->vcpu);
1984 return 1;
1985 }
1986
1987 static int invalid_op_interception(struct vcpu_svm *svm,
1988 struct kvm_run *kvm_run)
1989 {
1990 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1991 return 1;
1992 }
1993
1994 static int task_switch_interception(struct vcpu_svm *svm,
1995 struct kvm_run *kvm_run)
1996 {
1997 u16 tss_selector;
1998 int reason;
1999 int int_type = svm->vmcb->control.exit_int_info &
2000 SVM_EXITINTINFO_TYPE_MASK;
2001 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2002 uint32_t type =
2003 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2004 uint32_t idt_v =
2005 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2006
2007 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2008
2009 if (svm->vmcb->control.exit_info_2 &
2010 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2011 reason = TASK_SWITCH_IRET;
2012 else if (svm->vmcb->control.exit_info_2 &
2013 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2014 reason = TASK_SWITCH_JMP;
2015 else if (idt_v)
2016 reason = TASK_SWITCH_GATE;
2017 else
2018 reason = TASK_SWITCH_CALL;
2019
2020 if (reason == TASK_SWITCH_GATE) {
2021 switch (type) {
2022 case SVM_EXITINTINFO_TYPE_NMI:
2023 svm->vcpu.arch.nmi_injected = false;
2024 break;
2025 case SVM_EXITINTINFO_TYPE_EXEPT:
2026 kvm_clear_exception_queue(&svm->vcpu);
2027 break;
2028 case SVM_EXITINTINFO_TYPE_INTR:
2029 kvm_clear_interrupt_queue(&svm->vcpu);
2030 break;
2031 default:
2032 break;
2033 }
2034 }
2035
2036 if (reason != TASK_SWITCH_GATE ||
2037 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2038 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2039 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2040 skip_emulated_instruction(&svm->vcpu);
2041
2042 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2043 }
2044
2045 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2046 {
2047 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2048 kvm_emulate_cpuid(&svm->vcpu);
2049 return 1;
2050 }
2051
2052 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2053 {
2054 ++svm->vcpu.stat.nmi_window_exits;
2055 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2056 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2057 return 1;
2058 }
2059
2060 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2061 {
2062 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2063 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2064 return 1;
2065 }
2066
2067 static int emulate_on_interception(struct vcpu_svm *svm,
2068 struct kvm_run *kvm_run)
2069 {
2070 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
2071 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2072 return 1;
2073 }
2074
2075 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2076 {
2077 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2078 /* instruction emulation calls kvm_set_cr8() */
2079 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
2080 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2081 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2082 return 1;
2083 }
2084 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2085 return 1;
2086 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2087 return 0;
2088 }
2089
2090 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2091 {
2092 struct vcpu_svm *svm = to_svm(vcpu);
2093
2094 switch (ecx) {
2095 case MSR_IA32_TSC: {
2096 u64 tsc;
2097
2098 rdtscll(tsc);
2099 *data = svm->vmcb->control.tsc_offset + tsc;
2100 break;
2101 }
2102 case MSR_K6_STAR:
2103 *data = svm->vmcb->save.star;
2104 break;
2105 #ifdef CONFIG_X86_64
2106 case MSR_LSTAR:
2107 *data = svm->vmcb->save.lstar;
2108 break;
2109 case MSR_CSTAR:
2110 *data = svm->vmcb->save.cstar;
2111 break;
2112 case MSR_KERNEL_GS_BASE:
2113 *data = svm->vmcb->save.kernel_gs_base;
2114 break;
2115 case MSR_SYSCALL_MASK:
2116 *data = svm->vmcb->save.sfmask;
2117 break;
2118 #endif
2119 case MSR_IA32_SYSENTER_CS:
2120 *data = svm->vmcb->save.sysenter_cs;
2121 break;
2122 case MSR_IA32_SYSENTER_EIP:
2123 *data = svm->sysenter_eip;
2124 break;
2125 case MSR_IA32_SYSENTER_ESP:
2126 *data = svm->sysenter_esp;
2127 break;
2128 /* Nobody will change the following 5 values in the VMCB so
2129 we can safely return them on rdmsr. They will always be 0
2130 until LBRV is implemented. */
2131 case MSR_IA32_DEBUGCTLMSR:
2132 *data = svm->vmcb->save.dbgctl;
2133 break;
2134 case MSR_IA32_LASTBRANCHFROMIP:
2135 *data = svm->vmcb->save.br_from;
2136 break;
2137 case MSR_IA32_LASTBRANCHTOIP:
2138 *data = svm->vmcb->save.br_to;
2139 break;
2140 case MSR_IA32_LASTINTFROMIP:
2141 *data = svm->vmcb->save.last_excp_from;
2142 break;
2143 case MSR_IA32_LASTINTTOIP:
2144 *data = svm->vmcb->save.last_excp_to;
2145 break;
2146 case MSR_VM_HSAVE_PA:
2147 *data = svm->nested.hsave_msr;
2148 break;
2149 case MSR_VM_CR:
2150 *data = 0;
2151 break;
2152 case MSR_IA32_UCODE_REV:
2153 *data = 0x01000065;
2154 break;
2155 default:
2156 return kvm_get_msr_common(vcpu, ecx, data);
2157 }
2158 return 0;
2159 }
2160
2161 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2162 {
2163 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2164 u64 data;
2165
2166 if (svm_get_msr(&svm->vcpu, ecx, &data))
2167 kvm_inject_gp(&svm->vcpu, 0);
2168 else {
2169 trace_kvm_msr_read(ecx, data);
2170
2171 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2172 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2173 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2174 skip_emulated_instruction(&svm->vcpu);
2175 }
2176 return 1;
2177 }
2178
2179 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2180 {
2181 struct vcpu_svm *svm = to_svm(vcpu);
2182
2183 switch (ecx) {
2184 case MSR_IA32_TSC: {
2185 u64 tsc;
2186
2187 rdtscll(tsc);
2188 svm->vmcb->control.tsc_offset = data - tsc;
2189 break;
2190 }
2191 case MSR_K6_STAR:
2192 svm->vmcb->save.star = data;
2193 break;
2194 #ifdef CONFIG_X86_64
2195 case MSR_LSTAR:
2196 svm->vmcb->save.lstar = data;
2197 break;
2198 case MSR_CSTAR:
2199 svm->vmcb->save.cstar = data;
2200 break;
2201 case MSR_KERNEL_GS_BASE:
2202 svm->vmcb->save.kernel_gs_base = data;
2203 break;
2204 case MSR_SYSCALL_MASK:
2205 svm->vmcb->save.sfmask = data;
2206 break;
2207 #endif
2208 case MSR_IA32_SYSENTER_CS:
2209 svm->vmcb->save.sysenter_cs = data;
2210 break;
2211 case MSR_IA32_SYSENTER_EIP:
2212 svm->sysenter_eip = data;
2213 svm->vmcb->save.sysenter_eip = data;
2214 break;
2215 case MSR_IA32_SYSENTER_ESP:
2216 svm->sysenter_esp = data;
2217 svm->vmcb->save.sysenter_esp = data;
2218 break;
2219 case MSR_IA32_DEBUGCTLMSR:
2220 if (!svm_has(SVM_FEATURE_LBRV)) {
2221 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2222 __func__, data);
2223 break;
2224 }
2225 if (data & DEBUGCTL_RESERVED_BITS)
2226 return 1;
2227
2228 svm->vmcb->save.dbgctl = data;
2229 if (data & (1ULL<<0))
2230 svm_enable_lbrv(svm);
2231 else
2232 svm_disable_lbrv(svm);
2233 break;
2234 case MSR_VM_HSAVE_PA:
2235 svm->nested.hsave_msr = data;
2236 break;
2237 case MSR_VM_CR:
2238 case MSR_VM_IGNNE:
2239 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2240 break;
2241 default:
2242 return kvm_set_msr_common(vcpu, ecx, data);
2243 }
2244 return 0;
2245 }
2246
2247 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2248 {
2249 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2250 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2251 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2252
2253 trace_kvm_msr_write(ecx, data);
2254
2255 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2256 if (svm_set_msr(&svm->vcpu, ecx, data))
2257 kvm_inject_gp(&svm->vcpu, 0);
2258 else
2259 skip_emulated_instruction(&svm->vcpu);
2260 return 1;
2261 }
2262
2263 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2264 {
2265 if (svm->vmcb->control.exit_info_1)
2266 return wrmsr_interception(svm, kvm_run);
2267 else
2268 return rdmsr_interception(svm, kvm_run);
2269 }
2270
2271 static int interrupt_window_interception(struct vcpu_svm *svm,
2272 struct kvm_run *kvm_run)
2273 {
2274 svm_clear_vintr(svm);
2275 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2276 /*
2277 * If the user space waits to inject interrupts, exit as soon as
2278 * possible
2279 */
2280 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2281 kvm_run->request_interrupt_window &&
2282 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2283 ++svm->vcpu.stat.irq_window_exits;
2284 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2285 return 0;
2286 }
2287
2288 return 1;
2289 }
2290
2291 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2292 struct kvm_run *kvm_run) = {
2293 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2294 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2295 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2296 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2297 /* for now: */
2298 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2299 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2300 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2301 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2302 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2303 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2304 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2305 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2306 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2307 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2308 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2309 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2310 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2311 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2312 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2313 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2314 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2315 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2316 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2317 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2318 [SVM_EXIT_INTR] = intr_interception,
2319 [SVM_EXIT_NMI] = nmi_interception,
2320 [SVM_EXIT_SMI] = nop_on_interception,
2321 [SVM_EXIT_INIT] = nop_on_interception,
2322 [SVM_EXIT_VINTR] = interrupt_window_interception,
2323 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2324 [SVM_EXIT_CPUID] = cpuid_interception,
2325 [SVM_EXIT_IRET] = iret_interception,
2326 [SVM_EXIT_INVD] = emulate_on_interception,
2327 [SVM_EXIT_HLT] = halt_interception,
2328 [SVM_EXIT_INVLPG] = invlpg_interception,
2329 [SVM_EXIT_INVLPGA] = invlpga_interception,
2330 [SVM_EXIT_IOIO] = io_interception,
2331 [SVM_EXIT_MSR] = msr_interception,
2332 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2333 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2334 [SVM_EXIT_VMRUN] = vmrun_interception,
2335 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2336 [SVM_EXIT_VMLOAD] = vmload_interception,
2337 [SVM_EXIT_VMSAVE] = vmsave_interception,
2338 [SVM_EXIT_STGI] = stgi_interception,
2339 [SVM_EXIT_CLGI] = clgi_interception,
2340 [SVM_EXIT_SKINIT] = invalid_op_interception,
2341 [SVM_EXIT_WBINVD] = emulate_on_interception,
2342 [SVM_EXIT_MONITOR] = invalid_op_interception,
2343 [SVM_EXIT_MWAIT] = invalid_op_interception,
2344 [SVM_EXIT_NPF] = pf_interception,
2345 };
2346
2347 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2348 {
2349 struct vcpu_svm *svm = to_svm(vcpu);
2350 u32 exit_code = svm->vmcb->control.exit_code;
2351
2352 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2353
2354 if (is_nested(svm)) {
2355 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2356 exit_code, svm->vmcb->control.exit_info_1,
2357 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2358 if (nested_svm_exit_handled(svm, true))
2359 return 1;
2360 }
2361
2362 svm_complete_interrupts(svm);
2363
2364 if (npt_enabled) {
2365 int mmu_reload = 0;
2366 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2367 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2368 mmu_reload = 1;
2369 }
2370 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2371 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2372 if (mmu_reload) {
2373 kvm_mmu_reset_context(vcpu);
2374 kvm_mmu_load(vcpu);
2375 }
2376 }
2377
2378
2379 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2380 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2381 kvm_run->fail_entry.hardware_entry_failure_reason
2382 = svm->vmcb->control.exit_code;
2383 return 0;
2384 }
2385
2386 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2387 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2388 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2389 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2390 "exit_code 0x%x\n",
2391 __func__, svm->vmcb->control.exit_int_info,
2392 exit_code);
2393
2394 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2395 || !svm_exit_handlers[exit_code]) {
2396 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2397 kvm_run->hw.hardware_exit_reason = exit_code;
2398 return 0;
2399 }
2400
2401 return svm_exit_handlers[exit_code](svm, kvm_run);
2402 }
2403
2404 static void reload_tss(struct kvm_vcpu *vcpu)
2405 {
2406 int cpu = raw_smp_processor_id();
2407
2408 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2409 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2410 load_TR_desc();
2411 }
2412
2413 static void pre_svm_run(struct vcpu_svm *svm)
2414 {
2415 int cpu = raw_smp_processor_id();
2416
2417 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2418
2419 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2420 /* FIXME: handle wraparound of asid_generation */
2421 if (svm->asid_generation != svm_data->asid_generation)
2422 new_asid(svm, svm_data);
2423 }
2424
2425 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2426 {
2427 struct vcpu_svm *svm = to_svm(vcpu);
2428
2429 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2430 vcpu->arch.hflags |= HF_NMI_MASK;
2431 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2432 ++vcpu->stat.nmi_injections;
2433 }
2434
2435 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2436 {
2437 struct vmcb_control_area *control;
2438
2439 trace_kvm_inj_virq(irq);
2440
2441 ++svm->vcpu.stat.irq_injections;
2442 control = &svm->vmcb->control;
2443 control->int_vector = irq;
2444 control->int_ctl &= ~V_INTR_PRIO_MASK;
2445 control->int_ctl |= V_IRQ_MASK |
2446 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2447 }
2448
2449 static void svm_set_irq(struct kvm_vcpu *vcpu)
2450 {
2451 struct vcpu_svm *svm = to_svm(vcpu);
2452
2453 BUG_ON(!(gif_set(svm)));
2454
2455 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2456 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2457 }
2458
2459 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2460 {
2461 struct vcpu_svm *svm = to_svm(vcpu);
2462
2463 if (irr == -1)
2464 return;
2465
2466 if (tpr >= irr)
2467 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2468 }
2469
2470 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2471 {
2472 struct vcpu_svm *svm = to_svm(vcpu);
2473 struct vmcb *vmcb = svm->vmcb;
2474 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2475 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2476 }
2477
2478 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2479 {
2480 struct vcpu_svm *svm = to_svm(vcpu);
2481 struct vmcb *vmcb = svm->vmcb;
2482 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2483 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2484 gif_set(svm) &&
2485 !is_nested(svm);
2486 }
2487
2488 static void enable_irq_window(struct kvm_vcpu *vcpu)
2489 {
2490 struct vcpu_svm *svm = to_svm(vcpu);
2491 nsvm_printk("Trying to open IRQ window\n");
2492
2493 nested_svm_intr(svm);
2494
2495 /* In case GIF=0 we can't rely on the CPU to tell us when
2496 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2497 * The next time we get that intercept, this function will be
2498 * called again though and we'll get the vintr intercept. */
2499 if (gif_set(svm)) {
2500 svm_set_vintr(svm);
2501 svm_inject_irq(svm, 0x0);
2502 }
2503 }
2504
2505 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2506 {
2507 struct vcpu_svm *svm = to_svm(vcpu);
2508
2509 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2510 == HF_NMI_MASK)
2511 return; /* IRET will cause a vm exit */
2512
2513 /* Something prevents NMI from been injected. Single step over
2514 possible problem (IRET or exception injection or interrupt
2515 shadow) */
2516 vcpu->arch.singlestep = true;
2517 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2518 update_db_intercept(vcpu);
2519 }
2520
2521 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2522 {
2523 return 0;
2524 }
2525
2526 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2527 {
2528 force_new_asid(vcpu);
2529 }
2530
2531 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2532 {
2533 }
2534
2535 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2536 {
2537 struct vcpu_svm *svm = to_svm(vcpu);
2538
2539 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2540 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2541 kvm_set_cr8(vcpu, cr8);
2542 }
2543 }
2544
2545 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2546 {
2547 struct vcpu_svm *svm = to_svm(vcpu);
2548 u64 cr8;
2549
2550 cr8 = kvm_get_cr8(vcpu);
2551 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2552 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2553 }
2554
2555 static void svm_complete_interrupts(struct vcpu_svm *svm)
2556 {
2557 u8 vector;
2558 int type;
2559 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2560
2561 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2562 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2563
2564 svm->vcpu.arch.nmi_injected = false;
2565 kvm_clear_exception_queue(&svm->vcpu);
2566 kvm_clear_interrupt_queue(&svm->vcpu);
2567
2568 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2569 return;
2570
2571 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2572 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2573
2574 switch (type) {
2575 case SVM_EXITINTINFO_TYPE_NMI:
2576 svm->vcpu.arch.nmi_injected = true;
2577 break;
2578 case SVM_EXITINTINFO_TYPE_EXEPT:
2579 /* In case of software exception do not reinject an exception
2580 vector, but re-execute and instruction instead */
2581 if (is_nested(svm))
2582 break;
2583 if (kvm_exception_is_soft(vector))
2584 break;
2585 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2586 u32 err = svm->vmcb->control.exit_int_info_err;
2587 kvm_queue_exception_e(&svm->vcpu, vector, err);
2588
2589 } else
2590 kvm_queue_exception(&svm->vcpu, vector);
2591 break;
2592 case SVM_EXITINTINFO_TYPE_INTR:
2593 kvm_queue_interrupt(&svm->vcpu, vector, false);
2594 break;
2595 default:
2596 break;
2597 }
2598 }
2599
2600 #ifdef CONFIG_X86_64
2601 #define R "r"
2602 #else
2603 #define R "e"
2604 #endif
2605
2606 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2607 {
2608 struct vcpu_svm *svm = to_svm(vcpu);
2609 u16 fs_selector;
2610 u16 gs_selector;
2611 u16 ldt_selector;
2612
2613 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2614 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2615 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2616
2617 pre_svm_run(svm);
2618
2619 sync_lapic_to_cr8(vcpu);
2620
2621 save_host_msrs(vcpu);
2622 fs_selector = kvm_read_fs();
2623 gs_selector = kvm_read_gs();
2624 ldt_selector = kvm_read_ldt();
2625 if (!is_nested(svm))
2626 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2627 /* required for live migration with NPT */
2628 if (npt_enabled)
2629 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2630
2631 clgi();
2632
2633 local_irq_enable();
2634
2635 asm volatile (
2636 "push %%"R"bp; \n\t"
2637 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2638 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2639 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2640 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2641 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2642 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2643 #ifdef CONFIG_X86_64
2644 "mov %c[r8](%[svm]), %%r8 \n\t"
2645 "mov %c[r9](%[svm]), %%r9 \n\t"
2646 "mov %c[r10](%[svm]), %%r10 \n\t"
2647 "mov %c[r11](%[svm]), %%r11 \n\t"
2648 "mov %c[r12](%[svm]), %%r12 \n\t"
2649 "mov %c[r13](%[svm]), %%r13 \n\t"
2650 "mov %c[r14](%[svm]), %%r14 \n\t"
2651 "mov %c[r15](%[svm]), %%r15 \n\t"
2652 #endif
2653
2654 /* Enter guest mode */
2655 "push %%"R"ax \n\t"
2656 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2657 __ex(SVM_VMLOAD) "\n\t"
2658 __ex(SVM_VMRUN) "\n\t"
2659 __ex(SVM_VMSAVE) "\n\t"
2660 "pop %%"R"ax \n\t"
2661
2662 /* Save guest registers, load host registers */
2663 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2664 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2665 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2666 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2667 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2668 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2669 #ifdef CONFIG_X86_64
2670 "mov %%r8, %c[r8](%[svm]) \n\t"
2671 "mov %%r9, %c[r9](%[svm]) \n\t"
2672 "mov %%r10, %c[r10](%[svm]) \n\t"
2673 "mov %%r11, %c[r11](%[svm]) \n\t"
2674 "mov %%r12, %c[r12](%[svm]) \n\t"
2675 "mov %%r13, %c[r13](%[svm]) \n\t"
2676 "mov %%r14, %c[r14](%[svm]) \n\t"
2677 "mov %%r15, %c[r15](%[svm]) \n\t"
2678 #endif
2679 "pop %%"R"bp"
2680 :
2681 : [svm]"a"(svm),
2682 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2683 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2684 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2685 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2686 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2687 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2688 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2689 #ifdef CONFIG_X86_64
2690 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2691 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2692 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2693 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2694 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2695 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2696 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2697 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2698 #endif
2699 : "cc", "memory"
2700 , R"bx", R"cx", R"dx", R"si", R"di"
2701 #ifdef CONFIG_X86_64
2702 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2703 #endif
2704 );
2705
2706 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2707 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2708 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2709 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2710
2711 kvm_load_fs(fs_selector);
2712 kvm_load_gs(gs_selector);
2713 kvm_load_ldt(ldt_selector);
2714 load_host_msrs(vcpu);
2715
2716 reload_tss(vcpu);
2717
2718 local_irq_disable();
2719
2720 stgi();
2721
2722 sync_cr8_to_lapic(vcpu);
2723
2724 svm->next_rip = 0;
2725
2726 if (npt_enabled) {
2727 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2728 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2729 }
2730 }
2731
2732 #undef R
2733
2734 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2735 {
2736 struct vcpu_svm *svm = to_svm(vcpu);
2737
2738 if (npt_enabled) {
2739 svm->vmcb->control.nested_cr3 = root;
2740 force_new_asid(vcpu);
2741 return;
2742 }
2743
2744 svm->vmcb->save.cr3 = root;
2745 force_new_asid(vcpu);
2746
2747 if (vcpu->fpu_active) {
2748 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2749 svm->vmcb->save.cr0 |= X86_CR0_TS;
2750 vcpu->fpu_active = 0;
2751 }
2752 }
2753
2754 static int is_disabled(void)
2755 {
2756 u64 vm_cr;
2757
2758 rdmsrl(MSR_VM_CR, vm_cr);
2759 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2760 return 1;
2761
2762 return 0;
2763 }
2764
2765 static void
2766 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2767 {
2768 /*
2769 * Patch in the VMMCALL instruction:
2770 */
2771 hypercall[0] = 0x0f;
2772 hypercall[1] = 0x01;
2773 hypercall[2] = 0xd9;
2774 }
2775
2776 static void svm_check_processor_compat(void *rtn)
2777 {
2778 *(int *)rtn = 0;
2779 }
2780
2781 static bool svm_cpu_has_accelerated_tpr(void)
2782 {
2783 return false;
2784 }
2785
2786 static int get_npt_level(void)
2787 {
2788 #ifdef CONFIG_X86_64
2789 return PT64_ROOT_LEVEL;
2790 #else
2791 return PT32E_ROOT_LEVEL;
2792 #endif
2793 }
2794
2795 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2796 {
2797 return 0;
2798 }
2799
2800 static const struct trace_print_flags svm_exit_reasons_str[] = {
2801 { SVM_EXIT_READ_CR0, "read_cr0" },
2802 { SVM_EXIT_READ_CR3, "read_cr3" },
2803 { SVM_EXIT_READ_CR4, "read_cr4" },
2804 { SVM_EXIT_READ_CR8, "read_cr8" },
2805 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2806 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2807 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2808 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2809 { SVM_EXIT_READ_DR0, "read_dr0" },
2810 { SVM_EXIT_READ_DR1, "read_dr1" },
2811 { SVM_EXIT_READ_DR2, "read_dr2" },
2812 { SVM_EXIT_READ_DR3, "read_dr3" },
2813 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2814 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2815 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2816 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2817 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2818 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2819 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2820 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2821 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2822 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2823 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2824 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2825 { SVM_EXIT_INTR, "interrupt" },
2826 { SVM_EXIT_NMI, "nmi" },
2827 { SVM_EXIT_SMI, "smi" },
2828 { SVM_EXIT_INIT, "init" },
2829 { SVM_EXIT_VINTR, "vintr" },
2830 { SVM_EXIT_CPUID, "cpuid" },
2831 { SVM_EXIT_INVD, "invd" },
2832 { SVM_EXIT_HLT, "hlt" },
2833 { SVM_EXIT_INVLPG, "invlpg" },
2834 { SVM_EXIT_INVLPGA, "invlpga" },
2835 { SVM_EXIT_IOIO, "io" },
2836 { SVM_EXIT_MSR, "msr" },
2837 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2838 { SVM_EXIT_SHUTDOWN, "shutdown" },
2839 { SVM_EXIT_VMRUN, "vmrun" },
2840 { SVM_EXIT_VMMCALL, "hypercall" },
2841 { SVM_EXIT_VMLOAD, "vmload" },
2842 { SVM_EXIT_VMSAVE, "vmsave" },
2843 { SVM_EXIT_STGI, "stgi" },
2844 { SVM_EXIT_CLGI, "clgi" },
2845 { SVM_EXIT_SKINIT, "skinit" },
2846 { SVM_EXIT_WBINVD, "wbinvd" },
2847 { SVM_EXIT_MONITOR, "monitor" },
2848 { SVM_EXIT_MWAIT, "mwait" },
2849 { SVM_EXIT_NPF, "npf" },
2850 { -1, NULL }
2851 };
2852
2853 static bool svm_gb_page_enable(void)
2854 {
2855 return true;
2856 }
2857
2858 static struct kvm_x86_ops svm_x86_ops = {
2859 .cpu_has_kvm_support = has_svm,
2860 .disabled_by_bios = is_disabled,
2861 .hardware_setup = svm_hardware_setup,
2862 .hardware_unsetup = svm_hardware_unsetup,
2863 .check_processor_compatibility = svm_check_processor_compat,
2864 .hardware_enable = svm_hardware_enable,
2865 .hardware_disable = svm_hardware_disable,
2866 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2867
2868 .vcpu_create = svm_create_vcpu,
2869 .vcpu_free = svm_free_vcpu,
2870 .vcpu_reset = svm_vcpu_reset,
2871
2872 .prepare_guest_switch = svm_prepare_guest_switch,
2873 .vcpu_load = svm_vcpu_load,
2874 .vcpu_put = svm_vcpu_put,
2875
2876 .set_guest_debug = svm_guest_debug,
2877 .get_msr = svm_get_msr,
2878 .set_msr = svm_set_msr,
2879 .get_segment_base = svm_get_segment_base,
2880 .get_segment = svm_get_segment,
2881 .set_segment = svm_set_segment,
2882 .get_cpl = svm_get_cpl,
2883 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2884 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2885 .set_cr0 = svm_set_cr0,
2886 .set_cr3 = svm_set_cr3,
2887 .set_cr4 = svm_set_cr4,
2888 .set_efer = svm_set_efer,
2889 .get_idt = svm_get_idt,
2890 .set_idt = svm_set_idt,
2891 .get_gdt = svm_get_gdt,
2892 .set_gdt = svm_set_gdt,
2893 .get_dr = svm_get_dr,
2894 .set_dr = svm_set_dr,
2895 .cache_reg = svm_cache_reg,
2896 .get_rflags = svm_get_rflags,
2897 .set_rflags = svm_set_rflags,
2898
2899 .tlb_flush = svm_flush_tlb,
2900
2901 .run = svm_vcpu_run,
2902 .handle_exit = handle_exit,
2903 .skip_emulated_instruction = skip_emulated_instruction,
2904 .set_interrupt_shadow = svm_set_interrupt_shadow,
2905 .get_interrupt_shadow = svm_get_interrupt_shadow,
2906 .patch_hypercall = svm_patch_hypercall,
2907 .set_irq = svm_set_irq,
2908 .set_nmi = svm_inject_nmi,
2909 .queue_exception = svm_queue_exception,
2910 .interrupt_allowed = svm_interrupt_allowed,
2911 .nmi_allowed = svm_nmi_allowed,
2912 .enable_nmi_window = enable_nmi_window,
2913 .enable_irq_window = enable_irq_window,
2914 .update_cr8_intercept = update_cr8_intercept,
2915
2916 .set_tss_addr = svm_set_tss_addr,
2917 .get_tdp_level = get_npt_level,
2918 .get_mt_mask = svm_get_mt_mask,
2919
2920 .exit_reasons_str = svm_exit_reasons_str,
2921 .gb_page_enable = svm_gb_page_enable,
2922 };
2923
2924 static int __init svm_init(void)
2925 {
2926 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2927 THIS_MODULE);
2928 }
2929
2930 static void __exit svm_exit(void)
2931 {
2932 kvm_exit();
2933 }
2934
2935 module_init(svm_init)
2936 module_exit(svm_exit)
Linux 2.6 libata-dev (mirror)