include/linux/clk-provider.h

   1 /*
   2  *  linux/include/linux/clk-provider.h
   3  *
   4  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
   5  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #ifndef __LINUX_CLK_PROVIDER_H
  12 #define __LINUX_CLK_PROVIDER_H
  13
  14 #include <linux/clk.h>
  15
  16 #ifdef CONFIG_COMMON_CLK
  17
  18 /**
  19  * struct clk_hw - handle for traversing from a struct clk to its corresponding
  20  * hardware-specific structure.  struct clk_hw should be declared within struct
  21  * clk_foo and then referenced by the struct clk instance that uses struct
  22  * clk_foo's clk_ops
  23  *
  24  * clk: pointer to the struct clk instance that points back to this struct
  25  * clk_hw instance
  26  */
  27 struct clk_hw {
  28         struct clk *clk;
  29 };
  30
  31 /*
  32  * flags used across common struct clk.  these flags should only affect the
  33  * top-level framework.  custom flags for dealing with hardware specifics
  34  * belong in struct clk_foo
  35  */
  36 #define CLK_SET_RATE_GATE       BIT(0) /* must be gated across rate change */
  37 #define CLK_SET_PARENT_GATE     BIT(1) /* must be gated across re-parent */
  38 #define CLK_SET_RATE_PARENT     BIT(2) /* propagate rate change up one level */
  39 #define CLK_IGNORE_UNUSED       BIT(3) /* do not gate even if unused */
  40 #define CLK_IS_ROOT             BIT(4) /* root clk, has no parent */
  41
  42 /**
  43  * struct clk_ops -  Callback operations for hardware clocks; these are to
  44  * be provided by the clock implementation, and will be called by drivers
  45  * through the clk_* api.
  46  *
  47  * @prepare:    Prepare the clock for enabling. This must not return until
  48  *              the clock is fully prepared, and it's safe to call clk_enable.
  49  *              This callback is intended to allow clock implementations to
  50  *              do any initialisation that may sleep. Called with
  51  *              prepare_lock held.
  52  *
  53  * @unprepare:  Release the clock from its prepared state. This will typically
  54  *              undo any work done in the @prepare callback. Called with
  55  *              prepare_lock held.
  56  *
  57  * @enable:     Enable the clock atomically. This must not return until the
  58  *              clock is generating a valid clock signal, usable by consumer
  59  *              devices. Called with enable_lock held. This function must not
  60  *              sleep.
  61  *
  62  * @disable:    Disable the clock atomically. Called with enable_lock held.
  63  *              This function must not sleep.
  64  *
  65  * @recalc_rate Recalculate the rate of this clock, by quering hardware.  The
  66  *              parent rate is an input parameter.  It is up to the caller to
  67  *              insure that the prepare_mutex is held across this call.
  68  *              Returns the calculated rate.  Optional, but recommended - if
  69  *              this op is not set then clock rate will be initialized to 0.
  70  *
  71  * @round_rate: Given a target rate as input, returns the closest rate actually
  72  *              supported by the clock.
  73  *
  74  * @get_parent: Queries the hardware to determine the parent of a clock.  The
  75  *              return value is a u8 which specifies the index corresponding to
  76  *              the parent clock.  This index can be applied to either the
  77  *              .parent_names or .parents arrays.  In short, this function
  78  *              translates the parent value read from hardware into an array
  79  *              index.  Currently only called when the clock is initialized by
  80  *              __clk_init.  This callback is mandatory for clocks with
  81  *              multiple parents.  It is optional (and unnecessary) for clocks
  82  *              with 0 or 1 parents.
  83  *
  84  * @set_parent: Change the input source of this clock; for clocks with multiple
  85  *              possible parents specify a new parent by passing in the index
  86  *              as a u8 corresponding to the parent in either the .parent_names
  87  *              or .parents arrays.  This function in affect translates an
  88  *              array index into the value programmed into the hardware.
  89  *              Returns 0 on success, -EERROR otherwise.
  90  *
  91  * @set_rate:   Change the rate of this clock. If this callback returns
  92  *              CLK_SET_RATE_PARENT, the rate change will be propagated to the
  93  *              parent clock (which may propagate again if the parent clock
  94  *              also sets this flag). The requested rate of the parent is
  95  *              passed back from the callback in the second 'unsigned long *'
  96  *              argument.  Note that it is up to the hardware clock's set_rate
  97  *              implementation to insure that clocks do not run out of spec
  98  *              when propgating the call to set_rate up to the parent.  One way
  99  *              to do this is to gate the clock (via clk_disable and/or
 100  *              clk_unprepare) before calling clk_set_rate, then ungating it
 101  *              afterward.  If your clock also has the CLK_GATE_SET_RATE flag
 102  *              set then this will insure safety.  Returns 0 on success,
 103  *              -EERROR otherwise.
 104  *
 105  * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
 106  * implementations to split any work between atomic (enable) and sleepable
 107  * (prepare) contexts.  If enabling a clock requires code that might sleep,
 108  * this must be done in clk_prepare.  Clock enable code that will never be
 109  * called in a sleepable context may be implement in clk_enable.
 110  *
 111  * Typically, drivers will call clk_prepare when a clock may be needed later
 112  * (eg. when a device is opened), and clk_enable when the clock is actually
 113  * required (eg. from an interrupt). Note that clk_prepare MUST have been
 114  * called before clk_enable.
 115  */
 116 struct clk_ops {
 117         int             (*prepare)(struct clk_hw *hw);
 118         void            (*unprepare)(struct clk_hw *hw);
 119         int             (*enable)(struct clk_hw *hw);
 120         void            (*disable)(struct clk_hw *hw);
 121         int             (*is_enabled)(struct clk_hw *hw);
 122         unsigned long   (*recalc_rate)(struct clk_hw *hw,
 123                                         unsigned long parent_rate);
 124         long            (*round_rate)(struct clk_hw *hw, unsigned long,
 125                                         unsigned long *);
 126         int             (*set_parent)(struct clk_hw *hw, u8 index);
 127         u8              (*get_parent)(struct clk_hw *hw);
 128         int             (*set_rate)(struct clk_hw *hw, unsigned long);
 129         void            (*init)(struct clk_hw *hw);
 130 };
 131
 132 /*
 133  * DOC: Basic clock implementations common to many platforms
 134  *
 135  * Each basic clock hardware type is comprised of a structure describing the
 136  * clock hardware, implementations of the relevant callbacks in struct clk_ops,
 137  * unique flags for that hardware type, a registration function and an
 138  * alternative macro for static initialization
 139  */
 140
 141 /**
 142  * struct clk_fixed_rate - fixed-rate clock
 143  * @hw:         handle between common and hardware-specific interfaces
 144  * @fixed_rate: constant frequency of clock
 145  */
 146 struct clk_fixed_rate {
 147         struct          clk_hw hw;
 148         unsigned long   fixed_rate;
 149         u8              flags;
 150 };
 151
 152 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 153                 const char *parent_name, unsigned long flags,
 154                 unsigned long fixed_rate);
 155
 156 /**
 157  * struct clk_gate - gating clock
 158  *
 159  * @hw:         handle between common and hardware-specific interfaces
 160  * @reg:        register controlling gate
 161  * @bit_idx:    single bit controlling gate
 162  * @flags:      hardware-specific flags
 163  * @lock:       register lock
 164  *
 165  * Clock which can gate its output.  Implements .enable & .disable
 166  *
 167  * Flags:
 168  * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
 169  *      enable the clock.  Setting this flag does the opposite: setting the bit
 170  *      disable the clock and clearing it enables the clock
 171  */
 172 struct clk_gate {
 173         struct clk_hw hw;
 174         void __iomem    *reg;
 175         u8              bit_idx;
 176         u8              flags;
 177         spinlock_t      *lock;
 178         char            *parent[1];
 179 };
 180
 181 #define CLK_GATE_SET_TO_DISABLE         BIT(0)
 182
 183 struct clk *clk_register_gate(struct device *dev, const char *name,
 184                 const char *parent_name, unsigned long flags,
 185                 void __iomem *reg, u8 bit_idx,
 186                 u8 clk_gate_flags, spinlock_t *lock);
 187
 188 /**
 189  * struct clk_divider - adjustable divider clock
 190  *
 191  * @hw:         handle between common and hardware-specific interfaces
 192  * @reg:        register containing the divider
 193  * @shift:      shift to the divider bit field
 194  * @width:      width of the divider bit field
 195  * @lock:       register lock
 196  *
 197  * Clock with an adjustable divider affecting its output frequency.  Implements
 198  * .recalc_rate, .set_rate and .round_rate
 199  *
 200  * Flags:
 201  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
 202  *      register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
 203  *      the raw value read from the register, with the value of zero considered
 204  *      invalid
 205  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
 206  *      the hardware register
 207  */
 208 struct clk_divider {
 209         struct clk_hw   hw;
 210         void __iomem    *reg;
 211         u8              shift;
 212         u8              width;
 213         u8              flags;
 214         spinlock_t      *lock;
 215         char            *parent[1];
 216 };
 217
 218 #define CLK_DIVIDER_ONE_BASED           BIT(0)
 219 #define CLK_DIVIDER_POWER_OF_TWO        BIT(1)
 220
 221 struct clk *clk_register_divider(struct device *dev, const char *name,
 222                 const char *parent_name, unsigned long flags,
 223                 void __iomem *reg, u8 shift, u8 width,
 224                 u8 clk_divider_flags, spinlock_t *lock);
 225
 226 /**
 227  * struct clk_mux - multiplexer clock
 228  *
 229  * @hw:         handle between common and hardware-specific interfaces
 230  * @reg:        register controlling multiplexer
 231  * @shift:      shift to multiplexer bit field
 232  * @width:      width of mutliplexer bit field
 233  * @num_clks:   number of parent clocks
 234  * @lock:       register lock
 235  *
 236  * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
 237  * and .recalc_rate
 238  *
 239  * Flags:
 240  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
 241  * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two)
 242  */
 243 struct clk_mux {
 244         struct clk_hw   hw;
 245         void __iomem    *reg;
 246         u8              shift;
 247         u8              width;
 248         u8              flags;
 249         spinlock_t      *lock;
 250 };
 251
 252 #define CLK_MUX_INDEX_ONE               BIT(0)
 253 #define CLK_MUX_INDEX_BIT               BIT(1)
 254
 255 struct clk *clk_register_mux(struct device *dev, const char *name,
 256                 char **parent_names, u8 num_parents, unsigned long flags,
 257                 void __iomem *reg, u8 shift, u8 width,
 258                 u8 clk_mux_flags, spinlock_t *lock);
 259
 260 /**
 261  * clk_register - allocate a new clock, register it and return an opaque cookie
 262  * @dev: device that is registering this clock
 263  * @name: clock name
 264  * @ops: operations this clock supports
 265  * @hw: link to hardware-specific clock data
 266  * @parent_names: array of string names for all possible parents
 267  * @num_parents: number of possible parents
 268  * @flags: framework-level hints and quirks
 269  *
 270  * clk_register is the primary interface for populating the clock tree with new
 271  * clock nodes.  It returns a pointer to the newly allocated struct clk which
 272  * cannot be dereferenced by driver code but may be used in conjuction with the
 273  * rest of the clock API.
 274  */
 275 struct clk *clk_register(struct device *dev, const char *name,
 276                 const struct clk_ops *ops, struct clk_hw *hw,
 277                 char **parent_names, u8 num_parents, unsigned long flags);
 278
 279 /* helper functions */
 280 const char *__clk_get_name(struct clk *clk);
 281 struct clk_hw *__clk_get_hw(struct clk *clk);
 282 u8 __clk_get_num_parents(struct clk *clk);
 283 struct clk *__clk_get_parent(struct clk *clk);
 284 inline int __clk_get_enable_count(struct clk *clk);
 285 inline int __clk_get_prepare_count(struct clk *clk);
 286 unsigned long __clk_get_rate(struct clk *clk);
 287 unsigned long __clk_get_flags(struct clk *clk);
 288 int __clk_is_enabled(struct clk *clk);
 289 struct clk *__clk_lookup(const char *name);
 290
 291 /*
 292  * FIXME clock api without lock protection
 293  */
 294 int __clk_prepare(struct clk *clk);
 295 void __clk_unprepare(struct clk *clk);
 296 void __clk_reparent(struct clk *clk, struct clk *new_parent);
 297 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
 298
 299 #endif /* CONFIG_COMMON_CLK */
 300 #endif /* CLK_PROVIDER_H */