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ARM: imx: dynamically register imx-uart devices (imx21)
[linux-2.6/libata-dev.git] / arch / arm / mach-imx / devices.c
blob9ea2ef1b238720e407646814266b133659544d73
1 /*
2 * Author: MontaVista Software, Inc.
3 * <source@mvista.com>
4 *
5 * Based on the OMAP devices.c
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
15 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
16 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version 2
21 * of the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
30 * MA 02110-1301, USA.
31 */
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/platform_device.h>
36 #include <linux/gpio.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/serial.h>
39
40 #include <mach/irqs.h>
41 #include <mach/hardware.h>
42 #include <mach/common.h>
43 #include <mach/mmc.h>
44
45 #include "devices.h"
46
47 #if defined(CONFIG_ARCH_MX1)
48 static struct resource imx1_camera_resources[] = {
49 {
50 .start = 0x00224000,
51 .end = 0x00224010,
52 .flags = IORESOURCE_MEM,
53 }, {
54 .start = MX1_CSI_INT,
55 .end = MX1_CSI_INT,
56 .flags = IORESOURCE_IRQ,
57 },
58 };
59
60 static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
61
62 struct platform_device imx1_camera_device = {
63 .name = "mx1-camera",
64 .id = 0, /* This is used to put cameras on this interface */
65 .dev = {
66 .dma_mask = &imx1_camera_dmamask,
67 .coherent_dma_mask = DMA_BIT_MASK(32),
68 },
69 .resource = imx1_camera_resources,
70 .num_resources = ARRAY_SIZE(imx1_camera_resources),
71 };
72
73 static struct resource imx_rtc_resources[] = {
74 {
75 .start = 0x00204000,
76 .end = 0x00204024,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = MX1_RTC_INT,
80 .end = MX1_RTC_INT,
81 .flags = IORESOURCE_IRQ,
82 }, {
83 .start = MX1_RTC_SAMINT,
84 .end = MX1_RTC_SAMINT,
85 .flags = IORESOURCE_IRQ,
86 },
87 };
88
89 struct platform_device imx_rtc_device = {
90 .name = "rtc-imx",
91 .id = 0,
92 .resource = imx_rtc_resources,
93 .num_resources = ARRAY_SIZE(imx_rtc_resources),
94 };
95
96 static struct resource imx_wdt_resources[] = {
97 {
98 .start = 0x00201000,
99 .end = 0x00201008,
100 .flags = IORESOURCE_MEM,
101 }, {
102 .start = MX1_WDT_INT,
103 .end = MX1_WDT_INT,
104 .flags = IORESOURCE_IRQ,
105 },
106 };
107
108 struct platform_device imx_wdt_device = {
109 .name = "imx-wdt",
110 .id = 0,
111 .resource = imx_wdt_resources,
112 .num_resources = ARRAY_SIZE(imx_wdt_resources),
113 };
114
115 static struct resource imx_usb_resources[] = {
116 {
117 .start = 0x00212000,
118 .end = 0x00212148,
119 .flags = IORESOURCE_MEM,
120 }, {
121 .start = MX1_USBD_INT0,
122 .end = MX1_USBD_INT0,
123 .flags = IORESOURCE_IRQ,
124 }, {
125 .start = MX1_USBD_INT1,
126 .end = MX1_USBD_INT1,
127 .flags = IORESOURCE_IRQ,
128 }, {
129 .start = MX1_USBD_INT2,
130 .end = MX1_USBD_INT2,
131 .flags = IORESOURCE_IRQ,
132 }, {
133 .start = MX1_USBD_INT3,
134 .end = MX1_USBD_INT3,
135 .flags = IORESOURCE_IRQ,
136 }, {
137 .start = MX1_USBD_INT4,
138 .end = MX1_USBD_INT4,
139 .flags = IORESOURCE_IRQ,
140 }, {
141 .start = MX1_USBD_INT5,
142 .end = MX1_USBD_INT5,
143 .flags = IORESOURCE_IRQ,
144 }, {
145 .start = MX1_USBD_INT6,
146 .end = MX1_USBD_INT6,
147 .flags = IORESOURCE_IRQ,
148 },
149 };
150
151 struct platform_device imx_usb_device = {
152 .name = "imx_udc",
153 .id = 0,
154 .num_resources = ARRAY_SIZE(imx_usb_resources),
155 .resource = imx_usb_resources,
156 };
157
158 /* GPIO port description */
159 static struct mxc_gpio_port imx_gpio_ports[] = {
160 {
161 .chip.label = "gpio-0",
162 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
163 .irq = MX1_GPIO_INT_PORTA,
164 .virtual_irq_start = MXC_GPIO_IRQ_START,
165 }, {
166 .chip.label = "gpio-1",
167 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
168 .irq = MX1_GPIO_INT_PORTB,
169 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
170 }, {
171 .chip.label = "gpio-2",
172 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
173 .irq = MX1_GPIO_INT_PORTC,
174 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
175 }, {
176 .chip.label = "gpio-3",
177 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
178 .irq = MX1_GPIO_INT_PORTD,
179 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
180 }
181 };
182
183 int __init imx1_register_gpios(void)
184 {
185 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
186 }
187 #endif
188
189 #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
190 /*
191 * General Purpose Timer
192 * - i.MX21: 3 timers
193 * - i.MX27: 6 timers
194 */
195 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
196 static struct resource timer ## n ##_resources[] = { \
197 { \
198 .start = baseaddr, \
199 .end = baseaddr + SZ_4K - 1, \
200 .flags = IORESOURCE_MEM, \
201 }, { \
202 .start = irq, \
203 .end = irq, \
204 .flags = IORESOURCE_IRQ, \
205 } \
206 }; \
207 \
208 struct platform_device mxc_gpt ## n = { \
209 .name = "imx_gpt", \
210 .id = n, \
211 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
212 .resource = timer ## n ## _resources, \
213 }
214
215 /* We use gpt1 as system timer, so do not add a device for this one */
216 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
217 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
218
219 #ifdef CONFIG_MACH_MX27
220 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
221 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
222 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
223 #endif
224
225 /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
226 static struct resource mxc_wdt_resources[] = {
227 {
228 .start = MX2x_WDOG_BASE_ADDR,
229 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
230 .flags = IORESOURCE_MEM,
231 },
232 };
233
234 struct platform_device mxc_wdt = {
235 .name = "imx2-wdt",
236 .id = 0,
237 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
238 .resource = mxc_wdt_resources,
239 };
240
241 static struct resource mxc_w1_master_resources[] = {
242 {
243 .start = MX2x_OWIRE_BASE_ADDR,
244 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
245 .flags = IORESOURCE_MEM,
246 },
247 };
248
249 struct platform_device mxc_w1_master_device = {
250 .name = "mxc_w1",
251 .id = 0,
252 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
253 .resource = mxc_w1_master_resources,
254 };
255
256 /*
257 * lcdc:
258 * - i.MX1: the basic controller
259 * - i.MX21: to be checked
260 * - i.MX27: like i.MX1, with slightly variations
261 */
262 static struct resource mxc_fb[] = {
263 {
264 .start = MX2x_LCDC_BASE_ADDR,
265 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
266 .flags = IORESOURCE_MEM,
267 }, {
268 .start = MX2x_INT_LCDC,
269 .end = MX2x_INT_LCDC,
270 .flags = IORESOURCE_IRQ,
271 }
272 };
273
274 /* mxc lcd driver */
275 struct platform_device mxc_fb_device = {
276 .name = "imx-fb",
277 .id = 0,
278 .num_resources = ARRAY_SIZE(mxc_fb),
279 .resource = mxc_fb,
280 .dev = {
281 .coherent_dma_mask = DMA_BIT_MASK(32),
282 },
283 };
284
285 #ifdef CONFIG_MACH_MX27
286 static struct resource mxc_fec_resources[] = {
287 {
288 .start = MX27_FEC_BASE_ADDR,
289 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
290 .flags = IORESOURCE_MEM,
291 }, {
292 .start = MX27_INT_FEC,
293 .end = MX27_INT_FEC,
294 .flags = IORESOURCE_IRQ,
295 },
296 };
297
298 struct platform_device mxc_fec_device = {
299 .name = "fec",
300 .id = 0,
301 .num_resources = ARRAY_SIZE(mxc_fec_resources),
302 .resource = mxc_fec_resources,
303 };
304 #endif
305
306 static struct resource mxc_pwm_resources[] = {
307 {
308 .start = MX2x_PWM_BASE_ADDR,
309 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
310 .flags = IORESOURCE_MEM,
311 }, {
312 .start = MX2x_INT_PWM,
313 .end = MX2x_INT_PWM,
314 .flags = IORESOURCE_IRQ,
315 }
316 };
317
318 struct platform_device mxc_pwm_device = {
319 .name = "mxc_pwm",
320 .id = 0,
321 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
322 .resource = mxc_pwm_resources,
323 };
324
325 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
326 static struct resource mxc_sdhc_resources ## n[] = { \
327 { \
328 .start = baseaddr, \
329 .end = baseaddr + SZ_4K - 1, \
330 .flags = IORESOURCE_MEM, \
331 }, { \
332 .start = irq, \
333 .end = irq, \
334 .flags = IORESOURCE_IRQ, \
335 }, { \
336 .start = dmareq, \
337 .end = dmareq, \
338 .flags = IORESOURCE_DMA, \
339 }, \
340 }; \
341 \
342 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
343 \
344 struct platform_device mxc_sdhc_device ## n = { \
345 .name = "mxc-mmc", \
346 .id = n, \
347 .dev = { \
348 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
349 .coherent_dma_mask = DMA_BIT_MASK(32), \
350 }, \
351 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
352 .resource = mxc_sdhc_resources ## n, \
353 }
354
355 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
356 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
357
358 #ifdef CONFIG_MACH_MX27
359 static struct resource otg_resources[] = {
360 {
361 .start = MX27_USBOTG_BASE_ADDR,
362 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
363 .flags = IORESOURCE_MEM,
364 }, {
365 .start = MX27_INT_USB3,
366 .end = MX27_INT_USB3,
367 .flags = IORESOURCE_IRQ,
368 },
369 };
370
371 static u64 otg_dmamask = DMA_BIT_MASK(32);
372
373 /* OTG gadget device */
374 struct platform_device mxc_otg_udc_device = {
375 .name = "fsl-usb2-udc",
376 .id = -1,
377 .dev = {
378 .dma_mask = &otg_dmamask,
379 .coherent_dma_mask = DMA_BIT_MASK(32),
380 },
381 .resource = otg_resources,
382 .num_resources = ARRAY_SIZE(otg_resources),
383 };
384
385 /* OTG host */
386 struct platform_device mxc_otg_host = {
387 .name = "mxc-ehci",
388 .id = 0,
389 .dev = {
390 .coherent_dma_mask = DMA_BIT_MASK(32),
391 .dma_mask = &otg_dmamask,
392 },
393 .resource = otg_resources,
394 .num_resources = ARRAY_SIZE(otg_resources),
395 };
396
397 /* USB host 1 */
398
399 static u64 usbh1_dmamask = DMA_BIT_MASK(32);
400
401 static struct resource mxc_usbh1_resources[] = {
402 {
403 .start = MX27_USBOTG_BASE_ADDR + 0x200,
404 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
405 .flags = IORESOURCE_MEM,
406 }, {
407 .start = MX27_INT_USB1,
408 .end = MX27_INT_USB1,
409 .flags = IORESOURCE_IRQ,
410 },
411 };
412
413 struct platform_device mxc_usbh1 = {
414 .name = "mxc-ehci",
415 .id = 1,
416 .dev = {
417 .coherent_dma_mask = DMA_BIT_MASK(32),
418 .dma_mask = &usbh1_dmamask,
419 },
420 .resource = mxc_usbh1_resources,
421 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
422 };
423
424 /* USB host 2 */
425 static u64 usbh2_dmamask = DMA_BIT_MASK(32);
426
427 static struct resource mxc_usbh2_resources[] = {
428 {
429 .start = MX27_USBOTG_BASE_ADDR + 0x400,
430 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
431 .flags = IORESOURCE_MEM,
432 }, {
433 .start = MX27_INT_USB2,
434 .end = MX27_INT_USB2,
435 .flags = IORESOURCE_IRQ,
436 },
437 };
438
439 struct platform_device mxc_usbh2 = {
440 .name = "mxc-ehci",
441 .id = 2,
442 .dev = {
443 .coherent_dma_mask = DMA_BIT_MASK(32),
444 .dma_mask = &usbh2_dmamask,
445 },
446 .resource = mxc_usbh2_resources,
447 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
448 };
449 #endif
450
451 #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
452 { \
453 .name = _name, \
454 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
455 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
456 .flags = IORESOURCE_DMA, \
457 }
458
459 #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
460 static struct resource imx_ssi_resources ## n[] = { \
461 { \
462 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
463 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
464 .flags = IORESOURCE_MEM, \
465 }, { \
466 .start = MX2x_INT_SSI1, \
467 .end = MX2x_INT_SSI1, \
468 .flags = IORESOURCE_IRQ, \
469 }, \
470 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
471 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
472 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
473 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
474 }; \
475 \
476 struct platform_device imx_ssi_device ## n = { \
477 .name = "imx-ssi", \
478 .id = n, \
479 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
480 .resource = imx_ssi_resources ## n, \
481 }
482
483 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
484 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
485
486 #ifdef CONFIG_MACH_MX27
487 #define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq) \
488 static struct resource imx2x_uart_resources ## n[] = { \
489 { \
490 .start = baseaddr, \
491 .end = baseaddr + 0xb5, \
492 .flags = IORESOURCE_MEM, \
493 }, { \
494 .start = irq, \
495 .end = irq, \
496 .flags = IORESOURCE_IRQ, \
497 }, \
498 }; \
499 \
500 struct platform_device imx2x_uart_device ## n = { \
501 .name = "imx-uart", \
502 .id = n, \
503 .num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
504 .resource = imx2x_uart_resources ## n, \
505 }
506
507 DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
508 DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
509 DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
510 DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
511 DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
512 DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
513 #endif
514
515 /* GPIO port description */
516 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
517 { \
518 .chip.label = "gpio-" #n, \
519 .irq = _irq, \
520 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
521 n * 0x100), \
522 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
523 }
524
525 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
526 { \
527 .chip.label = "gpio-" #n, \
528 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
529 n * 0x100), \
530 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
531 }
532
533 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
534 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
535 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
536 DEFINE_MXC_GPIO_PORT(SOC, 1), \
537 DEFINE_MXC_GPIO_PORT(SOC, 2), \
538 DEFINE_MXC_GPIO_PORT(SOC, 3), \
539 DEFINE_MXC_GPIO_PORT(SOC, 4), \
540 DEFINE_MXC_GPIO_PORT(SOC, 5), \
541 }
542
543 #ifdef CONFIG_MACH_MX21
544 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
545
546 int __init imx21_register_gpios(void)
547 {
548 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
549 }
550 #endif
551
552 #ifdef CONFIG_MACH_MX27
553 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
554
555 int __init imx27_register_gpios(void)
556 {
557 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
558 }
559 #endif
560
561 #ifdef CONFIG_MACH_MX21
562 static struct resource mx21_usbhc_resources[] = {
563 {
564 .start = MX21_USBOTG_BASE_ADDR,
565 .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
566 .flags = IORESOURCE_MEM,
567 },
568 {
569 .start = MX21_INT_USBHOST,
570 .end = MX21_INT_USBHOST,
571 .flags = IORESOURCE_IRQ,
572 },
573 };
574
575 struct platform_device mx21_usbhc_device = {
576 .name = "imx21-hcd",
577 .id = 0,
578 .dev = {
579 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
580 .coherent_dma_mask = DMA_BIT_MASK(32),
581 },
582 .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
583 .resource = mx21_usbhc_resources,
584 };
585 #endif
586 #endif
Linux 2.6 libata-dev (mirror)