1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/netdevice.h>
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
37 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
);
38 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
);
39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
);
40 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
);
41 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
);
42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
44 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
);
45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
47 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
);
49 static void ixgbe_enable_rar(struct ixgbe_hw
*hw
, u32 index
);
50 static void ixgbe_disable_rar(struct ixgbe_hw
*hw
, u32 index
);
51 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
);
52 static void ixgbe_add_uc_addr(struct ixgbe_hw
*hw
, u8
*addr
, u32 vmdq
);
53 static s32
ixgbe_setup_fc(struct ixgbe_hw
*hw
, s32 packetbuf_num
);
56 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
57 * @hw: pointer to hardware structure
59 * Starts the hardware by filling the bus info structure and media type, clears
60 * all on chip counters, initializes receive address registers, multicast
61 * table, VLAN filter table, calls routine to set up link and flow control
62 * settings, and leaves transmit and receive units disabled and uninitialized
64 s32
ixgbe_start_hw_generic(struct ixgbe_hw
*hw
)
68 /* Set the media type */
69 hw
->phy
.media_type
= hw
->mac
.ops
.get_media_type(hw
);
71 /* Identify the PHY */
72 hw
->phy
.ops
.identify(hw
);
74 /* Clear the VLAN filter table */
75 hw
->mac
.ops
.clear_vfta(hw
);
77 /* Clear statistics registers */
78 hw
->mac
.ops
.clear_hw_cntrs(hw
);
80 /* Set No Snoop Disable */
81 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
82 ctrl_ext
|= IXGBE_CTRL_EXT_NS_DIS
;
83 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
84 IXGBE_WRITE_FLUSH(hw
);
86 /* Setup flow control */
87 ixgbe_setup_fc(hw
, 0);
89 /* Clear adapter stopped flag */
90 hw
->adapter_stopped
= false;
96 * ixgbe_init_hw_generic - Generic hardware initialization
97 * @hw: pointer to hardware structure
99 * Initialize the hardware by resetting the hardware, filling the bus info
100 * structure and media type, clears all on chip counters, initializes receive
101 * address registers, multicast table, VLAN filter table, calls routine to set
102 * up link and flow control settings, and leaves transmit and receive units
103 * disabled and uninitialized
105 s32
ixgbe_init_hw_generic(struct ixgbe_hw
*hw
)
109 /* Reset the hardware */
110 status
= hw
->mac
.ops
.reset_hw(hw
);
114 status
= hw
->mac
.ops
.start_hw(hw
);
121 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
122 * @hw: pointer to hardware structure
124 * Clears all hardware statistics counters by reading them from the hardware
125 * Statistics counters are clear on read.
127 s32
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw
*hw
)
131 IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
132 IXGBE_READ_REG(hw
, IXGBE_ILLERRC
);
133 IXGBE_READ_REG(hw
, IXGBE_ERRBC
);
134 IXGBE_READ_REG(hw
, IXGBE_MSPDC
);
135 for (i
= 0; i
< 8; i
++)
136 IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
138 IXGBE_READ_REG(hw
, IXGBE_MLFC
);
139 IXGBE_READ_REG(hw
, IXGBE_MRFC
);
140 IXGBE_READ_REG(hw
, IXGBE_RLEC
);
141 IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
142 IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
143 IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
144 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
146 for (i
= 0; i
< 8; i
++) {
147 IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
148 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
149 IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
150 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
153 IXGBE_READ_REG(hw
, IXGBE_PRC64
);
154 IXGBE_READ_REG(hw
, IXGBE_PRC127
);
155 IXGBE_READ_REG(hw
, IXGBE_PRC255
);
156 IXGBE_READ_REG(hw
, IXGBE_PRC511
);
157 IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
158 IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
159 IXGBE_READ_REG(hw
, IXGBE_GPRC
);
160 IXGBE_READ_REG(hw
, IXGBE_BPRC
);
161 IXGBE_READ_REG(hw
, IXGBE_MPRC
);
162 IXGBE_READ_REG(hw
, IXGBE_GPTC
);
163 IXGBE_READ_REG(hw
, IXGBE_GORCL
);
164 IXGBE_READ_REG(hw
, IXGBE_GORCH
);
165 IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
166 IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
167 for (i
= 0; i
< 8; i
++)
168 IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
169 IXGBE_READ_REG(hw
, IXGBE_RUC
);
170 IXGBE_READ_REG(hw
, IXGBE_RFC
);
171 IXGBE_READ_REG(hw
, IXGBE_ROC
);
172 IXGBE_READ_REG(hw
, IXGBE_RJC
);
173 IXGBE_READ_REG(hw
, IXGBE_MNGPRC
);
174 IXGBE_READ_REG(hw
, IXGBE_MNGPDC
);
175 IXGBE_READ_REG(hw
, IXGBE_MNGPTC
);
176 IXGBE_READ_REG(hw
, IXGBE_TORL
);
177 IXGBE_READ_REG(hw
, IXGBE_TORH
);
178 IXGBE_READ_REG(hw
, IXGBE_TPR
);
179 IXGBE_READ_REG(hw
, IXGBE_TPT
);
180 IXGBE_READ_REG(hw
, IXGBE_PTC64
);
181 IXGBE_READ_REG(hw
, IXGBE_PTC127
);
182 IXGBE_READ_REG(hw
, IXGBE_PTC255
);
183 IXGBE_READ_REG(hw
, IXGBE_PTC511
);
184 IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
185 IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
186 IXGBE_READ_REG(hw
, IXGBE_MPTC
);
187 IXGBE_READ_REG(hw
, IXGBE_BPTC
);
188 for (i
= 0; i
< 16; i
++) {
189 IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
190 IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
191 IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
192 IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
199 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
200 * @hw: pointer to hardware structure
201 * @pba_num: stores the part number string from the EEPROM
202 * @pba_num_size: part number string buffer length
204 * Reads the part number string from the EEPROM.
206 s32
ixgbe_read_pba_string_generic(struct ixgbe_hw
*hw
, u8
*pba_num
,
215 if (pba_num
== NULL
) {
216 hw_dbg(hw
, "PBA string buffer was null\n");
217 return IXGBE_ERR_INVALID_ARGUMENT
;
220 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM0_PTR
, &data
);
222 hw_dbg(hw
, "NVM Read Error\n");
226 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM1_PTR
, &pba_ptr
);
228 hw_dbg(hw
, "NVM Read Error\n");
233 * if data is not ptr guard the PBA must be in legacy format which
234 * means pba_ptr is actually our second data word for the PBA number
235 * and we can decode it into an ascii string
237 if (data
!= IXGBE_PBANUM_PTR_GUARD
) {
238 hw_dbg(hw
, "NVM PBA number is not stored as string\n");
240 /* we will need 11 characters to store the PBA */
241 if (pba_num_size
< 11) {
242 hw_dbg(hw
, "PBA string buffer too small\n");
243 return IXGBE_ERR_NO_SPACE
;
246 /* extract hex string from data and pba_ptr */
247 pba_num
[0] = (data
>> 12) & 0xF;
248 pba_num
[1] = (data
>> 8) & 0xF;
249 pba_num
[2] = (data
>> 4) & 0xF;
250 pba_num
[3] = data
& 0xF;
251 pba_num
[4] = (pba_ptr
>> 12) & 0xF;
252 pba_num
[5] = (pba_ptr
>> 8) & 0xF;
255 pba_num
[8] = (pba_ptr
>> 4) & 0xF;
256 pba_num
[9] = pba_ptr
& 0xF;
258 /* put a null character on the end of our string */
261 /* switch all the data but the '-' to hex char */
262 for (offset
= 0; offset
< 10; offset
++) {
263 if (pba_num
[offset
] < 0xA)
264 pba_num
[offset
] += '0';
265 else if (pba_num
[offset
] < 0x10)
266 pba_num
[offset
] += 'A' - 0xA;
272 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
, &length
);
274 hw_dbg(hw
, "NVM Read Error\n");
278 if (length
== 0xFFFF || length
== 0) {
279 hw_dbg(hw
, "NVM PBA number section invalid length\n");
280 return IXGBE_ERR_PBA_SECTION
;
283 /* check if pba_num buffer is big enough */
284 if (pba_num_size
< (((u32
)length
* 2) - 1)) {
285 hw_dbg(hw
, "PBA string buffer too small\n");
286 return IXGBE_ERR_NO_SPACE
;
289 /* trim pba length from start of string */
293 for (offset
= 0; offset
< length
; offset
++) {
294 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
+ offset
, &data
);
296 hw_dbg(hw
, "NVM Read Error\n");
299 pba_num
[offset
* 2] = (u8
)(data
>> 8);
300 pba_num
[(offset
* 2) + 1] = (u8
)(data
& 0xFF);
302 pba_num
[offset
* 2] = '\0';
308 * ixgbe_get_mac_addr_generic - Generic get MAC address
309 * @hw: pointer to hardware structure
310 * @mac_addr: Adapter MAC address
312 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
313 * A reset of the adapter must be performed prior to calling this function
314 * in order for the MAC address to have been loaded from the EEPROM into RAR0
316 s32
ixgbe_get_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*mac_addr
)
322 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(0));
323 rar_low
= IXGBE_READ_REG(hw
, IXGBE_RAL(0));
325 for (i
= 0; i
< 4; i
++)
326 mac_addr
[i
] = (u8
)(rar_low
>> (i
*8));
328 for (i
= 0; i
< 2; i
++)
329 mac_addr
[i
+4] = (u8
)(rar_high
>> (i
*8));
335 * ixgbe_get_bus_info_generic - Generic set PCI bus info
336 * @hw: pointer to hardware structure
338 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
340 s32
ixgbe_get_bus_info_generic(struct ixgbe_hw
*hw
)
342 struct ixgbe_adapter
*adapter
= hw
->back
;
343 struct ixgbe_mac_info
*mac
= &hw
->mac
;
346 hw
->bus
.type
= ixgbe_bus_type_pci_express
;
348 /* Get the negotiated link width and speed from PCI config space */
349 pci_read_config_word(adapter
->pdev
, IXGBE_PCI_LINK_STATUS
,
352 switch (link_status
& IXGBE_PCI_LINK_WIDTH
) {
353 case IXGBE_PCI_LINK_WIDTH_1
:
354 hw
->bus
.width
= ixgbe_bus_width_pcie_x1
;
356 case IXGBE_PCI_LINK_WIDTH_2
:
357 hw
->bus
.width
= ixgbe_bus_width_pcie_x2
;
359 case IXGBE_PCI_LINK_WIDTH_4
:
360 hw
->bus
.width
= ixgbe_bus_width_pcie_x4
;
362 case IXGBE_PCI_LINK_WIDTH_8
:
363 hw
->bus
.width
= ixgbe_bus_width_pcie_x8
;
366 hw
->bus
.width
= ixgbe_bus_width_unknown
;
370 switch (link_status
& IXGBE_PCI_LINK_SPEED
) {
371 case IXGBE_PCI_LINK_SPEED_2500
:
372 hw
->bus
.speed
= ixgbe_bus_speed_2500
;
374 case IXGBE_PCI_LINK_SPEED_5000
:
375 hw
->bus
.speed
= ixgbe_bus_speed_5000
;
378 hw
->bus
.speed
= ixgbe_bus_speed_unknown
;
382 mac
->ops
.set_lan_id(hw
);
388 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
389 * @hw: pointer to the HW structure
391 * Determines the LAN function id by reading memory-mapped registers
392 * and swaps the port value if requested.
394 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw
*hw
)
396 struct ixgbe_bus_info
*bus
= &hw
->bus
;
399 reg
= IXGBE_READ_REG(hw
, IXGBE_STATUS
);
400 bus
->func
= (reg
& IXGBE_STATUS_LAN_ID
) >> IXGBE_STATUS_LAN_ID_SHIFT
;
401 bus
->lan_id
= bus
->func
;
403 /* check for a port swap */
404 reg
= IXGBE_READ_REG(hw
, IXGBE_FACTPS
);
405 if (reg
& IXGBE_FACTPS_LFS
)
410 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
411 * @hw: pointer to hardware structure
413 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
414 * disables transmit and receive units. The adapter_stopped flag is used by
415 * the shared code and drivers to determine if the adapter is in a stopped
416 * state and should not touch the hardware.
418 s32
ixgbe_stop_adapter_generic(struct ixgbe_hw
*hw
)
420 u32 number_of_queues
;
425 * Set the adapter_stopped flag so other driver functions stop touching
428 hw
->adapter_stopped
= true;
430 /* Disable the receive unit */
431 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
432 reg_val
&= ~(IXGBE_RXCTRL_RXEN
);
433 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, reg_val
);
434 IXGBE_WRITE_FLUSH(hw
);
437 /* Clear interrupt mask to stop from interrupts being generated */
438 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
440 /* Clear any pending interrupts */
441 IXGBE_READ_REG(hw
, IXGBE_EICR
);
443 /* Disable the transmit unit. Each queue must be disabled. */
444 number_of_queues
= hw
->mac
.max_tx_queues
;
445 for (i
= 0; i
< number_of_queues
; i
++) {
446 reg_val
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
447 if (reg_val
& IXGBE_TXDCTL_ENABLE
) {
448 reg_val
&= ~IXGBE_TXDCTL_ENABLE
;
449 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(i
), reg_val
);
454 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
455 * access and verify no pending requests
457 if (ixgbe_disable_pcie_master(hw
) != 0)
458 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
464 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
465 * @hw: pointer to hardware structure
466 * @index: led number to turn on
468 s32
ixgbe_led_on_generic(struct ixgbe_hw
*hw
, u32 index
)
470 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
472 /* To turn on the LED, set mode to ON. */
473 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
474 led_reg
|= IXGBE_LED_ON
<< IXGBE_LED_MODE_SHIFT(index
);
475 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
476 IXGBE_WRITE_FLUSH(hw
);
482 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
483 * @hw: pointer to hardware structure
484 * @index: led number to turn off
486 s32
ixgbe_led_off_generic(struct ixgbe_hw
*hw
, u32 index
)
488 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
490 /* To turn off the LED, set mode to OFF. */
491 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
492 led_reg
|= IXGBE_LED_OFF
<< IXGBE_LED_MODE_SHIFT(index
);
493 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
494 IXGBE_WRITE_FLUSH(hw
);
500 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
501 * @hw: pointer to hardware structure
503 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
504 * ixgbe_hw struct in order to set up EEPROM access.
506 s32
ixgbe_init_eeprom_params_generic(struct ixgbe_hw
*hw
)
508 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
512 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
513 eeprom
->type
= ixgbe_eeprom_none
;
514 /* Set default semaphore delay to 10ms which is a well
516 eeprom
->semaphore_delay
= 10;
519 * Check for EEPROM present first.
520 * If not present leave as none
522 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
523 if (eec
& IXGBE_EEC_PRES
) {
524 eeprom
->type
= ixgbe_eeprom_spi
;
527 * SPI EEPROM is assumed here. This code would need to
528 * change if a future EEPROM is not SPI.
530 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
531 IXGBE_EEC_SIZE_SHIFT
);
532 eeprom
->word_size
= 1 << (eeprom_size
+
533 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
536 if (eec
& IXGBE_EEC_ADDR_SIZE
)
537 eeprom
->address_bits
= 16;
539 eeprom
->address_bits
= 8;
540 hw_dbg(hw
, "Eeprom params: type = %d, size = %d, address bits: "
541 "%d\n", eeprom
->type
, eeprom
->word_size
,
542 eeprom
->address_bits
);
549 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
550 * @hw: pointer to hardware structure
551 * @offset: offset within the EEPROM to be written to
552 * @data: 16 bit word to be written to the EEPROM
554 * If ixgbe_eeprom_update_checksum is not called after this function, the
555 * EEPROM will most likely contain an invalid checksum.
557 s32
ixgbe_write_eeprom_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
560 u8 write_opcode
= IXGBE_EEPROM_WRITE_OPCODE_SPI
;
562 hw
->eeprom
.ops
.init_params(hw
);
564 if (offset
>= hw
->eeprom
.word_size
) {
565 status
= IXGBE_ERR_EEPROM
;
569 /* Prepare the EEPROM for writing */
570 status
= ixgbe_acquire_eeprom(hw
);
573 if (ixgbe_ready_eeprom(hw
) != 0) {
574 ixgbe_release_eeprom(hw
);
575 status
= IXGBE_ERR_EEPROM
;
580 ixgbe_standby_eeprom(hw
);
582 /* Send the WRITE ENABLE command (8 bit opcode ) */
583 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_WREN_OPCODE_SPI
,
584 IXGBE_EEPROM_OPCODE_BITS
);
586 ixgbe_standby_eeprom(hw
);
589 * Some SPI eeproms use the 8th address bit embedded in the
592 if ((hw
->eeprom
.address_bits
== 8) && (offset
>= 128))
593 write_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
595 /* Send the Write command (8-bit opcode + addr) */
596 ixgbe_shift_out_eeprom_bits(hw
, write_opcode
,
597 IXGBE_EEPROM_OPCODE_BITS
);
598 ixgbe_shift_out_eeprom_bits(hw
, (u16
)(offset
*2),
599 hw
->eeprom
.address_bits
);
602 data
= (data
>> 8) | (data
<< 8);
603 ixgbe_shift_out_eeprom_bits(hw
, data
, 16);
604 ixgbe_standby_eeprom(hw
);
606 msleep(hw
->eeprom
.semaphore_delay
);
607 /* Done with writing - release the EEPROM */
608 ixgbe_release_eeprom(hw
);
616 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
617 * @hw: pointer to hardware structure
618 * @offset: offset within the EEPROM to be read
619 * @data: read 16 bit value from EEPROM
621 * Reads 16 bit value from EEPROM through bit-bang method
623 s32
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
628 u8 read_opcode
= IXGBE_EEPROM_READ_OPCODE_SPI
;
630 hw
->eeprom
.ops
.init_params(hw
);
632 if (offset
>= hw
->eeprom
.word_size
) {
633 status
= IXGBE_ERR_EEPROM
;
637 /* Prepare the EEPROM for reading */
638 status
= ixgbe_acquire_eeprom(hw
);
641 if (ixgbe_ready_eeprom(hw
) != 0) {
642 ixgbe_release_eeprom(hw
);
643 status
= IXGBE_ERR_EEPROM
;
648 ixgbe_standby_eeprom(hw
);
651 * Some SPI eeproms use the 8th address bit embedded in the
654 if ((hw
->eeprom
.address_bits
== 8) && (offset
>= 128))
655 read_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
657 /* Send the READ command (opcode + addr) */
658 ixgbe_shift_out_eeprom_bits(hw
, read_opcode
,
659 IXGBE_EEPROM_OPCODE_BITS
);
660 ixgbe_shift_out_eeprom_bits(hw
, (u16
)(offset
*2),
661 hw
->eeprom
.address_bits
);
664 word_in
= ixgbe_shift_in_eeprom_bits(hw
, 16);
665 *data
= (word_in
>> 8) | (word_in
<< 8);
667 /* End this read operation */
668 ixgbe_release_eeprom(hw
);
676 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
677 * @hw: pointer to hardware structure
678 * @offset: offset of word in the EEPROM to read
679 * @data: word read from the EEPROM
681 * Reads a 16 bit word from the EEPROM using the EERD register.
683 s32
ixgbe_read_eerd_generic(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
688 hw
->eeprom
.ops
.init_params(hw
);
690 if (offset
>= hw
->eeprom
.word_size
) {
691 status
= IXGBE_ERR_EEPROM
;
695 eerd
= (offset
<< IXGBE_EEPROM_RW_ADDR_SHIFT
) +
696 IXGBE_EEPROM_RW_REG_START
;
698 IXGBE_WRITE_REG(hw
, IXGBE_EERD
, eerd
);
699 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_READ
);
702 *data
= (IXGBE_READ_REG(hw
, IXGBE_EERD
) >>
703 IXGBE_EEPROM_RW_REG_DATA
);
705 hw_dbg(hw
, "Eeprom read timed out\n");
712 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
713 * @hw: pointer to hardware structure
714 * @ee_reg: EEPROM flag for polling
716 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
717 * read or write is done respectively.
719 s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
)
723 s32 status
= IXGBE_ERR_EEPROM
;
725 for (i
= 0; i
< IXGBE_EERD_EEWR_ATTEMPTS
; i
++) {
726 if (ee_reg
== IXGBE_NVM_POLL_READ
)
727 reg
= IXGBE_READ_REG(hw
, IXGBE_EERD
);
729 reg
= IXGBE_READ_REG(hw
, IXGBE_EEWR
);
731 if (reg
& IXGBE_EEPROM_RW_REG_DONE
) {
741 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
742 * @hw: pointer to hardware structure
744 * Prepares EEPROM for access using bit-bang method. This function should
745 * be called before issuing a command to the EEPROM.
747 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
)
753 if (ixgbe_acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) != 0)
754 status
= IXGBE_ERR_SWFW_SYNC
;
757 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
759 /* Request EEPROM Access */
760 eec
|= IXGBE_EEC_REQ
;
761 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
763 for (i
= 0; i
< IXGBE_EEPROM_GRANT_ATTEMPTS
; i
++) {
764 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
765 if (eec
& IXGBE_EEC_GNT
)
770 /* Release if grant not acquired */
771 if (!(eec
& IXGBE_EEC_GNT
)) {
772 eec
&= ~IXGBE_EEC_REQ
;
773 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
774 hw_dbg(hw
, "Could not acquire EEPROM grant\n");
776 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
777 status
= IXGBE_ERR_EEPROM
;
781 /* Setup EEPROM for Read/Write */
783 /* Clear CS and SK */
784 eec
&= ~(IXGBE_EEC_CS
| IXGBE_EEC_SK
);
785 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
786 IXGBE_WRITE_FLUSH(hw
);
793 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
794 * @hw: pointer to hardware structure
796 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
798 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
)
800 s32 status
= IXGBE_ERR_EEPROM
;
805 /* Set timeout value based on size of EEPROM */
806 timeout
= hw
->eeprom
.word_size
+ 1;
808 /* Get SMBI software semaphore between device drivers first */
809 for (i
= 0; i
< timeout
; i
++) {
811 * If the SMBI bit is 0 when we read it, then the bit will be
812 * set and we have the semaphore
814 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
815 if (!(swsm
& IXGBE_SWSM_SMBI
)) {
822 /* Now get the semaphore between SW/FW through the SWESMBI bit */
824 for (i
= 0; i
< timeout
; i
++) {
825 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
827 /* Set the SW EEPROM semaphore bit to request access */
828 swsm
|= IXGBE_SWSM_SWESMBI
;
829 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
832 * If we set the bit successfully then we got the
835 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
836 if (swsm
& IXGBE_SWSM_SWESMBI
)
843 * Release semaphores and return error if SW EEPROM semaphore
844 * was not granted because we don't have access to the EEPROM
847 hw_dbg(hw
, "Driver can't access the Eeprom - Semaphore "
849 ixgbe_release_eeprom_semaphore(hw
);
850 status
= IXGBE_ERR_EEPROM
;
858 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
859 * @hw: pointer to hardware structure
861 * This function clears hardware semaphore bits.
863 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
)
867 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
869 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
870 swsm
&= ~(IXGBE_SWSM_SWESMBI
| IXGBE_SWSM_SMBI
);
871 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
872 IXGBE_WRITE_FLUSH(hw
);
876 * ixgbe_ready_eeprom - Polls for EEPROM ready
877 * @hw: pointer to hardware structure
879 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
)
886 * Read "Status Register" repeatedly until the LSB is cleared. The
887 * EEPROM will signal that the command has been completed by clearing
888 * bit 0 of the internal status register. If it's not cleared within
889 * 5 milliseconds, then error out.
891 for (i
= 0; i
< IXGBE_EEPROM_MAX_RETRY_SPI
; i
+= 5) {
892 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_RDSR_OPCODE_SPI
,
893 IXGBE_EEPROM_OPCODE_BITS
);
894 spi_stat_reg
= (u8
)ixgbe_shift_in_eeprom_bits(hw
, 8);
895 if (!(spi_stat_reg
& IXGBE_EEPROM_STATUS_RDY_SPI
))
899 ixgbe_standby_eeprom(hw
);
903 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
904 * devices (and only 0-5mSec on 5V devices)
906 if (i
>= IXGBE_EEPROM_MAX_RETRY_SPI
) {
907 hw_dbg(hw
, "SPI EEPROM Status error\n");
908 status
= IXGBE_ERR_EEPROM
;
915 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
916 * @hw: pointer to hardware structure
918 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
)
922 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
924 /* Toggle CS to flush commands */
926 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
927 IXGBE_WRITE_FLUSH(hw
);
929 eec
&= ~IXGBE_EEC_CS
;
930 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
931 IXGBE_WRITE_FLUSH(hw
);
936 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
937 * @hw: pointer to hardware structure
938 * @data: data to send to the EEPROM
939 * @count: number of bits to shift out
941 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
948 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
951 * Mask is used to shift "count" bits of "data" out to the EEPROM
952 * one bit at a time. Determine the starting bit based on count
954 mask
= 0x01 << (count
- 1);
956 for (i
= 0; i
< count
; i
++) {
958 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
959 * "1", and then raising and then lowering the clock (the SK
960 * bit controls the clock input to the EEPROM). A "0" is
961 * shifted out to the EEPROM by setting "DI" to "0" and then
962 * raising and then lowering the clock.
967 eec
&= ~IXGBE_EEC_DI
;
969 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
970 IXGBE_WRITE_FLUSH(hw
);
974 ixgbe_raise_eeprom_clk(hw
, &eec
);
975 ixgbe_lower_eeprom_clk(hw
, &eec
);
978 * Shift mask to signify next bit of data to shift in to the
984 /* We leave the "DI" bit set to "0" when we leave this routine. */
985 eec
&= ~IXGBE_EEC_DI
;
986 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
987 IXGBE_WRITE_FLUSH(hw
);
991 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
992 * @hw: pointer to hardware structure
994 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
)
1001 * In order to read a register from the EEPROM, we need to shift
1002 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1003 * the clock input to the EEPROM (setting the SK bit), and then reading
1004 * the value of the "DO" bit. During this "shifting in" process the
1005 * "DI" bit should always be clear.
1007 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1009 eec
&= ~(IXGBE_EEC_DO
| IXGBE_EEC_DI
);
1011 for (i
= 0; i
< count
; i
++) {
1013 ixgbe_raise_eeprom_clk(hw
, &eec
);
1015 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1017 eec
&= ~(IXGBE_EEC_DI
);
1018 if (eec
& IXGBE_EEC_DO
)
1021 ixgbe_lower_eeprom_clk(hw
, &eec
);
1028 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1029 * @hw: pointer to hardware structure
1030 * @eec: EEC register's current value
1032 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1035 * Raise the clock input to the EEPROM
1036 * (setting the SK bit), then delay
1038 *eec
= *eec
| IXGBE_EEC_SK
;
1039 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
1040 IXGBE_WRITE_FLUSH(hw
);
1045 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1046 * @hw: pointer to hardware structure
1047 * @eecd: EECD's current value
1049 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1052 * Lower the clock input to the EEPROM (clearing the SK bit), then
1055 *eec
= *eec
& ~IXGBE_EEC_SK
;
1056 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
1057 IXGBE_WRITE_FLUSH(hw
);
1062 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1063 * @hw: pointer to hardware structure
1065 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
)
1069 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1071 eec
|= IXGBE_EEC_CS
; /* Pull CS high */
1072 eec
&= ~IXGBE_EEC_SK
; /* Lower SCK */
1074 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1075 IXGBE_WRITE_FLUSH(hw
);
1079 /* Stop requesting EEPROM access */
1080 eec
&= ~IXGBE_EEC_REQ
;
1081 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1083 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1087 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1088 * @hw: pointer to hardware structure
1090 u16
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1099 /* Include 0x0-0x3F in the checksum */
1100 for (i
= 0; i
< IXGBE_EEPROM_CHECKSUM
; i
++) {
1101 if (hw
->eeprom
.ops
.read(hw
, i
, &word
) != 0) {
1102 hw_dbg(hw
, "EEPROM read failed\n");
1108 /* Include all data from pointers except for the fw pointer */
1109 for (i
= IXGBE_PCIE_ANALOG_PTR
; i
< IXGBE_FW_PTR
; i
++) {
1110 hw
->eeprom
.ops
.read(hw
, i
, &pointer
);
1112 /* Make sure the pointer seems valid */
1113 if (pointer
!= 0xFFFF && pointer
!= 0) {
1114 hw
->eeprom
.ops
.read(hw
, pointer
, &length
);
1116 if (length
!= 0xFFFF && length
!= 0) {
1117 for (j
= pointer
+1; j
<= pointer
+length
; j
++) {
1118 hw
->eeprom
.ops
.read(hw
, j
, &word
);
1125 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
1131 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1132 * @hw: pointer to hardware structure
1133 * @checksum_val: calculated checksum
1135 * Performs checksum calculation and validates the EEPROM checksum. If the
1136 * caller does not need checksum_val, the value can be NULL.
1138 s32
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw
*hw
,
1143 u16 read_checksum
= 0;
1146 * Read the first word from the EEPROM. If this times out or fails, do
1147 * not continue or we could be in for a very long wait while every
1150 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1153 checksum
= hw
->eeprom
.ops
.calc_checksum(hw
);
1155 hw
->eeprom
.ops
.read(hw
, IXGBE_EEPROM_CHECKSUM
, &read_checksum
);
1158 * Verify read checksum from EEPROM is the same as
1159 * calculated checksum
1161 if (read_checksum
!= checksum
)
1162 status
= IXGBE_ERR_EEPROM_CHECKSUM
;
1164 /* If the user cares, return the calculated checksum */
1166 *checksum_val
= checksum
;
1168 hw_dbg(hw
, "EEPROM read failed\n");
1175 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1176 * @hw: pointer to hardware structure
1178 s32
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1184 * Read the first word from the EEPROM. If this times out or fails, do
1185 * not continue or we could be in for a very long wait while every
1188 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1191 checksum
= hw
->eeprom
.ops
.calc_checksum(hw
);
1192 status
= hw
->eeprom
.ops
.write(hw
, IXGBE_EEPROM_CHECKSUM
,
1195 hw_dbg(hw
, "EEPROM read failed\n");
1202 * ixgbe_validate_mac_addr - Validate MAC address
1203 * @mac_addr: pointer to MAC address.
1205 * Tests a MAC address to ensure it is a valid Individual Address
1207 s32
ixgbe_validate_mac_addr(u8
*mac_addr
)
1211 /* Make sure it is not a multicast address */
1212 if (IXGBE_IS_MULTICAST(mac_addr
))
1213 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1214 /* Not a broadcast address */
1215 else if (IXGBE_IS_BROADCAST(mac_addr
))
1216 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1217 /* Reject the zero address */
1218 else if (mac_addr
[0] == 0 && mac_addr
[1] == 0 && mac_addr
[2] == 0 &&
1219 mac_addr
[3] == 0 && mac_addr
[4] == 0 && mac_addr
[5] == 0)
1220 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1226 * ixgbe_set_rar_generic - Set Rx address register
1227 * @hw: pointer to hardware structure
1228 * @index: Receive address register to write
1229 * @addr: Address to put into receive address register
1230 * @vmdq: VMDq "set" or "pool" index
1231 * @enable_addr: set flag that address is active
1233 * Puts an ethernet address into a receive address register.
1235 s32
ixgbe_set_rar_generic(struct ixgbe_hw
*hw
, u32 index
, u8
*addr
, u32 vmdq
,
1238 u32 rar_low
, rar_high
;
1239 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1241 /* setup VMDq pool selection before this RAR gets enabled */
1242 hw
->mac
.ops
.set_vmdq(hw
, index
, vmdq
);
1244 /* Make sure we are using a valid rar index range */
1245 if (index
< rar_entries
) {
1247 * HW expects these in little endian so we reverse the byte
1248 * order from network order (big endian) to little endian
1250 rar_low
= ((u32
)addr
[0] |
1251 ((u32
)addr
[1] << 8) |
1252 ((u32
)addr
[2] << 16) |
1253 ((u32
)addr
[3] << 24));
1255 * Some parts put the VMDq setting in the extra RAH bits,
1256 * so save everything except the lower 16 bits that hold part
1257 * of the address and the address valid bit.
1259 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1260 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1261 rar_high
|= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1263 if (enable_addr
!= 0)
1264 rar_high
|= IXGBE_RAH_AV
;
1266 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), rar_low
);
1267 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1269 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1270 return IXGBE_ERR_RAR_INDEX
;
1277 * ixgbe_clear_rar_generic - Remove Rx address register
1278 * @hw: pointer to hardware structure
1279 * @index: Receive address register to write
1281 * Clears an ethernet address from a receive address register.
1283 s32
ixgbe_clear_rar_generic(struct ixgbe_hw
*hw
, u32 index
)
1286 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1288 /* Make sure we are using a valid rar index range */
1289 if (index
< rar_entries
) {
1291 * Some parts put the VMDq setting in the extra RAH bits,
1292 * so save everything except the lower 16 bits that hold part
1293 * of the address and the address valid bit.
1295 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1296 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1298 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), 0);
1299 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1301 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1302 return IXGBE_ERR_RAR_INDEX
;
1305 /* clear VMDq pool/queue selection for this RAR */
1306 hw
->mac
.ops
.clear_vmdq(hw
, index
, IXGBE_CLEAR_VMDQ_ALL
);
1312 * ixgbe_enable_rar - Enable Rx address register
1313 * @hw: pointer to hardware structure
1314 * @index: index into the RAR table
1316 * Enables the select receive address register.
1318 static void ixgbe_enable_rar(struct ixgbe_hw
*hw
, u32 index
)
1322 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1323 rar_high
|= IXGBE_RAH_AV
;
1324 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1328 * ixgbe_disable_rar - Disable Rx address register
1329 * @hw: pointer to hardware structure
1330 * @index: index into the RAR table
1332 * Disables the select receive address register.
1334 static void ixgbe_disable_rar(struct ixgbe_hw
*hw
, u32 index
)
1338 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1339 rar_high
&= (~IXGBE_RAH_AV
);
1340 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1344 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1345 * @hw: pointer to hardware structure
1347 * Places the MAC address in receive address register 0 and clears the rest
1348 * of the receive address registers. Clears the multicast table. Assumes
1349 * the receiver is in reset when the routine is called.
1351 s32
ixgbe_init_rx_addrs_generic(struct ixgbe_hw
*hw
)
1354 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1357 * If the current mac address is valid, assume it is a software override
1358 * to the permanent address.
1359 * Otherwise, use the permanent address from the eeprom.
1361 if (ixgbe_validate_mac_addr(hw
->mac
.addr
) ==
1362 IXGBE_ERR_INVALID_MAC_ADDR
) {
1363 /* Get the MAC address from the RAR0 for later reference */
1364 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.addr
);
1366 hw_dbg(hw
, " Keeping Current RAR0 Addr =%pM\n", hw
->mac
.addr
);
1368 /* Setup the receive address. */
1369 hw_dbg(hw
, "Overriding MAC Address in RAR[0]\n");
1370 hw_dbg(hw
, " New MAC Addr =%pM\n", hw
->mac
.addr
);
1372 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
1374 hw
->addr_ctrl
.overflow_promisc
= 0;
1376 hw
->addr_ctrl
.rar_used_count
= 1;
1378 /* Zero out the other receive addresses. */
1379 hw_dbg(hw
, "Clearing RAR[1-%d]\n", rar_entries
- 1);
1380 for (i
= 1; i
< rar_entries
; i
++) {
1381 IXGBE_WRITE_REG(hw
, IXGBE_RAL(i
), 0);
1382 IXGBE_WRITE_REG(hw
, IXGBE_RAH(i
), 0);
1386 hw
->addr_ctrl
.mc_addr_in_rar_count
= 0;
1387 hw
->addr_ctrl
.mta_in_use
= 0;
1388 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1390 hw_dbg(hw
, " Clearing MTA\n");
1391 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1392 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1394 if (hw
->mac
.ops
.init_uta_tables
)
1395 hw
->mac
.ops
.init_uta_tables(hw
);
1401 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1402 * @hw: pointer to hardware structure
1403 * @addr: new address
1405 * Adds it to unused receive address register or goes into promiscuous mode.
1407 static void ixgbe_add_uc_addr(struct ixgbe_hw
*hw
, u8
*addr
, u32 vmdq
)
1409 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1412 hw_dbg(hw
, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1413 addr
[0], addr
[1], addr
[2], addr
[3], addr
[4], addr
[5]);
1416 * Place this address in the RAR if there is room,
1417 * else put the controller into promiscuous mode
1419 if (hw
->addr_ctrl
.rar_used_count
< rar_entries
) {
1420 rar
= hw
->addr_ctrl
.rar_used_count
-
1421 hw
->addr_ctrl
.mc_addr_in_rar_count
;
1422 hw
->mac
.ops
.set_rar(hw
, rar
, addr
, vmdq
, IXGBE_RAH_AV
);
1423 hw_dbg(hw
, "Added a secondary address to RAR[%d]\n", rar
);
1424 hw
->addr_ctrl
.rar_used_count
++;
1426 hw
->addr_ctrl
.overflow_promisc
++;
1429 hw_dbg(hw
, "ixgbe_add_uc_addr Complete\n");
1433 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1434 * @hw: pointer to hardware structure
1435 * @netdev: pointer to net device structure
1437 * The given list replaces any existing list. Clears the secondary addrs from
1438 * receive address registers. Uses unused receive address registers for the
1439 * first secondary addresses, and falls back to promiscuous mode as needed.
1441 * Drivers using secondary unicast addresses must set user_set_promisc when
1442 * manually putting the device into promiscuous mode.
1444 s32
ixgbe_update_uc_addr_list_generic(struct ixgbe_hw
*hw
,
1445 struct net_device
*netdev
)
1448 u32 old_promisc_setting
= hw
->addr_ctrl
.overflow_promisc
;
1451 struct netdev_hw_addr
*ha
;
1454 * Clear accounting of old secondary address list,
1455 * don't count RAR[0]
1457 uc_addr_in_use
= hw
->addr_ctrl
.rar_used_count
- 1;
1458 hw
->addr_ctrl
.rar_used_count
-= uc_addr_in_use
;
1459 hw
->addr_ctrl
.overflow_promisc
= 0;
1461 /* Zero out the other receive addresses */
1462 hw_dbg(hw
, "Clearing RAR[1-%d]\n", uc_addr_in_use
+ 1);
1463 for (i
= 0; i
< uc_addr_in_use
; i
++) {
1464 IXGBE_WRITE_REG(hw
, IXGBE_RAL(1+i
), 0);
1465 IXGBE_WRITE_REG(hw
, IXGBE_RAH(1+i
), 0);
1468 /* Add the new addresses */
1469 netdev_for_each_uc_addr(ha
, netdev
) {
1470 hw_dbg(hw
, " Adding the secondary addresses:\n");
1471 ixgbe_add_uc_addr(hw
, ha
->addr
, 0);
1474 if (hw
->addr_ctrl
.overflow_promisc
) {
1475 /* enable promisc if not already in overflow or set by user */
1476 if (!old_promisc_setting
&& !hw
->addr_ctrl
.user_set_promisc
) {
1477 hw_dbg(hw
, " Entering address overflow promisc mode\n");
1478 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
1479 fctrl
|= IXGBE_FCTRL_UPE
;
1480 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
1481 hw
->addr_ctrl
.uc_set_promisc
= true;
1484 /* only disable if set by overflow, not by user */
1485 if ((old_promisc_setting
&& hw
->addr_ctrl
.uc_set_promisc
) &&
1486 !(hw
->addr_ctrl
.user_set_promisc
)) {
1487 hw_dbg(hw
, " Leaving address overflow promisc mode\n");
1488 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
1489 fctrl
&= ~IXGBE_FCTRL_UPE
;
1490 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
1491 hw
->addr_ctrl
.uc_set_promisc
= false;
1495 hw_dbg(hw
, "ixgbe_update_uc_addr_list_generic Complete\n");
1500 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1501 * @hw: pointer to hardware structure
1502 * @mc_addr: the multicast address
1504 * Extracts the 12 bits, from a multicast address, to determine which
1505 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1506 * incoming rx multicast addresses, to determine the bit-vector to check in
1507 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1508 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1509 * to mc_filter_type.
1511 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1515 switch (hw
->mac
.mc_filter_type
) {
1516 case 0: /* use bits [47:36] of the address */
1517 vector
= ((mc_addr
[4] >> 4) | (((u16
)mc_addr
[5]) << 4));
1519 case 1: /* use bits [46:35] of the address */
1520 vector
= ((mc_addr
[4] >> 3) | (((u16
)mc_addr
[5]) << 5));
1522 case 2: /* use bits [45:34] of the address */
1523 vector
= ((mc_addr
[4] >> 2) | (((u16
)mc_addr
[5]) << 6));
1525 case 3: /* use bits [43:32] of the address */
1526 vector
= ((mc_addr
[4]) | (((u16
)mc_addr
[5]) << 8));
1528 default: /* Invalid mc_filter_type */
1529 hw_dbg(hw
, "MC filter type param set incorrectly\n");
1533 /* vector can only be 12-bits or boundary will be exceeded */
1539 * ixgbe_set_mta - Set bit-vector in multicast table
1540 * @hw: pointer to hardware structure
1541 * @hash_value: Multicast address hash value
1543 * Sets the bit-vector in the multicast table.
1545 static void ixgbe_set_mta(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1552 hw
->addr_ctrl
.mta_in_use
++;
1554 vector
= ixgbe_mta_vector(hw
, mc_addr
);
1555 hw_dbg(hw
, " bit-vector = 0x%03X\n", vector
);
1558 * The MTA is a register array of 128 32-bit registers. It is treated
1559 * like an array of 4096 bits. We want to set bit
1560 * BitArray[vector_value]. So we figure out what register the bit is
1561 * in, read it, OR in the new bit, then write back the new value. The
1562 * register is determined by the upper 7 bits of the vector value and
1563 * the bit within that register are determined by the lower 5 bits of
1566 vector_reg
= (vector
>> 5) & 0x7F;
1567 vector_bit
= vector
& 0x1F;
1568 mta_reg
= IXGBE_READ_REG(hw
, IXGBE_MTA(vector_reg
));
1569 mta_reg
|= (1 << vector_bit
);
1570 IXGBE_WRITE_REG(hw
, IXGBE_MTA(vector_reg
), mta_reg
);
1574 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1575 * @hw: pointer to hardware structure
1576 * @netdev: pointer to net device structure
1578 * The given list replaces any existing list. Clears the MC addrs from receive
1579 * address registers and the multicast table. Uses unused receive address
1580 * registers for the first multicast addresses, and hashes the rest into the
1583 s32
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw
*hw
,
1584 struct net_device
*netdev
)
1586 struct netdev_hw_addr
*ha
;
1590 * Set the new number of MC addresses that we are being requested to
1593 hw
->addr_ctrl
.num_mc_addrs
= netdev_mc_count(netdev
);
1594 hw
->addr_ctrl
.mta_in_use
= 0;
1597 hw_dbg(hw
, " Clearing MTA\n");
1598 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1599 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1601 /* Add the new addresses */
1602 netdev_for_each_mc_addr(ha
, netdev
) {
1603 hw_dbg(hw
, " Adding the multicast addresses:\n");
1604 ixgbe_set_mta(hw
, ha
->addr
);
1608 if (hw
->addr_ctrl
.mta_in_use
> 0)
1609 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
,
1610 IXGBE_MCSTCTRL_MFE
| hw
->mac
.mc_filter_type
);
1612 hw_dbg(hw
, "ixgbe_update_mc_addr_list_generic Complete\n");
1617 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1618 * @hw: pointer to hardware structure
1620 * Enables multicast address in RAR and the use of the multicast hash table.
1622 s32
ixgbe_enable_mc_generic(struct ixgbe_hw
*hw
)
1625 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1626 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
1628 if (a
->mc_addr_in_rar_count
> 0)
1629 for (i
= (rar_entries
- a
->mc_addr_in_rar_count
);
1630 i
< rar_entries
; i
++)
1631 ixgbe_enable_rar(hw
, i
);
1633 if (a
->mta_in_use
> 0)
1634 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, IXGBE_MCSTCTRL_MFE
|
1635 hw
->mac
.mc_filter_type
);
1641 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1642 * @hw: pointer to hardware structure
1644 * Disables multicast address in RAR and the use of the multicast hash table.
1646 s32
ixgbe_disable_mc_generic(struct ixgbe_hw
*hw
)
1649 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1650 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
1652 if (a
->mc_addr_in_rar_count
> 0)
1653 for (i
= (rar_entries
- a
->mc_addr_in_rar_count
);
1654 i
< rar_entries
; i
++)
1655 ixgbe_disable_rar(hw
, i
);
1657 if (a
->mta_in_use
> 0)
1658 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1664 * ixgbe_fc_enable_generic - Enable flow control
1665 * @hw: pointer to hardware structure
1666 * @packetbuf_num: packet buffer number (0-7)
1668 * Enable flow control according to the current settings.
1670 s32
ixgbe_fc_enable_generic(struct ixgbe_hw
*hw
, s32 packetbuf_num
)
1673 u32 mflcn_reg
, fccfg_reg
;
1679 if (hw
->fc
.requested_mode
== ixgbe_fc_pfc
)
1682 #endif /* CONFIG_DCB */
1683 /* Negotiate the fc mode to use */
1684 ret_val
= ixgbe_fc_autoneg(hw
);
1688 /* Disable any previous flow control settings */
1689 mflcn_reg
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
1690 mflcn_reg
&= ~(IXGBE_MFLCN_RFCE
| IXGBE_MFLCN_RPFCE
);
1692 fccfg_reg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
1693 fccfg_reg
&= ~(IXGBE_FCCFG_TFCE_802_3X
| IXGBE_FCCFG_TFCE_PRIORITY
);
1696 * The possible values of fc.current_mode are:
1697 * 0: Flow control is completely disabled
1698 * 1: Rx flow control is enabled (we can receive pause frames,
1699 * but not send pause frames).
1700 * 2: Tx flow control is enabled (we can send pause frames but
1701 * we do not support receiving pause frames).
1702 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1703 * 4: Priority Flow Control is enabled.
1706 switch (hw
->fc
.current_mode
) {
1709 * Flow control is disabled by software override or autoneg.
1710 * The code below will actually disable it in the HW.
1713 case ixgbe_fc_rx_pause
:
1715 * Rx Flow control is enabled and Tx Flow control is
1716 * disabled by software override. Since there really
1717 * isn't a way to advertise that we are capable of RX
1718 * Pause ONLY, we will advertise that we support both
1719 * symmetric and asymmetric Rx PAUSE. Later, we will
1720 * disable the adapter's ability to send PAUSE frames.
1722 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
1724 case ixgbe_fc_tx_pause
:
1726 * Tx Flow control is enabled, and Rx Flow control is
1727 * disabled by software override.
1729 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
1732 /* Flow control (both Rx and Tx) is enabled by SW override. */
1733 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
1734 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
1740 #endif /* CONFIG_DCB */
1742 hw_dbg(hw
, "Flow control param set incorrectly\n");
1743 ret_val
= IXGBE_ERR_CONFIG
;
1748 /* Set 802.3x based flow control settings. */
1749 mflcn_reg
|= IXGBE_MFLCN_DPF
;
1750 IXGBE_WRITE_REG(hw
, IXGBE_MFLCN
, mflcn_reg
);
1751 IXGBE_WRITE_REG(hw
, IXGBE_FCCFG
, fccfg_reg
);
1753 rx_pba_size
= IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(packetbuf_num
));
1754 rx_pba_size
>>= IXGBE_RXPBSIZE_SHIFT
;
1756 fcrth
= (rx_pba_size
- hw
->fc
.high_water
) << 10;
1757 fcrtl
= (rx_pba_size
- hw
->fc
.low_water
) << 10;
1759 if (hw
->fc
.current_mode
& ixgbe_fc_tx_pause
) {
1760 fcrth
|= IXGBE_FCRTH_FCEN
;
1761 if (hw
->fc
.send_xon
)
1762 fcrtl
|= IXGBE_FCRTL_XONE
;
1765 IXGBE_WRITE_REG(hw
, IXGBE_FCRTH_82599(packetbuf_num
), fcrth
);
1766 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL_82599(packetbuf_num
), fcrtl
);
1768 /* Configure pause time (2 TCs per register) */
1769 reg
= IXGBE_READ_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2));
1770 if ((packetbuf_num
& 1) == 0)
1771 reg
= (reg
& 0xFFFF0000) | hw
->fc
.pause_time
;
1773 reg
= (reg
& 0x0000FFFF) | (hw
->fc
.pause_time
<< 16);
1774 IXGBE_WRITE_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2), reg
);
1776 IXGBE_WRITE_REG(hw
, IXGBE_FCRTV
, (hw
->fc
.pause_time
>> 1));
1783 * ixgbe_fc_autoneg - Configure flow control
1784 * @hw: pointer to hardware structure
1786 * Compares our advertised flow control capabilities to those advertised by
1787 * our link partner, and determines the proper flow control mode to use.
1789 s32
ixgbe_fc_autoneg(struct ixgbe_hw
*hw
)
1792 ixgbe_link_speed speed
;
1793 u32 pcs_anadv_reg
, pcs_lpab_reg
, linkstat
;
1794 u32 links2
, anlp1_reg
, autoc_reg
, links
;
1798 * AN should have completed when the cable was plugged in.
1799 * Look for reasons to bail out. Bail out if:
1800 * - FC autoneg is disabled, or if
1803 * Since we're being called from an LSC, link is already known to be up.
1804 * So use link_up_wait_to_complete=false.
1806 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
1808 if (hw
->fc
.disable_fc_autoneg
|| (!link_up
)) {
1809 hw
->fc
.fc_was_autonegged
= false;
1810 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1815 * On backplane, bail out if
1816 * - backplane autoneg was not completed, or if
1817 * - we are 82599 and link partner is not AN enabled
1819 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
1820 links
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
1821 if ((links
& IXGBE_LINKS_KX_AN_COMP
) == 0) {
1822 hw
->fc
.fc_was_autonegged
= false;
1823 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1827 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1828 links2
= IXGBE_READ_REG(hw
, IXGBE_LINKS2
);
1829 if ((links2
& IXGBE_LINKS2_AN_SUPPORTED
) == 0) {
1830 hw
->fc
.fc_was_autonegged
= false;
1831 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1838 * On multispeed fiber at 1g, bail out if
1839 * - link is up but AN did not complete, or if
1840 * - link is up and AN completed but timed out
1842 if (hw
->phy
.multispeed_fiber
&& (speed
== IXGBE_LINK_SPEED_1GB_FULL
)) {
1843 linkstat
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLSTA
);
1844 if (((linkstat
& IXGBE_PCS1GLSTA_AN_COMPLETE
) == 0) ||
1845 ((linkstat
& IXGBE_PCS1GLSTA_AN_TIMED_OUT
) == 1)) {
1846 hw
->fc
.fc_was_autonegged
= false;
1847 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1854 * - copper or CX4 adapters
1855 * - fiber adapters running at 10gig
1857 if ((hw
->phy
.media_type
== ixgbe_media_type_copper
) ||
1858 (hw
->phy
.media_type
== ixgbe_media_type_cx4
) ||
1859 ((hw
->phy
.media_type
== ixgbe_media_type_fiber
) &&
1860 (speed
== IXGBE_LINK_SPEED_10GB_FULL
))) {
1861 hw
->fc
.fc_was_autonegged
= false;
1862 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1867 * Read the AN advertisement and LP ability registers and resolve
1868 * local flow control settings accordingly
1870 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
1871 (hw
->phy
.media_type
!= ixgbe_media_type_backplane
)) {
1872 pcs_anadv_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
1873 pcs_lpab_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANLP
);
1874 if ((pcs_anadv_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1875 (pcs_lpab_reg
& IXGBE_PCS1GANA_SYM_PAUSE
)) {
1877 * Now we need to check if the user selected Rx ONLY
1878 * of pause frames. In this case, we had to advertise
1879 * FULL flow control because we could not advertise RX
1880 * ONLY. Hence, we must now check to see if we need to
1881 * turn OFF the TRANSMISSION of PAUSE frames.
1883 if (hw
->fc
.requested_mode
== ixgbe_fc_full
) {
1884 hw
->fc
.current_mode
= ixgbe_fc_full
;
1885 hw_dbg(hw
, "Flow Control = FULL.\n");
1887 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1888 hw_dbg(hw
, "Flow Control=RX PAUSE only\n");
1890 } else if (!(pcs_anadv_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1891 (pcs_anadv_reg
& IXGBE_PCS1GANA_ASM_PAUSE
) &&
1892 (pcs_lpab_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1893 (pcs_lpab_reg
& IXGBE_PCS1GANA_ASM_PAUSE
)) {
1894 hw
->fc
.current_mode
= ixgbe_fc_tx_pause
;
1895 hw_dbg(hw
, "Flow Control = TX PAUSE frames only.\n");
1896 } else if ((pcs_anadv_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1897 (pcs_anadv_reg
& IXGBE_PCS1GANA_ASM_PAUSE
) &&
1898 !(pcs_lpab_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1899 (pcs_lpab_reg
& IXGBE_PCS1GANA_ASM_PAUSE
)) {
1900 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1901 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\n");
1903 hw
->fc
.current_mode
= ixgbe_fc_none
;
1904 hw_dbg(hw
, "Flow Control = NONE.\n");
1908 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
1910 * Read the 10g AN autoc and LP ability registers and resolve
1911 * local flow control settings accordingly
1913 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1914 anlp1_reg
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
1916 if ((autoc_reg
& IXGBE_AUTOC_SYM_PAUSE
) &&
1917 (anlp1_reg
& IXGBE_ANLP1_SYM_PAUSE
)) {
1919 * Now we need to check if the user selected Rx ONLY
1920 * of pause frames. In this case, we had to advertise
1921 * FULL flow control because we could not advertise RX
1922 * ONLY. Hence, we must now check to see if we need to
1923 * turn OFF the TRANSMISSION of PAUSE frames.
1925 if (hw
->fc
.requested_mode
== ixgbe_fc_full
) {
1926 hw
->fc
.current_mode
= ixgbe_fc_full
;
1927 hw_dbg(hw
, "Flow Control = FULL.\n");
1929 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1930 hw_dbg(hw
, "Flow Control=RX PAUSE only\n");
1932 } else if (!(autoc_reg
& IXGBE_AUTOC_SYM_PAUSE
) &&
1933 (autoc_reg
& IXGBE_AUTOC_ASM_PAUSE
) &&
1934 (anlp1_reg
& IXGBE_ANLP1_SYM_PAUSE
) &&
1935 (anlp1_reg
& IXGBE_ANLP1_ASM_PAUSE
)) {
1936 hw
->fc
.current_mode
= ixgbe_fc_tx_pause
;
1937 hw_dbg(hw
, "Flow Control = TX PAUSE frames only.\n");
1938 } else if ((autoc_reg
& IXGBE_AUTOC_SYM_PAUSE
) &&
1939 (autoc_reg
& IXGBE_AUTOC_ASM_PAUSE
) &&
1940 !(anlp1_reg
& IXGBE_ANLP1_SYM_PAUSE
) &&
1941 (anlp1_reg
& IXGBE_ANLP1_ASM_PAUSE
)) {
1942 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1943 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\n");
1945 hw
->fc
.current_mode
= ixgbe_fc_none
;
1946 hw_dbg(hw
, "Flow Control = NONE.\n");
1949 /* Record that current_mode is the result of a successful autoneg */
1950 hw
->fc
.fc_was_autonegged
= true;
1957 * ixgbe_setup_fc - Set up flow control
1958 * @hw: pointer to hardware structure
1960 * Called at init time to set up flow control.
1962 static s32
ixgbe_setup_fc(struct ixgbe_hw
*hw
, s32 packetbuf_num
)
1968 if (hw
->fc
.requested_mode
== ixgbe_fc_pfc
) {
1969 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1974 /* Validate the packetbuf configuration */
1975 if (packetbuf_num
< 0 || packetbuf_num
> 7) {
1976 hw_dbg(hw
, "Invalid packet buffer number [%d], expected range "
1977 "is 0-7\n", packetbuf_num
);
1978 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
1983 * Validate the water mark configuration. Zero water marks are invalid
1984 * because it causes the controller to just blast out fc packets.
1986 if (!hw
->fc
.low_water
|| !hw
->fc
.high_water
|| !hw
->fc
.pause_time
) {
1987 hw_dbg(hw
, "Invalid water mark configuration\n");
1988 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
1993 * Validate the requested mode. Strict IEEE mode does not allow
1994 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
1996 if (hw
->fc
.strict_ieee
&& hw
->fc
.requested_mode
== ixgbe_fc_rx_pause
) {
1997 hw_dbg(hw
, "ixgbe_fc_rx_pause not valid in strict "
1999 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
2004 * 10gig parts do not have a word in the EEPROM to determine the
2005 * default flow control setting, so we explicitly set it to full.
2007 if (hw
->fc
.requested_mode
== ixgbe_fc_default
)
2008 hw
->fc
.requested_mode
= ixgbe_fc_full
;
2011 * Set up the 1G flow control advertisement registers so the HW will be
2012 * able to do fc autoneg once the cable is plugged in. If we end up
2013 * using 10g instead, this is harmless.
2015 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
2018 * The possible values of fc.requested_mode are:
2019 * 0: Flow control is completely disabled
2020 * 1: Rx flow control is enabled (we can receive pause frames,
2021 * but not send pause frames).
2022 * 2: Tx flow control is enabled (we can send pause frames but
2023 * we do not support receiving pause frames).
2024 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2026 * 4: Priority Flow Control is enabled.
2030 switch (hw
->fc
.requested_mode
) {
2032 /* Flow control completely disabled by software override. */
2033 reg
&= ~(IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
2035 case ixgbe_fc_rx_pause
:
2037 * Rx Flow control is enabled and Tx Flow control is
2038 * disabled by software override. Since there really
2039 * isn't a way to advertise that we are capable of RX
2040 * Pause ONLY, we will advertise that we support both
2041 * symmetric and asymmetric Rx PAUSE. Later, we will
2042 * disable the adapter's ability to send PAUSE frames.
2044 reg
|= (IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
2046 case ixgbe_fc_tx_pause
:
2048 * Tx Flow control is enabled, and Rx Flow control is
2049 * disabled by software override.
2051 reg
|= (IXGBE_PCS1GANA_ASM_PAUSE
);
2052 reg
&= ~(IXGBE_PCS1GANA_SYM_PAUSE
);
2055 /* Flow control (both Rx and Tx) is enabled by SW override. */
2056 reg
|= (IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
2062 #endif /* CONFIG_DCB */
2064 hw_dbg(hw
, "Flow control param set incorrectly\n");
2065 ret_val
= IXGBE_ERR_CONFIG
;
2070 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GANA
, reg
);
2071 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLCTL
);
2073 /* Disable AN timeout */
2074 if (hw
->fc
.strict_ieee
)
2075 reg
&= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN
;
2077 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GLCTL
, reg
);
2078 hw_dbg(hw
, "Set up FC; PCS1GLCTL = 0x%08X\n", reg
);
2081 * Set up the 10G flow control advertisement registers so the HW
2082 * can do fc autoneg once the cable is plugged in. If we end up
2083 * using 1g instead, this is harmless.
2085 reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2088 * The possible values of fc.requested_mode are:
2089 * 0: Flow control is completely disabled
2090 * 1: Rx flow control is enabled (we can receive pause frames,
2091 * but not send pause frames).
2092 * 2: Tx flow control is enabled (we can send pause frames but
2093 * we do not support receiving pause frames).
2094 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2097 switch (hw
->fc
.requested_mode
) {
2099 /* Flow control completely disabled by software override. */
2100 reg
&= ~(IXGBE_AUTOC_SYM_PAUSE
| IXGBE_AUTOC_ASM_PAUSE
);
2102 case ixgbe_fc_rx_pause
:
2104 * Rx Flow control is enabled and Tx Flow control is
2105 * disabled by software override. Since there really
2106 * isn't a way to advertise that we are capable of RX
2107 * Pause ONLY, we will advertise that we support both
2108 * symmetric and asymmetric Rx PAUSE. Later, we will
2109 * disable the adapter's ability to send PAUSE frames.
2111 reg
|= (IXGBE_AUTOC_SYM_PAUSE
| IXGBE_AUTOC_ASM_PAUSE
);
2113 case ixgbe_fc_tx_pause
:
2115 * Tx Flow control is enabled, and Rx Flow control is
2116 * disabled by software override.
2118 reg
|= (IXGBE_AUTOC_ASM_PAUSE
);
2119 reg
&= ~(IXGBE_AUTOC_SYM_PAUSE
);
2122 /* Flow control (both Rx and Tx) is enabled by SW override. */
2123 reg
|= (IXGBE_AUTOC_SYM_PAUSE
| IXGBE_AUTOC_ASM_PAUSE
);
2129 #endif /* CONFIG_DCB */
2131 hw_dbg(hw
, "Flow control param set incorrectly\n");
2132 ret_val
= IXGBE_ERR_CONFIG
;
2137 * AUTOC restart handles negotiation of 1G and 10G. There is
2138 * no need to set the PCS1GCTL register.
2140 reg
|= IXGBE_AUTOC_AN_RESTART
;
2141 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, reg
);
2142 hw_dbg(hw
, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg
);
2149 * ixgbe_disable_pcie_master - Disable PCI-express master access
2150 * @hw: pointer to hardware structure
2152 * Disables PCI-Express master access and verifies there are no pending
2153 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2154 * bit hasn't caused the master requests to be disabled, else 0
2155 * is returned signifying master requests disabled.
2157 s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
)
2161 u32 number_of_queues
;
2162 s32 status
= IXGBE_ERR_MASTER_REQUESTS_PENDING
;
2164 /* Disable the receive unit by stopping each queue */
2165 number_of_queues
= hw
->mac
.max_rx_queues
;
2166 for (i
= 0; i
< number_of_queues
; i
++) {
2167 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
2168 if (reg_val
& IXGBE_RXDCTL_ENABLE
) {
2169 reg_val
&= ~IXGBE_RXDCTL_ENABLE
;
2170 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(i
), reg_val
);
2174 reg_val
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
2175 reg_val
|= IXGBE_CTRL_GIO_DIS
;
2176 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, reg_val
);
2178 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
2179 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
)) {
2191 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2192 * @hw: pointer to hardware structure
2193 * @mask: Mask to specify which semaphore to acquire
2195 * Acquires the SWFW semaphore thought the GSSR register for the specified
2196 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2198 s32
ixgbe_acquire_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
2202 u32 fwmask
= mask
<< 5;
2206 if (ixgbe_get_eeprom_semaphore(hw
))
2207 return IXGBE_ERR_SWFW_SYNC
;
2209 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2210 if (!(gssr
& (fwmask
| swmask
)))
2214 * Firmware currently using resource (fwmask) or other software
2215 * thread currently using resource (swmask)
2217 ixgbe_release_eeprom_semaphore(hw
);
2223 hw_dbg(hw
, "Driver can't access resource, GSSR timeout.\n");
2224 return IXGBE_ERR_SWFW_SYNC
;
2228 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2230 ixgbe_release_eeprom_semaphore(hw
);
2235 * ixgbe_release_swfw_sync - Release SWFW semaphore
2236 * @hw: pointer to hardware structure
2237 * @mask: Mask to specify which semaphore to release
2239 * Releases the SWFW semaphore thought the GSSR register for the specified
2240 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2242 void ixgbe_release_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
2247 ixgbe_get_eeprom_semaphore(hw
);
2249 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2251 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2253 ixgbe_release_eeprom_semaphore(hw
);
2257 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2258 * @hw: pointer to hardware structure
2259 * @regval: register value to write to RXCTRL
2261 * Enables the Rx DMA unit
2263 s32
ixgbe_enable_rx_dma_generic(struct ixgbe_hw
*hw
, u32 regval
)
2265 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
2271 * ixgbe_blink_led_start_generic - Blink LED based on index.
2272 * @hw: pointer to hardware structure
2273 * @index: led number to blink
2275 s32
ixgbe_blink_led_start_generic(struct ixgbe_hw
*hw
, u32 index
)
2277 ixgbe_link_speed speed
= 0;
2279 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2280 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2283 * Link must be up to auto-blink the LEDs;
2284 * Force it if link is down.
2286 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
2289 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2290 autoc_reg
|= IXGBE_AUTOC_FLU
;
2291 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
2295 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2296 led_reg
|= IXGBE_LED_BLINK(index
);
2297 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2298 IXGBE_WRITE_FLUSH(hw
);
2304 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2305 * @hw: pointer to hardware structure
2306 * @index: led number to stop blinking
2308 s32
ixgbe_blink_led_stop_generic(struct ixgbe_hw
*hw
, u32 index
)
2310 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2311 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2313 autoc_reg
&= ~IXGBE_AUTOC_FLU
;
2314 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2315 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
2317 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2318 led_reg
&= ~IXGBE_LED_BLINK(index
);
2319 led_reg
|= IXGBE_LED_LINK_ACTIVE
<< IXGBE_LED_MODE_SHIFT(index
);
2320 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2321 IXGBE_WRITE_FLUSH(hw
);
2327 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2328 * @hw: pointer to hardware structure
2329 * @san_mac_offset: SAN MAC address offset
2331 * This function will read the EEPROM location for the SAN MAC address
2332 * pointer, and returns the value at that location. This is used in both
2333 * get and set mac_addr routines.
2335 static s32
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw
*hw
,
2336 u16
*san_mac_offset
)
2339 * First read the EEPROM pointer to see if the MAC addresses are
2342 hw
->eeprom
.ops
.read(hw
, IXGBE_SAN_MAC_ADDR_PTR
, san_mac_offset
);
2348 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2349 * @hw: pointer to hardware structure
2350 * @san_mac_addr: SAN MAC address
2352 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2353 * per-port, so set_lan_id() must be called before reading the addresses.
2354 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2355 * upon for non-SFP connections, so we must call it here.
2357 s32
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*san_mac_addr
)
2359 u16 san_mac_data
, san_mac_offset
;
2363 * First read the EEPROM pointer to see if the MAC addresses are
2364 * available. If they're not, no point in calling set_lan_id() here.
2366 ixgbe_get_san_mac_addr_offset(hw
, &san_mac_offset
);
2368 if ((san_mac_offset
== 0) || (san_mac_offset
== 0xFFFF)) {
2370 * No addresses available in this EEPROM. It's not an
2371 * error though, so just wipe the local address and return.
2373 for (i
= 0; i
< 6; i
++)
2374 san_mac_addr
[i
] = 0xFF;
2376 goto san_mac_addr_out
;
2379 /* make sure we know which port we need to program */
2380 hw
->mac
.ops
.set_lan_id(hw
);
2381 /* apply the port offset to the address offset */
2382 (hw
->bus
.func
) ? (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
) :
2383 (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
);
2384 for (i
= 0; i
< 3; i
++) {
2385 hw
->eeprom
.ops
.read(hw
, san_mac_offset
, &san_mac_data
);
2386 san_mac_addr
[i
* 2] = (u8
)(san_mac_data
);
2387 san_mac_addr
[i
* 2 + 1] = (u8
)(san_mac_data
>> 8);
2396 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2397 * @hw: pointer to hardware structure
2399 * Read PCIe configuration space, and get the MSI-X vector count from
2400 * the capabilities table.
2402 u32
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw
*hw
)
2404 struct ixgbe_adapter
*adapter
= hw
->back
;
2406 pci_read_config_word(adapter
->pdev
, IXGBE_PCIE_MSIX_82599_CAPS
,
2408 msix_count
&= IXGBE_PCIE_MSIX_TBL_SZ_MASK
;
2410 /* MSI-X count is zero-based in HW, so increment to give proper value */
2417 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2418 * @hw: pointer to hardware struct
2419 * @rar: receive address register index to disassociate
2420 * @vmdq: VMDq pool index to remove from the rar
2422 s32
ixgbe_clear_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2424 u32 mpsar_lo
, mpsar_hi
;
2425 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2427 if (rar
< rar_entries
) {
2428 mpsar_lo
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2429 mpsar_hi
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2431 if (!mpsar_lo
&& !mpsar_hi
)
2434 if (vmdq
== IXGBE_CLEAR_VMDQ_ALL
) {
2436 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 0);
2440 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 0);
2443 } else if (vmdq
< 32) {
2444 mpsar_lo
&= ~(1 << vmdq
);
2445 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar_lo
);
2447 mpsar_hi
&= ~(1 << (vmdq
- 32));
2448 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar_hi
);
2451 /* was that the last pool using this rar? */
2452 if (mpsar_lo
== 0 && mpsar_hi
== 0 && rar
!= 0)
2453 hw
->mac
.ops
.clear_rar(hw
, rar
);
2455 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2463 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2464 * @hw: pointer to hardware struct
2465 * @rar: receive address register index to associate with a VMDq index
2466 * @vmdq: VMDq pool index
2468 s32
ixgbe_set_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2471 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2473 if (rar
< rar_entries
) {
2475 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2477 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar
);
2479 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2480 mpsar
|= 1 << (vmdq
- 32);
2481 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar
);
2484 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2490 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2491 * @hw: pointer to hardware structure
2493 s32
ixgbe_init_uta_tables_generic(struct ixgbe_hw
*hw
)
2498 for (i
= 0; i
< 128; i
++)
2499 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), 0);
2505 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2506 * @hw: pointer to hardware structure
2507 * @vlan: VLAN id to write to VLAN filter
2509 * return the VLVF index where this VLAN id should be placed
2512 static s32
ixgbe_find_vlvf_slot(struct ixgbe_hw
*hw
, u32 vlan
)
2515 u32 first_empty_slot
= 0;
2518 /* short cut the special case */
2523 * Search for the vlan id in the VLVF entries. Save off the first empty
2524 * slot found along the way
2526 for (regindex
= 1; regindex
< IXGBE_VLVF_ENTRIES
; regindex
++) {
2527 bits
= IXGBE_READ_REG(hw
, IXGBE_VLVF(regindex
));
2528 if (!bits
&& !(first_empty_slot
))
2529 first_empty_slot
= regindex
;
2530 else if ((bits
& 0x0FFF) == vlan
)
2535 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2536 * in the VLVF. Else use the first empty VLVF register for this
2539 if (regindex
>= IXGBE_VLVF_ENTRIES
) {
2540 if (first_empty_slot
)
2541 regindex
= first_empty_slot
;
2543 hw_dbg(hw
, "No space in VLVF.\n");
2544 regindex
= IXGBE_ERR_NO_SPACE
;
2552 * ixgbe_set_vfta_generic - Set VLAN filter table
2553 * @hw: pointer to hardware structure
2554 * @vlan: VLAN id to write to VLAN filter
2555 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2556 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2558 * Turn on/off specified VLAN in the VLAN filter table.
2560 s32
ixgbe_set_vfta_generic(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
2569 bool vfta_changed
= false;
2572 return IXGBE_ERR_PARAM
;
2575 * this is a 2 part operation - first the VFTA, then the
2576 * VLVF and VLVFB if VT Mode is set
2577 * We don't write the VFTA until we know the VLVF part succeeded.
2581 * The VFTA is a bitstring made up of 128 32-bit registers
2582 * that enable the particular VLAN id, much like the MTA:
2583 * bits[11-5]: which register
2584 * bits[4-0]: which bit in the register
2586 regindex
= (vlan
>> 5) & 0x7F;
2587 bitindex
= vlan
& 0x1F;
2588 targetbit
= (1 << bitindex
);
2589 vfta
= IXGBE_READ_REG(hw
, IXGBE_VFTA(regindex
));
2592 if (!(vfta
& targetbit
)) {
2594 vfta_changed
= true;
2597 if ((vfta
& targetbit
)) {
2599 vfta_changed
= true;
2606 * make sure the vlan is in VLVF
2607 * set the vind bit in the matching VLVFB
2609 * clear the pool bit and possibly the vind
2611 vt
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2612 if (vt
& IXGBE_VT_CTL_VT_ENABLE
) {
2615 vlvf_index
= ixgbe_find_vlvf_slot(hw
, vlan
);
2620 /* set the pool bit */
2622 bits
= IXGBE_READ_REG(hw
,
2623 IXGBE_VLVFB(vlvf_index
*2));
2624 bits
|= (1 << vind
);
2626 IXGBE_VLVFB(vlvf_index
*2),
2629 bits
= IXGBE_READ_REG(hw
,
2630 IXGBE_VLVFB((vlvf_index
*2)+1));
2631 bits
|= (1 << (vind
-32));
2633 IXGBE_VLVFB((vlvf_index
*2)+1),
2637 /* clear the pool bit */
2639 bits
= IXGBE_READ_REG(hw
,
2640 IXGBE_VLVFB(vlvf_index
*2));
2641 bits
&= ~(1 << vind
);
2643 IXGBE_VLVFB(vlvf_index
*2),
2645 bits
|= IXGBE_READ_REG(hw
,
2646 IXGBE_VLVFB((vlvf_index
*2)+1));
2648 bits
= IXGBE_READ_REG(hw
,
2649 IXGBE_VLVFB((vlvf_index
*2)+1));
2650 bits
&= ~(1 << (vind
-32));
2652 IXGBE_VLVFB((vlvf_index
*2)+1),
2654 bits
|= IXGBE_READ_REG(hw
,
2655 IXGBE_VLVFB(vlvf_index
*2));
2660 * If there are still bits set in the VLVFB registers
2661 * for the VLAN ID indicated we need to see if the
2662 * caller is requesting that we clear the VFTA entry bit.
2663 * If the caller has requested that we clear the VFTA
2664 * entry bit but there are still pools/VFs using this VLAN
2665 * ID entry then ignore the request. We're not worried
2666 * about the case where we're turning the VFTA VLAN ID
2667 * entry bit on, only when requested to turn it off as
2668 * there may be multiple pools and/or VFs using the
2669 * VLAN ID entry. In that case we cannot clear the
2670 * VFTA bit until all pools/VFs using that VLAN ID have also
2671 * been cleared. This will be indicated by "bits" being
2675 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
),
2676 (IXGBE_VLVF_VIEN
| vlan
));
2678 /* someone wants to clear the vfta entry
2679 * but some pools/VFs are still using it.
2681 vfta_changed
= false;
2685 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
), 0);
2689 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regindex
), vfta
);
2695 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2696 * @hw: pointer to hardware structure
2698 * Clears the VLAN filer table, and the VMDq index associated with the filter
2700 s32
ixgbe_clear_vfta_generic(struct ixgbe_hw
*hw
)
2704 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
2705 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(offset
), 0);
2707 for (offset
= 0; offset
< IXGBE_VLVF_ENTRIES
; offset
++) {
2708 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(offset
), 0);
2709 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(offset
*2), 0);
2710 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB((offset
*2)+1), 0);
2717 * ixgbe_check_mac_link_generic - Determine link and speed status
2718 * @hw: pointer to hardware structure
2719 * @speed: pointer to link speed
2720 * @link_up: true when link is up
2721 * @link_up_wait_to_complete: bool used to wait for link up or not
2723 * Reads the links register to determine if link is up and the current speed
2725 s32
ixgbe_check_mac_link_generic(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
,
2726 bool *link_up
, bool link_up_wait_to_complete
)
2731 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2732 if (link_up_wait_to_complete
) {
2733 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
2734 if (links_reg
& IXGBE_LINKS_UP
) {
2741 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2744 if (links_reg
& IXGBE_LINKS_UP
)
2750 if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
2751 IXGBE_LINKS_SPEED_10G_82599
)
2752 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
2753 else if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
2754 IXGBE_LINKS_SPEED_1G_82599
)
2755 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
2757 *speed
= IXGBE_LINK_SPEED_100_FULL
;
2759 /* if link is down, zero out the current_mode */
2760 if (*link_up
== false) {
2761 hw
->fc
.current_mode
= ixgbe_fc_none
;
2762 hw
->fc
.fc_was_autonegged
= false;
2769 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
2771 * @hw: pointer to hardware structure
2772 * @wwnn_prefix: the alternative WWNN prefix
2773 * @wwpn_prefix: the alternative WWPN prefix
2775 * This function will read the EEPROM from the alternative SAN MAC address
2776 * block to check the support for the alternative WWNN/WWPN prefix support.
2778 s32
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw
*hw
, u16
*wwnn_prefix
,
2782 u16 alt_san_mac_blk_offset
;
2784 /* clear output first */
2785 *wwnn_prefix
= 0xFFFF;
2786 *wwpn_prefix
= 0xFFFF;
2788 /* check if alternative SAN MAC is supported */
2789 hw
->eeprom
.ops
.read(hw
, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR
,
2790 &alt_san_mac_blk_offset
);
2792 if ((alt_san_mac_blk_offset
== 0) ||
2793 (alt_san_mac_blk_offset
== 0xFFFF))
2794 goto wwn_prefix_out
;
2796 /* check capability in alternative san mac address block */
2797 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET
;
2798 hw
->eeprom
.ops
.read(hw
, offset
, &caps
);
2799 if (!(caps
& IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN
))
2800 goto wwn_prefix_out
;
2802 /* get the corresponding prefix for WWNN/WWPN */
2803 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET
;
2804 hw
->eeprom
.ops
.read(hw
, offset
, wwnn_prefix
);
2806 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET
;
2807 hw
->eeprom
.ops
.read(hw
, offset
, wwpn_prefix
);
2814 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2815 * @hw: pointer to hardware structure
2816 * @enable: enable or disable switch for anti-spoofing
2817 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
2820 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int pf
)
2823 int pf_target_reg
= pf
>> 3;
2824 int pf_target_shift
= pf
% 8;
2827 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2831 pfvfspoof
= IXGBE_SPOOF_MACAS_MASK
;
2834 * PFVFSPOOF register array is size 8 with 8 bits assigned to
2835 * MAC anti-spoof enables in each register array element.
2837 for (j
= 0; j
< IXGBE_PFVFSPOOF_REG_COUNT
; j
++)
2838 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(j
), pfvfspoof
);
2840 /* If not enabling anti-spoofing then done */
2845 * The PF should be allowed to spoof so that it can support
2846 * emulation mode NICs. Reset the bit assigned to the PF
2848 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(pf_target_reg
));
2849 pfvfspoof
^= (1 << pf_target_shift
);
2850 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(pf_target_reg
), pfvfspoof
);
2854 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
2855 * @hw: pointer to hardware structure
2856 * @enable: enable or disable switch for VLAN anti-spoofing
2857 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
2860 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int vf
)
2862 int vf_target_reg
= vf
>> 3;
2863 int vf_target_shift
= vf
% 8 + IXGBE_SPOOF_VLANAS_SHIFT
;
2866 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2869 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
));
2871 pfvfspoof
|= (1 << vf_target_shift
);
2873 pfvfspoof
&= ~(1 << vf_target_shift
);
2874 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
), pfvfspoof
);