2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/irq_work.h>
40 #include <linux/export.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex
);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly
;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count
);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly
= 1;
76 static int banks __read_mostly
;
77 static int rip_msr __read_mostly
;
78 static int mce_bootlog __read_mostly
= -1;
79 static int monarch_timeout __read_mostly
= -1;
80 static int mce_panic_timeout __read_mostly
;
81 static int mce_dont_log_ce __read_mostly
;
82 int mce_cmci_disabled __read_mostly
;
83 int mce_ignore_ce __read_mostly
;
84 int mce_ser __read_mostly
;
86 struct mce_bank
*mce_banks __read_mostly
;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify
;
90 static char mce_helper
[128];
91 static char *mce_helper_argv
[2] = { mce_helper
, NULL
};
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait
);
95 static DEFINE_PER_CPU(struct mce
, mces_seen
);
96 static int cpu_missing
;
98 /* MCA banks polled by the period polling timer for corrected events */
99 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
100 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
103 static DEFINE_PER_CPU(struct work_struct
, mce_work
);
106 * CPU/chipset specific EDAC code can register a notifier call here to print
107 * MCE errors in a human-readable form.
109 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain
);
111 /* Do initial initialization of a struct mce */
112 void mce_setup(struct mce
*m
)
114 memset(m
, 0, sizeof(struct mce
));
115 m
->cpu
= m
->extcpu
= smp_processor_id();
117 /* We hope get_seconds stays lockless */
118 m
->time
= get_seconds();
119 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
120 m
->cpuid
= cpuid_eax(1);
122 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
124 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
125 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
128 DEFINE_PER_CPU(struct mce
, injectm
);
129 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
132 * Lockless MCE logging infrastructure.
133 * This avoids deadlocks on printk locks without having to break locks. Also
134 * separate MCEs from kernel messages to avoid bogus bug reports.
137 static struct mce_log mcelog
= {
138 .signature
= MCE_LOG_SIGNATURE
,
140 .recordlen
= sizeof(struct mce
),
143 void mce_log(struct mce
*mce
)
145 unsigned next
, entry
;
148 /* Emit the trace record: */
149 trace_mce_record(mce
);
151 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, mce
);
152 if (ret
== NOTIFY_STOP
)
158 entry
= rcu_dereference_check_mce(mcelog
.next
);
162 * When the buffer fills up discard new entries.
163 * Assume that the earlier errors are the more
166 if (entry
>= MCE_LOG_LEN
) {
167 set_bit(MCE_OVERFLOW
,
168 (unsigned long *)&mcelog
.flags
);
171 /* Old left over entry. Skip: */
172 if (mcelog
.entry
[entry
].finished
) {
180 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
183 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
185 mcelog
.entry
[entry
].finished
= 1;
189 set_bit(0, &mce_need_notify
);
192 void mce_register_decode_chain(struct notifier_block
*nb
)
194 atomic_notifier_chain_register(&x86_mce_decoder_chain
, nb
);
196 EXPORT_SYMBOL_GPL(mce_register_decode_chain
);
198 void mce_unregister_decode_chain(struct notifier_block
*nb
)
200 atomic_notifier_chain_unregister(&x86_mce_decoder_chain
, nb
);
202 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain
);
204 static void print_mce(struct mce
*m
)
208 pr_emerg(HW_ERR
"CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
209 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
212 pr_emerg(HW_ERR
"RIP%s %02x:<%016Lx> ",
213 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
216 if (m
->cs
== __KERNEL_CS
)
217 print_symbol("{%s}", m
->ip
);
221 pr_emerg(HW_ERR
"TSC %llx ", m
->tsc
);
223 pr_cont("ADDR %llx ", m
->addr
);
225 pr_cont("MISC %llx ", m
->misc
);
229 * Note this output is parsed by external tools and old fields
230 * should not be changed.
232 pr_emerg(HW_ERR
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
233 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
, m
->apicid
,
234 cpu_data(m
->extcpu
).microcode
);
237 * Print out human-readable details about the MCE error,
238 * (if the CPU has an implementation for that)
240 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
241 if (ret
== NOTIFY_STOP
)
244 pr_emerg_ratelimited(HW_ERR
"Run the above through 'mcelog --ascii'\n");
247 #define PANIC_TIMEOUT 5 /* 5 seconds */
249 static atomic_t mce_paniced
;
251 static int fake_panic
;
252 static atomic_t mce_fake_paniced
;
254 /* Panic in progress. Enable interrupts and wait for final IPI */
255 static void wait_for_panic(void)
257 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
261 while (timeout
-- > 0)
263 if (panic_timeout
== 0)
264 panic_timeout
= mce_panic_timeout
;
265 panic("Panicing machine check CPU died");
268 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
274 * Make sure only one CPU runs in machine check panic
276 if (atomic_inc_return(&mce_paniced
) > 1)
283 /* Don't log too much for fake panic */
284 if (atomic_inc_return(&mce_fake_paniced
) > 1)
287 /* First print corrected ones that are still unlogged */
288 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
289 struct mce
*m
= &mcelog
.entry
[i
];
290 if (!(m
->status
& MCI_STATUS_VAL
))
292 if (!(m
->status
& MCI_STATUS_UC
)) {
295 apei_err
= apei_write_mce(m
);
298 /* Now print uncorrected but with the final one last */
299 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
300 struct mce
*m
= &mcelog
.entry
[i
];
301 if (!(m
->status
& MCI_STATUS_VAL
))
303 if (!(m
->status
& MCI_STATUS_UC
))
305 if (!final
|| memcmp(m
, final
, sizeof(struct mce
))) {
308 apei_err
= apei_write_mce(m
);
314 apei_err
= apei_write_mce(final
);
317 pr_emerg(HW_ERR
"Some CPUs didn't answer in synchronization\n");
319 pr_emerg(HW_ERR
"Machine check: %s\n", exp
);
321 if (panic_timeout
== 0)
322 panic_timeout
= mce_panic_timeout
;
325 pr_emerg(HW_ERR
"Fake kernel panic: %s\n", msg
);
328 /* Support code for software error injection */
330 static int msr_to_offset(u32 msr
)
332 unsigned bank
= __this_cpu_read(injectm
.bank
);
335 return offsetof(struct mce
, ip
);
336 if (msr
== MSR_IA32_MCx_STATUS(bank
))
337 return offsetof(struct mce
, status
);
338 if (msr
== MSR_IA32_MCx_ADDR(bank
))
339 return offsetof(struct mce
, addr
);
340 if (msr
== MSR_IA32_MCx_MISC(bank
))
341 return offsetof(struct mce
, misc
);
342 if (msr
== MSR_IA32_MCG_STATUS
)
343 return offsetof(struct mce
, mcgstatus
);
347 /* MSR access wrappers used for error injection */
348 static u64
mce_rdmsrl(u32 msr
)
352 if (__this_cpu_read(injectm
.finished
)) {
353 int offset
= msr_to_offset(msr
);
357 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
360 if (rdmsrl_safe(msr
, &v
)) {
361 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr
);
363 * Return zero in case the access faulted. This should
364 * not happen normally but can happen if the CPU does
365 * something weird, or if the code is buggy.
373 static void mce_wrmsrl(u32 msr
, u64 v
)
375 if (__this_cpu_read(injectm
.finished
)) {
376 int offset
= msr_to_offset(msr
);
379 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
386 * Collect all global (w.r.t. this processor) status about this machine
387 * check into our "mce" struct so that we can use it later to assess
388 * the severity of the problem as we read per-bank specific details.
390 static inline void mce_gather_info(struct mce
*m
, struct pt_regs
*regs
)
394 m
->mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
397 * Get the address of the instruction at the time of
398 * the machine check error.
400 if (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
)) {
404 /* Use accurate RIP reporting if available. */
406 m
->ip
= mce_rdmsrl(rip_msr
);
411 * Simple lockless ring to communicate PFNs from the exception handler with the
412 * process context work function. This is vastly simplified because there's
413 * only a single reader and a single writer.
415 #define MCE_RING_SIZE 16 /* we use one entry less */
418 unsigned short start
;
420 unsigned long ring
[MCE_RING_SIZE
];
422 static DEFINE_PER_CPU(struct mce_ring
, mce_ring
);
424 /* Runs with CPU affinity in workqueue */
425 static int mce_ring_empty(void)
427 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
429 return r
->start
== r
->end
;
432 static int mce_ring_get(unsigned long *pfn
)
439 r
= &__get_cpu_var(mce_ring
);
440 if (r
->start
== r
->end
)
442 *pfn
= r
->ring
[r
->start
];
443 r
->start
= (r
->start
+ 1) % MCE_RING_SIZE
;
450 /* Always runs in MCE context with preempt off */
451 static int mce_ring_add(unsigned long pfn
)
453 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
456 next
= (r
->end
+ 1) % MCE_RING_SIZE
;
457 if (next
== r
->start
)
459 r
->ring
[r
->end
] = pfn
;
465 int mce_available(struct cpuinfo_x86
*c
)
469 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
472 static void mce_schedule_work(void)
474 if (!mce_ring_empty()) {
475 struct work_struct
*work
= &__get_cpu_var(mce_work
);
476 if (!work_pending(work
))
481 DEFINE_PER_CPU(struct irq_work
, mce_irq_work
);
483 static void mce_irq_work_cb(struct irq_work
*entry
)
489 static void mce_report_event(struct pt_regs
*regs
)
491 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
494 * Triggering the work queue here is just an insurance
495 * policy in case the syscall exit notify handler
496 * doesn't run soon enough or ends up running on the
497 * wrong CPU (can happen when audit sleeps)
503 irq_work_queue(&__get_cpu_var(mce_irq_work
));
506 DEFINE_PER_CPU(unsigned, mce_poll_count
);
509 * Poll for corrected events or events that happened before reset.
510 * Those are just logged through /dev/mcelog.
512 * This is executed in standard interrupt context.
514 * Note: spec recommends to panic for fatal unsignalled
515 * errors here. However this would be quite problematic --
516 * we would need to reimplement the Monarch handling and
517 * it would mess up the exclusion between exception handler
518 * and poll hander -- * so we skip this for now.
519 * These cases should not happen anyways, or only when the CPU
520 * is already totally * confused. In this case it's likely it will
521 * not fully execute the machine check handler either.
523 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
528 percpu_inc(mce_poll_count
);
530 mce_gather_info(&m
, NULL
);
532 for (i
= 0; i
< banks
; i
++) {
533 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
542 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
543 if (!(m
.status
& MCI_STATUS_VAL
))
547 * Uncorrected or signalled events are handled by the exception
548 * handler when it is enabled, so don't process those here.
550 * TBD do the same check for MCI_STATUS_EN here?
552 if (!(flags
& MCP_UC
) &&
553 (m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)))
556 if (m
.status
& MCI_STATUS_MISCV
)
557 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
558 if (m
.status
& MCI_STATUS_ADDRV
)
559 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
561 if (!(flags
& MCP_TIMESTAMP
))
564 * Don't get the IP here because it's unlikely to
565 * have anything to do with the actual error location.
567 if (!(flags
& MCP_DONTLOG
) && !mce_dont_log_ce
)
571 * Clear state for this bank.
573 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
577 * Don't clear MCG_STATUS here because it's only defined for
583 EXPORT_SYMBOL_GPL(machine_check_poll
);
586 * Do a quick check if any of the events requires a panic.
587 * This decides if we keep the events around or clear them.
589 static int mce_no_way_out(struct mce
*m
, char **msg
)
593 for (i
= 0; i
< banks
; i
++) {
594 m
->status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
595 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
602 * Variable to establish order between CPUs while scanning.
603 * Each CPU spins initially until executing is equal its number.
605 static atomic_t mce_executing
;
608 * Defines order of CPUs on entry. First CPU becomes Monarch.
610 static atomic_t mce_callin
;
613 * Check if a timeout waiting for other CPUs happened.
615 static int mce_timed_out(u64
*t
)
618 * The others already did panic for some reason.
619 * Bail out like in a timeout.
620 * rmb() to tell the compiler that system_state
621 * might have been modified by someone else.
624 if (atomic_read(&mce_paniced
))
626 if (!monarch_timeout
)
628 if ((s64
)*t
< SPINUNIT
) {
629 /* CHECKME: Make panic default for 1 too? */
631 mce_panic("Timeout synchronizing machine check over CPUs",
638 touch_nmi_watchdog();
643 * The Monarch's reign. The Monarch is the CPU who entered
644 * the machine check handler first. It waits for the others to
645 * raise the exception too and then grades them. When any
646 * error is fatal panic. Only then let the others continue.
648 * The other CPUs entering the MCE handler will be controlled by the
649 * Monarch. They are called Subjects.
651 * This way we prevent any potential data corruption in a unrecoverable case
652 * and also makes sure always all CPU's errors are examined.
654 * Also this detects the case of a machine check event coming from outer
655 * space (not detected by any CPUs) In this case some external agent wants
656 * us to shut down, so panic too.
658 * The other CPUs might still decide to panic if the handler happens
659 * in a unrecoverable place, but in this case the system is in a semi-stable
660 * state and won't corrupt anything by itself. It's ok to let the others
661 * continue for a bit first.
663 * All the spin loops have timeouts; when a timeout happens a CPU
664 * typically elects itself to be Monarch.
666 static void mce_reign(void)
669 struct mce
*m
= NULL
;
670 int global_worst
= 0;
675 * This CPU is the Monarch and the other CPUs have run
676 * through their handlers.
677 * Grade the severity of the errors of all the CPUs.
679 for_each_possible_cpu(cpu
) {
680 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
682 if (severity
> global_worst
) {
684 global_worst
= severity
;
685 m
= &per_cpu(mces_seen
, cpu
);
690 * Cannot recover? Panic here then.
691 * This dumps all the mces in the log buffer and stops the
694 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
695 mce_panic("Fatal Machine check", m
, msg
);
698 * For UC somewhere we let the CPU who detects it handle it.
699 * Also must let continue the others, otherwise the handling
700 * CPU could deadlock on a lock.
704 * No machine check event found. Must be some external
705 * source or one CPU is hung. Panic.
707 if (global_worst
<= MCE_KEEP_SEVERITY
&& tolerant
< 3)
708 mce_panic("Machine check from unknown source", NULL
, NULL
);
711 * Now clear all the mces_seen so that they don't reappear on
714 for_each_possible_cpu(cpu
)
715 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
718 static atomic_t global_nwo
;
721 * Start of Monarch synchronization. This waits until all CPUs have
722 * entered the exception handler and then determines if any of them
723 * saw a fatal event that requires panic. Then it executes them
724 * in the entry order.
725 * TBD double check parallel CPU hotunplug
727 static int mce_start(int *no_way_out
)
730 int cpus
= num_online_cpus();
731 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
736 atomic_add(*no_way_out
, &global_nwo
);
738 * global_nwo should be updated before mce_callin
741 order
= atomic_inc_return(&mce_callin
);
746 while (atomic_read(&mce_callin
) != cpus
) {
747 if (mce_timed_out(&timeout
)) {
748 atomic_set(&global_nwo
, 0);
755 * mce_callin should be read before global_nwo
761 * Monarch: Starts executing now, the others wait.
763 atomic_set(&mce_executing
, 1);
766 * Subject: Now start the scanning loop one by one in
767 * the original callin order.
768 * This way when there are any shared banks it will be
769 * only seen by one CPU before cleared, avoiding duplicates.
771 while (atomic_read(&mce_executing
) < order
) {
772 if (mce_timed_out(&timeout
)) {
773 atomic_set(&global_nwo
, 0);
781 * Cache the global no_way_out state.
783 *no_way_out
= atomic_read(&global_nwo
);
789 * Synchronize between CPUs after main scanning loop.
790 * This invokes the bulk of the Monarch processing.
792 static int mce_end(int order
)
795 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
803 * Allow others to run.
805 atomic_inc(&mce_executing
);
808 /* CHECKME: Can this race with a parallel hotplug? */
809 int cpus
= num_online_cpus();
812 * Monarch: Wait for everyone to go through their scanning
815 while (atomic_read(&mce_executing
) <= cpus
) {
816 if (mce_timed_out(&timeout
))
826 * Subject: Wait for Monarch to finish.
828 while (atomic_read(&mce_executing
) != 0) {
829 if (mce_timed_out(&timeout
))
835 * Don't reset anything. That's done by the Monarch.
841 * Reset all global state.
844 atomic_set(&global_nwo
, 0);
845 atomic_set(&mce_callin
, 0);
849 * Let others run again.
851 atomic_set(&mce_executing
, 0);
856 * Check if the address reported by the CPU is in a format we can parse.
857 * It would be possible to add code for most other cases, but all would
858 * be somewhat complicated (e.g. segment offset would require an instruction
859 * parser). So only support physical addresses up to page granuality for now.
861 static int mce_usable_address(struct mce
*m
)
863 if (!(m
->status
& MCI_STATUS_MISCV
) || !(m
->status
& MCI_STATUS_ADDRV
))
865 if (MCI_MISC_ADDR_LSB(m
->misc
) > PAGE_SHIFT
)
867 if (MCI_MISC_ADDR_MODE(m
->misc
) != MCI_MISC_ADDR_PHYS
)
872 static void mce_clear_state(unsigned long *toclear
)
876 for (i
= 0; i
< banks
; i
++) {
877 if (test_bit(i
, toclear
))
878 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
883 * The actual machine check handler. This only handles real
884 * exceptions when something got corrupted coming in through int 18.
886 * This is executed in NMI context not subject to normal locking rules. This
887 * implies that most kernel services cannot be safely used. Don't even
888 * think about putting a printk in there!
890 * On Intel systems this is entered on all CPUs in parallel through
891 * MCE broadcast. However some CPUs might be broken beyond repair,
892 * so be always careful when synchronizing with others.
894 void do_machine_check(struct pt_regs
*regs
, long error_code
)
896 struct mce m
, *final
;
901 * Establish sequential order between the CPUs entering the machine
906 * If no_way_out gets set, there is no safe way to recover from this
907 * MCE. If tolerant is cranked up, we'll try anyway.
911 * If kill_it gets set, there might be a way to recover from this
915 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
916 char *msg
= "Unknown";
918 atomic_inc(&mce_entry
);
920 percpu_inc(mce_exception_count
);
925 mce_gather_info(&m
, regs
);
927 final
= &__get_cpu_var(mces_seen
);
930 no_way_out
= mce_no_way_out(&m
, &msg
);
935 * When no restart IP must always kill or panic.
937 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
941 * Go through all the banks in exclusion of the other CPUs.
942 * This way we don't report duplicated events on shared banks
943 * because the first one to see it will clear it.
945 order
= mce_start(&no_way_out
);
946 for (i
= 0; i
< banks
; i
++) {
947 __clear_bit(i
, toclear
);
948 if (!mce_banks
[i
].ctl
)
955 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
956 if ((m
.status
& MCI_STATUS_VAL
) == 0)
960 * Non uncorrected or non signaled errors are handled by
961 * machine_check_poll. Leave them alone, unless this panics.
963 if (!(m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
968 * Set taint even when machine check was not enabled.
970 add_taint(TAINT_MACHINE_CHECK
);
972 severity
= mce_severity(&m
, tolerant
, NULL
);
975 * When machine check was for corrected handler don't touch,
976 * unless we're panicing.
978 if (severity
== MCE_KEEP_SEVERITY
&& !no_way_out
)
980 __set_bit(i
, toclear
);
981 if (severity
== MCE_NO_SEVERITY
) {
983 * Machine check event was not enabled. Clear, but
990 * Kill on action required.
992 if (severity
== MCE_AR_SEVERITY
)
995 if (m
.status
& MCI_STATUS_MISCV
)
996 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
997 if (m
.status
& MCI_STATUS_ADDRV
)
998 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
1001 * Action optional error. Queue address for later processing.
1002 * When the ring overflows we just ignore the AO error.
1003 * RED-PEN add some logging mechanism when
1004 * usable_address or mce_add_ring fails.
1005 * RED-PEN don't ignore overflow for tolerant == 0
1007 if (severity
== MCE_AO_SEVERITY
&& mce_usable_address(&m
))
1008 mce_ring_add(m
.addr
>> PAGE_SHIFT
);
1012 if (severity
> worst
) {
1019 mce_clear_state(toclear
);
1022 * Do most of the synchronization with other CPUs.
1023 * When there's any problem use only local no_way_out state.
1025 if (mce_end(order
) < 0)
1026 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
1029 * If we have decided that we just CAN'T continue, and the user
1030 * has not set tolerant to an insane level, give up and die.
1032 * This is mainly used in the case when the system doesn't
1033 * support MCE broadcasting or it has been disabled.
1035 if (no_way_out
&& tolerant
< 3)
1036 mce_panic("Fatal machine check on current CPU", final
, msg
);
1039 * If the error seems to be unrecoverable, something should be
1040 * done. Try to kill as little as possible. If we can kill just
1041 * one task, do that. If the user has set the tolerance very
1042 * high, don't try to do anything at all.
1045 if (kill_it
&& tolerant
< 3)
1046 force_sig(SIGBUS
, current
);
1048 /* notify userspace ASAP */
1049 set_thread_flag(TIF_MCE_NOTIFY
);
1052 mce_report_event(regs
);
1053 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1055 atomic_dec(&mce_entry
);
1058 EXPORT_SYMBOL_GPL(do_machine_check
);
1060 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1061 void __attribute__((weak
)) memory_failure(unsigned long pfn
, int vector
)
1063 printk(KERN_ERR
"Action optional memory failure at %lx ignored\n", pfn
);
1067 * Called after mce notification in process context. This code
1068 * is allowed to sleep. Call the high level VM handler to process
1069 * any corrupted pages.
1070 * Assume that the work queue code only calls this one at a time
1072 * Note we don't disable preemption, so this code might run on the wrong
1073 * CPU. In this case the event is picked up by the scheduled work queue.
1074 * This is merely a fast path to expedite processing in some common
1077 void mce_notify_process(void)
1081 while (mce_ring_get(&pfn
))
1082 memory_failure(pfn
, MCE_VECTOR
);
1085 static void mce_process_work(struct work_struct
*dummy
)
1087 mce_notify_process();
1090 #ifdef CONFIG_X86_MCE_INTEL
1092 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1093 * @cpu: The CPU on which the event occurred.
1094 * @status: Event status information
1096 * This function should be called by the thermal interrupt after the
1097 * event has been processed and the decision was made to log the event
1100 * The status parameter will be saved to the 'status' field of 'struct mce'
1101 * and historically has been the register value of the
1102 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1104 void mce_log_therm_throt_event(__u64 status
)
1109 m
.bank
= MCE_THERMAL_BANK
;
1113 #endif /* CONFIG_X86_MCE_INTEL */
1116 * Periodic polling timer for "silent" machine check errors. If the
1117 * poller finds an MCE, poll 2x faster. When the poller finds no more
1118 * errors, poll 2x slower (up to check_interval seconds).
1120 static int check_interval
= 5 * 60; /* 5 minutes */
1122 static DEFINE_PER_CPU(int, mce_next_interval
); /* in jiffies */
1123 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1125 static void mce_start_timer(unsigned long data
)
1127 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
1130 WARN_ON(smp_processor_id() != data
);
1132 if (mce_available(__this_cpu_ptr(&cpu_info
))) {
1133 machine_check_poll(MCP_TIMESTAMP
,
1134 &__get_cpu_var(mce_poll_banks
));
1138 * Alert userspace if needed. If we logged an MCE, reduce the
1139 * polling interval, otherwise increase the polling interval.
1141 n
= &__get_cpu_var(mce_next_interval
);
1142 if (mce_notify_irq())
1143 *n
= max(*n
/2, HZ
/100);
1145 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
1147 t
->expires
= jiffies
+ *n
;
1148 add_timer_on(t
, smp_processor_id());
1151 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1152 static void mce_timer_delete_all(void)
1156 for_each_online_cpu(cpu
)
1157 del_timer_sync(&per_cpu(mce_timer
, cpu
));
1160 static void mce_do_trigger(struct work_struct
*work
)
1162 call_usermodehelper(mce_helper
, mce_helper_argv
, NULL
, UMH_NO_WAIT
);
1165 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
1168 * Notify the user(s) about new machine check events.
1169 * Can be called from interrupt context, but not from machine check/NMI
1172 int mce_notify_irq(void)
1174 /* Not more than two messages every minute */
1175 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1177 clear_thread_flag(TIF_MCE_NOTIFY
);
1179 if (test_and_clear_bit(0, &mce_need_notify
)) {
1180 /* wake processes polling /dev/mcelog */
1181 wake_up_interruptible(&mce_chrdev_wait
);
1184 * There is no risk of missing notifications because
1185 * work_pending is always cleared before the function is
1188 if (mce_helper
[0] && !work_pending(&mce_trigger_work
))
1189 schedule_work(&mce_trigger_work
);
1191 if (__ratelimit(&ratelimit
))
1192 pr_info(HW_ERR
"Machine check events logged\n");
1198 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1200 static int __cpuinit
__mcheck_cpu_mce_banks_init(void)
1204 mce_banks
= kzalloc(banks
* sizeof(struct mce_bank
), GFP_KERNEL
);
1207 for (i
= 0; i
< banks
; i
++) {
1208 struct mce_bank
*b
= &mce_banks
[i
];
1217 * Initialize Machine Checks for a CPU.
1219 static int __cpuinit
__mcheck_cpu_cap_init(void)
1224 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1226 b
= cap
& MCG_BANKCNT_MASK
;
1228 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
1230 if (b
> MAX_NR_BANKS
) {
1232 "MCE: Using only %u machine check banks out of %u\n",
1237 /* Don't support asymmetric configurations today */
1238 WARN_ON(banks
!= 0 && b
!= banks
);
1241 int err
= __mcheck_cpu_mce_banks_init();
1247 /* Use accurate RIP reporting if available. */
1248 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1249 rip_msr
= MSR_IA32_MCG_EIP
;
1251 if (cap
& MCG_SER_P
)
1257 static void __mcheck_cpu_init_generic(void)
1259 mce_banks_t all_banks
;
1264 * Log the machine checks left over from the previous reset.
1266 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1267 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1269 set_in_cr4(X86_CR4_MCE
);
1271 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1272 if (cap
& MCG_CTL_P
)
1273 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1275 for (i
= 0; i
< banks
; i
++) {
1276 struct mce_bank
*b
= &mce_banks
[i
];
1280 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1281 wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
1285 /* Add per CPU specific workarounds here */
1286 static int __cpuinit
__mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c
)
1288 if (c
->x86_vendor
== X86_VENDOR_UNKNOWN
) {
1289 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1293 /* This should be disabled by the BIOS, but isn't always */
1294 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1295 if (c
->x86
== 15 && banks
> 4) {
1297 * disable GART TBL walk error reporting, which
1298 * trips off incorrectly with the IOMMU & 3ware
1301 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1303 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1305 * Lots of broken BIOS around that don't clear them
1306 * by default and leave crap in there. Don't log:
1311 * Various K7s with broken bank 0 around. Always disable
1314 if (c
->x86
== 6 && banks
> 0)
1315 mce_banks
[0].ctl
= 0;
1318 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1320 * SDM documents that on family 6 bank 0 should not be written
1321 * because it aliases to another special BIOS controlled
1323 * But it's not aliased anymore on model 0x1a+
1324 * Don't ignore bank 0 completely because there could be a
1325 * valid event later, merely don't write CTL0.
1328 if (c
->x86
== 6 && c
->x86_model
< 0x1A && banks
> 0)
1329 mce_banks
[0].init
= 0;
1332 * All newer Intel systems support MCE broadcasting. Enable
1333 * synchronization with a one second timeout.
1335 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1336 monarch_timeout
< 0)
1337 monarch_timeout
= USEC_PER_SEC
;
1340 * There are also broken BIOSes on some Pentium M and
1343 if (c
->x86
== 6 && c
->x86_model
<= 13 && mce_bootlog
< 0)
1346 if (monarch_timeout
< 0)
1347 monarch_timeout
= 0;
1348 if (mce_bootlog
!= 0)
1349 mce_panic_timeout
= 30;
1354 static int __cpuinit
__mcheck_cpu_ancient_init(struct cpuinfo_x86
*c
)
1359 switch (c
->x86_vendor
) {
1360 case X86_VENDOR_INTEL
:
1361 intel_p5_mcheck_init(c
);
1364 case X86_VENDOR_CENTAUR
:
1365 winchip_mcheck_init(c
);
1373 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c
)
1375 switch (c
->x86_vendor
) {
1376 case X86_VENDOR_INTEL
:
1377 mce_intel_feature_init(c
);
1379 case X86_VENDOR_AMD
:
1380 mce_amd_feature_init(c
);
1387 static void __mcheck_cpu_init_timer(void)
1389 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1390 int *n
= &__get_cpu_var(mce_next_interval
);
1392 setup_timer(t
, mce_start_timer
, smp_processor_id());
1397 *n
= check_interval
* HZ
;
1400 t
->expires
= round_jiffies(jiffies
+ *n
);
1401 add_timer_on(t
, smp_processor_id());
1404 /* Handle unconfigured int18 (should never happen) */
1405 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1407 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
1408 smp_processor_id());
1411 /* Call the installed machine check handler for this CPU setup. */
1412 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1413 unexpected_machine_check
;
1416 * Called for each booted CPU to set up machine checks.
1417 * Must be called with preempt off:
1419 void __cpuinit
mcheck_cpu_init(struct cpuinfo_x86
*c
)
1424 if (__mcheck_cpu_ancient_init(c
))
1427 if (!mce_available(c
))
1430 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c
) < 0) {
1435 machine_check_vector
= do_machine_check
;
1437 __mcheck_cpu_init_generic();
1438 __mcheck_cpu_init_vendor(c
);
1439 __mcheck_cpu_init_timer();
1440 INIT_WORK(&__get_cpu_var(mce_work
), mce_process_work
);
1441 init_irq_work(&__get_cpu_var(mce_irq_work
), &mce_irq_work_cb
);
1445 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1448 static DEFINE_SPINLOCK(mce_chrdev_state_lock
);
1449 static int mce_chrdev_open_count
; /* #times opened */
1450 static int mce_chrdev_open_exclu
; /* already open exclusive? */
1452 static int mce_chrdev_open(struct inode
*inode
, struct file
*file
)
1454 spin_lock(&mce_chrdev_state_lock
);
1456 if (mce_chrdev_open_exclu
||
1457 (mce_chrdev_open_count
&& (file
->f_flags
& O_EXCL
))) {
1458 spin_unlock(&mce_chrdev_state_lock
);
1463 if (file
->f_flags
& O_EXCL
)
1464 mce_chrdev_open_exclu
= 1;
1465 mce_chrdev_open_count
++;
1467 spin_unlock(&mce_chrdev_state_lock
);
1469 return nonseekable_open(inode
, file
);
1472 static int mce_chrdev_release(struct inode
*inode
, struct file
*file
)
1474 spin_lock(&mce_chrdev_state_lock
);
1476 mce_chrdev_open_count
--;
1477 mce_chrdev_open_exclu
= 0;
1479 spin_unlock(&mce_chrdev_state_lock
);
1484 static void collect_tscs(void *data
)
1486 unsigned long *cpu_tsc
= (unsigned long *)data
;
1488 rdtscll(cpu_tsc
[smp_processor_id()]);
1491 static int mce_apei_read_done
;
1493 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1494 static int __mce_read_apei(char __user
**ubuf
, size_t usize
)
1500 if (usize
< sizeof(struct mce
))
1503 rc
= apei_read_mce(&m
, &record_id
);
1504 /* Error or no more MCE record */
1506 mce_apei_read_done
= 1;
1510 if (copy_to_user(*ubuf
, &m
, sizeof(struct mce
)))
1513 * In fact, we should have cleared the record after that has
1514 * been flushed to the disk or sent to network in
1515 * /sbin/mcelog, but we have no interface to support that now,
1516 * so just clear it to avoid duplication.
1518 rc
= apei_clear_mce(record_id
);
1520 mce_apei_read_done
= 1;
1523 *ubuf
+= sizeof(struct mce
);
1528 static ssize_t
mce_chrdev_read(struct file
*filp
, char __user
*ubuf
,
1529 size_t usize
, loff_t
*off
)
1531 char __user
*buf
= ubuf
;
1532 unsigned long *cpu_tsc
;
1533 unsigned prev
, next
;
1536 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1540 mutex_lock(&mce_chrdev_read_mutex
);
1542 if (!mce_apei_read_done
) {
1543 err
= __mce_read_apei(&buf
, usize
);
1544 if (err
|| buf
!= ubuf
)
1548 next
= rcu_dereference_check_mce(mcelog
.next
);
1550 /* Only supports full reads right now */
1552 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
))
1558 for (i
= prev
; i
< next
; i
++) {
1559 unsigned long start
= jiffies
;
1560 struct mce
*m
= &mcelog
.entry
[i
];
1562 while (!m
->finished
) {
1563 if (time_after_eq(jiffies
, start
+ 2)) {
1564 memset(m
, 0, sizeof(*m
));
1570 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1576 memset(mcelog
.entry
+ prev
, 0,
1577 (next
- prev
) * sizeof(struct mce
));
1579 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1580 } while (next
!= prev
);
1582 synchronize_sched();
1585 * Collect entries that were still getting written before the
1588 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1590 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1591 struct mce
*m
= &mcelog
.entry
[i
];
1593 if (m
->finished
&& m
->tsc
< cpu_tsc
[m
->cpu
]) {
1594 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1597 memset(m
, 0, sizeof(*m
));
1605 mutex_unlock(&mce_chrdev_read_mutex
);
1608 return err
? err
: buf
- ubuf
;
1611 static unsigned int mce_chrdev_poll(struct file
*file
, poll_table
*wait
)
1613 poll_wait(file
, &mce_chrdev_wait
, wait
);
1614 if (rcu_access_index(mcelog
.next
))
1615 return POLLIN
| POLLRDNORM
;
1616 if (!mce_apei_read_done
&& apei_check_mce())
1617 return POLLIN
| POLLRDNORM
;
1621 static long mce_chrdev_ioctl(struct file
*f
, unsigned int cmd
,
1624 int __user
*p
= (int __user
*)arg
;
1626 if (!capable(CAP_SYS_ADMIN
))
1630 case MCE_GET_RECORD_LEN
:
1631 return put_user(sizeof(struct mce
), p
);
1632 case MCE_GET_LOG_LEN
:
1633 return put_user(MCE_LOG_LEN
, p
);
1634 case MCE_GETCLEAR_FLAGS
: {
1638 flags
= mcelog
.flags
;
1639 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1641 return put_user(flags
, p
);
1648 static ssize_t (*mce_write
)(struct file
*filp
, const char __user
*ubuf
,
1649 size_t usize
, loff_t
*off
);
1651 void register_mce_write_callback(ssize_t (*fn
)(struct file
*filp
,
1652 const char __user
*ubuf
,
1653 size_t usize
, loff_t
*off
))
1657 EXPORT_SYMBOL_GPL(register_mce_write_callback
);
1659 ssize_t
mce_chrdev_write(struct file
*filp
, const char __user
*ubuf
,
1660 size_t usize
, loff_t
*off
)
1663 return mce_write(filp
, ubuf
, usize
, off
);
1668 static const struct file_operations mce_chrdev_ops
= {
1669 .open
= mce_chrdev_open
,
1670 .release
= mce_chrdev_release
,
1671 .read
= mce_chrdev_read
,
1672 .write
= mce_chrdev_write
,
1673 .poll
= mce_chrdev_poll
,
1674 .unlocked_ioctl
= mce_chrdev_ioctl
,
1675 .llseek
= no_llseek
,
1678 static struct miscdevice mce_chrdev_device
= {
1685 * mce=off Disables machine check
1686 * mce=no_cmci Disables CMCI
1687 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1688 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1689 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1690 * monarchtimeout is how long to wait for other CPUs on machine
1691 * check, or 0 to not wait
1692 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1693 * mce=nobootlog Don't log MCEs from before booting.
1695 static int __init
mcheck_enable(char *str
)
1703 if (!strcmp(str
, "off"))
1705 else if (!strcmp(str
, "no_cmci"))
1706 mce_cmci_disabled
= 1;
1707 else if (!strcmp(str
, "dont_log_ce"))
1708 mce_dont_log_ce
= 1;
1709 else if (!strcmp(str
, "ignore_ce"))
1711 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1712 mce_bootlog
= (str
[0] == 'b');
1713 else if (isdigit(str
[0])) {
1714 get_option(&str
, &tolerant
);
1717 get_option(&str
, &monarch_timeout
);
1720 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1726 __setup("mce", mcheck_enable
);
1728 int __init
mcheck_init(void)
1730 mcheck_intel_therm_init();
1736 * mce_syscore: PM support
1740 * Disable machine checks on suspend and shutdown. We can't really handle
1743 static int mce_disable_error_reporting(void)
1747 for (i
= 0; i
< banks
; i
++) {
1748 struct mce_bank
*b
= &mce_banks
[i
];
1751 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1756 static int mce_syscore_suspend(void)
1758 return mce_disable_error_reporting();
1761 static void mce_syscore_shutdown(void)
1763 mce_disable_error_reporting();
1767 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1768 * Only one CPU is active at this time, the others get re-added later using
1771 static void mce_syscore_resume(void)
1773 __mcheck_cpu_init_generic();
1774 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info
));
1777 static struct syscore_ops mce_syscore_ops
= {
1778 .suspend
= mce_syscore_suspend
,
1779 .shutdown
= mce_syscore_shutdown
,
1780 .resume
= mce_syscore_resume
,
1784 * mce_sysdev: Sysfs support
1787 static void mce_cpu_restart(void *data
)
1789 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1791 __mcheck_cpu_init_generic();
1792 __mcheck_cpu_init_timer();
1795 /* Reinit MCEs after user configuration changes */
1796 static void mce_restart(void)
1798 mce_timer_delete_all();
1799 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1802 /* Toggle features for corrected errors */
1803 static void mce_disable_cmci(void *data
)
1805 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1810 static void mce_enable_ce(void *all
)
1812 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1817 __mcheck_cpu_init_timer();
1820 static struct sysdev_class mce_sysdev_class
= {
1821 .name
= "machinecheck",
1824 DEFINE_PER_CPU(struct sys_device
, mce_sysdev
);
1827 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1829 static inline struct mce_bank
*attr_to_bank(struct sysdev_attribute
*attr
)
1831 return container_of(attr
, struct mce_bank
, attr
);
1834 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1837 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
1840 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1841 const char *buf
, size_t size
)
1845 if (strict_strtoull(buf
, 0, &new) < 0)
1848 attr_to_bank(attr
)->ctl
= new;
1855 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1857 strcpy(buf
, mce_helper
);
1859 return strlen(mce_helper
) + 1;
1862 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1863 const char *buf
, size_t siz
)
1867 strncpy(mce_helper
, buf
, sizeof(mce_helper
));
1868 mce_helper
[sizeof(mce_helper
)-1] = 0;
1869 p
= strchr(mce_helper
, '\n');
1874 return strlen(mce_helper
) + !!p
;
1877 static ssize_t
set_ignore_ce(struct sys_device
*s
,
1878 struct sysdev_attribute
*attr
,
1879 const char *buf
, size_t size
)
1883 if (strict_strtoull(buf
, 0, &new) < 0)
1886 if (mce_ignore_ce
^ !!new) {
1888 /* disable ce features */
1889 mce_timer_delete_all();
1890 on_each_cpu(mce_disable_cmci
, NULL
, 1);
1893 /* enable ce features */
1895 on_each_cpu(mce_enable_ce
, (void *)1, 1);
1901 static ssize_t
set_cmci_disabled(struct sys_device
*s
,
1902 struct sysdev_attribute
*attr
,
1903 const char *buf
, size_t size
)
1907 if (strict_strtoull(buf
, 0, &new) < 0)
1910 if (mce_cmci_disabled
^ !!new) {
1913 on_each_cpu(mce_disable_cmci
, NULL
, 1);
1914 mce_cmci_disabled
= 1;
1917 mce_cmci_disabled
= 0;
1918 on_each_cpu(mce_enable_ce
, NULL
, 1);
1924 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1925 struct sysdev_attribute
*attr
,
1926 const char *buf
, size_t size
)
1928 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1933 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1934 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1935 static SYSDEV_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
1936 static SYSDEV_INT_ATTR(dont_log_ce
, 0644, mce_dont_log_ce
);
1938 static struct sysdev_ext_attribute attr_check_interval
= {
1939 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1940 store_int_with_restart
),
1944 static struct sysdev_ext_attribute attr_ignore_ce
= {
1945 _SYSDEV_ATTR(ignore_ce
, 0644, sysdev_show_int
, set_ignore_ce
),
1949 static struct sysdev_ext_attribute attr_cmci_disabled
= {
1950 _SYSDEV_ATTR(cmci_disabled
, 0644, sysdev_show_int
, set_cmci_disabled
),
1954 static struct sysdev_attribute
*mce_sysdev_attrs
[] = {
1955 &attr_tolerant
.attr
,
1956 &attr_check_interval
.attr
,
1958 &attr_monarch_timeout
.attr
,
1959 &attr_dont_log_ce
.attr
,
1960 &attr_ignore_ce
.attr
,
1961 &attr_cmci_disabled
.attr
,
1965 static cpumask_var_t mce_sysdev_initialized
;
1967 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1968 static __cpuinit
int mce_sysdev_create(unsigned int cpu
)
1970 struct sys_device
*sysdev
= &per_cpu(mce_sysdev
, cpu
);
1974 if (!mce_available(&boot_cpu_data
))
1977 memset(&sysdev
->kobj
, 0, sizeof(struct kobject
));
1979 sysdev
->cls
= &mce_sysdev_class
;
1981 err
= sysdev_register(sysdev
);
1985 for (i
= 0; mce_sysdev_attrs
[i
]; i
++) {
1986 err
= sysdev_create_file(sysdev
, mce_sysdev_attrs
[i
]);
1990 for (j
= 0; j
< banks
; j
++) {
1991 err
= sysdev_create_file(sysdev
, &mce_banks
[j
].attr
);
1995 cpumask_set_cpu(cpu
, mce_sysdev_initialized
);
2000 sysdev_remove_file(sysdev
, &mce_banks
[j
].attr
);
2003 sysdev_remove_file(sysdev
, mce_sysdev_attrs
[i
]);
2005 sysdev_unregister(sysdev
);
2010 static __cpuinit
void mce_sysdev_remove(unsigned int cpu
)
2012 struct sys_device
*sysdev
= &per_cpu(mce_sysdev
, cpu
);
2015 if (!cpumask_test_cpu(cpu
, mce_sysdev_initialized
))
2018 for (i
= 0; mce_sysdev_attrs
[i
]; i
++)
2019 sysdev_remove_file(sysdev
, mce_sysdev_attrs
[i
]);
2021 for (i
= 0; i
< banks
; i
++)
2022 sysdev_remove_file(sysdev
, &mce_banks
[i
].attr
);
2024 sysdev_unregister(sysdev
);
2025 cpumask_clear_cpu(cpu
, mce_sysdev_initialized
);
2028 /* Make sure there are no machine checks on offlined CPUs. */
2029 static void __cpuinit
mce_disable_cpu(void *h
)
2031 unsigned long action
= *(unsigned long *)h
;
2034 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2037 if (!(action
& CPU_TASKS_FROZEN
))
2039 for (i
= 0; i
< banks
; i
++) {
2040 struct mce_bank
*b
= &mce_banks
[i
];
2043 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
2047 static void __cpuinit
mce_reenable_cpu(void *h
)
2049 unsigned long action
= *(unsigned long *)h
;
2052 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2055 if (!(action
& CPU_TASKS_FROZEN
))
2057 for (i
= 0; i
< banks
; i
++) {
2058 struct mce_bank
*b
= &mce_banks
[i
];
2061 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
2065 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2066 static int __cpuinit
2067 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
2069 unsigned int cpu
= (unsigned long)hcpu
;
2070 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
2074 case CPU_ONLINE_FROZEN
:
2075 mce_sysdev_create(cpu
);
2076 if (threshold_cpu_callback
)
2077 threshold_cpu_callback(action
, cpu
);
2080 case CPU_DEAD_FROZEN
:
2081 if (threshold_cpu_callback
)
2082 threshold_cpu_callback(action
, cpu
);
2083 mce_sysdev_remove(cpu
);
2085 case CPU_DOWN_PREPARE
:
2086 case CPU_DOWN_PREPARE_FROZEN
:
2088 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
2090 case CPU_DOWN_FAILED
:
2091 case CPU_DOWN_FAILED_FROZEN
:
2092 if (!mce_ignore_ce
&& check_interval
) {
2093 t
->expires
= round_jiffies(jiffies
+
2094 __get_cpu_var(mce_next_interval
));
2095 add_timer_on(t
, cpu
);
2097 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
2100 /* intentionally ignoring frozen here */
2101 cmci_rediscover(cpu
);
2107 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
2108 .notifier_call
= mce_cpu_callback
,
2111 static __init
void mce_init_banks(void)
2115 for (i
= 0; i
< banks
; i
++) {
2116 struct mce_bank
*b
= &mce_banks
[i
];
2117 struct sysdev_attribute
*a
= &b
->attr
;
2119 sysfs_attr_init(&a
->attr
);
2120 a
->attr
.name
= b
->attrname
;
2121 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
2123 a
->attr
.mode
= 0644;
2124 a
->show
= show_bank
;
2125 a
->store
= set_bank
;
2129 static __init
int mcheck_init_device(void)
2134 if (!mce_available(&boot_cpu_data
))
2137 zalloc_cpumask_var(&mce_sysdev_initialized
, GFP_KERNEL
);
2141 err
= sysdev_class_register(&mce_sysdev_class
);
2145 for_each_online_cpu(i
) {
2146 err
= mce_sysdev_create(i
);
2151 register_syscore_ops(&mce_syscore_ops
);
2152 register_hotcpu_notifier(&mce_cpu_notifier
);
2154 /* register character device /dev/mcelog */
2155 misc_register(&mce_chrdev_device
);
2159 device_initcall(mcheck_init_device
);
2162 * Old style boot options parsing. Only for compatibility.
2164 static int __init
mcheck_disable(char *str
)
2169 __setup("nomce", mcheck_disable
);
2171 #ifdef CONFIG_DEBUG_FS
2172 struct dentry
*mce_get_debugfs_dir(void)
2174 static struct dentry
*dmce
;
2177 dmce
= debugfs_create_dir("mce", NULL
);
2182 static void mce_reset(void)
2185 atomic_set(&mce_fake_paniced
, 0);
2186 atomic_set(&mce_executing
, 0);
2187 atomic_set(&mce_callin
, 0);
2188 atomic_set(&global_nwo
, 0);
2191 static int fake_panic_get(void *data
, u64
*val
)
2197 static int fake_panic_set(void *data
, u64 val
)
2204 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops
, fake_panic_get
,
2205 fake_panic_set
, "%llu\n");
2207 static int __init
mcheck_debugfs_init(void)
2209 struct dentry
*dmce
, *ffake_panic
;
2211 dmce
= mce_get_debugfs_dir();
2214 ffake_panic
= debugfs_create_file("fake_panic", 0444, dmce
, NULL
,
2221 late_initcall(mcheck_debugfs_init
);