2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
8 * QUICC Engine (QE) external definitions and structure.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 #ifndef _ASM_POWERPC_QE_H
16 #define _ASM_POWERPC_QE_H
19 #include <linux/spinlock.h>
20 #include <asm/immap_qe.h>
22 #define QE_NUM_OF_SNUM 28
23 #define QE_NUM_OF_BRGS 16
24 #define QE_NUM_OF_PORTS 1024
28 #define MEM_PART_SYSTEM 0
29 #define MEM_PART_SECONDARY 1
30 #define MEM_PART_MURAM 2
35 QE_BRG1
, /* Baud Rate Generator 1 */
36 QE_BRG2
, /* Baud Rate Generator 2 */
37 QE_BRG3
, /* Baud Rate Generator 3 */
38 QE_BRG4
, /* Baud Rate Generator 4 */
39 QE_BRG5
, /* Baud Rate Generator 5 */
40 QE_BRG6
, /* Baud Rate Generator 6 */
41 QE_BRG7
, /* Baud Rate Generator 7 */
42 QE_BRG8
, /* Baud Rate Generator 8 */
43 QE_BRG9
, /* Baud Rate Generator 9 */
44 QE_BRG10
, /* Baud Rate Generator 10 */
45 QE_BRG11
, /* Baud Rate Generator 11 */
46 QE_BRG12
, /* Baud Rate Generator 12 */
47 QE_BRG13
, /* Baud Rate Generator 13 */
48 QE_BRG14
, /* Baud Rate Generator 14 */
49 QE_BRG15
, /* Baud Rate Generator 15 */
50 QE_BRG16
, /* Baud Rate Generator 16 */
51 QE_CLK1
, /* Clock 1 */
52 QE_CLK2
, /* Clock 2 */
53 QE_CLK3
, /* Clock 3 */
54 QE_CLK4
, /* Clock 4 */
55 QE_CLK5
, /* Clock 5 */
56 QE_CLK6
, /* Clock 6 */
57 QE_CLK7
, /* Clock 7 */
58 QE_CLK8
, /* Clock 8 */
59 QE_CLK9
, /* Clock 9 */
60 QE_CLK10
, /* Clock 10 */
61 QE_CLK11
, /* Clock 11 */
62 QE_CLK12
, /* Clock 12 */
63 QE_CLK13
, /* Clock 13 */
64 QE_CLK14
, /* Clock 14 */
65 QE_CLK15
, /* Clock 15 */
66 QE_CLK16
, /* Clock 16 */
67 QE_CLK17
, /* Clock 17 */
68 QE_CLK18
, /* Clock 18 */
69 QE_CLK19
, /* Clock 19 */
70 QE_CLK20
, /* Clock 20 */
71 QE_CLK21
, /* Clock 21 */
72 QE_CLK22
, /* Clock 22 */
73 QE_CLK23
, /* Clock 23 */
74 QE_CLK24
, /* Clock 24 */
78 static inline bool qe_clock_is_brg(enum qe_clock clk
)
80 return clk
>= QE_BRG1
&& clk
<= QE_BRG16
;
83 extern spinlock_t cmxgcr_lock
;
85 /* Export QE common operations */
86 extern void qe_reset(void);
89 #define QE_PIO_PINS 32
92 __be32 cpodr
; /* Open drain register */
93 __be32 cpdata
; /* Data register */
94 __be32 cpdir1
; /* Direction register */
95 __be32 cpdir2
; /* Direction register */
96 __be32 cppar1
; /* Pin assignment register */
97 __be32 cppar2
; /* Pin assignment register */
98 #ifdef CONFIG_PPC_85xx
103 extern void __init
qe_add_gpiochips(void);
104 extern int par_io_init(struct device_node
*np
);
105 extern int par_io_of_config(struct device_node
*np
);
106 #define QE_PIO_DIR_IN 2
107 #define QE_PIO_DIR_OUT 1
108 extern void __par_io_config_pin(struct qe_pio_regs __iomem
*par_io
, u8 pin
,
109 int dir
, int open_drain
, int assignment
,
111 extern int par_io_config_pin(u8 port
, u8 pin
, int dir
, int open_drain
,
112 int assignment
, int has_irq
);
113 extern int par_io_data_set(u8 port
, u8 pin
, u8 val
);
115 /* QE internal API */
116 int qe_issue_cmd(u32 cmd
, u32 device
, u8 mcn_protocol
, u32 cmd_input
);
117 enum qe_clock
qe_clock_source(const char *source
);
118 unsigned int qe_get_brg_clk(void);
119 int qe_setbrg(enum qe_clock brg
, unsigned int rate
, unsigned int multiplier
);
120 int qe_get_snum(void);
121 void qe_put_snum(u8 snum
);
122 unsigned long qe_muram_alloc(int size
, int align
);
123 int qe_muram_free(unsigned long offset
);
124 unsigned long qe_muram_alloc_fixed(unsigned long offset
, int size
);
125 void qe_muram_dump(void);
127 static inline void __iomem
*qe_muram_addr(unsigned long offset
)
129 return (void __iomem
*)&qe_immr
->muram
[offset
];
132 static inline unsigned long qe_muram_offset(void __iomem
*addr
)
134 return addr
- (void __iomem
*)qe_immr
->muram
;
137 /* Structure that defines QE firmware binary files.
139 * See Documentation/powerpc/qe-firmware.txt for a description of these
144 __be32 length
; /* Length of the entire structure, in bytes */
145 u8 magic
[3]; /* Set to { 'Q', 'E', 'F' } */
146 u8 version
; /* Version of this layout. First ver is '1' */
148 u8 id
[62]; /* Null-terminated identifier string */
149 u8 split
; /* 0 = shared I-RAM, 1 = split I-RAM */
150 u8 count
; /* Number of microcode[] structures */
152 __be16 model
; /* The SOC model */
153 u8 major
; /* The SOC revision major */
154 u8 minor
; /* The SOC revision minor */
155 } __attribute__ ((packed
)) soc
;
156 u8 padding
[4]; /* Reserved, for alignment */
157 __be64 extended_modes
; /* Extended modes */
158 __be32 vtraps
[8]; /* Virtual trap addresses */
159 u8 reserved
[4]; /* Reserved, for future expansion */
160 struct qe_microcode
{
161 u8 id
[32]; /* Null-terminated identifier */
162 __be32 traps
[16]; /* Trap addresses, 0 == ignore */
163 __be32 eccr
; /* The value for the ECCR register */
164 __be32 iram_offset
; /* Offset into I-RAM for the code */
165 __be32 count
; /* Number of 32-bit words of the code */
166 __be32 code_offset
; /* Offset of the actual microcode */
167 u8 major
; /* The microcode version major */
168 u8 minor
; /* The microcode version minor */
169 u8 revision
; /* The microcode version revision */
170 u8 padding
; /* Reserved, for alignment */
171 u8 reserved
[4]; /* Reserved, for future expansion */
172 } __attribute__ ((packed
)) microcode
[1];
173 /* All microcode binaries should be located here */
174 /* CRC32 should be located here, after the microcode binaries */
175 } __attribute__ ((packed
));
177 struct qe_firmware_info
{
178 char id
[64]; /* Firmware name */
179 u32 vtraps
[8]; /* Virtual trap addresses */
180 u64 extended_modes
; /* Extended modes */
183 /* Upload a firmware to the QE */
184 int qe_upload_firmware(const struct qe_firmware
*firmware
);
186 /* Obtain information on the uploaded firmware */
187 struct qe_firmware_info
*qe_get_firmware_info(void);
190 int qe_usb_clock_set(enum qe_clock clk
, int rate
);
192 /* Buffer descriptors */
197 } __attribute__ ((packed
));
199 #define BD_STATUS_MASK 0xffff0000
200 #define BD_LENGTH_MASK 0x0000ffff
202 #define BD_SC_EMPTY 0x8000 /* Receive is empty */
203 #define BD_SC_READY 0x8000 /* Transmit is ready */
204 #define BD_SC_WRAP 0x2000 /* Last buffer descriptor */
205 #define BD_SC_INTRPT 0x1000 /* Interrupt on change */
206 #define BD_SC_LAST 0x0800 /* Last buffer in frame */
207 #define BD_SC_CM 0x0200 /* Continous mode */
208 #define BD_SC_ID 0x0100 /* Rec'd too many idles */
209 #define BD_SC_P 0x0100 /* xmt preamble */
210 #define BD_SC_BR 0x0020 /* Break received */
211 #define BD_SC_FR 0x0010 /* Framing error */
212 #define BD_SC_PR 0x0008 /* Parity error */
213 #define BD_SC_OV 0x0002 /* Overrun */
214 #define BD_SC_CD 0x0001 /* ?? */
217 #define QE_INTR_TABLE_ALIGN 16 /* ??? */
218 #define QE_ALIGNMENT_OF_BD 8
219 #define QE_ALIGNMENT_OF_PRAM 64
221 /* RISC allocation */
222 enum qe_risc_allocation
{
223 QE_RISC_ALLOCATION_RISC1
= 1, /* RISC 1 */
224 QE_RISC_ALLOCATION_RISC2
= 2, /* RISC 2 */
225 QE_RISC_ALLOCATION_RISC1_AND_RISC2
= 3 /* Dynamically choose
229 /* QE extended filtering Table Lookup Key Size */
230 enum qe_fltr_tbl_lookup_key_size
{
231 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
232 = 0x3f, /* LookupKey parsed by the Generate LookupKey
233 CMD is truncated to 8 bytes */
234 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
235 = 0x5f, /* LookupKey parsed by the Generate LookupKey
236 CMD is truncated to 16 bytes */
239 /* QE FLTR extended filtering Largest External Table Lookup Key Size */
240 enum qe_fltr_largest_external_tbl_lookup_key_size
{
241 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
243 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
244 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
, /* 8 bytes */
245 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
246 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
, /* 16 bytes */
249 /* structure representing QE parameter RAM */
250 struct qe_timer_tables
{
251 u16 tm_base
; /* QE timer table base adr */
252 u16 tm_ptr
; /* QE timer table pointer */
253 u16 r_tmr
; /* QE timer mode register */
254 u16 r_tmv
; /* QE timer valid register */
255 u32 tm_cmd
; /* QE timer cmd register */
256 u32 tm_cnt
; /* QE timer internal cnt */
257 } __attribute__ ((packed
));
259 #define QE_FLTR_TAD_SIZE 8
261 /* QE extended filtering Termination Action Descriptor (TAD) */
263 u8 serialized
[QE_FLTR_TAD_SIZE
];
264 } __attribute__ ((packed
));
266 /* Communication Direction */
271 COMM_DIR_RX_AND_TX
= 3
274 /* QE CMXUCR Registers.
275 * There are two UCCs represented in each of the four CMXUCR registers.
276 * These values are for the UCC in the LSBs
278 #define QE_CMXUCR_MII_ENET_MNG 0x00007000
279 #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
280 #define QE_CMXUCR_GRANT 0x00008000
281 #define QE_CMXUCR_TSA 0x00004000
282 #define QE_CMXUCR_BKPT 0x00000100
283 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
285 /* QE CMXGCR Registers.
287 #define QE_CMXGCR_MII_ENET_MNG 0x00007000
288 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
289 #define QE_CMXGCR_USBCS 0x0000000f
290 #define QE_CMXGCR_USBCS_CLK3 0x1
291 #define QE_CMXGCR_USBCS_CLK5 0x2
292 #define QE_CMXGCR_USBCS_CLK7 0x3
293 #define QE_CMXGCR_USBCS_CLK9 0x4
294 #define QE_CMXGCR_USBCS_CLK13 0x5
295 #define QE_CMXGCR_USBCS_CLK17 0x6
296 #define QE_CMXGCR_USBCS_CLK19 0x7
297 #define QE_CMXGCR_USBCS_CLK21 0x8
298 #define QE_CMXGCR_USBCS_BRG9 0x9
299 #define QE_CMXGCR_USBCS_BRG10 0xa
303 #define QE_CR_FLG 0x00010000
304 #define QE_RESET 0x80000000
305 #define QE_INIT_TX_RX 0x00000000
306 #define QE_INIT_RX 0x00000001
307 #define QE_INIT_TX 0x00000002
308 #define QE_ENTER_HUNT_MODE 0x00000003
309 #define QE_STOP_TX 0x00000004
310 #define QE_GRACEFUL_STOP_TX 0x00000005
311 #define QE_RESTART_TX 0x00000006
312 #define QE_CLOSE_RX_BD 0x00000007
313 #define QE_SWITCH_COMMAND 0x00000007
314 #define QE_SET_GROUP_ADDRESS 0x00000008
315 #define QE_START_IDMA 0x00000009
316 #define QE_MCC_STOP_RX 0x00000009
317 #define QE_ATM_TRANSMIT 0x0000000a
318 #define QE_HPAC_CLEAR_ALL 0x0000000b
319 #define QE_GRACEFUL_STOP_RX 0x0000001a
320 #define QE_RESTART_RX 0x0000001b
321 #define QE_HPAC_SET_PRIORITY 0x0000010b
322 #define QE_HPAC_STOP_TX 0x0000020b
323 #define QE_HPAC_STOP_RX 0x0000030b
324 #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
325 #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
326 #define QE_HPAC_START_TX 0x0000060b
327 #define QE_HPAC_START_RX 0x0000070b
328 #define QE_USB_STOP_TX 0x0000000a
329 #define QE_USB_RESTART_TX 0x0000000c
330 #define QE_QMC_STOP_TX 0x0000000c
331 #define QE_QMC_STOP_RX 0x0000000d
332 #define QE_SS7_SU_FIL_RESET 0x0000000e
333 /* jonathbr added from here down for 83xx */
334 #define QE_RESET_BCS 0x0000000a
335 #define QE_MCC_INIT_TX_RX_16 0x00000003
336 #define QE_MCC_STOP_TX 0x00000004
337 #define QE_MCC_INIT_TX_1 0x00000005
338 #define QE_MCC_INIT_RX_1 0x00000006
339 #define QE_MCC_RESET 0x00000007
340 #define QE_SET_TIMER 0x00000008
341 #define QE_RANDOM_NUMBER 0x0000000c
342 #define QE_ATM_MULTI_THREAD_INIT 0x00000011
343 #define QE_ASSIGN_PAGE 0x00000012
344 #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
345 #define QE_START_FLOW_CONTROL 0x00000014
346 #define QE_STOP_FLOW_CONTROL 0x00000015
347 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
349 #define QE_ASSIGN_RISC 0x00000010
350 #define QE_CR_MCN_NORMAL_SHIFT 6
351 #define QE_CR_MCN_USB_SHIFT 4
352 #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
353 #define QE_CR_SNUM_SHIFT 17
355 /* QE CECR Sub Block - sub block of QE command.
357 #define QE_CR_SUBBLOCK_INVALID 0x00000000
358 #define QE_CR_SUBBLOCK_USB 0x03200000
359 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
360 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
361 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
362 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
363 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
364 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
365 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
366 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
367 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
368 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
369 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
370 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
371 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
372 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
373 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
374 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
375 #define QE_CR_SUBBLOCK_MCC1 0x03800000
376 #define QE_CR_SUBBLOCK_MCC2 0x03a00000
377 #define QE_CR_SUBBLOCK_MCC3 0x03000000
378 #define QE_CR_SUBBLOCK_IDMA1 0x02800000
379 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000
380 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000
381 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000
382 #define QE_CR_SUBBLOCK_HPAC 0x01e00000
383 #define QE_CR_SUBBLOCK_SPI1 0x01400000
384 #define QE_CR_SUBBLOCK_SPI2 0x01600000
385 #define QE_CR_SUBBLOCK_RAND 0x01c00000
386 #define QE_CR_SUBBLOCK_TIMER 0x01e00000
387 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000
389 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
390 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
391 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
392 #define QE_CR_PROTOCOL_QMC 0x02
393 #define QE_CR_PROTOCOL_UART 0x04
394 #define QE_CR_PROTOCOL_ATM_POS 0x0A
395 #define QE_CR_PROTOCOL_ETHERNET 0x0C
396 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D
398 /* BRG configuration register */
399 #define QE_BRGC_ENABLE 0x00010000
400 #define QE_BRGC_DIVISOR_SHIFT 1
401 #define QE_BRGC_DIVISOR_MAX 0xFFF
402 #define QE_BRGC_DIV16 1
404 /* QE Timers registers */
405 #define QE_GTCFR1_PCAS 0x80
406 #define QE_GTCFR1_STP2 0x20
407 #define QE_GTCFR1_RST2 0x10
408 #define QE_GTCFR1_GM2 0x08
409 #define QE_GTCFR1_GM1 0x04
410 #define QE_GTCFR1_STP1 0x02
411 #define QE_GTCFR1_RST1 0x01
414 #define QE_SDSR_BER1 0x02000000
415 #define QE_SDSR_BER2 0x01000000
417 #define QE_SDMR_GLB_1_MSK 0x80000000
418 #define QE_SDMR_ADR_SEL 0x20000000
419 #define QE_SDMR_BER1_MSK 0x02000000
420 #define QE_SDMR_BER2_MSK 0x01000000
421 #define QE_SDMR_EB1_MSK 0x00800000
422 #define QE_SDMR_ER1_MSK 0x00080000
423 #define QE_SDMR_ER2_MSK 0x00040000
424 #define QE_SDMR_CEN_MASK 0x0000E000
425 #define QE_SDMR_SBER_1 0x00000200
426 #define QE_SDMR_SBER_2 0x00000200
427 #define QE_SDMR_EB1_PR_MASK 0x000000C0
428 #define QE_SDMR_ER1_PR 0x00000008
430 #define QE_SDMR_CEN_SHIFT 13
431 #define QE_SDMR_EB1_PR_SHIFT 6
433 #define QE_SDTM_MSNUM_SHIFT 24
435 #define QE_SDEBCR_BA_MASK 0x01FFFFFF
437 /* Communication Processor */
438 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
439 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
440 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
443 #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
444 #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
447 #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
448 #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
449 #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
450 #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
451 #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
453 /* UCC GUEMR register */
454 #define UCC_GUEMR_MODE_MASK_RX 0x02
455 #define UCC_GUEMR_MODE_FAST_RX 0x02
456 #define UCC_GUEMR_MODE_SLOW_RX 0x00
457 #define UCC_GUEMR_MODE_MASK_TX 0x01
458 #define UCC_GUEMR_MODE_FAST_TX 0x01
459 #define UCC_GUEMR_MODE_SLOW_TX 0x00
460 #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
461 #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
464 /* structure representing UCC SLOW parameter RAM */
465 struct ucc_slow_pram
{
466 __be16 rbase
; /* RX BD base address */
467 __be16 tbase
; /* TX BD base address */
468 u8 rbmr
; /* RX bus mode register (same as CPM's RFCR) */
469 u8 tbmr
; /* TX bus mode register (same as CPM's TFCR) */
470 __be16 mrblr
; /* Rx buffer length */
471 __be32 rstate
; /* Rx internal state */
472 __be32 rptr
; /* Rx internal data pointer */
473 __be16 rbptr
; /* rb BD Pointer */
474 __be16 rcount
; /* Rx internal byte count */
475 __be32 rtemp
; /* Rx temp */
476 __be32 tstate
; /* Tx internal state */
477 __be32 tptr
; /* Tx internal data pointer */
478 __be16 tbptr
; /* Tx BD pointer */
479 __be16 tcount
; /* Tx byte count */
480 __be32 ttemp
; /* Tx temp */
481 __be32 rcrc
; /* temp receive CRC */
482 __be32 tcrc
; /* temp transmit CRC */
483 } __attribute__ ((packed
));
485 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */
486 #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
487 #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
488 #define UCC_SLOW_GUMR_H_REVD 0x00002000
489 #define UCC_SLOW_GUMR_H_TRX 0x00001000
490 #define UCC_SLOW_GUMR_H_TTX 0x00000800
491 #define UCC_SLOW_GUMR_H_CDP 0x00000400
492 #define UCC_SLOW_GUMR_H_CTSP 0x00000200
493 #define UCC_SLOW_GUMR_H_CDS 0x00000100
494 #define UCC_SLOW_GUMR_H_CTSS 0x00000080
495 #define UCC_SLOW_GUMR_H_TFL 0x00000040
496 #define UCC_SLOW_GUMR_H_RFW 0x00000020
497 #define UCC_SLOW_GUMR_H_TXSY 0x00000010
498 #define UCC_SLOW_GUMR_H_4SYNC 0x00000004
499 #define UCC_SLOW_GUMR_H_8SYNC 0x00000008
500 #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
501 #define UCC_SLOW_GUMR_H_RTSM 0x00000002
502 #define UCC_SLOW_GUMR_H_RSYN 0x00000001
504 #define UCC_SLOW_GUMR_L_TCI 0x10000000
505 #define UCC_SLOW_GUMR_L_RINV 0x02000000
506 #define UCC_SLOW_GUMR_L_TINV 0x01000000
507 #define UCC_SLOW_GUMR_L_TEND 0x00040000
508 #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
509 #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
510 #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
511 #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
512 #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
513 #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
514 #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
515 #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
516 #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
517 #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
518 #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
519 #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
520 #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
521 #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
522 #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
523 #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
524 #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
525 #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
526 #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
527 #define UCC_SLOW_GUMR_L_ENR 0x00000020
528 #define UCC_SLOW_GUMR_L_ENT 0x00000010
529 #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
530 #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
531 #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
532 #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
533 #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
535 /* General UCC FAST Mode Register */
536 #define UCC_FAST_GUMR_TCI 0x20000000
537 #define UCC_FAST_GUMR_TRX 0x10000000
538 #define UCC_FAST_GUMR_TTX 0x08000000
539 #define UCC_FAST_GUMR_CDP 0x04000000
540 #define UCC_FAST_GUMR_CTSP 0x02000000
541 #define UCC_FAST_GUMR_CDS 0x01000000
542 #define UCC_FAST_GUMR_CTSS 0x00800000
543 #define UCC_FAST_GUMR_TXSY 0x00020000
544 #define UCC_FAST_GUMR_RSYN 0x00010000
545 #define UCC_FAST_GUMR_RTSM 0x00002000
546 #define UCC_FAST_GUMR_REVD 0x00000400
547 #define UCC_FAST_GUMR_ENR 0x00000020
548 #define UCC_FAST_GUMR_ENT 0x00000010
550 /* UART Slow UCC Event Register (UCCE) */
551 #define UCC_UART_UCCE_AB 0x0200
552 #define UCC_UART_UCCE_IDLE 0x0100
553 #define UCC_UART_UCCE_GRA 0x0080
554 #define UCC_UART_UCCE_BRKE 0x0040
555 #define UCC_UART_UCCE_BRKS 0x0020
556 #define UCC_UART_UCCE_CCR 0x0008
557 #define UCC_UART_UCCE_BSY 0x0004
558 #define UCC_UART_UCCE_TX 0x0002
559 #define UCC_UART_UCCE_RX 0x0001
561 /* HDLC Slow UCC Event Register (UCCE) */
562 #define UCC_HDLC_UCCE_GLR 0x1000
563 #define UCC_HDLC_UCCE_GLT 0x0800
564 #define UCC_HDLC_UCCE_IDLE 0x0100
565 #define UCC_HDLC_UCCE_BRKE 0x0040
566 #define UCC_HDLC_UCCE_BRKS 0x0020
567 #define UCC_HDLC_UCCE_TXE 0x0010
568 #define UCC_HDLC_UCCE_RXF 0x0008
569 #define UCC_HDLC_UCCE_BSY 0x0004
570 #define UCC_HDLC_UCCE_TXB 0x0002
571 #define UCC_HDLC_UCCE_RXB 0x0001
573 /* BISYNC Slow UCC Event Register (UCCE) */
574 #define UCC_BISYNC_UCCE_GRA 0x0080
575 #define UCC_BISYNC_UCCE_TXE 0x0010
576 #define UCC_BISYNC_UCCE_RCH 0x0008
577 #define UCC_BISYNC_UCCE_BSY 0x0004
578 #define UCC_BISYNC_UCCE_TXB 0x0002
579 #define UCC_BISYNC_UCCE_RXB 0x0001
581 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */
582 #define UCC_GETH_UCCE_MPD 0x80000000
583 #define UCC_GETH_UCCE_SCAR 0x40000000
584 #define UCC_GETH_UCCE_GRA 0x20000000
585 #define UCC_GETH_UCCE_CBPR 0x10000000
586 #define UCC_GETH_UCCE_BSY 0x08000000
587 #define UCC_GETH_UCCE_RXC 0x04000000
588 #define UCC_GETH_UCCE_TXC 0x02000000
589 #define UCC_GETH_UCCE_TXE 0x01000000
590 #define UCC_GETH_UCCE_TXB7 0x00800000
591 #define UCC_GETH_UCCE_TXB6 0x00400000
592 #define UCC_GETH_UCCE_TXB5 0x00200000
593 #define UCC_GETH_UCCE_TXB4 0x00100000
594 #define UCC_GETH_UCCE_TXB3 0x00080000
595 #define UCC_GETH_UCCE_TXB2 0x00040000
596 #define UCC_GETH_UCCE_TXB1 0x00020000
597 #define UCC_GETH_UCCE_TXB0 0x00010000
598 #define UCC_GETH_UCCE_RXB7 0x00008000
599 #define UCC_GETH_UCCE_RXB6 0x00004000
600 #define UCC_GETH_UCCE_RXB5 0x00002000
601 #define UCC_GETH_UCCE_RXB4 0x00001000
602 #define UCC_GETH_UCCE_RXB3 0x00000800
603 #define UCC_GETH_UCCE_RXB2 0x00000400
604 #define UCC_GETH_UCCE_RXB1 0x00000200
605 #define UCC_GETH_UCCE_RXB0 0x00000100
606 #define UCC_GETH_UCCE_RXF7 0x00000080
607 #define UCC_GETH_UCCE_RXF6 0x00000040
608 #define UCC_GETH_UCCE_RXF5 0x00000020
609 #define UCC_GETH_UCCE_RXF4 0x00000010
610 #define UCC_GETH_UCCE_RXF3 0x00000008
611 #define UCC_GETH_UCCE_RXF2 0x00000004
612 #define UCC_GETH_UCCE_RXF1 0x00000002
613 #define UCC_GETH_UCCE_RXF0 0x00000001
615 /* UPSMR, when used as a UART */
616 #define UCC_UART_UPSMR_FLC 0x8000
617 #define UCC_UART_UPSMR_SL 0x4000
618 #define UCC_UART_UPSMR_CL_MASK 0x3000
619 #define UCC_UART_UPSMR_CL_8 0x3000
620 #define UCC_UART_UPSMR_CL_7 0x2000
621 #define UCC_UART_UPSMR_CL_6 0x1000
622 #define UCC_UART_UPSMR_CL_5 0x0000
623 #define UCC_UART_UPSMR_UM_MASK 0x0c00
624 #define UCC_UART_UPSMR_UM_NORMAL 0x0000
625 #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
626 #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
627 #define UCC_UART_UPSMR_FRZ 0x0200
628 #define UCC_UART_UPSMR_RZS 0x0100
629 #define UCC_UART_UPSMR_SYN 0x0080
630 #define UCC_UART_UPSMR_DRT 0x0040
631 #define UCC_UART_UPSMR_PEN 0x0010
632 #define UCC_UART_UPSMR_RPM_MASK 0x000c
633 #define UCC_UART_UPSMR_RPM_ODD 0x0000
634 #define UCC_UART_UPSMR_RPM_LOW 0x0004
635 #define UCC_UART_UPSMR_RPM_EVEN 0x0008
636 #define UCC_UART_UPSMR_RPM_HIGH 0x000C
637 #define UCC_UART_UPSMR_TPM_MASK 0x0003
638 #define UCC_UART_UPSMR_TPM_ODD 0x0000
639 #define UCC_UART_UPSMR_TPM_LOW 0x0001
640 #define UCC_UART_UPSMR_TPM_EVEN 0x0002
641 #define UCC_UART_UPSMR_TPM_HIGH 0x0003
643 /* UCC Transmit On Demand Register (UTODR) */
644 #define UCC_SLOW_TOD 0x8000
645 #define UCC_FAST_TOD 0x8000
647 /* UCC Bus Mode Register masks */
648 /* Not to be confused with the Bundle Mode Register */
649 #define UCC_BMR_GBL 0x20
650 #define UCC_BMR_BO_BE 0x10
651 #define UCC_BMR_CETM 0x04
652 #define UCC_BMR_DTB 0x02
653 #define UCC_BMR_BDB 0x01
655 /* Function code masks */
657 #define FC_DTB_LCL 0x02
658 #define UCC_FAST_FUNCTION_CODE_GBL 0x20
659 #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
660 #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
662 #endif /* __KERNEL__ */
663 #endif /* _ASM_POWERPC_QE_H */