1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/if_ether.h>
29 #include <linux/delay.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
33 #include "e1000_mac.h"
37 static s32
igb_set_default_fc(struct e1000_hw
*hw
);
38 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
);
40 static s32
igb_read_pcie_cap_reg(struct e1000_hw
*hw
, u32 reg
, u16
*value
)
42 struct igb_adapter
*adapter
= hw
->back
;
45 cap_offset
= pci_find_capability(adapter
->pdev
, PCI_CAP_ID_EXP
);
47 return -E1000_ERR_CONFIG
;
49 pci_read_config_word(adapter
->pdev
, cap_offset
+ reg
, value
);
55 * igb_get_bus_info_pcie - Get PCIe bus information
56 * @hw: pointer to the HW structure
58 * Determines and stores the system bus information for a particular
59 * network interface. The following bus information is determined and stored:
60 * bus speed, bus width, type (PCIe), and PCIe function.
62 s32
igb_get_bus_info_pcie(struct e1000_hw
*hw
)
64 struct e1000_bus_info
*bus
= &hw
->bus
;
69 bus
->type
= e1000_bus_type_pci_express
;
70 bus
->speed
= e1000_bus_speed_2500
;
72 ret_val
= igb_read_pcie_cap_reg(hw
,
76 bus
->width
= e1000_bus_width_unknown
;
78 bus
->width
= (enum e1000_bus_width
)((pcie_link_status
&
79 PCIE_LINK_WIDTH_MASK
) >>
80 PCIE_LINK_WIDTH_SHIFT
);
82 reg
= rd32(E1000_STATUS
);
83 bus
->func
= (reg
& E1000_STATUS_FUNC_MASK
) >> E1000_STATUS_FUNC_SHIFT
;
89 * igb_clear_vfta - Clear VLAN filter table
90 * @hw: pointer to the HW structure
92 * Clears the register array which contains the VLAN filter table by
93 * setting all the values to 0.
95 void igb_clear_vfta(struct e1000_hw
*hw
)
99 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
100 array_wr32(E1000_VFTA
, offset
, 0);
106 * igb_write_vfta - Write value to VLAN filter table
107 * @hw: pointer to the HW structure
108 * @offset: register offset in VLAN filter table
109 * @value: register value written to VLAN filter table
111 * Writes value at the given offset in the register array which stores
112 * the VLAN filter table.
114 void igb_write_vfta(struct e1000_hw
*hw
, u32 offset
, u32 value
)
116 array_wr32(E1000_VFTA
, offset
, value
);
121 * igb_check_alt_mac_addr - Check for alternate MAC addr
122 * @hw: pointer to the HW structure
124 * Checks the nvm for an alternate MAC address. An alternate MAC address
125 * can be setup by pre-boot software and must be treated like a permanent
126 * address and must override the actual permanent MAC address. If an
127 * alternate MAC address is fopund it is saved in the hw struct and
128 * prgrammed into RAR0 and the cuntion returns success, otherwise the
129 * fucntion returns an error.
131 s32
igb_check_alt_mac_addr(struct e1000_hw
*hw
)
135 u16 offset
, nvm_alt_mac_addr_offset
, nvm_data
;
136 u8 alt_mac_addr
[ETH_ALEN
];
138 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ALT_MAC_ADDR_PTR
, 1,
139 &nvm_alt_mac_addr_offset
);
141 hw_dbg("NVM Read Error\n");
145 if (nvm_alt_mac_addr_offset
== 0xFFFF) {
146 ret_val
= -(E1000_NOT_IMPLEMENTED
);
150 if (hw
->bus
.func
== E1000_FUNC_1
)
151 nvm_alt_mac_addr_offset
+= ETH_ALEN
/sizeof(u16
);
153 for (i
= 0; i
< ETH_ALEN
; i
+= 2) {
154 offset
= nvm_alt_mac_addr_offset
+ (i
>> 1);
155 ret_val
= hw
->nvm
.ops
.read(hw
, offset
, 1, &nvm_data
);
157 hw_dbg("NVM Read Error\n");
161 alt_mac_addr
[i
] = (u8
)(nvm_data
& 0xFF);
162 alt_mac_addr
[i
+ 1] = (u8
)(nvm_data
>> 8);
165 /* if multicast bit is set, the alternate address will not be used */
166 if (alt_mac_addr
[0] & 0x01) {
167 ret_val
= -(E1000_NOT_IMPLEMENTED
);
171 for (i
= 0; i
< ETH_ALEN
; i
++)
172 hw
->mac
.addr
[i
] = hw
->mac
.perm_addr
[i
] = alt_mac_addr
[i
];
174 hw
->mac
.ops
.rar_set(hw
, hw
->mac
.perm_addr
, 0);
181 * igb_rar_set - Set receive address register
182 * @hw: pointer to the HW structure
183 * @addr: pointer to the receive address
184 * @index: receive address array register
186 * Sets the receive address array register at index to the address passed
189 void igb_rar_set(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
191 u32 rar_low
, rar_high
;
194 * HW expects these in little endian so we reverse the byte order
195 * from network order (big endian) to little endian
197 rar_low
= ((u32
) addr
[0] |
198 ((u32
) addr
[1] << 8) |
199 ((u32
) addr
[2] << 16) | ((u32
) addr
[3] << 24));
201 rar_high
= ((u32
) addr
[4] | ((u32
) addr
[5] << 8));
203 if (!hw
->mac
.disable_av
)
204 rar_high
|= E1000_RAH_AV
;
206 wr32(E1000_RAL(index
), rar_low
);
207 wr32(E1000_RAH(index
), rar_high
);
211 * igb_mta_set - Set multicast filter table address
212 * @hw: pointer to the HW structure
213 * @hash_value: determines the MTA register and bit to set
215 * The multicast table address is a register array of 32-bit registers.
216 * The hash_value is used to determine what register the bit is in, the
217 * current value is read, the new bit is OR'd in and the new value is
218 * written back into the register.
220 void igb_mta_set(struct e1000_hw
*hw
, u32 hash_value
)
222 u32 hash_bit
, hash_reg
, mta
;
225 * The MTA is a register array of 32-bit registers. It is
226 * treated like an array of (32*mta_reg_count) bits. We want to
227 * set bit BitArray[hash_value]. So we figure out what register
228 * the bit is in, read it, OR in the new bit, then write
229 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
230 * mask to bits 31:5 of the hash value which gives us the
231 * register we're modifying. The hash bit within that register
232 * is determined by the lower 5 bits of the hash value.
234 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
235 hash_bit
= hash_value
& 0x1F;
237 mta
= array_rd32(E1000_MTA
, hash_reg
);
239 mta
|= (1 << hash_bit
);
241 array_wr32(E1000_MTA
, hash_reg
, mta
);
246 * igb_hash_mc_addr - Generate a multicast hash value
247 * @hw: pointer to the HW structure
248 * @mc_addr: pointer to a multicast address
250 * Generates a multicast address hash value which is used to determine
251 * the multicast filter table array address and new table value. See
254 u32
igb_hash_mc_addr(struct e1000_hw
*hw
, u8
*mc_addr
)
256 u32 hash_value
, hash_mask
;
259 /* Register count multiplied by bits per register */
260 hash_mask
= (hw
->mac
.mta_reg_count
* 32) - 1;
263 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
264 * where 0xFF would still fall within the hash mask.
266 while (hash_mask
>> bit_shift
!= 0xFF)
270 * The portion of the address that is used for the hash table
271 * is determined by the mc_filter_type setting.
272 * The algorithm is such that there is a total of 8 bits of shifting.
273 * The bit_shift for a mc_filter_type of 0 represents the number of
274 * left-shifts where the MSB of mc_addr[5] would still fall within
275 * the hash_mask. Case 0 does this exactly. Since there are a total
276 * of 8 bits of shifting, then mc_addr[4] will shift right the
277 * remaining number of bits. Thus 8 - bit_shift. The rest of the
278 * cases are a variation of this algorithm...essentially raising the
279 * number of bits to shift mc_addr[5] left, while still keeping the
280 * 8-bit shifting total.
282 * For example, given the following Destination MAC Address and an
283 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
284 * we can see that the bit_shift for case 0 is 4. These are the hash
285 * values resulting from each mc_filter_type...
286 * [0] [1] [2] [3] [4] [5]
290 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
291 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
292 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
293 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
295 switch (hw
->mac
.mc_filter_type
) {
310 hash_value
= hash_mask
& (((mc_addr
[4] >> (8 - bit_shift
)) |
311 (((u16
) mc_addr
[5]) << bit_shift
)));
317 * igb_clear_hw_cntrs_base - Clear base hardware counters
318 * @hw: pointer to the HW structure
320 * Clears the base hardware counters by reading the counter registers.
322 void igb_clear_hw_cntrs_base(struct e1000_hw
*hw
)
326 temp
= rd32(E1000_CRCERRS
);
327 temp
= rd32(E1000_SYMERRS
);
328 temp
= rd32(E1000_MPC
);
329 temp
= rd32(E1000_SCC
);
330 temp
= rd32(E1000_ECOL
);
331 temp
= rd32(E1000_MCC
);
332 temp
= rd32(E1000_LATECOL
);
333 temp
= rd32(E1000_COLC
);
334 temp
= rd32(E1000_DC
);
335 temp
= rd32(E1000_SEC
);
336 temp
= rd32(E1000_RLEC
);
337 temp
= rd32(E1000_XONRXC
);
338 temp
= rd32(E1000_XONTXC
);
339 temp
= rd32(E1000_XOFFRXC
);
340 temp
= rd32(E1000_XOFFTXC
);
341 temp
= rd32(E1000_FCRUC
);
342 temp
= rd32(E1000_GPRC
);
343 temp
= rd32(E1000_BPRC
);
344 temp
= rd32(E1000_MPRC
);
345 temp
= rd32(E1000_GPTC
);
346 temp
= rd32(E1000_GORCL
);
347 temp
= rd32(E1000_GORCH
);
348 temp
= rd32(E1000_GOTCL
);
349 temp
= rd32(E1000_GOTCH
);
350 temp
= rd32(E1000_RNBC
);
351 temp
= rd32(E1000_RUC
);
352 temp
= rd32(E1000_RFC
);
353 temp
= rd32(E1000_ROC
);
354 temp
= rd32(E1000_RJC
);
355 temp
= rd32(E1000_TORL
);
356 temp
= rd32(E1000_TORH
);
357 temp
= rd32(E1000_TOTL
);
358 temp
= rd32(E1000_TOTH
);
359 temp
= rd32(E1000_TPR
);
360 temp
= rd32(E1000_TPT
);
361 temp
= rd32(E1000_MPTC
);
362 temp
= rd32(E1000_BPTC
);
366 * igb_check_for_copper_link - Check for link (Copper)
367 * @hw: pointer to the HW structure
369 * Checks to see of the link status of the hardware has changed. If a
370 * change in link status has been detected, then we read the PHY registers
371 * to get the current speed/duplex if link exists.
373 s32
igb_check_for_copper_link(struct e1000_hw
*hw
)
375 struct e1000_mac_info
*mac
= &hw
->mac
;
380 * We only want to go out to the PHY registers to see if Auto-Neg
381 * has completed and/or if our link status has changed. The
382 * get_link_status flag is set upon receiving a Link Status
383 * Change or Rx Sequence Error interrupt.
385 if (!mac
->get_link_status
) {
391 * First we want to see if the MII Status Register reports
392 * link. If so, then we want to get the current speed/duplex
395 ret_val
= igb_phy_has_link(hw
, 1, 0, &link
);
400 goto out
; /* No link detected */
402 mac
->get_link_status
= false;
405 * Check if there was DownShift, must be checked
406 * immediately after link-up
408 igb_check_downshift(hw
);
411 * If we are forcing speed/duplex, then we simply return since
412 * we have already determined whether we have link or not.
415 ret_val
= -E1000_ERR_CONFIG
;
420 * Auto-Neg is enabled. Auto Speed Detection takes care
421 * of MAC speed/duplex configuration. So we only need to
422 * configure Collision Distance in the MAC.
424 igb_config_collision_dist(hw
);
427 * Configure Flow Control now that Auto-Neg has completed.
428 * First, we need to restore the desired flow control
429 * settings because we may have had to re-autoneg with a
430 * different link partner.
432 ret_val
= igb_config_fc_after_link_up(hw
);
434 hw_dbg("Error configuring flow control\n");
441 * igb_setup_link - Setup flow control and link settings
442 * @hw: pointer to the HW structure
444 * Determines which flow control settings to use, then configures flow
445 * control. Calls the appropriate media-specific link configuration
446 * function. Assuming the adapter has a valid link partner, a valid link
447 * should be established. Assumes the hardware has previously been reset
448 * and the transmitter and receiver are not enabled.
450 s32
igb_setup_link(struct e1000_hw
*hw
)
455 * In the case of the phy reset being blocked, we already have a link.
456 * We do not need to set it up again.
458 if (igb_check_reset_block(hw
))
461 ret_val
= igb_set_default_fc(hw
);
466 * We want to save off the original Flow Control configuration just
467 * in case we get disconnected and then reconnected into a different
468 * hub or switch with different Flow Control capabilities.
470 hw
->fc
.original_type
= hw
->fc
.type
;
472 hw_dbg("After fix-ups FlowControl is now = %x\n", hw
->fc
.type
);
474 /* Call the necessary media_type subroutine to configure the link. */
475 ret_val
= hw
->mac
.ops
.setup_physical_interface(hw
);
480 * Initialize the flow control address, type, and PAUSE timer
481 * registers to their default values. This is done even if flow
482 * control is disabled, because it does not hurt anything to
483 * initialize these registers.
485 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
486 wr32(E1000_FCT
, FLOW_CONTROL_TYPE
);
487 wr32(E1000_FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
488 wr32(E1000_FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
490 wr32(E1000_FCTTV
, hw
->fc
.pause_time
);
492 ret_val
= igb_set_fc_watermarks(hw
);
499 * igb_config_collision_dist - Configure collision distance
500 * @hw: pointer to the HW structure
502 * Configures the collision distance to the default value and is used
503 * during link setup. Currently no func pointer exists and all
504 * implementations are handled in the generic version of this function.
506 void igb_config_collision_dist(struct e1000_hw
*hw
)
510 tctl
= rd32(E1000_TCTL
);
512 tctl
&= ~E1000_TCTL_COLD
;
513 tctl
|= E1000_COLLISION_DISTANCE
<< E1000_COLD_SHIFT
;
515 wr32(E1000_TCTL
, tctl
);
520 * igb_set_fc_watermarks - Set flow control high/low watermarks
521 * @hw: pointer to the HW structure
523 * Sets the flow control high/low threshold (watermark) registers. If
524 * flow control XON frame transmission is enabled, then set XON frame
525 * tansmission as well.
527 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
)
530 u32 fcrtl
= 0, fcrth
= 0;
533 * Set the flow control receive threshold registers. Normally,
534 * these registers will be set to a default threshold that may be
535 * adjusted later by the driver's runtime code. However, if the
536 * ability to transmit pause frames is not enabled, then these
537 * registers will be set to 0.
539 if (hw
->fc
.type
& e1000_fc_tx_pause
) {
541 * We need to set up the Receive Threshold high and low water
542 * marks as well as (optionally) enabling the transmission of
545 fcrtl
= hw
->fc
.low_water
;
547 fcrtl
|= E1000_FCRTL_XONE
;
549 fcrth
= hw
->fc
.high_water
;
551 wr32(E1000_FCRTL
, fcrtl
);
552 wr32(E1000_FCRTH
, fcrth
);
558 * igb_set_default_fc - Set flow control default values
559 * @hw: pointer to the HW structure
561 * Read the EEPROM for the default values for flow control and store the
564 static s32
igb_set_default_fc(struct e1000_hw
*hw
)
570 * Read and store word 0x0F of the EEPROM. This word contains bits
571 * that determine the hardware's default PAUSE (flow control) mode,
572 * a bit that determines whether the HW defaults to enabling or
573 * disabling auto-negotiation, and the direction of the
574 * SW defined pins. If there is no SW over-ride of the flow
575 * control setting, then the variable hw->fc will
576 * be initialized based on a value in the EEPROM.
578 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL2_REG
, 1, &nvm_data
);
581 hw_dbg("NVM Read Error\n");
585 if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) == 0)
586 hw
->fc
.type
= e1000_fc_none
;
587 else if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) ==
589 hw
->fc
.type
= e1000_fc_tx_pause
;
591 hw
->fc
.type
= e1000_fc_full
;
598 * igb_force_mac_fc - Force the MAC's flow control settings
599 * @hw: pointer to the HW structure
601 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
602 * device control register to reflect the adapter settings. TFCE and RFCE
603 * need to be explicitly set by software when a copper PHY is used because
604 * autonegotiation is managed by the PHY rather than the MAC. Software must
605 * also configure these bits when link is forced on a fiber connection.
607 s32
igb_force_mac_fc(struct e1000_hw
*hw
)
612 ctrl
= rd32(E1000_CTRL
);
615 * Because we didn't get link via the internal auto-negotiation
616 * mechanism (we either forced link or we got link via PHY
617 * auto-neg), we have to manually enable/disable transmit an
618 * receive flow control.
620 * The "Case" statement below enables/disable flow control
621 * according to the "hw->fc.type" parameter.
623 * The possible values of the "fc" parameter are:
624 * 0: Flow control is completely disabled
625 * 1: Rx flow control is enabled (we can receive pause
626 * frames but not send pause frames).
627 * 2: Tx flow control is enabled (we can send pause frames
628 * frames but we do not receive pause frames).
629 * 3: Both Rx and TX flow control (symmetric) is enabled.
630 * other: No other values should be possible at this point.
632 hw_dbg("hw->fc.type = %u\n", hw
->fc
.type
);
634 switch (hw
->fc
.type
) {
636 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
638 case e1000_fc_rx_pause
:
639 ctrl
&= (~E1000_CTRL_TFCE
);
640 ctrl
|= E1000_CTRL_RFCE
;
642 case e1000_fc_tx_pause
:
643 ctrl
&= (~E1000_CTRL_RFCE
);
644 ctrl
|= E1000_CTRL_TFCE
;
647 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
650 hw_dbg("Flow control param set incorrectly\n");
651 ret_val
= -E1000_ERR_CONFIG
;
655 wr32(E1000_CTRL
, ctrl
);
662 * igb_config_fc_after_link_up - Configures flow control after link
663 * @hw: pointer to the HW structure
665 * Checks the status of auto-negotiation after link up to ensure that the
666 * speed and duplex were not forced. If the link needed to be forced, then
667 * flow control needs to be forced also. If auto-negotiation is enabled
668 * and did not fail, then we configure flow control based on our link
671 s32
igb_config_fc_after_link_up(struct e1000_hw
*hw
)
673 struct e1000_mac_info
*mac
= &hw
->mac
;
675 u16 mii_status_reg
, mii_nway_adv_reg
, mii_nway_lp_ability_reg
;
679 * Check for the case where we have fiber media and auto-neg failed
680 * so we had to force link. In this case, we need to force the
681 * configuration of the MAC to match the "fc" parameter.
683 if (mac
->autoneg_failed
) {
684 if (hw
->phy
.media_type
== e1000_media_type_fiber
||
685 hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
686 ret_val
= igb_force_mac_fc(hw
);
688 if (hw
->phy
.media_type
== e1000_media_type_copper
)
689 ret_val
= igb_force_mac_fc(hw
);
693 hw_dbg("Error forcing flow control settings\n");
698 * Check for the case where we have copper media and auto-neg is
699 * enabled. In this case, we need to check and see if Auto-Neg
700 * has completed, and if so, how the PHY and link partner has
701 * flow control configured.
703 if ((hw
->phy
.media_type
== e1000_media_type_copper
) && mac
->autoneg
) {
705 * Read the MII Status Register and check to see if AutoNeg
706 * has completed. We read this twice because this reg has
707 * some "sticky" (latched) bits.
709 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
,
713 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
,
718 if (!(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
)) {
719 hw_dbg("Copper PHY and Auto Neg "
720 "has not completed.\n");
725 * The AutoNeg process has completed, so we now need to
726 * read both the Auto Negotiation Advertisement
727 * Register (Address 4) and the Auto_Negotiation Base
728 * Page Ability Register (Address 5) to determine how
729 * flow control was negotiated.
731 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_AUTONEG_ADV
,
735 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_LP_ABILITY
,
736 &mii_nway_lp_ability_reg
);
741 * Two bits in the Auto Negotiation Advertisement Register
742 * (Address 4) and two bits in the Auto Negotiation Base
743 * Page Ability Register (Address 5) determine flow control
744 * for both the PHY and the link partner. The following
745 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
746 * 1999, describes these PAUSE resolution bits and how flow
747 * control is determined based upon these settings.
748 * NOTE: DC = Don't Care
750 * LOCAL DEVICE | LINK PARTNER
751 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
752 *-------|---------|-------|---------|--------------------
753 * 0 | 0 | DC | DC | e1000_fc_none
754 * 0 | 1 | 0 | DC | e1000_fc_none
755 * 0 | 1 | 1 | 0 | e1000_fc_none
756 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
757 * 1 | 0 | 0 | DC | e1000_fc_none
758 * 1 | DC | 1 | DC | e1000_fc_full
759 * 1 | 1 | 0 | 0 | e1000_fc_none
760 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
762 * Are both PAUSE bits set to 1? If so, this implies
763 * Symmetric Flow Control is enabled at both ends. The
764 * ASM_DIR bits are irrelevant per the spec.
766 * For Symmetric Flow Control:
768 * LOCAL DEVICE | LINK PARTNER
769 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
770 *-------|---------|-------|---------|--------------------
771 * 1 | DC | 1 | DC | E1000_fc_full
774 if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
775 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
777 * Now we need to check if the user selected RX ONLY
778 * of pause frames. In this case, we had to advertise
779 * FULL flow control because we could not advertise RX
780 * ONLY. Hence, we must now check to see if we need to
781 * turn OFF the TRANSMISSION of PAUSE frames.
783 if (hw
->fc
.original_type
== e1000_fc_full
) {
784 hw
->fc
.type
= e1000_fc_full
;
785 hw_dbg("Flow Control = FULL.\r\n");
787 hw
->fc
.type
= e1000_fc_rx_pause
;
788 hw_dbg("Flow Control = "
789 "RX PAUSE frames only.\r\n");
793 * For receiving PAUSE frames ONLY.
795 * LOCAL DEVICE | LINK PARTNER
796 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
797 *-------|---------|-------|---------|--------------------
798 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
800 else if (!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
801 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
802 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
803 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
804 hw
->fc
.type
= e1000_fc_tx_pause
;
805 hw_dbg("Flow Control = TX PAUSE frames only.\r\n");
808 * For transmitting PAUSE frames ONLY.
810 * LOCAL DEVICE | LINK PARTNER
811 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
812 *-------|---------|-------|---------|--------------------
813 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
815 else if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
816 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
817 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
818 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
819 hw
->fc
.type
= e1000_fc_rx_pause
;
820 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
823 * Per the IEEE spec, at this point flow control should be
824 * disabled. However, we want to consider that we could
825 * be connected to a legacy switch that doesn't advertise
826 * desired flow control, but can be forced on the link
827 * partner. So if we advertised no flow control, that is
828 * what we will resolve to. If we advertised some kind of
829 * receive capability (Rx Pause Only or Full Flow Control)
830 * and the link partner advertised none, we will configure
831 * ourselves to enable Rx Flow Control only. We can do
832 * this safely for two reasons: If the link partner really
833 * didn't want flow control enabled, and we enable Rx, no
834 * harm done since we won't be receiving any PAUSE frames
835 * anyway. If the intent on the link partner was to have
836 * flow control enabled, then by us enabling RX only, we
837 * can at least receive pause frames and process them.
838 * This is a good idea because in most cases, since we are
839 * predominantly a server NIC, more times than not we will
840 * be asked to delay transmission of packets than asking
841 * our link partner to pause transmission of frames.
843 else if ((hw
->fc
.original_type
== e1000_fc_none
||
844 hw
->fc
.original_type
== e1000_fc_tx_pause
) ||
845 hw
->fc
.strict_ieee
) {
846 hw
->fc
.type
= e1000_fc_none
;
847 hw_dbg("Flow Control = NONE.\r\n");
849 hw
->fc
.type
= e1000_fc_rx_pause
;
850 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
854 * Now we need to do one last check... If we auto-
855 * negotiated to HALF DUPLEX, flow control should not be
856 * enabled per IEEE 802.3 spec.
858 ret_val
= hw
->mac
.ops
.get_speed_and_duplex(hw
, &speed
, &duplex
);
860 hw_dbg("Error getting link speed and duplex\n");
864 if (duplex
== HALF_DUPLEX
)
865 hw
->fc
.type
= e1000_fc_none
;
868 * Now we call a subroutine to actually force the MAC
869 * controller to use the correct flow control settings.
871 ret_val
= igb_force_mac_fc(hw
);
873 hw_dbg("Error forcing flow control settings\n");
883 * igb_get_speed_and_duplex_copper - Retreive current speed/duplex
884 * @hw: pointer to the HW structure
885 * @speed: stores the current speed
886 * @duplex: stores the current duplex
888 * Read the status register for the current speed/duplex and store the current
889 * speed and duplex for copper connections.
891 s32
igb_get_speed_and_duplex_copper(struct e1000_hw
*hw
, u16
*speed
,
896 status
= rd32(E1000_STATUS
);
897 if (status
& E1000_STATUS_SPEED_1000
) {
899 hw_dbg("1000 Mbs, ");
900 } else if (status
& E1000_STATUS_SPEED_100
) {
908 if (status
& E1000_STATUS_FD
) {
909 *duplex
= FULL_DUPLEX
;
910 hw_dbg("Full Duplex\n");
912 *duplex
= HALF_DUPLEX
;
913 hw_dbg("Half Duplex\n");
920 * igb_get_hw_semaphore - Acquire hardware semaphore
921 * @hw: pointer to the HW structure
923 * Acquire the HW semaphore to access the PHY or NVM
925 s32
igb_get_hw_semaphore(struct e1000_hw
*hw
)
929 s32 timeout
= hw
->nvm
.word_size
+ 1;
932 /* Get the SW semaphore */
933 while (i
< timeout
) {
934 swsm
= rd32(E1000_SWSM
);
935 if (!(swsm
& E1000_SWSM_SMBI
))
943 hw_dbg("Driver can't access device - SMBI bit is set.\n");
944 ret_val
= -E1000_ERR_NVM
;
948 /* Get the FW semaphore. */
949 for (i
= 0; i
< timeout
; i
++) {
950 swsm
= rd32(E1000_SWSM
);
951 wr32(E1000_SWSM
, swsm
| E1000_SWSM_SWESMBI
);
953 /* Semaphore acquired if bit latched */
954 if (rd32(E1000_SWSM
) & E1000_SWSM_SWESMBI
)
961 /* Release semaphores */
962 igb_put_hw_semaphore(hw
);
963 hw_dbg("Driver can't access the NVM\n");
964 ret_val
= -E1000_ERR_NVM
;
973 * igb_put_hw_semaphore - Release hardware semaphore
974 * @hw: pointer to the HW structure
976 * Release hardware semaphore used to access the PHY or NVM
978 void igb_put_hw_semaphore(struct e1000_hw
*hw
)
982 swsm
= rd32(E1000_SWSM
);
984 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
986 wr32(E1000_SWSM
, swsm
);
990 * igb_get_auto_rd_done - Check for auto read completion
991 * @hw: pointer to the HW structure
993 * Check EEPROM for Auto Read done bit.
995 s32
igb_get_auto_rd_done(struct e1000_hw
*hw
)
1001 while (i
< AUTO_READ_DONE_TIMEOUT
) {
1002 if (rd32(E1000_EECD
) & E1000_EECD_AUTO_RD
)
1008 if (i
== AUTO_READ_DONE_TIMEOUT
) {
1009 hw_dbg("Auto read by HW from NVM has not completed.\n");
1010 ret_val
= -E1000_ERR_RESET
;
1019 * igb_valid_led_default - Verify a valid default LED config
1020 * @hw: pointer to the HW structure
1021 * @data: pointer to the NVM (EEPROM)
1023 * Read the EEPROM for the current default LED configuration. If the
1024 * LED configuration is not valid, set to a valid LED configuration.
1026 static s32
igb_valid_led_default(struct e1000_hw
*hw
, u16
*data
)
1030 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1032 hw_dbg("NVM Read Error\n");
1036 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
)
1037 *data
= ID_LED_DEFAULT
;
1045 * @hw: pointer to the HW structure
1048 s32
igb_id_led_init(struct e1000_hw
*hw
)
1050 struct e1000_mac_info
*mac
= &hw
->mac
;
1052 const u32 ledctl_mask
= 0x000000FF;
1053 const u32 ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
1054 const u32 ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
1056 const u16 led_mask
= 0x0F;
1058 ret_val
= igb_valid_led_default(hw
, &data
);
1062 mac
->ledctl_default
= rd32(E1000_LEDCTL
);
1063 mac
->ledctl_mode1
= mac
->ledctl_default
;
1064 mac
->ledctl_mode2
= mac
->ledctl_default
;
1066 for (i
= 0; i
< 4; i
++) {
1067 temp
= (data
>> (i
<< 2)) & led_mask
;
1069 case ID_LED_ON1_DEF2
:
1070 case ID_LED_ON1_ON2
:
1071 case ID_LED_ON1_OFF2
:
1072 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1073 mac
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
1075 case ID_LED_OFF1_DEF2
:
1076 case ID_LED_OFF1_ON2
:
1077 case ID_LED_OFF1_OFF2
:
1078 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1079 mac
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
1086 case ID_LED_DEF1_ON2
:
1087 case ID_LED_ON1_ON2
:
1088 case ID_LED_OFF1_ON2
:
1089 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1090 mac
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
1092 case ID_LED_DEF1_OFF2
:
1093 case ID_LED_ON1_OFF2
:
1094 case ID_LED_OFF1_OFF2
:
1095 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1096 mac
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
1109 * igb_cleanup_led - Set LED config to default operation
1110 * @hw: pointer to the HW structure
1112 * Remove the current LED configuration and set the LED configuration
1113 * to the default value, saved from the EEPROM.
1115 s32
igb_cleanup_led(struct e1000_hw
*hw
)
1117 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_default
);
1122 * igb_blink_led - Blink LED
1123 * @hw: pointer to the HW structure
1125 * Blink the led's which are set to be on.
1127 s32
igb_blink_led(struct e1000_hw
*hw
)
1129 u32 ledctl_blink
= 0;
1132 if (hw
->phy
.media_type
== e1000_media_type_fiber
) {
1133 /* always blink LED0 for PCI-E fiber */
1134 ledctl_blink
= E1000_LEDCTL_LED0_BLINK
|
1135 (E1000_LEDCTL_MODE_LED_ON
<< E1000_LEDCTL_LED0_MODE_SHIFT
);
1138 * set the blink bit for each LED that's "on" (0x0E)
1141 ledctl_blink
= hw
->mac
.ledctl_mode2
;
1142 for (i
= 0; i
< 4; i
++)
1143 if (((hw
->mac
.ledctl_mode2
>> (i
* 8)) & 0xFF) ==
1144 E1000_LEDCTL_MODE_LED_ON
)
1145 ledctl_blink
|= (E1000_LEDCTL_LED0_BLINK
<<
1149 wr32(E1000_LEDCTL
, ledctl_blink
);
1155 * igb_led_off - Turn LED off
1156 * @hw: pointer to the HW structure
1160 s32
igb_led_off(struct e1000_hw
*hw
)
1164 switch (hw
->phy
.media_type
) {
1165 case e1000_media_type_fiber
:
1166 ctrl
= rd32(E1000_CTRL
);
1167 ctrl
|= E1000_CTRL_SWDPIN0
;
1168 ctrl
|= E1000_CTRL_SWDPIO0
;
1169 wr32(E1000_CTRL
, ctrl
);
1171 case e1000_media_type_copper
:
1172 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_mode1
);
1182 * igb_disable_pcie_master - Disables PCI-express master access
1183 * @hw: pointer to the HW structure
1185 * Returns 0 (0) if successful, else returns -10
1186 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
1187 * the master requests to be disabled.
1189 * Disables PCI-Express master access and verifies there are no pending
1192 s32
igb_disable_pcie_master(struct e1000_hw
*hw
)
1195 s32 timeout
= MASTER_DISABLE_TIMEOUT
;
1198 if (hw
->bus
.type
!= e1000_bus_type_pci_express
)
1201 ctrl
= rd32(E1000_CTRL
);
1202 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
1203 wr32(E1000_CTRL
, ctrl
);
1206 if (!(rd32(E1000_STATUS
) &
1207 E1000_STATUS_GIO_MASTER_ENABLE
))
1214 hw_dbg("Master requests are pending.\n");
1215 ret_val
= -E1000_ERR_MASTER_REQUESTS_PENDING
;
1224 * igb_reset_adaptive - Reset Adaptive Interframe Spacing
1225 * @hw: pointer to the HW structure
1227 * Reset the Adaptive Interframe Spacing throttle to default values.
1229 void igb_reset_adaptive(struct e1000_hw
*hw
)
1231 struct e1000_mac_info
*mac
= &hw
->mac
;
1233 if (!mac
->adaptive_ifs
) {
1234 hw_dbg("Not in Adaptive IFS mode!\n");
1238 if (!mac
->ifs_params_forced
) {
1239 mac
->current_ifs_val
= 0;
1240 mac
->ifs_min_val
= IFS_MIN
;
1241 mac
->ifs_max_val
= IFS_MAX
;
1242 mac
->ifs_step_size
= IFS_STEP
;
1243 mac
->ifs_ratio
= IFS_RATIO
;
1246 mac
->in_ifs_mode
= false;
1253 * igb_update_adaptive - Update Adaptive Interframe Spacing
1254 * @hw: pointer to the HW structure
1256 * Update the Adaptive Interframe Spacing Throttle value based on the
1257 * time between transmitted packets and time between collisions.
1259 void igb_update_adaptive(struct e1000_hw
*hw
)
1261 struct e1000_mac_info
*mac
= &hw
->mac
;
1263 if (!mac
->adaptive_ifs
) {
1264 hw_dbg("Not in Adaptive IFS mode!\n");
1268 if ((mac
->collision_delta
* mac
->ifs_ratio
) > mac
->tx_packet_delta
) {
1269 if (mac
->tx_packet_delta
> MIN_NUM_XMITS
) {
1270 mac
->in_ifs_mode
= true;
1271 if (mac
->current_ifs_val
< mac
->ifs_max_val
) {
1272 if (!mac
->current_ifs_val
)
1273 mac
->current_ifs_val
= mac
->ifs_min_val
;
1275 mac
->current_ifs_val
+=
1278 mac
->current_ifs_val
);
1282 if (mac
->in_ifs_mode
&&
1283 (mac
->tx_packet_delta
<= MIN_NUM_XMITS
)) {
1284 mac
->current_ifs_val
= 0;
1285 mac
->in_ifs_mode
= false;
1294 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1295 * @hw: pointer to the HW structure
1297 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1298 * set, which is forced to MDI mode only.
1300 s32
igb_validate_mdi_setting(struct e1000_hw
*hw
)
1304 if (!hw
->mac
.autoneg
&& (hw
->phy
.mdix
== 0 || hw
->phy
.mdix
== 3)) {
1305 hw_dbg("Invalid MDI setting detected\n");
1307 ret_val
= -E1000_ERR_CONFIG
;
1316 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1317 * @hw: pointer to the HW structure
1318 * @reg: 32bit register offset such as E1000_SCTL
1319 * @offset: register offset to write to
1320 * @data: data to write at register offset
1322 * Writes an address/data control type register. There are several of these
1323 * and they all have the format address << 8 | data and bit 31 is polled for
1326 s32
igb_write_8bit_ctrl_reg(struct e1000_hw
*hw
, u32 reg
,
1327 u32 offset
, u8 data
)
1329 u32 i
, regvalue
= 0;
1332 /* Set up the address and data */
1333 regvalue
= ((u32
)data
) | (offset
<< E1000_GEN_CTL_ADDRESS_SHIFT
);
1334 wr32(reg
, regvalue
);
1336 /* Poll the ready bit to see if the MDI read completed */
1337 for (i
= 0; i
< E1000_GEN_POLL_TIMEOUT
; i
++) {
1339 regvalue
= rd32(reg
);
1340 if (regvalue
& E1000_GEN_CTL_READY
)
1343 if (!(regvalue
& E1000_GEN_CTL_READY
)) {
1344 hw_dbg("Reg %08x did not indicate ready\n", reg
);
1345 ret_val
= -E1000_ERR_PHY
;
1354 * igb_enable_mng_pass_thru - Enable processing of ARP's
1355 * @hw: pointer to the HW structure
1357 * Verifies the hardware needs to allow ARPs to be processed by the host.
1359 bool igb_enable_mng_pass_thru(struct e1000_hw
*hw
)
1363 bool ret_val
= false;
1365 if (!hw
->mac
.asf_firmware_present
)
1368 manc
= rd32(E1000_MANC
);
1370 if (!(manc
& E1000_MANC_RCV_TCO_EN
) ||
1371 !(manc
& E1000_MANC_EN_MAC_ADDR_FILTER
))
1374 if (hw
->mac
.arc_subsystem_valid
) {
1375 fwsm
= rd32(E1000_FWSM
);
1376 factps
= rd32(E1000_FACTPS
);
1378 if (!(factps
& E1000_FACTPS_MNGCG
) &&
1379 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
1380 (e1000_mng_mode_pt
<< E1000_FWSM_MODE_SHIFT
))) {
1385 if ((manc
& E1000_MANC_SMBUS_EN
) &&
1386 !(manc
& E1000_MANC_ASF_EN
)) {