include/asm-powerpc/mpic.h

   1 #ifndef _ASM_POWERPC_MPIC_H
   2 #define _ASM_POWERPC_MPIC_H
   3 #ifdef __KERNEL__
   4
   5 #include <linux/irq.h>
   6
   7 /*
   8  * Global registers
   9  */
  10
  11 #define MPIC_GREG_BASE                  0x01000
  12
  13 #define MPIC_GREG_FEATURE_0             0x00000
  14 #define         MPIC_GREG_FEATURE_LAST_SRC_MASK         0x07ff0000
  15 #define         MPIC_GREG_FEATURE_LAST_SRC_SHIFT        16
  16 #define         MPIC_GREG_FEATURE_LAST_CPU_MASK         0x00001f00
  17 #define         MPIC_GREG_FEATURE_LAST_CPU_SHIFT        8
  18 #define         MPIC_GREG_FEATURE_VERSION_MASK          0xff
  19 #define MPIC_GREG_FEATURE_1             0x00010
  20 #define MPIC_GREG_GLOBAL_CONF_0         0x00020
  21 #define         MPIC_GREG_GCONF_RESET                   0x80000000
  22 #define         MPIC_GREG_GCONF_8259_PTHROU_DIS         0x20000000
  23 #define         MPIC_GREG_GCONF_BASE_MASK               0x000fffff
  24 #define MPIC_GREG_GLOBAL_CONF_1         0x00030
  25 #define MPIC_GREG_VENDOR_0              0x00040
  26 #define MPIC_GREG_VENDOR_1              0x00050
  27 #define MPIC_GREG_VENDOR_2              0x00060
  28 #define MPIC_GREG_VENDOR_3              0x00070
  29 #define MPIC_GREG_VENDOR_ID             0x00080
  30 #define         MPIC_GREG_VENDOR_ID_STEPPING_MASK       0x00ff0000
  31 #define         MPIC_GREG_VENDOR_ID_STEPPING_SHIFT      16
  32 #define         MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK      0x0000ff00
  33 #define         MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT     8
  34 #define         MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK      0x000000ff
  35 #define MPIC_GREG_PROCESSOR_INIT        0x00090
  36 #define MPIC_GREG_IPI_VECTOR_PRI_0      0x000a0
  37 #define MPIC_GREG_IPI_VECTOR_PRI_1      0x000b0
  38 #define MPIC_GREG_IPI_VECTOR_PRI_2      0x000c0
  39 #define MPIC_GREG_IPI_VECTOR_PRI_3      0x000d0
  40 #define MPIC_GREG_SPURIOUS              0x000e0
  41 #define MPIC_GREG_TIMER_FREQ            0x000f0
  42
  43 /*
  44  *
  45  * Timer registers
  46  */
  47 #define MPIC_TIMER_BASE                 0x01100
  48 #define MPIC_TIMER_STRIDE               0x40
  49
  50 #define MPIC_TIMER_CURRENT_CNT          0x00000
  51 #define MPIC_TIMER_BASE_CNT             0x00010
  52 #define MPIC_TIMER_VECTOR_PRI           0x00020
  53 #define MPIC_TIMER_DESTINATION          0x00030
  54
  55 /*
  56  * Per-Processor registers
  57  */
  58
  59 #define MPIC_CPU_THISBASE               0x00000
  60 #define MPIC_CPU_BASE                   0x20000
  61 #define MPIC_CPU_STRIDE                 0x01000
  62
  63 #define MPIC_CPU_IPI_DISPATCH_0         0x00040
  64 #define MPIC_CPU_IPI_DISPATCH_1         0x00050
  65 #define MPIC_CPU_IPI_DISPATCH_2         0x00060
  66 #define MPIC_CPU_IPI_DISPATCH_3         0x00070
  67 #define MPIC_CPU_CURRENT_TASK_PRI       0x00080
  68 #define         MPIC_CPU_TASKPRI_MASK                   0x0000000f
  69 #define MPIC_CPU_WHOAMI                 0x00090
  70 #define         MPIC_CPU_WHOAMI_MASK                    0x0000001f
  71 #define MPIC_CPU_INTACK                 0x000a0
  72 #define MPIC_CPU_EOI                    0x000b0
  73
  74 /*
  75  * Per-source registers
  76  */
  77
  78 #define MPIC_IRQ_BASE                   0x10000
  79 #define MPIC_IRQ_STRIDE                 0x00020
  80 #define MPIC_IRQ_VECTOR_PRI             0x00000
  81 #define         MPIC_VECPRI_MASK                        0x80000000
  82 #define         MPIC_VECPRI_ACTIVITY                    0x40000000      /* Read Only */
  83 #define         MPIC_VECPRI_PRIORITY_MASK               0x000f0000
  84 #define         MPIC_VECPRI_PRIORITY_SHIFT              16
  85 #define         MPIC_VECPRI_VECTOR_MASK                 0x000007ff
  86 #define         MPIC_VECPRI_POLARITY_POSITIVE           0x00800000
  87 #define         MPIC_VECPRI_POLARITY_NEGATIVE           0x00000000
  88 #define         MPIC_VECPRI_POLARITY_MASK               0x00800000
  89 #define         MPIC_VECPRI_SENSE_LEVEL                 0x00400000
  90 #define         MPIC_VECPRI_SENSE_EDGE                  0x00000000
  91 #define         MPIC_VECPRI_SENSE_MASK                  0x00400000
  92 #define MPIC_IRQ_DESTINATION            0x00010
  93
  94 #define MPIC_MAX_IRQ_SOURCES    2048
  95 #define MPIC_MAX_CPUS           32
  96 #define MPIC_MAX_ISU            32
  97
  98 /*
  99  * Special vector numbers (internal use only)
 100  */
 101 #define MPIC_VEC_SPURRIOUS      255
 102 #define MPIC_VEC_IPI_3          254
 103 #define MPIC_VEC_IPI_2          253
 104 #define MPIC_VEC_IPI_1          252
 105 #define MPIC_VEC_IPI_0          251
 106
 107 /* unused */
 108 #define MPIC_VEC_TIMER_3        250
 109 #define MPIC_VEC_TIMER_2        249
 110 #define MPIC_VEC_TIMER_1        248
 111 #define MPIC_VEC_TIMER_0        247
 112
 113 /* Type definition of the cascade handler */
 114 typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
 115
 116 #ifdef CONFIG_MPIC_BROKEN_U3
 117 /* Fixup table entry */
 118 struct mpic_irq_fixup
 119 {
 120         u8 __iomem      *base;
 121         u8 __iomem      *applebase;
 122         u32             data;
 123         unsigned int    index;
 124 };
 125 #endif /* CONFIG_MPIC_BROKEN_U3 */
 126
 127
 128 /* The instance data of a given MPIC */
 129 struct mpic
 130 {
 131         /* The "linux" controller struct */
 132         hw_irq_controller       hc_irq;
 133 #ifdef CONFIG_SMP
 134         hw_irq_controller       hc_ipi;
 135 #endif
 136         const char              *name;
 137         /* Flags */
 138         unsigned int            flags;
 139         /* How many irq sources in a given ISU */
 140         unsigned int            isu_size;
 141         unsigned int            isu_shift;
 142         unsigned int            isu_mask;
 143         /* Offset of irq vector numbers */
 144         unsigned int            irq_offset;
 145         unsigned int            irq_count;
 146         /* Offset of ipi vector numbers */
 147         unsigned int            ipi_offset;
 148         /* Number of sources */
 149         unsigned int            num_sources;
 150         /* Number of CPUs */
 151         unsigned int            num_cpus;
 152         /* cascade handler */
 153         mpic_cascade_t          cascade;
 154         void                    *cascade_data;
 155         unsigned int            cascade_vec;
 156         /* senses array */
 157         unsigned char           *senses;
 158         unsigned int            senses_count;
 159
 160 #ifdef CONFIG_MPIC_BROKEN_U3
 161         /* The fixup table */
 162         struct mpic_irq_fixup   *fixups;
 163         spinlock_t              fixup_lock;
 164 #endif
 165
 166         /* The various ioremap'ed bases */
 167         volatile u32 __iomem    *gregs;
 168         volatile u32 __iomem    *tmregs;
 169         volatile u32 __iomem    *cpuregs[MPIC_MAX_CPUS];
 170         volatile u32 __iomem    *isus[MPIC_MAX_ISU];
 171
 172         /* link */
 173         struct mpic             *next;
 174 };
 175
 176 /* This is the primary controller, only that one has IPIs and
 177  * has afinity control. A non-primary MPIC always uses CPU0
 178  * registers only
 179  */
 180 #define MPIC_PRIMARY                    0x00000001
 181 /* Set this for a big-endian MPIC */
 182 #define MPIC_BIG_ENDIAN                 0x00000002
 183 /* Broken U3 MPIC */
 184 #define MPIC_BROKEN_U3                  0x00000004
 185 /* Broken IPI registers (autodetected) */
 186 #define MPIC_BROKEN_IPI                 0x00000008
 187 /* MPIC wants a reset */
 188 #define MPIC_WANTS_RESET                0x00000010
 189
 190 /* Allocate the controller structure and setup the linux irq descs
 191  * for the range if interrupts passed in. No HW initialization is
 192  * actually performed.
 193  *
 194  * @phys_addr:  physial base address of the MPIC
 195  * @flags:      flags, see constants above
 196  * @isu_size:   number of interrupts in an ISU. Use 0 to use a
 197  *              standard ISU-less setup (aka powermac)
 198  * @irq_offset: first irq number to assign to this mpic
 199  * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
 200  *              to match the number of sources
 201  * @ipi_offset: first irq number to assign to this mpic IPI sources,
 202  *              used only on primary mpic
 203  * @senses:     array of sense values
 204  * @senses_num: number of entries in the array
 205  *
 206  * Note about the sense array. If none is passed, all interrupts are
 207  * setup to be level negative unless MPIC_BROKEN_U3 is set in which
 208  * case they are edge positive (and the array is ignored anyway).
 209  * The values in the array start at the first source of the MPIC,
 210  * that is senses[0] correspond to linux irq "irq_offset".
 211  */
 212 extern struct mpic *mpic_alloc(unsigned long phys_addr,
 213                                unsigned int flags,
 214                                unsigned int isu_size,
 215                                unsigned int irq_offset,
 216                                unsigned int irq_count,
 217                                unsigned int ipi_offset,
 218                                unsigned char *senses,
 219                                unsigned int senses_num,
 220                                const char *name);
 221
 222 /* Assign ISUs, to call before mpic_init()
 223  *
 224  * @mpic:       controller structure as returned by mpic_alloc()
 225  * @isu_num:    ISU number
 226  * @phys_addr:  physical address of the ISU
 227  */
 228 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
 229                             unsigned long phys_addr);
 230
 231 /* Initialize the controller. After this has been called, none of the above
 232  * should be called again for this mpic
 233  */
 234 extern void mpic_init(struct mpic *mpic);
 235
 236 /* Setup a cascade. Currently, only one cascade is supported this
 237  * way, though you can always do a normal request_irq() and add
 238  * other cascades this way. You should call this _after_ having
 239  * added all the ISUs
 240  *
 241  * @irq_no:     "linux" irq number of the cascade (that is offset'ed vector)
 242  * @handler:    cascade handler function
 243  */
 244 extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder,
 245                                void *data);
 246
 247 /*
 248  * All of the following functions must only be used after the
 249  * ISUs have been assigned and the controller fully initialized
 250  * with mpic_init()
 251  */
 252
 253
 254 /* Change/Read the priority of an interrupt. Default is 8 for irqs and
 255  * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
 256  * IPI number is then the offset'ed (linux irq number mapped to the IPI)
 257  */
 258 extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
 259 extern unsigned int mpic_irq_get_priority(unsigned int irq);
 260
 261 /* Setup a non-boot CPU */
 262 extern void mpic_setup_this_cpu(void);
 263
 264 /* Clean up for kexec (or cpu offline or ...) */
 265 extern void mpic_teardown_this_cpu(int secondary);
 266
 267 /* Get the current cpu priority for this cpu (0..15) */
 268 extern int mpic_cpu_get_priority(void);
 269
 270 /* Set the current cpu priority for this cpu */
 271 extern void mpic_cpu_set_priority(int prio);
 272
 273 /* Request IPIs on primary mpic */
 274 extern void mpic_request_ipis(void);
 275
 276 /* Send an IPI (non offseted number 0..3) */
 277 extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
 278
 279 /* Send a message (IPI) to a given target (cpu number or MSG_*) */
 280 void smp_mpic_message_pass(int target, int msg);
 281
 282 /* Fetch interrupt from a given mpic */
 283 extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
 284 /* This one gets to the primary mpic */
 285 extern int mpic_get_irq(struct pt_regs *regs);
 286
 287 /* global mpic for pSeries */
 288 extern struct mpic *pSeries_mpic;
 289
 290 #endif /* __KERNEL__ */
 291 #endif  /* _ASM_POWERPC_MPIC_H */