arch/mips/loongson/common/cs5536/cs5536_ide.c

   1 /*
   2  * the IDE Virtual Support Module of AMD CS5536
   3  *
   4  * Copyright (C) 2007 Lemote, Inc.
   5  * Author : jlliu, liujl@lemote.com
   6  *
   7  * Copyright (C) 2009 Lemote, Inc.
   8  * Author: Wu Zhangjin, wuzj@lemote.com
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <cs5536/cs5536.h>
  17 #include <cs5536/cs5536_pci.h>
  18
  19 void pci_ide_write_reg(int reg, u32 value)
  20 {
  21         u32 hi = 0, lo = value;
  22
  23         switch (reg) {
  24         case PCI_COMMAND:
  25                 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
  26                 if (value & PCI_COMMAND_MASTER)
  27                         lo |= (0x03 << 4);
  28                 else
  29                         lo &= ~(0x03 << 4);
  30                 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
  31                 break;
  32         case PCI_STATUS:
  33                 if (value & PCI_STATUS_PARITY) {
  34                         _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
  35                         if (lo & SB_PARE_ERR_FLAG) {
  36                                 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
  37                                 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
  38                         }
  39                 }
  40                 break;
  41         case PCI_CACHE_LINE_SIZE:
  42                 value &= 0x0000ff00;
  43                 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
  44                 hi &= 0xffffff00;
  45                 hi |= (value >> 8);
  46                 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
  47                 break;
  48         case PCI_BAR4_REG:
  49                 if (value == PCI_BAR_RANGE_MASK) {
  50                         _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
  51                         lo |= SOFT_BAR_IDE_FLAG;
  52                         _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
  53                 } else if (value & 0x01) {
  54                         lo = (value & 0xfffffff0) | 0x1;
  55                         _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);
  56
  57                         value &= 0xfffffffc;
  58                         hi = 0x60000000 | ((value & 0x000ff000) >> 12);
  59                         lo = 0x000ffff0 | ((value & 0x00000fff) << 20);
  60                         _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);
  61                 }
  62                 break;
  63         case PCI_IDE_CFG_REG:
  64                 if (value == CS5536_IDE_FLASH_SIGNATURE) {
  65                         _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
  66                         lo |= 0x01;
  67                         _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
  68                 } else
  69                         _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);
  70                 break;
  71         case PCI_IDE_DTC_REG:
  72                 _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
  73                 break;
  74         case PCI_IDE_CAST_REG:
  75                 _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
  76                 break;
  77         case PCI_IDE_ETC_REG:
  78                 _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
  79                 break;
  80         case PCI_IDE_PM_REG:
  81                 _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
  82                 break;
  83         default:
  84                 break;
  85         }
  86 }
  87
  88 u32 pci_ide_read_reg(int reg)
  89 {
  90         u32 conf_data = 0;
  91         u32 hi, lo;
  92
  93         switch (reg) {
  94         case PCI_VENDOR_ID:
  95                 conf_data =
  96                     CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID);
  97                 break;
  98         case PCI_COMMAND:
  99                 _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
 100                 if (lo & 0xfffffff0)
 101                         conf_data |= PCI_COMMAND_IO;
 102                 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
 103                 if ((lo & 0x30) == 0x30)
 104                         conf_data |= PCI_COMMAND_MASTER;
 105                 break;
 106         case PCI_STATUS:
 107                 conf_data |= PCI_STATUS_66MHZ;
 108                 conf_data |= PCI_STATUS_FAST_BACK;
 109                 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
 110                 if (lo & SB_PARE_ERR_FLAG)
 111                         conf_data |= PCI_STATUS_PARITY;
 112                 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
 113                 break;
 114         case PCI_CLASS_REVISION:
 115                 _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
 116                 conf_data = lo & 0x000000ff;
 117                 conf_data |= (CS5536_IDE_CLASS_CODE << 8);
 118                 break;
 119         case PCI_CACHE_LINE_SIZE:
 120                 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
 121                 hi &= 0x000000f8;
 122                 conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
 123                 break;
 124         case PCI_BAR4_REG:
 125                 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
 126                 if (lo & SOFT_BAR_IDE_FLAG) {
 127                         conf_data = CS5536_IDE_RANGE |
 128                             PCI_BASE_ADDRESS_SPACE_IO;
 129                         lo &= ~SOFT_BAR_IDE_FLAG;
 130                         _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
 131                 } else {
 132                         _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
 133                         conf_data = lo & 0xfffffff0;
 134                         conf_data |= 0x01;
 135                         conf_data &= ~0x02;
 136                 }
 137                 break;
 138         case PCI_CARDBUS_CIS:
 139                 conf_data = PCI_CARDBUS_CIS_POINTER;
 140                 break;
 141         case PCI_SUBSYSTEM_VENDOR_ID:
 142                 conf_data =
 143                     CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID);
 144                 break;
 145         case PCI_ROM_ADDRESS:
 146                 conf_data = PCI_EXPANSION_ROM_BAR;
 147                 break;
 148         case PCI_CAPABILITY_LIST:
 149                 conf_data = PCI_CAPLIST_POINTER;
 150                 break;
 151         case PCI_INTERRUPT_LINE:
 152                 conf_data =
 153                     CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
 154                 break;
 155         case PCI_IDE_CFG_REG:
 156                 _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
 157                 conf_data = lo;
 158                 break;
 159         case PCI_IDE_DTC_REG:
 160                 _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
 161                 conf_data = lo;
 162                 break;
 163         case PCI_IDE_CAST_REG:
 164                 _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
 165                 conf_data = lo;
 166                 break;
 167         case PCI_IDE_ETC_REG:
 168                 _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
 169                 conf_data = lo;
 170         case PCI_IDE_PM_REG:
 171                 _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
 172                 conf_data = lo;
 173                 break;
 174         default:
 175                 break;
 176         }
 177
 178         return conf_data;
 179 }