drivers/ide/pci/cs5535.c

   1 /*
   2  * linux/drivers/ide/pci/cs5535.c
   3  *
   4  * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
   5  *
   6  * History:
   7  * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
   8  * - Reworked tuneproc, set_drive, misc mods to prep for mainline
   9  * - Work was sponsored by CIS (M) Sdn Bhd.
  10  * Ported to Kernel 2.6.11 on June 26, 2005 by
  11  *   Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
  12  *   Alexander Kiausch <alex.kiausch@t-online.de>
  13  * Originally developed by AMD for 2.4/2.6
  14  *
  15  * Development of this chipset driver was funded
  16  * by the nice folks at National Semiconductor/AMD.
  17  *
  18  * This program is free software; you can redistribute it and/or modify it
  19  * under the terms of the GNU General Public License version 2 as published by
  20  * the Free Software Foundation.
  21  *
  22  * Documentation:
  23  *  CS5535 documentation available from AMD
  24  */
  25
  26 #include <linux/config.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include <linux/ide.h>
  30
  31 #include "ide-timing.h"
  32
  33 #define MSR_ATAC_BASE           0x51300000
  34 #define ATAC_GLD_MSR_CAP        (MSR_ATAC_BASE+0)
  35 #define ATAC_GLD_MSR_CONFIG     (MSR_ATAC_BASE+0x01)
  36 #define ATAC_GLD_MSR_SMI        (MSR_ATAC_BASE+0x02)
  37 #define ATAC_GLD_MSR_ERROR      (MSR_ATAC_BASE+0x03)
  38 #define ATAC_GLD_MSR_PM         (MSR_ATAC_BASE+0x04)
  39 #define ATAC_GLD_MSR_DIAG       (MSR_ATAC_BASE+0x05)
  40 #define ATAC_IO_BAR             (MSR_ATAC_BASE+0x08)
  41 #define ATAC_RESET              (MSR_ATAC_BASE+0x10)
  42 #define ATAC_CH0D0_PIO          (MSR_ATAC_BASE+0x20)
  43 #define ATAC_CH0D0_DMA          (MSR_ATAC_BASE+0x21)
  44 #define ATAC_CH0D1_PIO          (MSR_ATAC_BASE+0x22)
  45 #define ATAC_CH0D1_DMA          (MSR_ATAC_BASE+0x23)
  46 #define ATAC_PCI_ABRTERR        (MSR_ATAC_BASE+0x24)
  47 #define ATAC_BM0_CMD_PRIM       0x00
  48 #define ATAC_BM0_STS_PRIM       0x02
  49 #define ATAC_BM0_PRD            0x04
  50 #define CS5535_CABLE_DETECT     0x48
  51
  52 /* Format I PIO settings. We seperate out cmd and data for safer timings */
  53
  54 static unsigned int cs5535_pio_cmd_timings[5] =
  55 { 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
  56 static unsigned int cs5535_pio_dta_timings[5] =
  57 { 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
  58
  59 static unsigned int cs5535_mwdma_timings[3] =
  60 { 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
  61
  62 static unsigned int cs5535_udma_timings[5] =
  63 { 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
  64
  65 /* Macros to check if the register is the reset value -  reset value is an
  66    invalid timing and indicates the register has not been set previously */
  67
  68 #define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
  69 #define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
  70
  71 /****
  72  *      cs5535_set_speed         -     Configure the chipset to the new speed
  73  *      @drive: Drive to set up
  74  *      @speed: desired speed
  75  *
  76  *      cs5535_set_speed() configures the chipset to a new speed.
  77  */
  78 static void cs5535_set_speed(ide_drive_t *drive, u8 speed)
  79 {
  80
  81         u32 reg = 0, dummy;
  82         int unit = drive->select.b.unit;
  83
  84
  85         /* Set the PIO timings */
  86         if ((speed & XFER_MODE) == XFER_PIO) {
  87                 u8 pioa;
  88                 u8 piob;
  89                 u8 cmd;
  90
  91                 pioa = speed - XFER_PIO_0;
  92                 piob = ide_get_best_pio_mode(&(drive->hwif->drives[!unit]),
  93                                                 255, 4, NULL);
  94                 cmd = pioa < piob ? pioa : piob;
  95
  96                 /* Write the speed of the current drive */
  97                 reg = (cs5535_pio_cmd_timings[cmd] << 16) |
  98                         cs5535_pio_dta_timings[pioa];
  99                 wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
 100
 101                 /* And if nessesary - change the speed of the other drive */
 102                 rdmsr(unit ?  ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
 103
 104                 if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
 105                         cs5535_pio_cmd_timings[cmd]) {
 106                         reg &= 0x0000FFFF;
 107                         reg |= cs5535_pio_cmd_timings[cmd] << 16;
 108                         wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
 109                 }
 110
 111                 /* Set bit 31 of the DMA register for PIO format 1 timings */
 112                 rdmsr(unit ?  ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
 113                 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
 114                                         reg | 0x80000000UL, 0);
 115         } else {
 116                 rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
 117
 118                 reg &= 0x80000000UL;  /* Preserve the PIO format bit */
 119
 120                 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_7)
 121                         reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
 122                 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
 123                         reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
 124                 else
 125                         return;
 126
 127                 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
 128         }
 129 }
 130
 131 static u8 cs5535_ratemask(ide_drive_t *drive)
 132 {
 133         /* eighty93 will return 1 if it's 80core and capable of
 134         exceeding udma2, 0 otherwise. we need ratemask to set
 135         the max speed and if we can > udma2 then we return 2
 136         which selects speed_max as udma4 which is the 5535's max
 137         speed, and 1 selects udma2 which is the max for 40c */
 138         if (!eighty_ninty_three(drive))
 139                 return 1;
 140
 141         return 2;
 142 }
 143
 144
 145 /****
 146  *      cs5535_set_drive         -     Configure the drive to the new speed
 147  *      @drive: Drive to set up
 148  *      @speed: desired speed
 149  *
 150  *      cs5535_set_drive() configures the drive and the chipset to a
 151  *      new speed. It also can be called by upper layers.
 152  */
 153 static int cs5535_set_drive(ide_drive_t *drive, u8 speed)
 154 {
 155         speed = ide_rate_filter(cs5535_ratemask(drive), speed);
 156         ide_config_drive_speed(drive, speed);
 157         cs5535_set_speed(drive, speed);
 158
 159         return 0;
 160 }
 161
 162 /****
 163  *      cs5535_tuneproc    -       PIO setup
 164  *      @drive: drive to set up
 165  *      @pio: mode to use (255 for 'best possible')
 166  *
 167  *      A callback from the upper layers for PIO-only tuning.
 168  */
 169 static void cs5535_tuneproc(ide_drive_t *drive, u8 xferspeed)
 170 {
 171         u8 modes[] = {  XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3,
 172                         XFER_PIO_4 };
 173
 174         /* cs5535 max pio is pio 4, best_pio will check the blacklist.
 175         i think we don't need to rate_filter the incoming xferspeed
 176         since we know we're only going to choose pio */
 177         xferspeed = ide_get_best_pio_mode(drive, xferspeed, 4, NULL);
 178         ide_config_drive_speed(drive, modes[xferspeed]);
 179         cs5535_set_speed(drive, xferspeed);
 180 }
 181
 182 static int cs5535_config_drive_for_dma(ide_drive_t *drive)
 183 {
 184         u8 speed;
 185
 186         speed = ide_dma_speed(drive, cs5535_ratemask(drive));
 187
 188         /* If no DMA speed was available then let dma_check hit pio */
 189         if (!speed) {
 190                 return 0;
 191         }
 192
 193         cs5535_set_drive(drive, speed);
 194         return ide_dma_enable(drive);
 195 }
 196
 197 static int cs5535_dma_check(ide_drive_t *drive)
 198 {
 199         ide_hwif_t *hwif        = drive->hwif;
 200         struct hd_driveid *id   = drive->id;
 201         u8 speed;
 202
 203         drive->init_speed = 0;
 204
 205         if ((id->capability & 1) && drive->autodma) {
 206                 if (ide_use_dma(drive)) {
 207                         if (cs5535_config_drive_for_dma(drive))
 208                                 return hwif->ide_dma_on(drive);
 209                 }
 210
 211                 goto fast_ata_pio;
 212
 213         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 214 fast_ata_pio:
 215                 speed = ide_get_best_pio_mode(drive, 255, 4, NULL);
 216                 cs5535_set_drive(drive, speed);
 217                 return hwif->ide_dma_off_quietly(drive);
 218         }
 219         /* IORDY not supported */
 220         return 0;
 221 }
 222
 223 static u8 __devinit cs5535_cable_detect(struct pci_dev *dev)
 224 {
 225         u8 bit;
 226
 227         /* if a 80 wire cable was detected */
 228         pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
 229         return (bit & 1);
 230 }
 231
 232 /****
 233  *      init_hwif_cs5535        -       Initialize one ide cannel
 234  *      @hwif: Channel descriptor
 235  *
 236  *      This gets invoked by the IDE driver once for each channel. It
 237  *      performs channel-specific pre-initialization before drive probing.
 238  *
 239  */
 240 static void __devinit init_hwif_cs5535(ide_hwif_t *hwif)
 241 {
 242         int i;
 243
 244         hwif->autodma = 0;
 245
 246         hwif->tuneproc = &cs5535_tuneproc;
 247         hwif->speedproc = &cs5535_set_drive;
 248         hwif->ide_dma_check = &cs5535_dma_check;
 249
 250         hwif->atapi_dma = 1;
 251         hwif->ultra_mask = 0x1F;
 252         hwif->mwdma_mask = 0x07;
 253
 254
 255         hwif->udma_four = cs5535_cable_detect(hwif->pci_dev);
 256
 257         if (!noautodma)
 258                 hwif->autodma = 1;
 259
 260         /* just setting autotune and not worrying about bios timings */
 261         for (i = 0; i < 2; i++) {
 262                 hwif->drives[i].autotune = 1;
 263                 hwif->drives[i].autodma = hwif->autodma;
 264         }
 265 }
 266
 267 static ide_pci_device_t cs5535_chipset __devinitdata = {
 268         .name           = "CS5535",
 269         .init_hwif      = init_hwif_cs5535,
 270         .channels       = 1,
 271         .autodma        = AUTODMA,
 272         .bootable       = ON_BOARD,
 273 };
 274
 275 static int __devinit cs5535_init_one(struct pci_dev *dev,
 276                                         const struct pci_device_id *id)
 277 {
 278         return ide_setup_pci_device(dev, &cs5535_chipset);
 279 }
 280
 281 static struct pci_device_id cs5535_pci_tbl[] =
 282 {
 283         { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_IDE, PCI_ANY_ID,
 284                 PCI_ANY_ID, 0, 0, 0},
 285         { 0, },
 286 };
 287
 288 MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
 289
 290 static struct pci_driver driver = {
 291         .name       = "CS5535_IDE",
 292         .id_table   = cs5535_pci_tbl,
 293         .probe      = cs5535_init_one,
 294 };
 295
 296 static int __init cs5535_ide_init(void)
 297 {
 298         return ide_pci_register_driver(&driver);
 299 }
 300
 301 module_init(cs5535_ide_init);
 302
 303 MODULE_AUTHOR("AMD");
 304 MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
 305 MODULE_LICENSE("GPL");