2 * drivers/ata/sata_fsl.c
4 * Freescale 3.0Gbps SATA device driver
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
22 #include <scsi/scsi_host.h>
23 #include <scsi/scsi_cmnd.h>
24 #include <linux/libata.h>
26 #include <linux/of_platform.h>
28 /* Controller information */
30 SATA_FSL_QUEUE_DEPTH
= 16,
31 SATA_FSL_MAX_PRD
= 63,
32 SATA_FSL_MAX_PRD_USABLE
= SATA_FSL_MAX_PRD
- 1,
33 SATA_FSL_MAX_PRD_DIRECT
= 16, /* Direct PRDT entries */
35 SATA_FSL_HOST_FLAGS
= (ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
36 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
37 ATA_FLAG_NCQ
| ATA_FLAG_SKIP_D2H_BSY
),
39 SATA_FSL_MAX_CMDS
= SATA_FSL_QUEUE_DEPTH
,
40 SATA_FSL_CMD_HDR_SIZE
= 16, /* 4 DWORDS */
41 SATA_FSL_CMD_SLOT_SIZE
= (SATA_FSL_MAX_CMDS
* SATA_FSL_CMD_HDR_SIZE
),
44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
45 * chained indirect PRDEs upto a max count of 63.
46 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will
47 * be setup as an indirect descriptor, pointing to it's next
48 * (contigious) PRDE. Though chained indirect PRDE arrays are
49 * supported,it will be more efficient to use a direct PRDT and
50 * a single chain/link to indirect PRDE array/PRDT.
53 SATA_FSL_CMD_DESC_CFIS_SZ
= 32,
54 SATA_FSL_CMD_DESC_SFIS_SZ
= 32,
55 SATA_FSL_CMD_DESC_ACMD_SZ
= 16,
56 SATA_FSL_CMD_DESC_RSRVD
= 16,
58 SATA_FSL_CMD_DESC_SIZE
= (SATA_FSL_CMD_DESC_CFIS_SZ
+
59 SATA_FSL_CMD_DESC_SFIS_SZ
+
60 SATA_FSL_CMD_DESC_ACMD_SZ
+
61 SATA_FSL_CMD_DESC_RSRVD
+
62 SATA_FSL_MAX_PRD
* 16),
64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT
=
65 (SATA_FSL_CMD_DESC_CFIS_SZ
+
66 SATA_FSL_CMD_DESC_SFIS_SZ
+
67 SATA_FSL_CMD_DESC_ACMD_SZ
+
68 SATA_FSL_CMD_DESC_RSRVD
),
70 SATA_FSL_CMD_DESC_AR_SZ
= (SATA_FSL_CMD_DESC_SIZE
* SATA_FSL_MAX_CMDS
),
71 SATA_FSL_PORT_PRIV_DMA_SZ
= (SATA_FSL_CMD_SLOT_SIZE
+
72 SATA_FSL_CMD_DESC_AR_SZ
),
75 * MPC8315 has two SATA controllers, SATA1 & SATA2
76 * (one port per controller)
77 * MPC837x has 2/4 controllers, one port per controller
80 SATA_FSL_MAX_PORTS
= 1,
82 SATA_FSL_IRQ_FLAG
= IRQF_SHARED
,
86 * Host Controller command register set - per port
102 * Host Status Register (HStatus) bitdefs
105 GOING_OFFLINE
= (1 << 30),
106 BIST_ERR
= (1 << 29),
108 FATAL_ERR_HC_MASTER_ERR
= (1 << 18),
109 FATAL_ERR_PARITY_ERR_TX
= (1 << 17),
110 FATAL_ERR_PARITY_ERR_RX
= (1 << 16),
111 FATAL_ERR_DATA_UNDERRUN
= (1 << 13),
112 FATAL_ERR_DATA_OVERRUN
= (1 << 12),
113 FATAL_ERR_CRC_ERR_TX
= (1 << 11),
114 FATAL_ERR_CRC_ERR_RX
= (1 << 10),
115 FATAL_ERR_FIFO_OVRFL_TX
= (1 << 9),
116 FATAL_ERR_FIFO_OVRFL_RX
= (1 << 8),
118 FATAL_ERROR_DECODE
= FATAL_ERR_HC_MASTER_ERR
|
119 FATAL_ERR_PARITY_ERR_TX
|
120 FATAL_ERR_PARITY_ERR_RX
|
121 FATAL_ERR_DATA_UNDERRUN
|
122 FATAL_ERR_DATA_OVERRUN
|
123 FATAL_ERR_CRC_ERR_TX
|
124 FATAL_ERR_CRC_ERR_RX
|
125 FATAL_ERR_FIFO_OVRFL_TX
| FATAL_ERR_FIFO_OVRFL_RX
,
127 INT_ON_FATAL_ERR
= (1 << 5),
128 INT_ON_PHYRDY_CHG
= (1 << 4),
130 INT_ON_SIGNATURE_UPDATE
= (1 << 3),
131 INT_ON_SNOTIFY_UPDATE
= (1 << 2),
132 INT_ON_SINGL_DEVICE_ERR
= (1 << 1),
133 INT_ON_CMD_COMPLETE
= 1,
135 INT_ON_ERROR
= INT_ON_FATAL_ERR
|
136 INT_ON_PHYRDY_CHG
| INT_ON_SINGL_DEVICE_ERR
,
139 * Host Control Register (HControl) bitdefs
141 HCONTROL_ONLINE_PHY_RST
= (1 << 31),
142 HCONTROL_FORCE_OFFLINE
= (1 << 30),
143 HCONTROL_PARITY_PROT_MOD
= (1 << 14),
144 HCONTROL_DPATH_PARITY
= (1 << 12),
145 HCONTROL_SNOOP_ENABLE
= (1 << 10),
146 HCONTROL_PMP_ATTACHED
= (1 << 9),
147 HCONTROL_COPYOUT_STATFIS
= (1 << 8),
148 IE_ON_FATAL_ERR
= (1 << 5),
149 IE_ON_PHYRDY_CHG
= (1 << 4),
150 IE_ON_SIGNATURE_UPDATE
= (1 << 3),
151 IE_ON_SNOTIFY_UPDATE
= (1 << 2),
152 IE_ON_SINGL_DEVICE_ERR
= (1 << 1),
153 IE_ON_CMD_COMPLETE
= 1,
155 DEFAULT_PORT_IRQ_ENABLE_MASK
= IE_ON_FATAL_ERR
| IE_ON_PHYRDY_CHG
|
156 IE_ON_SIGNATURE_UPDATE
|
157 IE_ON_SINGL_DEVICE_ERR
| IE_ON_CMD_COMPLETE
,
159 EXT_INDIRECT_SEG_PRD_FLAG
= (1 << 31),
160 DATA_SNOOP_ENABLE
= (1 << 22),
164 * SATA Superset Registers
174 * Control Status Register Set
188 /* PHY (link-layer) configuration control */
190 PHY_BIST_ENABLE
= 0x01,
194 * Command Header Table entry, i.e, command slot
195 * 4 Dwords per command slot, command header size == 64 Dwords.
197 struct cmdhdr_tbl_entry
{
205 * Description information bitdefs
208 VENDOR_SPECIFIC_BIST
= (1 << 10),
209 CMD_DESC_SNOOP_ENABLE
= (1 << 9),
210 FPDMA_QUEUED_CMD
= (1 << 8),
213 ATAPI_CMD
= (1 << 5),
219 struct command_desc
{
224 u32 prdt
[SATA_FSL_MAX_PRD_DIRECT
* 4];
225 u32 prdt_indirect
[(SATA_FSL_MAX_PRD
- SATA_FSL_MAX_PRD_DIRECT
) * 4];
229 * Physical region table descriptor(PRD)
239 * ata_port private data
240 * This is our per-port instance data.
242 struct sata_fsl_port_priv
{
243 struct cmdhdr_tbl_entry
*cmdslot
;
244 dma_addr_t cmdslot_paddr
;
245 struct command_desc
*cmdentry
;
246 dma_addr_t cmdentry_paddr
;
249 * SATA FSL controller has a Status FIS which should contain the
250 * received D2H FIS & taskfile registers. This SFIS is present in
251 * the command descriptor, and to have a ready reference to it,
252 * we are caching it here, quite similar to what is done in H/W on
253 * AHCI compliant devices by copying taskfile fields to a 32-bit
257 struct ata_taskfile tf
;
261 * ata_port->host_set private data
263 struct sata_fsl_host_priv
{
264 void __iomem
*hcr_base
;
265 void __iomem
*ssr_base
;
266 void __iomem
*csr_base
;
269 static inline unsigned int sata_fsl_tag(unsigned int tag
,
270 void __iomem
* hcr_base
)
272 /* We let libATA core do actual (queue) tag allocation */
274 /* all non NCQ/queued commands should have tag#0 */
275 if (ata_tag_internal(tag
)) {
276 DPRINTK("mapping internal cmds to tag#0\n");
280 if (unlikely(tag
>= SATA_FSL_QUEUE_DEPTH
)) {
281 DPRINTK("tag %d invalid : out of range\n", tag
);
285 if (unlikely((ioread32(hcr_base
+ CQ
)) & (1 << tag
))) {
286 DPRINTK("tag %d invalid : in use!!\n", tag
);
293 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv
*pp
,
294 unsigned int tag
, u32 desc_info
,
295 u32 data_xfer_len
, u8 num_prde
,
298 dma_addr_t cmd_descriptor_address
;
300 cmd_descriptor_address
= pp
->cmdentry_paddr
+
301 tag
* SATA_FSL_CMD_DESC_SIZE
;
303 /* NOTE: both data_xfer_len & fis_len are Dword counts */
305 pp
->cmdslot
[tag
].cda
= cpu_to_le32(cmd_descriptor_address
);
306 pp
->cmdslot
[tag
].prde_fis_len
=
307 cpu_to_le32((num_prde
<< 16) | (fis_len
<< 2));
308 pp
->cmdslot
[tag
].ttl
= cpu_to_le32(data_xfer_len
& ~0x03);
309 pp
->cmdslot
[tag
].desc_info
= cpu_to_le32((desc_info
| (tag
& 0x1F)));
311 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
312 pp
->cmdslot
[tag
].cda
,
313 pp
->cmdslot
[tag
].prde_fis_len
,
314 pp
->cmdslot
[tag
].ttl
, pp
->cmdslot
[tag
].desc_info
);
318 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_desc
,
319 u32
* ttl
, dma_addr_t cmd_desc_paddr
)
321 struct scatterlist
*sg
;
322 unsigned int num_prde
= 0;
326 * NOTE : direct & indirect prdt's are contigiously allocated
328 struct prde
*prd
= (struct prde
*)&((struct command_desc
*)
331 struct prde
*prd_ptr_to_indirect_ext
= NULL
;
332 unsigned indirect_ext_segment_sz
= 0;
333 dma_addr_t indirect_ext_segment_paddr
;
335 VPRINTK("SATA FSL : cd = 0x%x, prd = 0x%x\n", cmd_desc
, prd
);
337 indirect_ext_segment_paddr
= cmd_desc_paddr
+
338 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT
+ SATA_FSL_MAX_PRD_DIRECT
* 16;
340 ata_for_each_sg(sg
, qc
) {
341 dma_addr_t sg_addr
= sg_dma_address(sg
);
342 u32 sg_len
= sg_dma_len(sg
);
344 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n",
347 /* warn if each s/g element is not dword aligned */
349 ata_port_printk(qc
->ap
, KERN_ERR
,
350 "s/g addr unaligned : 0x%x\n", sg_addr
);
352 ata_port_printk(qc
->ap
, KERN_ERR
,
353 "s/g len unaligned : 0x%x\n", sg_len
);
355 if ((num_prde
== (SATA_FSL_MAX_PRD_DIRECT
- 1)) &&
356 !ata_sg_is_last(sg
, qc
)) {
357 VPRINTK("setting indirect prde\n");
358 prd_ptr_to_indirect_ext
= prd
;
359 prd
->dba
= cpu_to_le32(indirect_ext_segment_paddr
);
360 indirect_ext_segment_sz
= 0;
365 ttl_dwords
+= sg_len
;
366 prd
->dba
= cpu_to_le32(sg_addr
);
368 cpu_to_le32(DATA_SNOOP_ENABLE
| (sg_len
& ~0x03));
370 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
371 ttl_dwords
, prd
->dba
, prd
->ddc_and_ext
);
375 if (prd_ptr_to_indirect_ext
)
376 indirect_ext_segment_sz
+= sg_len
;
379 if (prd_ptr_to_indirect_ext
) {
380 /* set indirect extension flag along with indirect ext. size */
381 prd_ptr_to_indirect_ext
->ddc_and_ext
=
382 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG
|
384 (indirect_ext_segment_sz
& ~0x03)));
391 static void sata_fsl_qc_prep(struct ata_queued_cmd
*qc
)
393 struct ata_port
*ap
= qc
->ap
;
394 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
395 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
396 void __iomem
*hcr_base
= host_priv
->hcr_base
;
397 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
398 struct command_desc
*cd
;
399 u32 desc_info
= CMD_DESC_SNOOP_ENABLE
;
404 cd
= (struct command_desc
*)pp
->cmdentry
+ tag
;
405 cd_paddr
= pp
->cmdentry_paddr
+ tag
* SATA_FSL_CMD_DESC_SIZE
;
407 ata_tf_to_fis(&qc
->tf
, 0, 1, (u8
*) & cd
->cfis
);
409 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
410 cd
->cfis
[0], cd
->cfis
[1], cd
->cfis
[2]);
412 if (qc
->tf
.protocol
== ATA_PROT_NCQ
) {
413 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
414 cd
->cfis
[3], cd
->cfis
[11]);
417 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
418 if (is_atapi_taskfile(&qc
->tf
)) {
419 desc_info
|= ATAPI_CMD
;
420 memset((void *)&cd
->acmd
, 0, 32);
421 memcpy((void *)&cd
->acmd
, qc
->cdb
, qc
->dev
->cdb_len
);
424 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
425 num_prde
= sata_fsl_fill_sg(qc
, (void *)cd
,
426 &ttl_dwords
, cd_paddr
);
428 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
429 desc_info
|= FPDMA_QUEUED_CMD
;
431 sata_fsl_setup_cmd_hdr_entry(pp
, tag
, desc_info
, ttl_dwords
,
434 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
435 desc_info
, ttl_dwords
, num_prde
);
438 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd
*qc
)
440 struct ata_port
*ap
= qc
->ap
;
441 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
442 void __iomem
*hcr_base
= host_priv
->hcr_base
;
443 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
445 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
446 ioread32(CQ
+ hcr_base
),
447 ioread32(CA
+ hcr_base
),
448 ioread32(CE
+ hcr_base
), ioread32(CC
+ hcr_base
));
450 /* Simply queue command to the controller/device */
451 iowrite32(1 << tag
, CQ
+ hcr_base
);
453 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
454 tag
, ioread32(CQ
+ hcr_base
), ioread32(CA
+ hcr_base
));
456 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
457 ioread32(CE
+ hcr_base
),
458 ioread32(DE
+ hcr_base
),
459 ioread32(CC
+ hcr_base
), ioread32(COMMANDSTAT
+ csr_base
));
464 static int sata_fsl_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
,
467 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
468 void __iomem
*ssr_base
= host_priv
->ssr_base
;
488 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg
);
490 iowrite32(val
, (void __iomem
*)ssr_base
+ (sc_reg
* 4));
494 static int sata_fsl_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
,
497 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
498 void __iomem
*ssr_base
= host_priv
->ssr_base
;
518 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg
);
520 *val
= ioread32((void __iomem
*)ssr_base
+ (sc_reg
* 4));
524 static void sata_fsl_freeze(struct ata_port
*ap
)
526 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
527 void __iomem
*hcr_base
= host_priv
->hcr_base
;
530 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
531 ioread32(CQ
+ hcr_base
),
532 ioread32(CA
+ hcr_base
),
533 ioread32(CE
+ hcr_base
), ioread32(DE
+ hcr_base
));
534 VPRINTK("CmdStat = 0x%x\n", ioread32(csr_base
+ COMMANDSTAT
));
536 /* disable interrupts on the controller/port */
537 temp
= ioread32(hcr_base
+ HCONTROL
);
538 iowrite32((temp
& ~0x3F), hcr_base
+ HCONTROL
);
540 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
541 ioread32(hcr_base
+ HCONTROL
), ioread32(hcr_base
+ HSTATUS
));
544 static void sata_fsl_thaw(struct ata_port
*ap
)
546 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
547 void __iomem
*hcr_base
= host_priv
->hcr_base
;
550 /* ack. any pending IRQs for this controller/port */
551 temp
= ioread32(hcr_base
+ HSTATUS
);
553 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp
& 0x3F));
556 iowrite32((temp
& 0x3F), hcr_base
+ HSTATUS
);
558 /* enable interrupts on the controller/port */
559 temp
= ioread32(hcr_base
+ HCONTROL
);
560 iowrite32((temp
| DEFAULT_PORT_IRQ_ENABLE_MASK
), hcr_base
+ HCONTROL
);
562 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
563 ioread32(hcr_base
+ HCONTROL
), ioread32(hcr_base
+ HSTATUS
));
567 * NOTE : 1st D2H FIS from device does not update sfis in command descriptor.
569 static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd
573 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
575 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
576 void __iomem
*hcr_base
= host_priv
->hcr_base
;
577 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
578 struct command_desc
*cd
;
580 cd
= pp
->cmdentry
+ tag
;
582 memcpy(fis
, &cd
->sfis
, 6 * 4); /* should we use memcpy_from_io() */
583 ata_tf_from_fis(fis
, &pp
->tf
);
586 static u8
sata_fsl_check_status(struct ata_port
*ap
)
588 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
590 return pp
->tf
.command
;
593 static void sata_fsl_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
595 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
600 static int sata_fsl_port_start(struct ata_port
*ap
)
602 struct device
*dev
= ap
->host
->dev
;
603 struct sata_fsl_port_priv
*pp
;
607 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
608 void __iomem
*hcr_base
= host_priv
->hcr_base
;
611 pp
= kzalloc(sizeof(*pp
), GFP_KERNEL
);
616 * allocate per command dma alignment pad buffer, which is used
617 * internally by libATA to ensure that all transfers ending on
618 * unaligned boundaries are padded, to align on Dword boundaries
620 retval
= ata_pad_alloc(ap
, dev
);
626 mem
= dma_alloc_coherent(dev
, SATA_FSL_PORT_PRIV_DMA_SZ
, &mem_dma
,
629 ata_pad_free(ap
, dev
);
633 memset(mem
, 0, SATA_FSL_PORT_PRIV_DMA_SZ
);
636 pp
->cmdslot_paddr
= mem_dma
;
638 mem
+= SATA_FSL_CMD_SLOT_SIZE
;
639 mem_dma
+= SATA_FSL_CMD_SLOT_SIZE
;
642 pp
->cmdentry_paddr
= mem_dma
;
644 ap
->private_data
= pp
;
646 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
647 pp
->cmdslot_paddr
, pp
->cmdentry_paddr
);
649 /* Now, update the CHBA register in host controller cmd register set */
650 iowrite32(pp
->cmdslot_paddr
& 0xffffffff, hcr_base
+ CHBA
);
653 * Now, we can bring the controller on-line & also initiate
654 * the COMINIT sequence, we simply return here and the boot-probing
655 * & device discovery process is re-initiated by libATA using a
656 * Softreset EH (dummy) session. Hence, boot probing and device
657 * discovey will be part of sata_fsl_softreset() callback.
660 temp
= ioread32(hcr_base
+ HCONTROL
);
661 iowrite32((temp
| HCONTROL_ONLINE_PHY_RST
), hcr_base
+ HCONTROL
);
663 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
664 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
665 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base
+ CHBA
));
668 * Workaround for 8315DS board 3gbps link-up issue,
669 * currently limit SATA port to GEN1 speed
671 sata_fsl_scr_read(ap
, SCR_CONTROL
, &temp
);
674 sata_fsl_scr_write(ap
, SCR_CONTROL
, temp
);
676 sata_fsl_scr_read(ap
, SCR_CONTROL
, &temp
);
677 dev_printk(KERN_WARNING
, dev
, "scr_control, speed limited to %x\n",
683 static void sata_fsl_port_stop(struct ata_port
*ap
)
685 struct device
*dev
= ap
->host
->dev
;
686 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
687 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
688 void __iomem
*hcr_base
= host_priv
->hcr_base
;
692 * Force host controller to go off-line, aborting current operations
694 temp
= ioread32(hcr_base
+ HCONTROL
);
695 temp
&= ~HCONTROL_ONLINE_PHY_RST
;
696 temp
|= HCONTROL_FORCE_OFFLINE
;
697 iowrite32(temp
, hcr_base
+ HCONTROL
);
699 /* Poll for controller to go offline - should happen immediately */
700 ata_wait_register(hcr_base
+ HSTATUS
, ONLINE
, ONLINE
, 1, 1);
702 ap
->private_data
= NULL
;
703 dma_free_coherent(dev
, SATA_FSL_PORT_PRIV_DMA_SZ
,
704 pp
->cmdslot
, pp
->cmdslot_paddr
);
706 ata_pad_free(ap
, dev
);
710 static unsigned int sata_fsl_dev_classify(struct ata_port
*ap
)
712 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
713 void __iomem
*hcr_base
= host_priv
->hcr_base
;
714 struct ata_taskfile tf
;
717 temp
= ioread32(hcr_base
+ SIGNATURE
);
719 VPRINTK("raw sig = 0x%x\n", temp
);
720 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
721 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
723 tf
.lbah
= (temp
>> 24) & 0xff;
724 tf
.lbam
= (temp
>> 16) & 0xff;
725 tf
.lbal
= (temp
>> 8) & 0xff;
726 tf
.nsect
= temp
& 0xff;
728 return ata_dev_classify(&tf
);
731 static int sata_fsl_softreset(struct ata_port
*ap
, unsigned int *class,
732 unsigned long deadline
)
734 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
735 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
736 void __iomem
*hcr_base
= host_priv
->hcr_base
;
738 struct ata_taskfile tf
;
742 struct ata_queued_cmd qc
;
744 dma_addr_t dma_address
;
745 struct scatterlist
*sg
;
746 unsigned long start_jiffies
;
748 DPRINTK("in xx_softreset\n");
752 * Force host controller to go off-line, aborting current operations
754 temp
= ioread32(hcr_base
+ HCONTROL
);
755 temp
&= ~HCONTROL_ONLINE_PHY_RST
;
756 iowrite32(temp
, hcr_base
+ HCONTROL
);
758 /* Poll for controller to go offline */
759 temp
= ata_wait_register(hcr_base
+ HSTATUS
, ONLINE
, ONLINE
, 1, 500);
762 ata_port_printk(ap
, KERN_ERR
,
763 "Softreset failed, not off-lined %d\n", i
);
766 * Try to offline controller atleast twice
772 goto try_offline_again
;
775 DPRINTK("softreset, controller off-lined\n");
776 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
777 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
780 * PHY reset should remain asserted for atleast 1ms
785 * Now, bring the host controller online again, this can take time
786 * as PHY reset and communication establishment, 1st D2H FIS and
787 * device signature update is done, on safe side assume 500ms
788 * NOTE : Host online status may be indicated immediately!!
791 temp
= ioread32(hcr_base
+ HCONTROL
);
792 temp
|= (HCONTROL_ONLINE_PHY_RST
| HCONTROL_SNOOP_ENABLE
);
793 iowrite32(temp
, hcr_base
+ HCONTROL
);
795 temp
= ata_wait_register(hcr_base
+ HSTATUS
, ONLINE
, 0, 1, 500);
797 if (!(temp
& ONLINE
)) {
798 ata_port_printk(ap
, KERN_ERR
,
799 "Softreset failed, not on-lined\n");
803 DPRINTK("softreset, controller off-lined & on-lined\n");
804 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
805 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
808 * First, wait for the PHYRDY change to occur before waiting for
809 * the signature, and also verify if SStatus indicates device
813 temp
= ata_wait_register(hcr_base
+ HSTATUS
, 0xFF, 0, 1, 500);
814 if ((!(temp
& 0x10)) || ata_port_offline(ap
)) {
815 ata_port_printk(ap
, KERN_WARNING
,
816 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
817 ioread32(hcr_base
+ HSTATUS
));
822 * Wait for the first D2H from device,i.e,signature update notification
824 start_jiffies
= jiffies
;
825 temp
= ata_wait_register(hcr_base
+ HSTATUS
, 0xFF, 0x10,
826 500, jiffies_to_msecs(deadline
- start_jiffies
));
828 if ((temp
& 0xFF) != 0x18) {
829 ata_port_printk(ap
, KERN_WARNING
, "No Signature Update\n");
832 ata_port_printk(ap
, KERN_INFO
,
833 "Signature Update detected @ %d msecs\n",
834 jiffies_to_msecs(jiffies
- start_jiffies
));
838 * Send a device reset (SRST) explicitly on command slot #0
839 * Check : will the command queue (reg) be cleared during offlining ??
840 * Also we will be online only if Phy commn. has been established
841 * and device presence has been detected, therefore if we have
842 * reached here, we can send a command to the target device
846 goto skip_srst_do_ncq_error_handling
;
848 DPRINTK("Sending SRST/device reset\n");
850 ata_tf_init(ap
->device
, &tf
);
851 cfis
= (u8
*) & pp
->cmdentry
->cfis
;
853 /* device reset/SRST is a control register update FIS, uses tag0 */
854 sata_fsl_setup_cmd_hdr_entry(pp
, 0,
855 SRST_CMD
| CMD_DESC_SNOOP_ENABLE
, 0, 0, 5);
857 tf
.ctl
|= ATA_SRST
; /* setup SRST bit in taskfile control reg */
858 ata_tf_to_fis(&tf
, 0, 0, cfis
);
860 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
861 cfis
[0], cfis
[1], cfis
[2], cfis
[3]);
864 * Queue SRST command to the controller/device, ensure that no
865 * other commands are active on the controller/device
868 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
869 ioread32(CQ
+ hcr_base
),
870 ioread32(CA
+ hcr_base
), ioread32(CC
+ hcr_base
));
872 iowrite32(0xFFFF, CC
+ hcr_base
);
873 iowrite32(1, CQ
+ hcr_base
);
875 temp
= ata_wait_register(CQ
+ hcr_base
, 0x1, 0x1, 1, 5000);
877 ata_port_printk(ap
, KERN_WARNING
, "ATA_SRST issue failed\n");
879 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
880 ioread32(CQ
+ hcr_base
),
881 ioread32(CA
+ hcr_base
), ioread32(CC
+ hcr_base
));
883 sata_fsl_scr_read(ap
, SCR_ERROR
, &Serror
);
885 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
886 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
887 DPRINTK("Serror = 0x%x\n", Serror
);
894 * SATA device enters reset state after receving a Control register
895 * FIS with SRST bit asserted and it awaits another H2D Control reg.
896 * FIS with SRST bit cleared, then the device does internal diags &
897 * initialization, followed by indicating it's initialization status
898 * using ATA signature D2H register FIS to the host controller.
901 sata_fsl_setup_cmd_hdr_entry(pp
, 0, CMD_DESC_SNOOP_ENABLE
, 0, 0, 5);
903 tf
.ctl
&= ~ATA_SRST
; /* 2nd H2D Ctl. register FIS */
904 ata_tf_to_fis(&tf
, 0, 0, cfis
);
906 iowrite32(1, CQ
+ hcr_base
);
907 msleep(150); /* ?? */
910 * The above command would have signalled an interrupt on command
911 * complete, which needs special handling, by clearing the Nth
912 * command bit of the CCreg
914 iowrite32(0x01, CC
+ hcr_base
); /* We know it will be cmd#0 always */
915 goto check_device_signature
;
917 skip_srst_do_ncq_error_handling
:
919 VPRINTK("Sending read log ext(10h) command\n");
921 memset(&qc
, 0, sizeof(struct ata_queued_cmd
));
922 ata_tf_init(ap
->device
, &tf
);
924 tf
.command
= ATA_CMD_READ_LOG_EXT
;
925 tf
.lbal
= ATA_LOG_SATA_NCQ
;
928 tf
.flags
|= ATA_TFLAG_ISADDR
| ATA_TFLAG_LBA48
| ATA_TFLAG_DEVICE
;
929 tf
.protocol
= ATA_PROT_PIO
;
931 qc
.tag
= ATA_TAG_INTERNAL
;
937 qc
.flags
|= ATA_QCFLAG_RESULT_TF
;
938 qc
.dma_dir
= DMA_FROM_DEVICE
;
940 buf
= ap
->sector_buf
;
941 ata_sg_init_one(&qc
, buf
, 1 * ATA_SECT_SIZE
);
944 * Need to DMA-map the memory buffer associated with the command
948 dma_address
= dma_map_single(ap
->dev
, qc
.buf_virt
,
949 sg
->length
, DMA_FROM_DEVICE
);
951 sg_dma_address(sg
) = dma_address
;
952 sg_dma_len(sg
) = sg
->length
;
954 VPRINTK("EH, addr = 0x%x, len = 0x%x\n", dma_address
, sg
->length
);
956 sata_fsl_qc_prep(&qc
);
957 sata_fsl_qc_issue(&qc
);
959 temp
= ata_wait_register(CQ
+ hcr_base
, 0x1, 0x1, 1, 5000);
961 VPRINTK("READ_LOG_EXT_10H issue failed\n");
963 VPRINTK("READ_LOG@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
964 ioread32(CQ
+ hcr_base
),
965 ioread32(CA
+ hcr_base
), ioread32(CC
+ hcr_base
));
967 sata_fsl_scr_read(ap
, SCR_ERROR
, &Serror
);
969 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
970 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
971 VPRINTK("Serror = 0x%x\n", Serror
);
975 iowrite32(0x01, CC
+ hcr_base
); /* We know it will be cmd#0 always */
977 check_device_signature
:
979 DPRINTK("SATA FSL : Now checking device signature\n");
981 *class = ATA_DEV_NONE
;
983 /* Verify if SStatus indicates device presence */
984 if (ata_port_online(ap
)) {
986 * if we are here, device presence has been detected,
987 * 1st D2H FIS would have been received, but sfis in
988 * command desc. is not updated, but signature register
989 * would have been updated
992 *class = sata_fsl_dev_classify(ap
);
994 DPRINTK("class = %d\n", *class);
995 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base
+ CC
));
996 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base
+ CE
));
1005 static int sata_fsl_hardreset(struct ata_port
*ap
, unsigned int *class,
1006 unsigned long deadline
)
1010 retval
= sata_std_hardreset(ap
, class, deadline
);
1012 DPRINTK("SATA FSL : in xx_hardreset, retval = 0x%d\n", retval
);
1017 static void sata_fsl_error_handler(struct ata_port
*ap
)
1020 DPRINTK("in xx_error_handler\n");
1022 /* perform recovery */
1023 ata_do_eh(ap
, ata_std_prereset
, sata_fsl_softreset
, sata_fsl_hardreset
,
1027 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd
*qc
)
1029 if (qc
->flags
& ATA_QCFLAG_FAILED
)
1030 qc
->err_mask
|= AC_ERR_OTHER
;
1033 /* make DMA engine forget about the failed command */
1038 static void sata_fsl_irq_clear(struct ata_port
*ap
)
1043 static void sata_fsl_error_intr(struct ata_port
*ap
)
1045 struct ata_eh_info
*ehi
= &ap
->eh_info
;
1046 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
1047 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1048 u32 hstatus
, dereg
, cereg
= 0, SError
= 0;
1049 unsigned int err_mask
= 0, action
= 0;
1050 struct ata_queued_cmd
*qc
;
1053 hstatus
= ioread32(hcr_base
+ HSTATUS
);
1054 cereg
= ioread32(hcr_base
+ CE
);
1056 ata_ehi_clear_desc(ehi
);
1059 * Handle & Clear SError
1062 sata_fsl_scr_read(ap
, SCR_ERROR
, &SError
);
1063 if (unlikely(SError
& 0xFFFF0000)) {
1064 sata_fsl_scr_write(ap
, SCR_ERROR
, SError
);
1065 err_mask
|= AC_ERR_ATA_BUS
;
1068 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1069 hstatus
, cereg
, ioread32(hcr_base
+ DE
), SError
);
1071 /* handle single device errors */
1074 * clear the command error, also clears queue to the device
1075 * in error, and we can (re)issue commands to this device.
1076 * When a device is in error all commands queued into the
1077 * host controller and at the device are considered aborted
1078 * and the queue for that device is stopped. Now, after
1079 * clearing the device error, we can issue commands to the
1080 * device to interrogate it to find the source of the error.
1082 dereg
= ioread32(hcr_base
+ DE
);
1083 iowrite32(dereg
, hcr_base
+ DE
);
1084 iowrite32(cereg
, hcr_base
+ CE
);
1086 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1087 ioread32(hcr_base
+ CE
), ioread32(hcr_base
+ DE
));
1089 * We should consider this as non fatal error, and TF must
1090 * be updated as done below.
1093 err_mask
|= AC_ERR_DEV
;
1096 /* handle fatal errors */
1097 if (hstatus
& FATAL_ERROR_DECODE
) {
1098 err_mask
|= AC_ERR_ATA_BUS
;
1099 action
|= ATA_EH_SOFTRESET
;
1100 /* how will fatal error interrupts be completed ?? */
1104 /* Handle PHYRDY change notification */
1105 if (hstatus
& INT_ON_PHYRDY_CHG
) {
1106 DPRINTK("SATA FSL: PHYRDY change indication\n");
1108 /* Setup a soft-reset EH action */
1109 ata_ehi_hotplugged(ehi
);
1113 /* record error info */
1114 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
1117 sata_fsl_cache_taskfile_from_d2h_fis(qc
, qc
->ap
);
1118 qc
->err_mask
|= err_mask
;
1120 ehi
->err_mask
|= err_mask
;
1122 ehi
->action
|= action
;
1123 ehi
->serror
|= SError
;
1125 /* freeze or abort */
1127 ata_port_freeze(ap
);
1132 static void sata_fsl_qc_complete(struct ata_queued_cmd
*qc
)
1134 if (qc
->flags
& ATA_QCFLAG_RESULT_TF
) {
1135 DPRINTK("xx_qc_complete called\n");
1136 sata_fsl_cache_taskfile_from_d2h_fis(qc
, qc
->ap
);
1140 static void sata_fsl_host_intr(struct ata_port
*ap
)
1142 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
1143 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1144 u32 hstatus
, qc_active
= 0;
1145 struct ata_queued_cmd
*qc
;
1148 hstatus
= ioread32(hcr_base
+ HSTATUS
);
1150 sata_fsl_scr_read(ap
, SCR_ERROR
, &SError
);
1152 if (unlikely(SError
& 0xFFFF0000)) {
1153 DPRINTK("serror @host_intr : 0x%x\n", SError
);
1154 sata_fsl_error_intr(ap
);
1158 if (unlikely(hstatus
& INT_ON_ERROR
)) {
1159 DPRINTK("error interrupt!!\n");
1160 sata_fsl_error_intr(ap
);
1164 if (ap
->sactive
) { /* only true for NCQ commands */
1166 /* Read command completed register */
1167 qc_active
= ioread32(hcr_base
+ CC
);
1168 /* clear CC bit, this will also complete the interrupt */
1169 iowrite32(qc_active
, hcr_base
+ CC
);
1171 DPRINTK("Status of all queues :\n");
1172 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1173 qc_active
, ioread32(hcr_base
+ CA
),
1174 ioread32(hcr_base
+ CE
));
1176 for (i
= 0; i
< SATA_FSL_QUEUE_DEPTH
; i
++) {
1177 if (qc_active
& (1 << i
)) {
1178 qc
= ata_qc_from_tag(ap
, i
);
1180 sata_fsl_qc_complete(qc
);
1181 ata_qc_complete(qc
);
1184 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1185 i
, ioread32(hcr_base
+ CC
),
1186 ioread32(hcr_base
+ CA
));
1191 } else if (ap
->qc_active
) {
1192 iowrite32(1, hcr_base
+ CC
);
1193 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
1195 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n",
1196 ap
->active_tag
, ioread32(hcr_base
+ CC
));
1199 sata_fsl_qc_complete(qc
);
1200 ata_qc_complete(qc
);
1203 /* Spurious Interrupt!! */
1204 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1205 ioread32(hcr_base
+ CC
));
1210 static irqreturn_t
sata_fsl_interrupt(int irq
, void *dev_instance
)
1212 struct ata_host
*host
= dev_instance
;
1213 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1214 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1215 u32 interrupt_enables
;
1216 unsigned handled
= 0;
1217 struct ata_port
*ap
;
1219 /* ack. any pending IRQs for this controller/port */
1220 interrupt_enables
= ioread32(hcr_base
+ HSTATUS
);
1221 interrupt_enables
&= 0x3F;
1223 DPRINTK("interrupt status 0x%x\n", interrupt_enables
);
1225 if (!interrupt_enables
)
1228 spin_lock(&host
->lock
);
1230 /* Assuming one port per host controller */
1232 ap
= host
->ports
[0];
1234 sata_fsl_host_intr(ap
);
1236 dev_printk(KERN_WARNING
, host
->dev
,
1237 "interrupt on disabled port 0\n");
1240 iowrite32(interrupt_enables
, hcr_base
+ HSTATUS
);
1243 spin_unlock(&host
->lock
);
1245 return IRQ_RETVAL(handled
);
1249 * Multiple ports are represented by multiple SATA controllers with
1250 * one port per controller
1252 static int sata_fsl_init_controller(struct ata_host
*host
)
1254 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1255 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1259 * NOTE : We cannot bring the controller online before setting
1260 * the CHBA, hence main controller initialization is done as
1261 * part of the port_start() callback
1264 /* ack. any pending IRQs for this controller/port */
1265 temp
= ioread32(hcr_base
+ HSTATUS
);
1267 iowrite32((temp
& 0x3F), hcr_base
+ HSTATUS
);
1269 /* Keep interrupts disabled on the controller */
1270 temp
= ioread32(hcr_base
+ HCONTROL
);
1271 iowrite32((temp
& ~0x3F), hcr_base
+ HCONTROL
);
1273 /* Disable interrupt coalescing control(icc), for the moment */
1274 DPRINTK("icc = 0x%x\n", ioread32(hcr_base
+ ICC
));
1275 iowrite32(0x01000000, hcr_base
+ ICC
);
1277 /* clear error registers, SError is cleared by libATA */
1278 iowrite32(0x00000FFFF, hcr_base
+ CE
);
1279 iowrite32(0x00000FFFF, hcr_base
+ DE
);
1281 /* initially assuming no Port multiplier, set CQPMP to 0 */
1282 iowrite32(0x0, hcr_base
+ CQPMP
);
1285 * host controller will be brought on-line, during xx_port_start()
1286 * callback, that should also initiate the OOB, COMINIT sequence
1289 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
1290 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
1296 * scsi mid-layer and libata interface structures
1298 static struct scsi_host_template sata_fsl_sht
= {
1299 .module
= THIS_MODULE
,
1301 .ioctl
= ata_scsi_ioctl
,
1302 .queuecommand
= ata_scsi_queuecmd
,
1303 .change_queue_depth
= ata_scsi_change_queue_depth
,
1304 .can_queue
= SATA_FSL_QUEUE_DEPTH
,
1305 .this_id
= ATA_SHT_THIS_ID
,
1306 .sg_tablesize
= SATA_FSL_MAX_PRD_USABLE
,
1307 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
1308 .emulated
= ATA_SHT_EMULATED
,
1309 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
1310 .proc_name
= "sata_fsl",
1311 .dma_boundary
= ATA_DMA_BOUNDARY
,
1312 .slave_configure
= ata_scsi_slave_config
,
1313 .slave_destroy
= ata_scsi_slave_destroy
,
1314 .bios_param
= ata_std_bios_param
,
1316 .suspend
= ata_scsi_device_suspend
,
1317 .resume
= ata_scsi_device_resume
,
1321 static const struct ata_port_operations sata_fsl_ops
= {
1322 .port_disable
= ata_port_disable
,
1324 .check_status
= sata_fsl_check_status
,
1325 .check_altstatus
= sata_fsl_check_status
,
1326 .dev_select
= ata_noop_dev_select
,
1328 .tf_read
= sata_fsl_tf_read
,
1330 .qc_prep
= sata_fsl_qc_prep
,
1331 .qc_issue
= sata_fsl_qc_issue
,
1332 .irq_clear
= sata_fsl_irq_clear
,
1333 .irq_on
= ata_dummy_irq_on
,
1334 .irq_ack
= ata_dummy_irq_ack
,
1336 .scr_read
= sata_fsl_scr_read
,
1337 .scr_write
= sata_fsl_scr_write
,
1339 .freeze
= sata_fsl_freeze
,
1340 .thaw
= sata_fsl_thaw
,
1341 .error_handler
= sata_fsl_error_handler
,
1342 .post_internal_cmd
= sata_fsl_post_internal_cmd
,
1344 .port_start
= sata_fsl_port_start
,
1345 .port_stop
= sata_fsl_port_stop
,
1348 static const struct ata_port_info sata_fsl_port_info
[] = {
1350 .flags
= SATA_FSL_HOST_FLAGS
,
1351 .pio_mask
= 0x1f, /* pio 0-4 */
1352 .udma_mask
= 0x7f, /* udma 0-6 */
1353 .port_ops
= &sata_fsl_ops
,
1357 static int sata_fsl_probe(struct of_device
*ofdev
,
1358 const struct of_device_id
*match
)
1361 void __iomem
*hcr_base
= NULL
;
1362 void __iomem
*ssr_base
= NULL
;
1363 void __iomem
*csr_base
= NULL
;
1364 struct sata_fsl_host_priv
*host_priv
= NULL
;
1367 struct ata_host
*host
;
1369 struct ata_port_info pi
= sata_fsl_port_info
[0];
1370 const struct ata_port_info
*ppi
[] = { &pi
, NULL
};
1372 dev_printk(KERN_INFO
, &ofdev
->dev
,
1373 "Sata FSL Platform/CSB Driver init\n");
1375 r
= kmalloc(sizeof(struct resource
), GFP_KERNEL
);
1377 hcr_base
= of_iomap(ofdev
->node
, 0);
1379 goto error_exit_with_cleanup
;
1381 ssr_base
= hcr_base
+ 0x100;
1382 csr_base
= hcr_base
+ 0x140;
1384 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base
+ TRANSCFG
));
1385 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc
));
1386 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE
);
1388 host_priv
= kzalloc(sizeof(struct sata_fsl_host_priv
), GFP_KERNEL
);
1390 goto error_exit_with_cleanup
;
1392 host_priv
->hcr_base
= hcr_base
;
1393 host_priv
->ssr_base
= ssr_base
;
1394 host_priv
->csr_base
= csr_base
;
1396 irq
= irq_of_parse_and_map(ofdev
->node
, 0);
1398 dev_printk(KERN_ERR
, &ofdev
->dev
, "invalid irq from platform\n");
1399 goto error_exit_with_cleanup
;
1402 /* allocate host structure */
1403 host
= ata_host_alloc_pinfo(&ofdev
->dev
, ppi
, SATA_FSL_MAX_PORTS
);
1405 /* host->iomap is not used currently */
1406 host
->private_data
= host_priv
;
1410 host
->ports
[0]->ioaddr
.cmd_addr
= host_priv
->hcr_base
;
1411 host
->ports
[0]->ioaddr
.scr_addr
= host_priv
->ssr_base
;
1413 /* initialize host controller */
1414 sata_fsl_init_controller(host
);
1417 * Now, register with libATA core, this will also initiate the
1418 * device discovery process, invoking our port_start() handler &
1419 * error_handler() to execute a dummy Softreset EH session
1421 ata_host_activate(host
, irq
, sata_fsl_interrupt
, SATA_FSL_IRQ_FLAG
,
1424 dev_set_drvdata(&ofdev
->dev
, host
);
1428 error_exit_with_cleanup
:
1438 static int sata_fsl_remove(struct of_device
*ofdev
)
1440 struct ata_host
*host
= dev_get_drvdata(&ofdev
->dev
);
1441 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1443 ata_host_detach(host
);
1445 dev_set_drvdata(&ofdev
->dev
, NULL
);
1447 irq_dispose_mapping(host
->irq
);
1448 iounmap(host_priv
->hcr_base
);
1454 static struct of_device_id fsl_sata_match
[] = {
1456 .compatible
= "fsl,mpc8315-sata",
1459 .compatible
= "fsl,mpc8379-sata",
1464 MODULE_DEVICE_TABLE(of
, fsl_sata_match
);
1466 static struct of_platform_driver fsl_sata_driver
= {
1468 .match_table
= fsl_sata_match
,
1469 .probe
= sata_fsl_probe
,
1470 .remove
= sata_fsl_remove
,
1473 static int __init
sata_fsl_init(void)
1475 of_register_platform_driver(&fsl_sata_driver
);
1479 static void __exit
sata_fsl_exit(void)
1481 of_unregister_platform_driver(&fsl_sata_driver
);
1484 MODULE_LICENSE("GPL");
1485 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1486 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1487 MODULE_VERSION("1.10");
1489 module_init(sata_fsl_init
);
1490 module_exit(sata_fsl_exit
);